Procedures for self-testing, data bus arrangement and use

Abstract

Method for self-testing a signal transmission for communication in a data bus arrangement, wherein the data bus arrangement has a first data bus line (3) and a transceiver (1) and the transceiver (1) has a first stage (15) and the first stage (15) is connected to the first data bus line (3), characterized in that the following further steps are carried out: - Transmitting a first test signal from the first stage (15) to the first data bus line (3), - Measuring a first voltage level (3b-d) on the first data bus line (3), - Comparing the measured first voltage level (3b-d) with a first target voltage level and - Determine whether the first stage (15) is functional by means of the result of the comparison, - wherein the transmission of the first test signal is aborted as soon as the first measured voltage level (3b-d) exceeds or falls below a threshold value.

Description

[0001] The invention relates to a method for self-testing according to the preamble of claim 1, a data bus arrangement according to claim 13 and a use according to claim 15.

[0002] In conventional data bus systems that comply with the CAN standard, two data bus lines are provided, each of which connects to several control units. These control units typically contain a controller and a transceiver. The control units are connected to the data bus lines via a stub line, with one of the data bus lines serving as a CAN high and one as a CAN low line. CAN data bus systems are used, for example, in motor vehicles to avoid multiple individual wiring between control units.

[0003] In the idle state, the same voltage value is set on both data bus lines, or the voltage values ​​on both data bus lines are not far apart. This idle state is also referred to as a recessive state. If the data bus lines are placed in a dominant state, the voltage on the CAN high line increases and the voltage on the CAN low line decreases. Thus, the two voltage levels of the data bus lines are further apart in the dominant state than in the recessive state. Furthermore, the input resistance of the CAN high and CAN low lines is lower in the transceiver's dominant mode.

[0004] The transceiver has two connections to the controller: a transmit input (TX) and a receive input (RX). The transmit input provides the transceiver with information for setting the dominant or recessive state. The receive input forms a readback line for the signals. These are read from the data bus by the transceiver and forwarded to the controller.

[0005] When CAN transceivers send telegrams to the bus—controlled by the CAN controller—a bit sequence of zeros and ones is present at the transceiver's transmit input (TX). While the individual bits are being transmitted, the transmitting CAN controller reads the bit back via the transceiver's receive input (RX).

[0006] During simultaneous communication between the control units, the bits in the data frames determine which control unit is allowed to send its data first ("arbitration"). The priority of each control unit is determined in such a way that, for example, safety-relevant messages (e.g., in the event of an engine control unit failure) can be sent before simple warnings (e.g., a failure of an LED display).

[0007] The transceivers comprise at least a first and a second driver. Each driver is assigned to a data bus line and generates the corresponding signals for the assigned bus line and transmits them to that bus line. By reading back the signals via the receive input RX, the priority can be determined during arbitration, and a non-functioning driver can be detected – e.g., by the microcontroller (if a recessive bit is read back when a dominant bit is transmitted).

[0008] Document DE 103 49 600 A1 describes a method for checking for line faults in a bus system having at least two bus devices connected to a data bus with at least two bus lines for the purpose of data communication. The bus devices can assume a recessive state and a dominant state, with an internal high potential and an internal low potential being available in the bus devices. A line fault check can then be performed by a predetermined bus device, after which corrective measures can be initiated.

[0009] Document DE 10 2017 212 544 A1 describes a transmitting / receiving device for a CAN bus system and a further method for detecting a short circuit with a CAN transmitting / receiving device. A diagnostic unit is provided to perform a diagnosis regarding short circuits in a predetermined communication phase of the bus signal.

[0010] Finally, document DE 10 2006 048 073 A1 describes an electrical circuit for operating a bus of a fieldbus system with means for sensing a fault current, which comprises: first means for determining a first current of a first bus line, second means for determining a second current of a second bus line, and means for detecting a fault based on the first current and the second current. Currently, there is no way to independently test a CAN transceiver upon startup. The only possibility would be to put the CAN controller into test mode, request a dominant level by applying a zero to the transmit input TX, and read this back to RX. This requires a high level of complexity, the duration of the dominant level is too long, and thus the bus is disrupted.

[0011] The same applies to a LIN bus and Flexray. The LIN bus has only one data bus line and only one stage in the transceiver, which controls the voltage on the bus line. Flexray, on the other hand, has two data bus lines, but two additional stages.

[0012] It is therefore the object of the invention to provide a testing option for the functionality of the CAN transceiver, in particular the associated drivers, in order to detect errors promptly.

[0013] The problem is solved by the independent claims.

[0014] The invention provides a method for self-testing a signal transmission for communication in a data bus arrangement, wherein the data bus arrangement has a first data bus line and a transceiver, the transceiver has a first stage, and the first stage is connected to the first data bus line. For the method, a first test signal is transmitted from the first stage to the first data bus line. Subsequently, a first voltage level is measured on the first data bus line. This first measured voltage level is then compared with a predetermined first target voltage level, and the transmission of the first test signal is aborted as soon as the first measured voltage level exceeds or falls below a threshold value. From the result of this comparison, it can then be determined whether the first stage is functional.

[0015] The procedure provides a cost-effective and inexpensive method to test the (CAN) transceiver, in particular the drivers (equal stages and referred to as so-called “dominant drivers”) of the transceiver.

[0016] The data bus arrangement is preferably based on the LIN, CAN or Flexray standards.

[0017] In a preferred embodiment of the invention, the data bus arrangement has a second data bus line, and the transceiver has a second stage, the second stage being connected to the second data bus line. In this case, the data bus arrangement preferably relates to the CAN or Flexray standard.

[0018] In further developments of the invention, the same steps are carried out with respect to the second stage. First, a second test signal is transmitted from the second stage to the second data bus line. Subsequently, a second voltage level is measured on the second data bus line, and the measured second voltage level is subsequently compared with a second target voltage level. The result of the comparison is then used to determine whether the second stage is functional. This further development makes it possible to advantageously test both stages for their functionality. The measurement of the voltage levels and the comparison with the target voltage levels preferably takes place using a comparator(s).

[0019] In a preferred embodiment of the invention, the test signals are transmitted from the first and second stages sequentially. A dominant state is only generated when both stages transmit signals to the bus at essentially the same time. Therefore, transmitting the test signals sequentially does not generate a dominant state; rather, the voltage of the data bus line associated with the respective stage is simply raised or lowered. Via a terminating resistor, the voltage of one line essentially follows that of the other.

[0020] In an alternative development of the invention, the test signals from the first and second stages are transmitted essentially simultaneously. This essentially corresponds to the normal function for transmitting data signals, with the addition of a monitoring function. This can be implemented in various ways. In this development, a CAN bus or Flexray is used.

[0021] In a first embodiment of this further development, the test signal is so short that the test signal does not fall within the sampling period of its own controller or the controllers of other participants in the data bus arrangement. In other words, the dominant level ends before the sampling time. This means that the connected controller and the other nodes do not detect this level as the start of a telegram. However, a voltage change on the bus may become visible without a dominant bit necessarily being detected on the RX path (receive connection) because the differential voltage threshold is not exceeded. Preferably, for example, in a CAN bus system, a comparator is assigned to each of the first and second data bus lines (CAN-H and CAN-L) and a check is carried out to determine whether the voltages change, since in the dominant state they are raised on CAN-H and lowered on CAN-L.

[0022] With a LIN bus, only the first test signal is relevant, as the LIN bus also only comprises one data bus line. With the CAN bus and Flexray, there is a second test signal in addition to the first test signal, so the formation of both is referred to here. This also applies to the following, second configuration.

[0023] In a second embodiment, the test signals are designed to be long enough to allow reception of the voltage levels resulting from the test signal via the readback path. The dominant level on the (CAN) high / low lines is therefore set to be "sufficiently" long so that it can be detected via the normal receive path (RX). This eliminates the need for an additional comparator; however, it does result in a signal change at the receive input RX. This signal change, in the form of a voltage level at the RX (corresponding to the dominant level on the bus), is preferably set shorter than the sampling time on the controller and therefore has no effect on the controller. The advantage of this solution is that the receiver can also be tested.

[0024] In a preferred development of the invention, the data bus arrangement has two comparators sequentially during transmission of the test signals. Preferably, one comparator is provided for each data bus line. This makes it possible to determine whether the transceiver currently being tested is actually the only one transmitting, or whether another node is also transmitting. Since this solution does not generate dominant states on the bus, this method is particularly preferred and is also suitable for use during regular operation. Particularly preferably, two comparators are provided for each data bus line. This makes it possible to reduce errors. A / D converters can also be used as an alternative to comparators.

[0025] In a further preferred embodiment of the invention, a time window is defined in which the voltage is detected and considered for further processing. Either the comparators or A / D converters are active during the time window and detect the voltage, or the comparators or A / D converters are continuously active and the comparator results are transferred within the defined time window.

[0026] In a further development of the two alternative embodiments, the transmission of the first and / or the second test signal is aborted as soon as the first measured voltage level and / or the second measured voltage level exceeds or falls below a threshold value. Thus, in both the first embodiment and the second embodiment, the activation of the stage can be aborted prematurely as soon as one of the comparators exceeds or falls below the expected threshold. Alternatively, the time of abort can be set to a time after a specific period of time starting from the exceedance or undershoot of the threshold. Furthermore, alternatively, the abort can also be triggered by a measured value at the receive input that exceeds or falls below a specific threshold value.

[0027] In a further development, the measured voltage levels and / or the voltage levels exceeded in the comparator are stored and made available to a microcontroller for processing and evaluation.

[0028] In a further development, the test signal in the first and second embodiments is suppressed and / or an error flag is set in the transceiver if a zero is present at the transmit input (i.e., TX=0), i.e., if the CAN controller is transmitting simultaneously. This advantageously ensures that the normal functionality of the transceiver is not disrupted by the self-test.

[0029] In a further preferred embodiment, the result of the self-test and the bus level are stored and made available to the connected microcontroller for reading via an interface (e.g. SPI).

[0030] In a further preferred development of the invention, a decision is made as to whether the transmission of test signals takes place sequentially or simultaneously.

[0031] In a further preferred embodiment, the result of the comparators is stored, preferably as one or more register flags. Either the raw data (comparator values) or the logical (further processed) response (pass / fail) is stored.

[0032] In a further preferred embodiment, the length of the test pulses is configurable. Particularly preferably, the comparator thresholds are also configurable.

[0033] In a further preferred embodiment, the method is executed multiple times during simultaneous and sequential transmission of the test signals to the data bus lines to improve error tolerance. Since the length of a bit is defined, it is possible to check whether only the test signal is present by reading the comparator(s) multiple times (e.g., before and after). Transmission by the connected, dedicated controller is diagnosed via TX=0, and the test is flagged with an error flag.

[0034] In a further preferred embodiment, the self-test is performed before the actual communication begins; for example, after a wake-up signal when the engine starts. The test can also be performed to test a failsafe function, which is to shut down the transceiver in the event of a fault. In further tests, the transceiver shutdown is preferably suppressed. Therefore, it is tested whether the transceiver is still turning on or not yet turning on.

[0035] It is particularly preferable to enable bus biasing before sending the test signal(s). Bus biasing refers to the activation of the recessive, high-impedance voltage levels on the high and low lines.

[0036] The invention further relates to a data bus arrangement having a first data bus line and at least one transceiver, wherein the transceiver has a first stage and wherein the first stage is connected to the first data bus line, wherein the transceiver has a communication interface or a control pin via which commands for carrying out a self-test can be transmitted to the transceiver.

[0037] In a preferred development of the data bus arrangement, it comprises a second data bus line and the transceiver comprises a second stage, wherein the second stage is connected to the second data bus line.

[0038] Preferably, the test signal is transmitted to the transceiver via the specified communication interface (e.g., SPI) or the control pin. This allows the test to be performed completely independently of the controller. The transceiver is preferably connected to a microcontroller via the interface or the control pin.

[0039] In a preferred embodiment of the invention, the data bus arrangement comprises a third and a fourth driver in the transceiver, with the third driver connected to the first data bus line and the fourth driver connected to the second data bus line. The standard of the data bus arrangement or the associated protocol refers to Flexray.

[0040] Furthermore, the invention relates to a use of the data bus arrangement in a motor vehicle.

[0041] Further preferred embodiments also emerge from the subclaims and the following description of embodiments with reference to figures.

[0042] In schematic representation, examples are shown: Fig. 1 a circuit diagram of a transceiver according to the invention using CAN as an example, Fig. 2 shows the signal curve when sending test signals simultaneously, Fig. 3 shows the idealized signal curve when test signals are not sent simultaneously in the case of many connected control units (= recessive drivers), Fig. 4 Superposition of the test pulses on the usual generation of a dominant bit.

[0043] Fig. 1 shows the schematic structure of a CAN transceiver 1, which is part of a data bus arrangement. The transceiver 1 is connected to a first data bus line 3 and a second data bus line 5, wherein the first data bus line 3 is designed as a CAN high line and the second data bus line 5 is designed as a CAN low line. The transceiver comprises a transmit input TX and a receive input RX as well as an interface 7 (e.g. designed as an SPI interface). A receive module 9 and a transmit module 11 as well as a test module 13 are arranged in the transceiver. The receive module 9 receives signals from the data bus lines 3, 5 and can process them in order to then forward corresponding data to the CAN controller via the receive input RX. The transmit module 11 receives signals via the transmit input TX and processes them. The transmit module 11 can then forward corresponding data to a first stage 15 and a second stage 17.The first stage 15 represents a driver / stage for the first data bus line 3 and is connected to it, and the second stage 17 represents a driver / stage for the second data bus line 5 and is connected to it. The test module 13 receives data from the microcontroller via the interface 7 and forwards corresponding signals via the transmitter module 11 to the first stage 15 and the second stage 17, which are connected to the first data bus line 3 and the second data bus line 5. Thus, test pulses can reach the data bus lines 3, 5 via the interface 7, the test module 13, the transmitter module 11, and the first and second stages 15, 17.

[0044] In addition, the transceiver 1 comprises a first trigger 19 and a second trigger 21, each of which is connected to one of the data bus lines 3, 5 and the test module 13 and is preferably designed as a comparator. Triggers 19, 21 make it possible to read the voltage on the data bus lines 3, 5 and process it in the test module 13. For storing the data, the test module 13 preferably contains a readback memory. Furthermore, the transceiver 1 comprises a bus biasing module 23.

[0045] Fig. Figure 2 shows the signal waveform on the data bus lines 3, 5 and the corresponding signal at the receive input RX when both stages 15, 17 are switched on simultaneously. The voltage on the first data bus line 3 is generally designated by the reference symbol 3x, while the voltage on the second data bus line 5 is designated by the reference symbol 5x. In the first period Z1 of the illustration, a dominant signal is generated on the data bus lines 3, 5 by increasing the voltage 3a on the first data bus line 3 (CAN high) and decreasing the voltage 5a on the second data bus line 5 (CAN low). At the receive input RX, the signal changes from a high ("1"), reference symbol 100, during the recessive state to a low ("0"), reference symbol 110, during the dominant state.

[0046] In the second period Z2 of the diagram, a test pulse 3b, 5b is applied to the data bus lines 3, 5. The first and second stages 15, 17 simultaneously transmit test signals 3b, 5b to the first and second data bus lines 3, 5. Here, too, the voltage 3b on the first data bus line 3 (CAN-High) is increased and the voltage 5b on the second data bus line 5 (CAN-Low) is decreased – but for a shorter period than that required to generate the dominant state. Accordingly, a shorter "0" state is also created at the receive input RX. By switching on the two stages 15, 17 for a very short time, it is possible to test the functionality of the transceiver while simultaneously keeping the interference on the data bus lines 3, 5 as low as possible. This is done by reading back the voltages from the data bus lines 3, 5 via the triggers 19, 21. Preferably, a voltage threshold is defined in each of the two triggers 19, 21.If the voltage on data bus lines 3 and 5 falls below or exceeds the respective voltage threshold, the transmission of the test pulse is aborted. Stages 15 and 17 are controlled accordingly.

[0047] Particularly preferably, the test signal 3b, 5b is so short in time that it does not fall within the sampling period of other participants in the data bus arrangement. This allows the test signal on the data bus lines 3, 5 to be easily identified and does not cause interference for the other participants.

[0048] Fig. 3 shows a self-test of the transceiver according to the invention, wherein test signals 3c, 5c, 3d, 5d from stages 15, 17 are not applied simultaneously to data bus lines 3, 5. In the first period Z1, a test signal 3c, 5c is transmitted from the first stage 17 and the second stage 19 to the first data bus line 3 and the second data bus line 5, so that the voltage 3c, 5c on the data bus lines 3, 5 is increased. In the second period Z2, a test signal 3d, 5d is transmitted from the first stage 17 and the second stage 19 for the first data bus line 3 and the second data bus line 5, so that the voltage 3d, 5d on the data bus lines 3, 5 is reduced. By not sending the test signals 3c,5c and 3d,5d simultaneously, no dominant state is generated on the data bus lines 3, 5, so that only a high (“1”) is present at the receive input RX, which does not change over time.

[0049] At the comparators, the threshold value 120 is exceeded during the test signal when the voltage on the first data bus lines 3, 5 increases, and the threshold value 130 is undershot during the test signal when the voltage on the data bus lines 3, 5 decreases. The signal change caused by the comparators by the undershoot or overshoot of the threshold values ​​120, 130 is preferably used to abort the transmission of the respective test signal in order to avoid unnecessary interference on the data bus lines 3, 5. The comparators are preferably configurable to enable the optimal voltage threshold to be set.

[0050] Fig. Figure 4 shows the superposition of a test pulse with dominant bits from other receivers, where the test signals for increasing and decreasing the voltage are not applied simultaneously to the data bus lines 3, 5. On the left side in Fig. 4a-d shows the superposition of a test signal by increasing the voltage on the data bus lines 3,5, while on the right side in the Fig. 4e-h, the superposition is represented by a decrease in voltage. Time is shown on the x-axis, and voltage is shown on the y-axis.

[0051] In Fig. Figure 4a shows a typical signal transmission for generating a dominant bit 3a, 5a to the data bus lines 3, 5, wherein the voltage 3a is increased on the first data bus line 3 (CAN-H line) and the voltage 5a is decreased on the second data bus line 5 (CAN-L line). Fig. 4b shows a test signal 3c, 5c, which is generated by the first stage 15 and the second stage 17. The test signal 3c, 5c can be seen on both data bus lines 3, 5. In Fig. 4c is the superposition of the signals from Fig. 4a and Fig. 4b. In Fig. 4d shows the voltage at the receive input RX, with a “1” being present during the recessive state 100 and a “0” during the dominant state 110.

[0052] The explanations apply equally to the Fig. 4e-h, with the difference that here a test signal 3d, 5d, generated by the first and second stages 15, 17, reduces the voltage on data bus lines 3, 5 and is superimposed on the dominant bit. In both examples, the test signal is not visible at the receive input RX. This allows the transceiver to be tested for functionality during operation without disturbing the signals on data bus lines 3, 5. List of reference symbols: TX transmit input RX receive input 1 (CAN) transceiver 3 first data bus line 5 second data bus line 3x voltage on the first data bus line (general) 5x voltage on the second data bus line (general) 3a Voltage on the first data bus line during a dominant bit 5a Voltage on the second data bus line during a dominant bit 3b Voltage on the first data bus line during a test pulse with simultaneous transmission of a signal by stage 15, 17 5b Voltage on the second data bus line during a test pulse with simultaneous transmission of a signal through stages 15, 17 3c increased voltage on the first data bus line during a test pulse when transmitted by the first stage 15 5c increased voltage on the second data bus line during a test pulse when transmitted by the second stage 17 3d reduced voltage on the first data bus line during a test pulse when transmitted by the first stage 15 5d reduced voltage on the second data bus line during a test pulse when transmitted by the second stage 17 7 Interface 9 Receiver module 11 Transmitter module 13 Test module 15 first stage 17 second stage 19 triggers 21 triggers 23 Bus biasing module 100 recessive condition 110 dominant state 120 Threshold for exceedance 130 Threshold for undershoot

Claims

[1] Method for self-testing a signal transmission for communication in a data bus arrangement, wherein the data bus arrangement comprises a first data bus line (3) and a transceiver (1), and the transceiver (1) comprises a first stage (15), and the first stage (15) is connected to the first data bus line (3), characterized by that the following further steps are carried out: - transmitting a first test signal from the first stage (15) to the first data bus line (3), - measuring a first voltage level (3b-d) on the first data bus line (3), - comparing the measured first voltage level (3b-d) with a first target voltage level and - Determine whether the first stage (15) is functional by means of the result of the comparison, - wherein the transmission of the first test signal is interrupted as soon as the first measured voltage level (3b-d) exceeds or falls below a threshold value. [2] Method according to claim 1, characterized by that the data bus arrangement has a second data bus line (5) and a second stage (17) and the second stage (17) is connected to the second data bus line (5) and the following step is carried out: - Transmitting a second test signal from the second stage (17) to the second data bus line (5). [3] Method according to claim 2, characterized by that the following step is carried out: - measuring a second voltage level (5b-d) on the second data bus line (5), - comparing the measured second voltage level (5b-d) with a second target voltage level and - Determine whether the second stage (17) is functional using the result of the comparison. [4] Method according to one of claims 2 or 3, characterized by that the transmission of the first and second test signals takes place one after the other. [5] Method according to one of claims 2 or 3, characterized by that the first and second test signals are transmitted simultaneously. [6] Method according to claim 5, characterized by that the first test signal is designed to be so short in time that the first test signal does not coincide with the sampling period of other participants in the data bus arrangement. [7] Method according to one of claims 5 or 6, characterized by that the second test signal is designed to be so short in time that the second test signal does not coincide with the sampling period of other participants in the data bus arrangement. [8] Method according to claim 5, characterized by that the following step is carried out: - Receiving signals via the first data bus line (3) by the transceiver (1), wherein the reception of the signals of the transceiver (1) takes place via a readback path and the first test signal is designed to be so long that reception of the voltage levels (3b-d) resulting from the first test signal can be carried out via the readback path. [9] Method according to one of claims 5 or 8, characterized by that the following step is carried out: - Receiving signals via the second data bus line (5) by the transceiver (1), wherein the reception of the signals of the transceiver (1) takes place via a readback path and the second test signal is designed to be so long that reception of the voltage levels (5b-d) resulting from the second test signal can be carried out via the readback path. [10] Method according to claims 2 and 3, characterized bythat the transmission of the second test signal is interrupted as soon as the second measured voltage level (5b-d) exceeds or falls below a threshold value. [11] Method according to one of the preceding claims, characterized by that the measured voltage levels are stored and made available to a microcontroller for processing. [12] Data bus arrangement with a first data bus line (3) and at least one transceiver (1), wherein the transceiver (1) has a first stage (15) and wherein the first stage (15) is connected to the first data bus line (3), characterized by that the transceiver has a communication interface (7) or a control pin via which commands for carrying out a self-test according to the method according to claim 1 can be transmitted to the transceiver (1). [13] Data bus arrangement according to claim 12, characterized bythat the data bus arrangement has a second data bus line (5) and the transceiver (1) has a second stage (17), and wherein the second stage (17) is connected to the second data bus line (5). [14] Use of the method according to one of claims 1 to 11 in a motor vehicle.

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