INTEGRATED CIRCUIT FOR FORMING A FLAT BOTTOM ELECTRODE VIA (BEVA) FOR STORAGE AND METHOD FOR MANUFACTURING

Abstract

Integrated circuit comprising the following: a conductive wire (114); a dielectric through-hole layer (204) that lies above the conductive wire (114); a via (106) extending through the dielectric via layer (204) to the conductive wire (114), wherein the via (106) comprises a conductive body (106lb, 106ub) and a conductive lining (106l), the conductive lining (106l) enclosing a lower part of the conductive body (106lb, 106ub) and having an upper surface recessed below an upper surface (106t) of the via (106), and wherein the conductive body (106lb, 106ub) hangs above the upper surface of the conductive lining (106l) and defines the upper surface (106t) of the via (106), and a memory cell (102) directly on the upper surface of the via, wherein the dielectric via layer (204) comprises a lower dielectric layer (204l) and an upper dielectric layer (204u) that directly contacts the lower dielectric layer (204l), wherein the upper surface of the conductive lining (106l) is located above the surface of the lower dielectric layer (204l).

Description

REFERENCE TO RELATED APPLICATION

[0001] An integrated circuit comprising: a conductive wire; a dielectric via layer overlying the conductive wire; a via extending through the dielectric via layer to the conductive wire, the via comprising a conductive body and a conductive liner, the conductive liner including a lower portion of the conductive body and an upper surface recessed below an upper surface of the via, the conductive body overhanging the upper surface of the conductive liner and defining the upper surface of the via, and a memory cell directly on the upper surface of the via, the dielectric via layer comprising a lower dielectric layer and an upper dielectric layer directly contacting the lower dielectric layer.wherein a width of the via decreases continuously from the upper surface of the via to an interface between the lower and upper dielectric layers, and wherein the width of the via is substantially uniform from the interface to the conductive wire. STATE OF THE ART

[0002] Many modern electronic components feature non-volatile memory. Non-volatile memory is electronic memory capable of storing data in the absence of power. Some promising candidates for the next generation of non-volatile memory include resistive random-access memory (RRAM) and magnetoresistive random-access memory (MRAM). RRAM and MRAM have relatively simple structures and are compatible with complementary metal-oxide-semiconductor (CMOS) logic manufacturing processes. An integrated circuit is known, for example, from the publication US 2017 / 0 473 75 A1. A similar integrated circuit is also known from the publication US 7 189 626 B2. Further integrated circuits are known from the publications DE 10 2016 100 136 A1, US 2017 / 0 053 967 A1, US 2003 / 0 203 512 A1, and KR 10 2003 0 049 027 A. The task is to improve corresponding integrated circuits. The object is achieved by the integrated circuits according to patent claims 1 and 20 and the method according to patent claim 10. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of the present disclosure are best understood from the following detailed description with reference to the accompanying figures. It is emphasized that, in accordance with standard industry practice, various elements are not drawn to scale. Indeed, the dimensions of various features may be arbitrarily exaggerated or reduced for clarity of discussion. Fig. 1 illustrates a cross-sectional view of some embodiments of an integrated circuit (IC) including a memory cell on a flat bottom electrode via surface. Fig. Figure 2 illustrates a cross-sectional view of some more detailed embodiments of the IC of the Fig. 1. Fig. Figure 3 illustrates a cross-sectional view of some more detailed embodiments of the IC of the Fig. 2. The Fig. 4 to 6, 7A to 7C, 8 to 20 illustrate a series of cross-sectional views of some embodiments of a method for forming an IC including a memory cell on a flat BEVA top surface. Fig. Figure 21 illustrates a flow diagram of some embodiments of the method of Fig. 4 to 6, 7A to 7C, 8 to 20. DETAILED DESCRIPTION

[0004] The present disclosure provides many different embodiments or examples for implementing different features of this disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, forming a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, the present disclosure may repeat reference numerals and / or reference letters in the various examples.This repetition is intended for simplicity and clarity and does not itself prescribe any relationship between the various embodiments and / or configurations discussed.

[0005] Furthermore, spatial reference terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein for ease of description to describe the relationship of an element or feature to one or more other elements or elements as illustrated in the figures. The spatial reference terms may be intended to encompass different orientations of the component during use or operation in addition to the orientation depicted in the figures. The device may be oriented differently (rotated 90 degrees or at other orientations), and the spatial reference descriptors used herein will be interpreted accordingly.

[0006] According to a method for forming an integrated circuit (IC), a bottom electrode via (BEVA) dielectric layer is formed covering a metal wire of a back-end-of-line (BEOL) interconnect structure. An etch is performed into the BEVA dielectric layer to form a BEVA opening that exposes the metal wire. A metallic barrier layer is formed covering the BEVA dielectric layer and conformally lining the BEVA opening such that the metallic barrier layer partially fills the BEVA opening. A metallic layer is formed covering the metallic barrier layer and filling a remainder of the BEVA opening above the metallic barrier layer. Planarization is performed into the metallic layer and the metallic barrier layer until the BEVA dielectric layer is reached, thereby forming a BEVA in the BEVA opening.The BEVA comprises a BEVA body formed from the metal layer and further comprises a BEVA liner lining the BEVA body and formed from the metallic barrier layer. A memory cell is then formed directly on a top surface of the BEVA.

[0007] A challenge with the process is that the metal layer and the metallic barrier layer have different hardness values, so planarization removes the metal layer and the metallic barrier layer at different rates. The top surface of the BEVA is consequently uneven or rough. For example, a top surface of the BEVA body may be vertically offset from a top surface of the BEVA liner. Because the top surface of the BEVA is uneven or rough, the electric field across the memory cell is not uniform. This uneven electric field, in turn, can lead to poor yield and / or uneven performance during bulk IC manufacturing. As feature sizes in ICs continue to shrink, so do BEVAs and memory cells, so electric field uniformity in memory cells will become increasingly important.

[0008] In view of the above, various embodiments of the present application relate to a method of forming a flat BEVA top surface for memory, as well as an IC resulting from the method. In some embodiments, an etch is performed into a dielectric layer of the via to form an opening overlying and exposing a conductive wire underlying the dielectric layer of the via. A via liner layer is formed covering the dielectric layer of the via and the liner in the opening. The via liner layer partially fills the opening. A bottom via body layer is formed covering the dielectric layer of the via and filling a remainder of the opening above the via liner layer.An upper surface of the lower via body layer and an upper surface of the via liner layer are recessed below an upper surface of the dielectric layer of the via to partially expose the opening and to form a via liner and a lower via body in the opening. An upper via body layer is formed covering the dielectric layer of the via and filling a portion of the opening exposed by the recess. The upper via body layer is homogeneous. Planarization is performed into the upper via body layer until the dielectric layer of the via is reached to form an upper via body of the opening and above the lower via body and the via liner.Together, the upper via body, the lower via body, and the via liner define a via in the opening.

[0009] Because the upper via body layer is homogeneous, the upper via body layer has a substantially uniform hardness, and planarization removes the upper via body layer at a substantially uniform rate. This, in turn, forms the upper via body with a top surface that is homogeneous and flat, or substantially flat. Furthermore, because the top surfaces of each of the lower via body and the via liner are recessed into the opening, the top surface of the upper via body completely defines a top surface of the via. The top surface of the via is therefore homogeneous and is flat, or substantially flat.Because the top surface of the via is flat or substantially flat, the electric field generated across a memory cell directly on the top via body can be uniform or substantially uniform.

[0010] With reference to Fig. 1 provides a cross-sectional view 100 of some embodiments of an IC including a memory cell 102. As illustrated, the memory cell 102 is located on a bottom dielectric layer 104 and a BEVA 106. The memory cell 102 reversibly transitions between a first data state and a second data state depending on a voltage applied across the memory cell 102. In some embodiments, the memory cell 102 is a resistive random access memory (RRAM) cell, a magnetoresistive random access memory (MRAM) cell, or another suitable memory cell type. Further, in some embodiments, the memory cell 102 includes a bottom electrode 108, a data storage element 110, and a top electrode 112.

[0011] The bottom electrode 108 overlies the bottom dielectric layer 104 and the BEVA 106. In some embodiments, the bottom electrode 108 directly contacts a top surface 106t in the BEVA 106 and / or directly contacts a top surface 104t of the bottom dielectric layer 104. The bottom electrode 108 may be, for example, tantalum nitride, titanium nitride, platinum, iridium, ruthenium, tungsten, silver, copper, other suitable conductive material(s), or any combination of the above. As used herein, a term (e.g., conductive material) with a suffix "(ies)," "(s)" may be, for example, singular or plural.

[0012] The data storage element 110 overlies the bottom electrode 108, and the top electrode overlies the data storage element 110. The data storage element 110 reversibly transitions between a first data state and a second data state depending on a voltage applied across the memory cell 102. In some embodiments where the memory cell is an RRAM cell, the memory element 110 is or includes hafnium oxide, other high-κ dielectric(s), other suitable dielectric(s), or any combination of the above. As used herein, a high-κ dielectric is a dielectric having a dielectric constant κ greater than or equal to about 3.9, 5, 10, 15, or 20.In some embodiments where memory cell 102 is an MRAM cell, data storage element 110 is or includes a magnetic tunnel junction (MTJ) or other suitable magnetic data storage structure. Top electrode 112 may be or include, for example, titanium nitride, tantalum nitride, platinum, iridium, tungsten, other suitable conductive material(s), or any combination of the above.

[0013] The bottom dielectric layer 104 separates the memory cell 102 from a bottom wire 114 underlying the memory cell 102 and the BEVA 106. The bottom dielectric layer 104 may be or include, for example, silicon dioxide, silicon oxynitride, a low-κ dielectric, silicon carbide, silicon nitride, or other suitable dielectric(s), or any combination of the above. As used herein, a low-κ dielectric is a dielectric having a dielectric constant κ less than about 3.9, 3, 2, or 1. The bottom wire 114 may be or include, for example, aluminum-copper, copper, aluminum, any other conductive material(s), or any combination of the above.

[0014] The BEVA 106 extends from a bottom of the memory cell 102 through the bottom dielectric layer 104 to the bottom wire 114. In some embodiments, the BEVA 106 directly contacts the bottom wire 114 and / or the top surface 106t of the BEVA 106 is flat or substantially flat with the top surface 104t of the bottom dielectric layer 104. The top surface 106t of the BEVA 106 is flat or substantially flat, such that an electric field generated across the memory cell 102 using the BEVA 106 is uniform or substantially uniform. Further, the top surface of the BEVA 106 is homogeneous (e.g., a single material).In some embodiments, the top surface 106t of the BEVA 106 extends continuously from a first sidewall 106s1 of the BEVA 106 to a second sidewall 106s2 of the BEVA 106, wherein the first and second sidewalls 106s1, 106s2 are on opposite sides of the BEVA 106 and contact sidewalls of the lower dielectric layer 104.

[0015] The BEVA 106 includes a BEVA liner 106l, a lower BEVA body 106lb, and an upper BEVA body 106ub. The upper BEVA body 106ub overlies the lower BEVA body 106lb and the BEVA liner 106l and defines the upper surface 106t of the BEVA 106. Furthermore, the lower BEVA body 106lb and the upper BEVA body 106ub together define a BEVA body such that the lower BEVA body 106lb and the upper BEVA body 106ub may also be called segments of a BEVA body. In some embodiments, the upper BEVA body 106ub directly contacts an upper surface 106t2 of the lower BEVA body 106lb. The upper BEVA body 106ub and the lower BEVA body 106lb may each be or comprise, for example, aluminum, copper, aluminum-copper, tungsten, other suitable conductive material(s), or any combination of the above.

[0016] In some embodiments, the upper BEVA body 106ub is made of the same material as the lower BEVA body 106lb, and / or is integrated into the lower BEVA body 106lb. In other embodiments, the upper BEVA body 106ub is made of a different material than the lower BEVA body 106lb. In some embodiments, the upper BEVA body 106ub is completely homogeneous (e.g., made of a single material), and / or the lower BEVA body 106lb is completely homogeneous (e.g., made of a single material). In some embodiments, the upper BEVA body 106ub is made of the same material as the bottom electrode 108 and / or is integrated into the lower bottom electrode 108. The upper BEVA body 106ub and the bottom electrode 108 may be formed from the same deposit. In other embodiments, the upper BEVA body 106ub is made of a different material than that of the bottom electrode 108.

[0017] The BEVA liner 106l encloses a bottom surface of the lower BEVA body 106lb to line a bottom surface of the lower BEVA body 106lb and sidewalls of the lower BEVA body 106lb. The BEVA liner 106l blocks material from the lower BEVA body 106lb from diffusing or otherwise moving out of the lower BEVA body 106lb and may be or include, for example, titanium nitride, titanium, tantalum nitride, tantalum, other suitable conductive barrier material(s) for the lower BEVA body 106lb, or any combination of the above. In some embodiments, the BEVA liner 106l protrudes to a location above the top surface 106t2 of the lower BEVA body 106lb. Furthermore, in some embodiments, the BEVA lining 106l partially lines side walls of the upper BEVA body 106ub.

[0018] An upper dielectric layer 116 covers the lower dielectric layer 104 and the memory cell 102, and further houses a top wire 118 and a TEVA 120. The upper dielectric layer 116 may be or include, for example, silicon dioxide, a low-kappa dielectric, silicon carbide, silicon nitride, other dielectric(s), or any combination of the above. The upper wire 118 may be or include, for example, aluminum-copper, copper, aluminum, other suitable conductive material(s), or any combination of the above.

[0019] The TEVA 120 lies directly between the top wire 118 and the memory cell 102 and extends from the top wire 118 through the top dielectric layer 116 to the memory cell 102. In some embodiments, the TEVA 120 is homogeneous (e.g., a single material). In other embodiments, the TEVA 120 is heterogeneous and includes a TEVA body 120b and a TEVA liner 120l. The TEVA body 120b may be or include, for example, copper, aluminum-copper, aluminum, tungsten, other suitable conductive material(s), or any combination of the above. The TEVA liner 120l blocks material of the TEVA body 120b from diffusing or otherwise moving out of the TEVA 120, and may be or include, for example, titanium nitride, tantalum nitride, tantalum, tantalum nitride, other suitable conductive barrier material(s) for the TEVA body 120b, or any combination of the above.In some embodiments where the TEVA 120 is heterogeneous, a top surface 120t of the TEVA 120 is heterogeneous and is rough or uneven.

[0020] With reference to Fig. 2, is a cross-sectional view 200 of some more detailed embodiments of the IC of the Fig. 1. As illustrated, the bottom wire 114 lies within a bottom interlayer dielectric (ILD) layer 202. The bottom ILD layer 202 may be or include, for example, silicon dioxide, silicon oxynitride, a low-kappa dielectric, silicon nitride, or other suitable dielectric(s), or any combination of the above. In some embodiments, the bottom wire 114 includes a bottom wire lower body 114b and a bottom wire liner 114l. The bottom wire body 114b may be or include, for example, aluminum-copper, copper, aluminum, another suitable metal, other suitable material(s), or any combination of the above.The bottom wire liner 114l encloses a bottom surface of the bottom wire body 114b such that a bottom surface of the bottom wire body 114b and sidewalls of the bottom wire body 114b are lined. Furthermore, the bottom wire liner 114l blocks material from the bottom wire body 114b from diffusing or otherwise moving out of the bottom wire body 114b. The bottom wire liner 114l may be or include, for example, tantalum, titanium, titanium nitride, tantalum nitride, other suitable conductive material(s) for the bottom wire body 114b, or any combination of the above.

[0021] A BEVA dielectric layer 204 overlies the lower wire 114 and the lower ILD layer 202 and receives the BEVA 106. In some embodiments, the BEVA dielectric layer 204 includes a lower BEVA dielectric layer 204l and an upper BEVA dielectric layer 204u overlying the lower BEVA dielectric layer 204l. Further, in some embodiments, the upper and lower BEVA dielectric layers 204u, 204l are different materials. The upper and lower BEVA dielectric layers 204u, 204l may be or include, for example, silicon carbide, silicon nitride, other suitable dielectric(s), or any combination of the above.In some embodiments, the upper dielectric BEVA-204u is or comprises silicon nitride, another suitable nitride, or another suitable dielectric, and / or the lower dielectric BEVA layer 204l is made of silicon carbide or another suitable dielectric.

[0022] The BEVA 106 extends through the BEVA dielectric 204 from the bottom wire 114 to the memory cell 102. In some embodiments, a width W of the BEVA 106 from the bottom wire 114 to an intersection between the bottom and top BEVA dielectric layers 204u, 204l is uniform or substantially uniform. Further, in some embodiments, the width W of the BEVA 106 increases continuously from the intersection to the top surface 106t of the BEVA 106. The BEVA 106 includes the BEVA liner 106l, the bottom BEVA body 106lb, and the top BEVA body 106ub. The upper BEVA body 106ub lies over the lower BEVA body 106lb and defines the upper surface 106t of the BEVA 106. The BEVA lining 106l encloses an underside of the lower body of the BEVA.The top surface 106t of the BEVA 106 supports the memory cell 102 and is flat or substantially flat to promote a uniform or substantially uniform electric field across the memory cell 102. Furthermore, the top surface 106t of the BEVA 106 is also homogeneous.

[0023] The memory cell 102 reversibly transitions between a first data state and a second data state depending on a voltage applied across the memory cell 102 and may, for example, be an RRAM cell, an MRAM cell, or another suitable memory cell type. In some embodiments where the memory cell 102 is an RRAM cell, the data storage element 110 of the memory cell 102 is normally insulating. However, the data storage element 110 may be made to conduct through conductive filaments 110f formed in the data storage element 110 by applying an appropriate voltage across the memory cell 102. For ease of illustration, only one of the conductive filaments 110f is labeled 110f.Once the conductive filaments 110f are formed, the conductive filaments 110f can be reset (e.g., broken, resulting in a high resistance) or set (e.g., reformed, resulting in a lower resistance) by applying an appropriate voltage across the memory cell 102. The low and high resistances can be used to indicate a digital signal (i.e., "1" or "0"), thereby allowing data storage.

[0024] A hard mask 206 overlies the memory cell 102, and a spacer 208 overlies the data storage element 100 of the memory cell 102. The spacer 208 includes a pair of segments, each adjacent to opposite sidewalls of the top electrode 112 of the memory cell 102. In some embodiments, the segments each adjacent to opposite sidewalls of the hard mask 206, each aligned with the opposite sidewalls of the top electrode 112. In some embodiments, the spacer 208 extends laterally along sidewalls of the top electrode 112 in a closed path to completely enclose the top electrode 112. It should be noted that the spacer 208 shown within the cross-sectional view 200 of the Fig. 2 is not visible. In some embodiments, the spacer 208 is recessed into a top surface of the data storage element 110 (e.g., due to overetching). The hard mask 206 and the spacer 208 may each be or include, for example, silicon nitride, silicon oxide, silicon oxynitride, or other suitable conductive dielectric(s), or any combination of the above.

[0025] A cap layer 210 lines sidewalls of the memory cell 102 and sidewalls of the spacer 208 and further overlies the hard mask 206 and the BEVA dielectric layer 204. A device ILD layer 212 further overlies the cap layer 210 and the BEVA dielectric layer 204. The cap layer 210 may be or include, for example, silicon oxide, other suitable oxide(s), other dielectric(s), or any combination of the above. The device ILD layer 212 may be or include, for example, silicon dioxide, a low-kappa dielectric, silicon nitride, other suitable dielectric(s), or any combination of the above.

[0026] The top wire 118 overlies the memory cell 102 and the device ILD layer 212 within a top ILD layer 214. The top ILD layer 214 may be or include, for example, silicon dioxide, a low-kappa dielectric, silicon nitride, other suitable dielectric(s), or any combination of the above. In some embodiments, the top wire 118 includes a top wire body 118b and a top wire liner 118l. The top wire body 118b may be or include, for example, aluminum-copper, copper, aluminum, other suitable metal(s), other suitable conductive material(s), or any combination of the above.The upper wire liner 118l encloses a bottom surface of the upper wire body 118b such that a bottom surface of the upper wire body 118b and sidewalls of the upper wire body 118b are lined. Furthermore, the upper wire liner 118l blocks material from the upper wire body 118b from diffusing or otherwise moving out of the upper wire body 118b and may be or include, for example, tantalum, titanium, titanium nitride, tantalum nitride, or other suitable barrier material(s) for the upper wire body 118b, or any combination of the above.

[0027] The TEVA 120 is in the device ILD layer 212 and extends from the top wire 118 through the device ILD layer 212 to the memory cell 102. In some embodiments, the TEVA 120 extends through the cap layer 210 and the hard mask layer 206 and / or is buried in a top surface of the top electrode 112 of the memory cell 102. The TEVA 120 includes a TEVA body 120b and a TEVA liner 120l. The TEVA liner 120l encloses a bottom surface of the TEVA body 120b and blocks material of the TEVA body 120b from migrating out of the TEVA 120.

[0028] With reference to Fig. 3 is an expanded cross-sectional view 300 of some embodiments of the IC of the Fig. 2. The cross-sectional view 200 of the Fig. 2 can be taken, for example, within box BX. As illustrated, the IC includes a memory region 302 and a logic region 304. The memory region 302 houses the memory cell 102. The memory cell 102 rests on the BEVA 106 and underlies the TEVA 120. The BEVA 106 has a homogeneous top surface. Furthermore, the top surface of the BEVA 106 is flat or substantially flat to form a uniform electric field across the memory cell 102.

[0029] In some embodiments, memory cell 102 is one of many memory cells that define a memory cell array (not labeled) in memory area 302. In some embodiments, each memory cell of the memory cell array, such as memory cell 102, is described with reference to Fig. 1 and / or Fig. 2. In some embodiments, each memory cell of the memory cell array rests on a BEVA and underlies a TEVA. Each TEVA of the memory cell array may, for example, be like the TEVA 120 described with reference to Fig. 1 and / or Fig. 2. Each BEVA of the memory cell array may, for example, be like the BEVA 106 described with reference to Fig. 1 and / or Fig. 2, to form a uniform or substantially uniform electric field across a corresponding memory cell. In some embodiments, each memory cell of the memory cell array overlies and is electrically coupled to an access device 306. The access device 306 facilitates access to or selection of a corresponding memory cell in the memory cell array and may be, for example, an insulated field-effect transistor (IGFET), a metal-oxide-semiconductor field-effect transistor (MOSFET), or another suitable semiconductor device type.

[0030] The logic region 304 houses a logic device 308. The logic device 308 may, for example, be an IGFET, a MOSFET, or another suitable semiconductor device type. In some embodiments, the logic device 308 is one of many logic devices that define a logic core (not named). In some such embodiments, the operation of the logic core is supported or assisted by the memory cell array and / or the memory cell array is embedded memory. Further, in some embodiments, the logic device 308 supports the operation of the memory cell 102 and / or the memory cell array. The logic device 308 may, for example, facilitate reading and / or writing data to / from the memory cell 102 and / or the memory cell array.

[0031] In addition to the memory cell 102 and the logic device 308, the IC further includes a semiconductor substrate 310 and a BEOL trace structure 312. The semiconductor substrate 310 supports and partially defines the logic device 308 and, in some embodiments, the access device 306. In some embodiments, the semiconductor substrate 310 supports and partially defines a logic core including the logic device 308. The semiconductor substrate 310 may be, for example, a bulk silicon substrate, a semiconductor-on-insulator (SOI) substrate, or another suitable semiconductor substrate type. The BEOL trace structure 312 overlies the semiconductor substrate 310 and receives the memory cell 102. In some embodiments, a memory cell array including memory cell 102 further overlies and houses BEOL trace structure 312.The BEOL trace structure 312 includes a dielectric stack and a plurality of conductive features.

[0032] The dielectric stack includes a bottom ILD layer 202 covering the semiconductor substrate 310 and the logic device 308. In some embodiments, the bottom ILD layer 202 further covers the access device 306. The dielectric stack further includes a BEVA dielectric layer 204 covering the bottom ILD layer 202, a device ILD layer 212 covering the BEVA dielectric layer 204, and a top ILD layer 214 covering the device ILD layer 212.

[0033] The conductive features are stacked in the dielectric stack to define conductive paths that interconnect the memory cell 102, the logic device 308, and other components of the IC (e.g., the access device 306). The conductive feature includes the bottom wire 114, the top wire 118, the BEVA 106, and the TEVA 120. Furthermore, the conductive features include a plurality of additional vias 314 and a plurality of additional wires 316. The additional vias 314 and the additional wires 316 may be or include, for example, tungsten, copper, aluminum-copper, aluminum, other suitable conductive material(s), or any combination of the above.

[0034] While the above discussion of the Fig. 1 to 3 concerned the memory on the BEVA 106, it must be appreciated that other types of electronic components may be on the BEVA 106. For example, a metal-insulator-metal (MIM) capacitor, another suitable type of MIM structure, or another suitable type of electronic component may be on the BEVA 106.

[0035] With reference to the Fig. 4 to 6, 7A to 7C, 8 to 20, a series of cross-sectional views 400 to 600, 700A to 700C, 800 to 2000 of some embodiments of a method for forming an IC that forms a memory cell on a flat BEVA top surface are provided. The IC may, for example, be the IC of Fig. 2 be.

[0036] As can be seen from the cross-sectional view 400 of the Fig. 4, a substrate 402 is provided or formed. The substrate 402 includes a lower ILD layer 202 and a lower wire 114. Furthermore, in some embodiments, the substrate 402 includes the semiconductor substrate 310 of the Fig. 3, a section of the conductor track structure 312 of the Fig. 3, which is located under the dielectric BEVA layer 204, the access component 306 of the Fig. 3, the logic component 308 of the Fig. 3 or any combination of the above. The lower ILD layer 202 may be or comprise, for example, silicon nitride, silicon oxide, a low-κ dielectric layer, other suitable dielectric(s), or any combination of the above. The lower wire 114 is recessed into a top surface of the lower ILD layer 202 such that a top surface of the lower wire 114 is flat or substantially flat with a top surface of the lower ILD layer 202. The lower wire 114 may be or comprise, for example, titanium nitride, tantalum, tantalum nitride, titanium, aluminum, aluminum-copper, copper, other suitable conductive material(s), or any combination of the above. In some embodiments, the lower wire 114 is heterogeneous (e.g., made of multiple materials) and includes a lower wire body 114b and a lower wire liner 114l.The lower wire liner 114l encloses a bottom surface of the lower wire body 114b and blocks material from the lower wire body 114b from migrating to the surrounding structure. The lower wire liner 114l may be or include, for example, titanium, tantalum, titanium nitride, tantalum nitride, other suitable barrier material(s) for the lower wire body 114b, or any combination of the above. The lower wire body 114b may be or include, for example, copper, aluminum-copper, aluminum, other suitable conductive material(s), or any combination of the above.

[0037] As can be seen from the cross-sectional view 400 of the Fig. 4, a BEVA dielectric layer 204 is formed covering the substrate 402. The BEVA dielectric layer 204 may be or comprise, for example, silicon carbide, silicon nitride, silicon oxide, silicon oxynitride, other suitable dielectric(s), or any combination of the above. In some embodiments, the BEVA dielectric layer 204 includes a lower BEVA dielectric layer 204l and an upper BEVA dielectric layer 204u covering the lower BEVA dielectric layer 204l. The lower BEVA dielectric layer 204l may be or comprise, for example, silicon carbide or another suitable dielectric, and / or the upper BEVA dielectric layer 204u may be or comprise, for example, silicon nitride or another suitable dielectric.In some embodiments, a process for forming the BEVA dielectric layer 204 includes chemical vapor deposition (CVD), physical vapor deposition (PVD), one or more other suitable deposition processes, or any combination of the above. As used herein, a term (e.g., process) with a suffix "(s)" may, for example, be singular or plural.

[0038] As can be seen from the cross-sectional view 500 of the Fig. 5, a first etch is performed into the BEVA dielectric layer 204 to form a BEVA opening 502 overlying and exposing the lower wire 114. In some embodiments, after completion of the first etch, the upper BEVA dielectric layer 204u has a pair of sloped sidewalls 204s in the BEVA opening 502 and on opposite sides of the BEVA opening 502, respectively, while the lower BEVA dielectric layer 204l has a pair of vertical or substantially vertical sidewalls 204v in the BEVA opening 502 and on opposite sides, respectively.

[0039] In some embodiments, a process for performing the first etch includes forming a photoresist mask 504 on the BEVA dielectric layer 204. The photoresist mask 504 may be formed, for example, by depositing a photoresist layer on the BEVA dielectric layer 204 and patterning the photoresist layer with a layout of the BEVA opening 502. The deposition may be performed, for example, by spin coating or another suitable deposition process, and / or the patterning may be performed, for example, by photolithography or another suitable patterning process. One or more first etchants are applied to the upper BEVA dielectric layer 204u until the lower BEVA dielectric layer 204l is reached by the first etchant(s) to partially form the BEVA opening 502.One or more second etchants are applied to the lower dielectric BEVA layer 204l through the partially formed BEVA opening 502 until the lower wire 114 is reached by the second etchant(s) to complete the formation of the BEVA opening 502. The photoresist mask 504 is then removed.

[0040] As can be seen from the cross-sectional view 600 of the Fig. 6, a BEVA liner layer 602 is formed covering the BEVA dielectric layer 204 and is further formed by lining the BEVA opening 502 (see Fig. 5) to partially fill the BEVA opening 502. In some embodiments, the BEVA lining layer 602 conformally lines the BEVA opening 502. The BEVA lining layer 602 is conductive and, in some embodiments, is homogeneous (e.g., made of a single material). The BEVA lining layer 602 may be or include, for example, titanium, titanium nitride, tantalum, tantalum nitride, other suitable conductive material(s), or any combination of the above. Further, the BEVA lining layer 602 may be formed, for example, by CVD, PVD, other suitable deposition process(es), or any combination of the above.

[0041] As can be seen from the cross-sectional view 600 of the Fig. 6, a layer of the lower BEVA body 604 is formed, covering the dielectric BEVA layer 204 and forming a remainder of the BEVA opening 502 (see Fig. 5) further fills over the BEVA lining layer 602. The lower BEVA body layer 604 is conductive and, in some embodiments, is homogeneous (e.g., made of a single material). Further, the lower BEVA body layer 604 is made of a different material than the BEVA lining layer 602, and in some embodiments, has a different hardness value than that of the BEVA lining layer 602. The lower BEVA body layer 604 may be or include, for example, copper, aluminum-copper, aluminum, tungsten, other suitable conductive material(s), or any combination of the above. In some embodiments, the BEVA liner layer 602 is or otherwise includes a barrier material for the lower BEVA body layer 604 to prevent material of the lower BEVA body layer 604 from migrating through the BEVA liner layer 602 to the surrounding structure.The layer of the lower BEVA body 604 may be formed, for example, by CVD, PVD, sputtering, electroless plating, electrochemical plating, other suitable coating or deposition process(es), or by any combination of the above.

[0042] As shown in cross-sectional view 700A of Fig. As illustrated in Figure 7A, a first planarization is performed into a top surface 604t of the lower BEVA body layer 604 to flatten or substantially flatten the top surface 604t and to recess the top surface 604t. Further, the first planarization stops before reaching the BEVA liner layer 602, such that the BEVA liner layer 602 remains completely covered by the lower BEVA body layer 604 upon completion of the first planarization. The first planarization may be performed, for example, by chemical mechanical polishing (CMP) or another suitable planarization process.

[0043] Alternatively, as shown in cross-sectional view 700B of the Fig. 7B, the first planarization stops on the BEVA liner layer 602, such that the BEVA liner layer 602 is exposed upon completion of the first planarization. Further, in some embodiments, the top surface 604t of the lower BEVA body layer 604 is vertically offset from a top surface 602t of the BEVA liner layer 602. The vertical offset may be due, for example, to different hardnesses between the lower BEVA body layer 604 and the BEVA liner layer 602. In particular, the different hardnesses may, for example, cause the lower BEVA body layer 604 and the BEVA liner layer 602 to be removed at different rates during the first planarization, thereby causing the vertical offset.

[0044] Alternatively, as shown in cross-sectional view 700B of the Fig. 7B, the first planarization stops on the BEVA liner layer 204, so that the BEVA liner layer 204 is exposed upon completion of the first planarization. Furthermore, the first planarization further deepens the top surface 602t of the BEVA liner layer 602. As shown in Fig. 7B, the upper surface 604t of the lower BEVA body layer 604 is vertically offset from the upper surface 602t of the BEVA lining layer 602, for example, due to different hardnesses between the lower BEVA body layer 604 and the BEVA lining layer 602.

[0045] As one can appreciate, the Fig. 7A to 7B show alternative embodiments of the same process step(s) (e.g., the first planarization). Therefore, in some embodiments, the method proceeds from Fig. 6 to Fig. 8 via any of the Fig. 7A to 7C. The procedure can be used, for example, by Fig. 6 to Fig. 8 over Fig. 7A. As another example, the procedure of Fig. 6 to Fig. 8 over Fig. 7B. As yet another example, the procedure of Fig. 6 to Fig. 8 over Fig. 7C. In some embodiments, the difference between the Fig. 7A to 7C the amount of semiconductor structure of the Fig. 6, which is removed by the first planarization. A first amount of the semiconductor structure of the Fig. 6 can be used for example Fig. 7A are removed, a second amount of the semiconductor substrate of the Fig. 6 can be Fig. 7B, and a third amount of the semiconductor substrate of the Fig. 6 can be Fig. 7C, wherein the third amount is greater than the second amount, which is greater than the first amount. In alternative embodiments, the method proceeds from the process step(s) of Fig. 6 to the process step(s) of the Fig. 8 without the process step(s) of Fig. 7A to 7C. In other words, the first planarization of the Fig. 7A to 7C may be omitted in alternative embodiments.

[0046] As can be seen from the cross-sectional view 800 of the Fig. 8, a second etching is performed into the layer of the lower BEVA body 604 (see Fig. 6, Fig. 7A, Fig. 7B or Fig. 7C) and the BEVA lining layer 602 (see Fig. 6, Fig. 7A, Fig. 7B or Fig. 7C) to etch back the lower BEVA body layer 604 and the BEVA lining layer 602. The second etch deepens the upper surface 604t of the lower BEVA body layer 604 (see Fig. 6, Fig. 7A, Fig. 7B or Fig. 7C) and the upper surface 602t of the BEVA lining layer 602 (see Fig. 6, Fig. 7A, Fig. 7B oder Fig. 7C) to locations spaced below a top surface 204t of the BEVA dielectric layer 204, thereby partially exposing the BEVA opening 502 and forming a BEVA liner 106l and a lower BEVA body 106lb. In some embodiments, the upper surface 602t of the BEVA liner layer 602 overlies the upper surface 604t of the lower BEVA body layer 604. In some embodiments, the upper surface 602t of the BEVA liner layer 602 is flush with the upper surface 604t of the lower BEVA body layer 604. In some embodiments, the upper surface 602t of the BEVA liner layer 602 underlies the upper surface 604t of the lower BEVA body layer 604. The BEVA liner 106l is formed from the BEVA liner layer 602, and the lower BEVA body 106lb is formed from the lower layer of the BEVA body 604.In some embodiments, the second etch also deepens the top surface 204t of the BEVA dielectric layer 204 (albeit at a slower rate than the bottom BEVA body layer 604 and the BEVA liner layer 602) to reduce a thickness T of the BEVA dielectric layer 204.

[0047] The second etch is performed using an etchant that preferentially etches the lower BEVA body layer 604 and the BEVA liner layer 602 with respect to the BEVA dielectric layer 204 such that the BEVA dielectric layer 204 is minimally etched. For example, the etchant may have a first etch rate for the lower BEVA body layer 604, a second etch rate for the BEVA liner layer 602, and a third etch rate for the BEVA dielectric layer 204, where the first and second etch rates are greater than the third etch rate. In some embodiments, the first and second etch rates are the same. In some embodiments, the first etch rate is greater than the second etch rate. In some embodiments, the first etch rate is less than the second etch rate.In some embodiments, the first etch rate(s) are between about 3 to 15 times greater than the second etch rate(s), between about 1 to 20 times greater than the second etch rate(s), between about 1 to 5 times greater than the second etch rate(s), between about 13 to 27 times greater than the second etch rate(s), or any other suitable relationship between the first and second etch rates. The second etch rate may be, for example, a wet etch or a dry etch. In some embodiments, the etchant of the second etch comprises hydrogen peroxide, other suitable chemical solution(s), or any combination of the above. In other embodiments, the etchant of the second etch comprises ions or other suitable dry etchant(s).

[0048] In some embodiments, the second etching is performed starting from any of the Fig. 7A to 7C. The second etching can be done, for example, by Fig. 7A. As another example, the second etching can be Fig. 7B. As yet another example, the second etching can be Fig. 7C. In some embodiments, depending on which of the Fig. 7A to 7C Fig. 8, the etching time for the second etching varies. Furthermore, in some embodiments, the etching time for the second etching is inversely proportional to the amount of semiconductor structure of the Fig. 6, which was the first planarization of the Fig. 7A to 7B. The second etching, for example, has a first etching time if it is Fig. 7A, a second etching time when it comes from Fig. 7B, and a third etching time when it comes from Fig. 7C, where the third etching time is shorter than the second etching time, which is shorter than the first etching time.

[0049] As can be seen from the cross-sectional view 900 of the Fig. 9, a layer of the upper BEVA body 902 is formed, covering the dielectric BEVA layer 204 and further forming a portion of the BEVA opening 502 (see Fig. 8) exposed by the second etch. The upper BEVA body layer 902 is conductive and homogeneous (e.g., made of a single material). In some embodiments, the upper BEVA body layer 902 is made of the same material as the lower BEVA body layer 106lb. In other embodiments, the upper BEVA body layer 902 is made of a different material than the lower BEVA body layer 106lb. The upper BEVA body layer 902 may, for example, be the same material as the BEVA liner 106l or another suitable barrier material for the lower BEVA body 106lb. The layer of the upper BEVA body 902 may be, for example, copper, aluminum-copper, aluminum, tungsten, other suitable metal(s), or other suitable conductive material(s).The layer of the upper BEVA body 902 may be formed, for example, by CVD, PVD, sputtering, electroless plating, electrochemical plating, other suitable coating or deposition process(es), or by any combination of the above.

[0050] As can be seen from the cross-sectional view 1000 of the Fig. 10, a second planarization is introduced into the layer of the upper BEVA body 902 (see Fig. 9) is performed until the dielectric BEVA layer 204 is reached to form an upper BEVA body 106ub from the layer of the upper BEVA body 902. The second planarization may be performed, for example, by chemical mechanical polishing (CMP) or another suitable planarization process. The upper BEVA body 106ub lies in the BEVA opening 502 (see Fig. 8) and overlies the lower BEVA body 106lb and the BEVA liner 106l. Furthermore, the upper BEVA body 106ub, the lower BEVA body 106lb, and the BEVA liner 106l collectively define a BEVA 106 in the BEVA opening 502, and the upper BEVA body 106ub individually defines an upper surface 106t of the BEVA 106.

[0051] The upper surface 106t of the BEVA 106 is homogeneous because the upper surface 106t is formed from the layer of the upper BEVA body 902 and because the layer of the upper BEVA body 902 is homogeneous. Similarly, the upper surface 106t of the BEVA 106 is flat or substantially flat because the upper surface 106t is formed from the layer of the upper BEVA body 902 and because the layer of the upper BEVA body 902 is homogeneous. In particular, because the layer of the upper BEVA body 902 is homogeneous, it has a substantially uniform hardness throughout and therefore a substantially uniform removal rate during the second planarization. The second planarization therefore uniformly or substantially uniformly removes material from the layer of the upper BEVA body 902 to make the upper surface 106t of the BEVA 106 flat or substantially flat.Because the top surface 106t of the BEVA 106 is flat or substantially flat, the electric field across a memory cell subsequently formed on the BEVA 106 is uniform or substantially uniform.

[0052] As can be seen from the cross-sectional view 1100 of the Fig. As illustrated in Figure 11, a bottom electrode layer 1102, a data storage layer 1104, and a top electrode layer 1106 are formed on the BEVA 106 and the BEVA dielectric layer 204. The bottom electrode layer 1102 is formed covering the BEVA dielectric layer 204 and the BEVA 106. The data storage layer 1104 is formed covering the bottom electrode layer 1102. The top electrode layer 1106 is formed covering the data storage layer 1104. The bottom and top electrode layers 1102, 1106 are conductive and may, for example, comprise metals, metal nitrides, or any other suitable conductive material(s). The data storage layer 1104 reversibly changes between a first data state (e.g., a first resistance) and a second data state (e.g., a second resistance) in response to a voltage applied across the data storage layer 1104.In some embodiments where the memory cell under manufacture is an RRAM cell, the data storage layer 1104 may be or include, for example, hafnium oxide, other suitable high-κ dielectric(s), or other suitable dielectric(s). In some embodiments where the memory cell under manufacture is an MRAM cell, the data storage layer 1104 may be or include, for example, an MTJ layer or other suitable magnetic storage structure. The MTJ may include, for example, a first ferromagnetic layer, an insulating layer overlying the first ferromagnetic layer, and a second ferromagnetic layer overlying the insulating layer.In some embodiments, the bottom and top electrode layers 1102, 1106 and the data storage layer 1104 are formed by CVD, PVD, electroless plating, electrochemical plating, sputtering, other suitable coating or deposition process(es), or any combination of the above.

[0053] As can be seen from the cross-sectional view 1200 of the Fig. 12, a hard mask layer 206 will cover a memory cell region of the top electrode layer 1106 (see Fig. 11) overlying the BEVA 106. The hard mask 206 may be or include, for example, silicon nitride, other suitable nitride(s), other suitable dielectric(s), or any combination of the above. The hard mask 200 may be formed, for example, by depositing a hard mask layer on the layer 1106 of the top electrode 1106 and by patterning the hard mask layer into the hard mask 206. The deposition may be performed, for example, by CVD, PVD, or other suitable deposition process, and / or the patterning may be performed, for example, by using a photolithography / etch process or other suitable patterning process.

[0054] As can be seen from the cross-sectional view 500 of the Fig. 12, a third etch is performed into the layer 1106 of the top electrode (see Fig. 11) with the hard mask 206 in place to form a top electrode 112 underlying the hard mask 206. In some embodiments, the data storage layer 1104 serves as an etch stop layer for the third etch and / or the third etch extends into the data storage layer 1104 to partially etch the data storage layer 1104.

[0055] As can be seen from the cross-sectional view 1300 of the Fig. 13, a spacer layer 1302 will define the structure of the Fig. 12. In some embodiments, the spacer layer 1302 is formed conformally and / or is formed by CVD, PVD, other suitable deposition process(es), or any combination of the above. For example, the spacer layer 1302 may be or include silicon nitride, other suitable nitride(s), other suitable dielectric(s), or any combination of the above.

[0056] As can be seen from the cross-sectional view 1400 of the Fig. 14, a fourth etch is performed into the spacer layer 1302 (see Fig. 13) is performed to etch back the spacer layer 1302 and form a spacer 208 from the spacer layer 1302. The spacer 208 comprises a pair of segments, each on opposite sidewalls of the top electrode 112. Further, in some embodiments, the segments each lie on opposite sidewalls of the hard mask 206, and / or the opposite sidewalls of the hard mask 206 are each flush with opposite sidewalls of the top electrode 112. In some embodiments, the spacer 208 extends laterally along sidewalls of the top electrode 112 in a closed path to completely enclose the top electrode 112. It should be noted that the cross-sectional view 1400 of the Fig. 14 is not visible. A process for performing the fourth etch may include, for example, applying one or more etching agents to the spacer layer 1302 to remove horizontal segments of the spacer layer 1302 without removing vertical segments of the spacer layer 1302, such that at least one of the vertical segments corresponds to the spacer 208.

[0057] As can be seen from the cross-sectional view 1500 of the Fig. 15, a fifth etch is performed in the data storage layer 1104 (see Fig. 14) and the layer 1102 of the bottom electrode (see Fig. 14) with the spacer 208 and the hard mask 206 in place to form a data storage element 110 and a bottom electrode 108. The data storage element 110 lies beneath the top electrode 112 and is formed from the data storage layer 1104. The bottom electrode 108 lies beneath the data storage element 110 and is formed from the bottom electrode layer 1102. A process for performing the fifth etch may, for example, include applying one or more etchants to the data storage layer 1104 and the bottom electrode layer 1102 until the BEVA dielectric layer 204 is reached by the etchant(s). The spacer 208 and the hard mask 206 together define a mask for the fifth etch, and the BEVA dielectric layer 204 serves as an etch stop layer.

[0058] As can be seen from the cross-sectional view 1600 of the Fig. As illustrated in Figure 16, a cap layer 210 is formed covering the BEVA dielectric layer 304, the spacer 208, and the hard mask 206. Further, the cap layer 210 is formed by lining sidewalls of the spacer 208, sidewalls of the data storage element 110, and sidewalls of the bottom electrode 108. The cap layer 210 may be or include, for example, silicon nitride, other suitable nitride(s), other suitable dielectric(s), or any combination of the above. In some embodiments, the spacer layer 210 is conformally formed and / or is formed by CVD, PVD, other suitable deposition process(es), or any combination of the above.

[0059] As can be seen from the cross-sectional view 1600 of the Fig. 16, a device ILD layer 212 covering the cap layer 210 is formed. Further, the device ILD layer 212 is formed with a top surface that is planar or substantially planar. The device ILD layer 212 may be or include, for example, silicon oxide, a low-kappa dielectric, other suitable dielectric(s), or any combination of the above. In some embodiments, a process for forming the device ILD layer 212 includes depositing the device ILD layer covering the cap layer 210 and then performing planarization into the top surface of the device ILD layer 212. The device ILD layer 212 may be deposited, for example, by CVD, PVD, sputtering, other suitable deposition process(es), or any combination of the above.Planarization can be performed, for example, by a CMP or other suitable planarization process.

[0060] As can be seen from the cross-sectional view 1700 of the Fig. 17, a sixth etch is performed into the device ILD layer 212, the cap layer 210, and the hard mask 206 to form a TEVA opening 1702 overlying and exposing the top electrode 112. In some embodiments, a process for performing the sixth etch includes forming a photoresist mask 1704 on the device ILD layer 212. The photoresist mask 1704 may be formed, for example, by depositing a photoresist layer on the device ILD layer 212 and patterning the photoresist layer with a layout of the TEVA opening 1702. The deposition may be performed, for example, by spin coating or another suitable deposition process, and / or the patterning may be performed, for example, by photolithography or another suitable patterning process.One or more etchants are then applied to the device ILD layer 212, the cap layer 210, and the hard mask 206 with the photoresist mask 1704 in place, and the photoresist mask 1704 is subsequently removed.

[0061] As can be seen from the cross-sectional view 1800 of the Fig. 18, a TEVA layer 1802 is formed covering the device ILD layer 212 and filling the TEVA opening 1702 (see Fig. 17). The TEVA layer 1802 includes a TEVA liner layer 1802l and a TEVA body layer 1802b. The TEVA liner layer 1802l covers the device ILD layer 212 and lines the TEVA opening 1702 to partially fill the TEVA opening 1702. In some embodiments, the TEVA liner layer 1802l conformally lines the TEVA opening 1702. The TEVA body layer 1802b covers the TEVA liner layer 1802l and fills a remainder of the TEVA opening 1702 above the TEVA liner layer 1802l. The TEVA lining layer 1802l is made of a material different from the TEVA body layer 1802b and has a hardness different from that of the TEVA body layer 1802b. Furthermore, the TEVA lining layer 1802l blocks material of the TEVA body layer 1802b from migrating to the surrounding structure.The TEVA body layer 1802b may be or comprise, for example, tungsten, copper, aluminum-copper, aluminum, other metal(s), or other suitable conductive material(s). The TEVA liner layer 1802l may be or comprise, for example, titanium, tantalum, titanium nitride, tantalum nitride, or another suitable barrier material for the TEVA body layer 1802b. The TEVA liner layer 1802l and the TEVA body layer 1802b may be formed, for example, by CVD, PVD, electroless plating, electrochemical plating, other suitable coating or deposition process(es), or any combination of the above.

[0062] As can be seen from the cross-sectional view of 1900 Fig. 19, a third planarization is formed into a top surface of the TEVA layer 1802 (see Fig. 18) which has a top side of the TEVA lining layer 1802l (see Fig. 18) and a top surface of the TEVA body layer 1802b (see Fig. 18) until the device ILD layer 212 is reached to form a TEVA 120 in the TEVA opening 1702 (see Fig. 17). The TEVA 120 includes a TEVA body 120b and a TEVA liner 120l. The TEVA body 120b is formed from the TEVA body layer 1802b, and the TEVA liner 120l is formed on the TEVA liner layer 1802l. Furthermore, the TEVA liner 120l sandwiches a bottom surface of the TEVA body 120b, thereby lining a bottom surface of the TEVA body 120b and sidewalls of the TEVA body 120b. The third planarization may be performed, for example, by a CMP or other suitable planarization process.

[0063] Because the TEVA 120 is formed from both the TEVA liner layer 1802l and the TEVA body layer 1802b, and because the TEVA liner layer 1802l and the TEVA body layer 1802b are different materials, the TEVA 120 is heterogeneous (e.g., composed of multiple materials) and has a heterogeneous top surface 120t. Furthermore, because the TEVA liner layer 1802l and the TEVA body layer 1802b are different materials, the TEVA liner layer 1802l and the TEVA body layer 1802b have different hardnesses and, consequently, different removal rates during the third planarization. The third planarization therefore unevenly removes material from the TEVA liner layer 1802l and the TEVA body layer 1802b. This, in turn, forms the TEVA 120 such that the top surface 120t of the TEVA 120 is rough or uneven.

[0064] As can be seen from the cross-sectional view 2000 of the Fig. As illustrated in Figure 20, a top ILD layer 214 and a top wire 118 are formed on the device ILD layer 212 and the TEVA 120. The top ILD layer 214 may be or include, for example, silicon nitride, silicon oxide, a low-kappa dielectric layer, other suitable dielectric(s), or any combination of the above. The top wire 118 is recessed into a bottom of the top ILD layer 214 such that a bottom surface of the top wire 118 is flat or substantially flat with a bottom surface of the top ILD layer 214. Further, the top wire 118 overlies and is electrically coupled to the TEVA 120. The upper wire 118 may be or comprise, for example, titanium nitride, tantalum, tantalum nitride, titanium, aluminum, aluminum-copper, copper, other suitable conductive material(s), or any combination of the above.In some embodiments, the upper wire 118 is heterogeneous (e.g., composed of multiple materials) and includes a top wire body 118b and a top wire liner 118l. The top wire body 118b may be or include, for example, copper, aluminum-copper, aluminum, or another suitable conductive material. The top wire liner 118l encloses a top wire body 118b and blocks material of the top wire body 118b from migrating to the surrounding structure. The top wire liner 118l may be, for example, titanium, tantalum, titanium nitride, tantalum nitride, or another suitable barrier material for the top wire body 118b.

[0065] In some embodiments where the data storage element 110 corresponds to an RRAM, a forming voltage is applied across the data storage element 110 from the bottom electrode 108 to the top electrode 112 to form one or more conductive threads (not shown) in the data storage element 110. Examples of the conductive threads are shown in Fig. 2 (see the conductive threads 110f in Fig. 2).

[0066] With reference to Fig. 21, is a flowchart 2100 of some embodiments of the method of Fig. 4 to 6, 7A to 7C, 8 to 20 provided.

[0067] At 2102, a dielectric BEVA layer covering a substrate is formed. See, for example, Fig. 4. The substrate includes a lower ILD layer and a lower wire. The lower wire is recessed into a top surface of a lower ILD layer 202 such that an upper surface of the lower wire is flat or substantially flat with an upper surface of the lower ILD layer. The lower ILD layer and the lower wire may, for example, be components of a BEOL conductive trace structure.

[0068] At 2104, a first etch is performed into the BEVA dielectric layer to form a BEVA opening overlying and exposing the bottom wire. See, for example, Fig. 5.

[0069] At 2106, a BEVA liner layer and a lower BEVA body layer are formed covering the dielectric BEVA layer and filling the BEVA opening. See, for example, Fig. 6. The BEVA lining layer lines the BEVA opening to partially fill the BEVA opening, and the lower layer of the BEVA body fills a remainder of the BEVA opening above the BEVA lining layer. The lower BEVA body layer is conductive and, in some embodiments, homogeneous. The BEVA lining is conductive and blocks material from the lower BEVA body layer from migrating (e.g., diffusing) out of the BEVA opening.

[0070] At 2108, an upper surface of the BEVA lining layer and an upper surface of the lower BEVA body layer are recessed to form a BEVA lining and a lower BEVA body in the BEVA opening and partially expose the BEVA opening. See, for example, Fig. 7A to 7C and 8. The recessing can be carried out, for example, by planarization followed by etching back.

[0071] At 2110, a BEVA body layer is formed, covering the BEVA dielectric layer and filling an exposed portion of the BEVA opening. See, for example, Fig. 9. The layer of the upper BEVA body is homogeneous.

[0072] At 2112, planarization is performed into the layer of the upper BEVA body until the dielectric BEVA layer is reached to form an upper BEVA body in the BEVA opening. See, for example, Fig. 10. The BEVA liner, the upper BEVA body, and the lower BEVA body define a BEVA with a top surface that is homogeneous and that is flat or substantially flat. The upper surface of the BEVA is flat or substantially flat because the top surface is formed from the layer of the upper BEVA body. In particular, because the layer of the upper BEVA body is homogeneous, the layer of the upper BEVA body is removed at a uniform or substantially uniform rate during planarization, forming the top surface of the BEVA flat or substantially flat. Because the top surface of the BEVA is flat or substantially flat, an electric field generated using the BEVA is uniform or substantially uniform.

[0073] At 2114, a memory cell is formed on the BEVA. See for example Fig. 11 to 15. The memory cell may be, for example, an RRAM cell, an MRAM cell, or another suitable memory cell type. In other embodiments, another type of electronic component is formed on the BEVA, such as a metal-insulator-metal (MIM) capacitor or another suitable type of electronic component.

[0074] At 2116, a device ILD layer is formed covering the memory cell and the BEVA dielectric layer. See, for example, Fig. 16.

[0075] At 2118, a TEVA is formed that extends through the device ILD layer to a top electrode of the memory cell. See, for example, Fig. 17 to 19

[0076] At 2120, a top ILD layer and a top wire are formed on the device ILD layer and the TEVA. See, for example, Fig. 20. The upper wire lies above the TEVA and is recessed into a bottom of the upper ILD layer such that a bottom surface of the upper wire is flush or substantially flush with a bottom surface of the upper ILD layer. The upper ILD layer and the upper wire can, for example, be components of a BEOL conductive pattern.

[0077] Although the flowchart 2100 of the Fig.21 is illustrated and described herein as a series of acts or events, it will be appreciated that the illustrated order of such acts or events is not to be construed in a limiting sense. For example, some acts may occur in different orders and / or concurrently with other acts or events separate from those illustrated and / or described herein. Further, not all of the illustrated acts may be required to practice one or more aspects or embodiments of the description, and one or more of the acts depicted herein may be performed at one or more separate acts and / or stages.

[0078] In some embodiments, therefore, the present application is directed to an integrated circuit comprising: a conductive wire; a dielectric via layer overlying the conductive wire; a via extending through the dielectric via layer to the conductive wire, the via comprising a conductive body and a conductive liner, the conductive liner including a bottom surface of the conductive body and a top surface recessed below a top surface of the via, the conductive body overhanging the top surface of the conductive liner and defining the top surface of the via, and a memory cell directly on the top surface of the via.In some embodiments, the top surface of the via extends continuously from a first sidewall of the via to a second sidewall of the via, wherein the first and second sidewalls of the via are on opposite sides of the via and directly contact the via dielectric layer. In some embodiments, the memory cell includes a bottom electrode, a data storage element overlying the bottom electrode, and a top electrode overlying the storage element, wherein a bottom surface of the bottom electrode directly contacts the top surface of the via and a top surface of the via dielectric layer.In some embodiments, the conductive liner is continuous and directly contacts sidewalls of the dielectric via layer and sidewalls of the conductive body, the conductive liner having a top surface recessed below the top surface of the conductive liner, and the conductive body directly contacts the top surface of the conductive liner and the top surface of the conductive liner. In some embodiments, the conductive liner directly contacts the conductive wire. In some embodiments, the conductive liner blocks diffusion of material from the conductive body to the dielectric via layer and the conductive wire.In some embodiments, the via dielectric layer comprises a lower dielectric layer and an upper dielectric layer overlying and directly contacting the lower dielectric layer, wherein a width of the via decreases continuously from the upper surface of the via to an intersection between the lower and upper dielectric layers, and wherein the width of the via is substantially uniform from the intersection to the conductive wire. In some embodiments, the upper surface of the via is homogeneous. In some embodiments, the conductive body comprises copper, wherein the conductive liner comprises titanium nitride, titanium, tantalum nitride, or tantalum.

[0079] In other embodiments, the present application relates to a method of forming an integrated circuit, the method comprising: performing an etch into a via dielectric layer to form an opening overlying and exposing a conductive wire underlying the via dielectric layer; forming a via liner layer covering the via dielectric layer and lining the opening, the via liner layer partially filling the opening; forming a bottom via body layer,which covers the dielectric via layer and fills a remainder of the opening above the via lining layer; recessing an upper surface of the lower via body layer and an upper surface of the via lining layer below an upper surface of the dielectric via layer to partially expose the opening, and forming a via lining and a lower via body in the opening; forming a layer of the upper via body covering the dielectric via layer and filling a portion of the opening exposed by the recessing, and performing planarization into the layer of the upper via body until the dielectric via layer is reached,to form an upper via body in the opening. In some embodiments, the lower via body, the upper via body, and the via liner together define a via in the opening, wherein the upper via body completely defines an upper surface of the via. In some embodiments, the upper via body layer is made of a single material. In some embodiments, recessing comprises: performing a second planarization into the upper surface of the lower via body layer, and performing a second etch into the upper surface of the lower via body layer and the upper surface of the via liner layer,to form a via liner and the lower via body. In some embodiments, the second planarization stops before reaching the via liner layer and the via dielectric layer, such that the via liner layer is covered by the lower via body layer outside the opening upon completion of the second planarization. In some embodiments, the second planarization stops on the via liner layer before reaching the via dielectric layer, such that the via liner layer is covered by the lower via body layer outside the opening upon completion of the second planarization. In some embodiments, the second planarization stops on the via dielectric layer,wherein the upper surface of the via lining layer is vertically offset from the upper surface of the lower via body layer upon completion of the second planarization. In some embodiments, the second etch is performed using an etchant that etches the lower via body layer and the via lining layer at a faster rate than the dielectric via layer. In some embodiments, the via lining layer contacts sidewalls of the dielectric via layer in the opening.wherein the layer of the lower via body directly contacts the via liner layer and is spaced from the dielectric via layer by the via liner layer. In some embodiments, the layer of the upper via body directly contacts sidewalls of the dielectric via layer, sidewalls of the via liner, a top surface of the via liner, and a top surface of the lower via body in the opening.

[0080] In other embodiments, the present application relates to another integrated circuit comprising: a conductive wire; a dielectric via layer overlying the conductive wire;a via extending through the dielectric via layer to the conductive wire, the via comprising a conductive body and a conductive liner, the conductive body comprising a pair of first sidewalls and a pair of second sidewalls, the first sidewalls being above the second sidewalls and each lying on opposite sides of the via, the second sidewalls each lying on opposite sides of the via, the conductive liner extending continuously from a bottom edge of one of the first sidewalls along the second sidewalls to a bottom edge of the other of the first sidewalls, and a memory cell directly on the via;

Claims

[1] Integrated circuit comprising: a conductive wire (114); a dielectric via layer (204) overlying the conductive wire (114); a via (106) extending through the dielectric via layer (204) to the conductive wire (114), the via (106) comprising a conductive body (106lb, 106ub) and a conductive liner (106l), the conductive liner (106l) enclosing a lower portion of the conductive body (106lb, 106ub) and having an upper surface that is recessed below an upper surface (106t) of the via (106), and the conductive body (106lb, 106ub) overhanging the upper surface of the conductive liner (106l) and defining the upper surface (106t) of the via (106), and a memory cell (102) directly on the upper surface of the via, wherein the via dielectric layer (204) comprises a lower dielectric layer (204l) and an upper dielectric layer (204u) directly contacting the lower dielectric layer (204l), the upper surface of the conductive liner (106l) being above the surface of the lower dielectric layer (204l). [2] The IC of claim 1, wherein the top surface (106t) of the via (106) extends continuously from a first sidewall of the via (106) to a second sidewall of the via (106), and wherein the first and second sidewalls of the via (106) are on opposite sides of the via (106) and directly contact the via dielectric layer (204). [3] The IC of claim 1 or 2, wherein the memory cell comprises a bottom electrode, a data storage element overlying the bottom electrode, and a top electrode overlying the data storage element, and wherein a bottom surface of the bottom electrode directly contacts the top surface of the via and a top surface of the via dielectric layer. [4] The IC of any preceding claim, wherein the conductive liner (106l) is continuous and directly contacts sidewalls of the dielectric via layer (204) and sidewalls of the conductive body (106lb, 106ub), the conductive liner (106l) having a top surface recessed below the top surface (106t) of the conductive body (106lb, 106ub), and the conductive body (106lb, 106ub) directly contacts the top surface of the conductive liner (106l). [5] The IC of any preceding claim, wherein the conductive liner (106l) directly contacts the conductive wire (114). [6] The IC of any preceding claim, wherein the conductive liner (106l) is configured to block diffusion of material from the conductive body (106lb, 106ub) to the dielectric via layer (204) and the conductive wire (114). [7] The IC of any preceding claim, wherein a width of the via decreases continuously from the top surface of the via to an intersection between the bottom and top dielectric layers, and wherein the width of the via is substantially uniform from the intersection to the conductive wire. [8] The IC of any preceding claim, wherein the upper surface (106t) of the via (106) is made of a single material. [9] The IC of any preceding claim, wherein the conductive body (106lb, 106ub) comprises copper, and wherein the conductive liner (106l) comprises titanium nitride, titanium, tantalum nitride, or tantalum. [10] A method of forming an integrated circuit, the method comprising: performing an etching into a dielectric via layer (204) to form an opening (502) overlying and exposing a conductive wire (114) underlying the dielectric layer (204) of a via (106), the dielectric via layer (204) comprising a lower dielectric layer (204l) and an upper dielectric layer (204u) directly contacting the lower dielectric layer (204l); Forming a via lining layer (602) covering the via dielectric layer (204) and lining the opening (502), the via lining layer (204) partially filling the opening (502); forming a layer of the lower via body (604) covering the dielectric via layer (204) and filling a remainder of the opening above the via liner layer (602); recessing an upper surface of the lower via body layer (604) and an upper surface of the via liner layer (602) below an upper surface of the dielectric via layer (204) to partially expose the opening (502) and to form a via liner (106l) and a lower via body (106lb) in the opening (502), the upper surface of the conductive liner (106l) being above the surface of the lower dielectric layer (204l); Forming a layer of the upper via body (902) covering the dielectric via layer (204) and filling a portion of the opening (502) exposed by the recess, and Performing planarization into the layer of the upper via body (902) until the dielectric via layer (204) is reached to form an upper via body (106ub) in the opening. [11] The method of claim 10, wherein the lower via body (106lb), the upper via body (106ub) and the via liner (106l) together define a via (106) in the opening (502), and wherein the upper via body (106ub) completely defines an upper surface (106t) of the via (106). [12] The method of claim 10 or 11, wherein the layer of the upper via body is made of a single material. [13] A method according to any one of claims 10 to 12, wherein the deepening comprises: Performing a second planarization into the upper surface (604t) of the layer of the lower via body (604), and Performing a second etch into the upper surface (604t) of the lower via body layer (604) and the upper surface (602t) of the via liner layer (602) to form a via liner (106l) and the lower via body (106lb). [14] The method of claim 13, wherein the second planarization stops before reaching the via liner layer and the via dielectric layer (204) such that the via liner layer (602) is covered by the layer of the lower via body (604) outside the opening (502) upon completion of the second planarization. [15] The method of claim 13, wherein the second planarization stops on the via liner layer (602) before reaching the via dielectric layer (204) such that the via liner layer (602) is not covered by the layer of the lower via body (604) outside the opening (502) upon completion of the second planarization. [16] The method of claim 13, wherein the second planarization stops on the via dielectric layer, and wherein the upper surface of the via liner layer is vertically offset from the upper surface of the lower via body layer upon completion of the second planarization. [17] The method of any one of the preceding claims 10 to 16, wherein the second etching is performed using an etchant that etches the lower via body layer (604) and the via liner layer (602) at a faster rate than the via dielectric layer (204). [18] The method of any one of the preceding claims 10 to 17, wherein the via lining layer (602) directly contacts sidewalls of the via dielectric layer (204) in the opening (502), and wherein the layer of the lower via body (604) directly contacts the via lining layer (602) and is spaced from the via dielectric layer (204) by the via lining layer (602). [19] The method of any one of the preceding claims 10 to 18, wherein the layer of the upper via body (902) directly contacts sidewalls of the dielectric via layer (204), sidewalls of the via liner (602), a top surface of the via liner (602t) and a top surface (604t) of the lower via body (106lb) in the opening. [20] Integrated circuit comprising: a conductive wire (114); a dielectric via layer (204) overlying the conductive wire (114); a via (106) extending through the dielectric via layer (204) to the conductive wire (114), the via (106) comprising a conductive body (106ub, 106lb) and a conductive liner (106l), the conductive body (106ub, 106lb) comprising a pair of first sidewalls and a pair of second sidewalls, the first sidewalls overlying the second sidewalls and being respectively on opposite sides of the via (106), the second sidewalls being respectively on opposite sides of the via (106), the second sidewalls being laterally between and laterally spaced from the first sidewalls, and the conductive liner (106l) extending continuously from a bottom edge of one of the first sidewalls along the second sidewalls to a bottom edge of another of the first sidewalls, and a memory cell (102) directly on the via (106), wherein the via dielectric layer (204) comprises a lower dielectric layer (204l) and an upper dielectric layer (204u) directly contacting the lower dielectric layer (204l), the upper surface of the conductive liner (106l) being above the surface of the lower dielectric layer (204l).

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