Selective boosting of power in memory channels based on a data pattern or physical non-uniformities

Abstract

Storage device (100) comprising: a plurality of NAND chains (300n-303n, 310n-313n, 320n-323n, 330n-333n, 412, 1640, 1641, 1642, 1643), each NAND chain having a set of series-connected memory cells among a set of memory cells and one or more select gate transistors at a drain end (390) of the NAND chain; a plurality of bit lines (BL0, BL1, BL2, BL3, 410, 1613b-1614b, 1616b-1617b), each bit line connected to the drain ends of one or more NAND chains of the plurality of NAND chains; a plurality of detection circuits (400, 400a, 400b, 400c, 1611, 1612), each detection circuit being connected to a respective bit line of the plurality of bit lines, each detection circuit comprising a bit line detection, BLC, transistor (404, 1613-1614, 1616-1617) with a source terminal (511, 1613s-1614s, 1616s-1617s) connected to the respective bit line, and by means of the detection circuits it is detectable whether a power current in the respective connected bit line is above or below a predetermined threshold level, wherein control gates (1613g-1614g, 1616g-1617g) of the BLC transistors (1613-1614, 1616-1617) are connected to a common voltage source (1648); wherein the BLC transistors comprise a first set and a second set of BLC transistors, wherein the first set of BLC transistors (1615) includes the BLC transistors (404, 1613-1614) of detection circuits (1611) connected to bit lines connected to the drain ends of a first set of NAND chains (1640, 1641), wherein the second set of BLC transistors (1619) includes the BLC transistors (404, 1616-1617) of detection circuits connected to bit lines connected to the drain ends of a second set of NAND chains (1642, 1643), and wherein the first set of BLC transistors (1615) has a higher threshold voltage than the second set of BLC transistors (1619).

Description

background

[0001] The present technology relates to the operation of storage devices.

[0002] Semiconductor memory devices have become increasingly popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in mobile phones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and other devices.

[0003] A charge-storage material, such as a floating gate or a charge-trapping material, can be used in such memory devices to store a charge representing a data state. A charge-trapping material can be arranged vertically in a three-dimensional (3D) stacked memory structure or horizontally in a two-dimensional (2D) memory structure. An example of a 3D memory structure is the Bit-Cost-Scalable (BiSC) architecture, which features a stack of alternating conductive and dielectric layers.

[0004] A memory device comprises memory cells that can be arranged in chains, for example, where select gate transistors are provided at the ends of the chain to selectively connect a channel of the chain to a source line or bit line. Furthermore, sensing circuits can be connected to the bit lines to detect a current in the chains. However, various challenges are presented when operating such memory devices.

[0005] US 2014 / 0 254 268 A1 discloses a plurality of memory chains, each chain comprising a set of series-connected memory cells among a set of memory cells, a plurality of select gate transistors having a source terminal connected to a respective memory chain of the plurality of memory chains, control gates of the select gate transistors being connected to a common voltage source, the select gate transistors comprising a first set of select gate transistors connected to a first set of memory chains and a second set of select gate transistors connected to a second set of memory chains, and the first set of select gate transistors having a higher threshold voltage than the second set of select gate transistors. US 2017 / 0 185 463 A1 relates to an operating method for a memory system having a plurality of memory blocks.US 2006 / 0 221 692 A1 relates to the compensation of coupling effects between charges stored in neighboring memory cells. US 2010 / 0 131 697 A1 relates to methods for grouping blocks in memory devices. US 2010 / 0 332 729 A1 relates to methods for performing memory access operations based on a memory location. Short description of the drawings

[0006] Like-numbered elements refer to common components in the different figures. Fig. 1A is a block diagram of an example memory device. Fig. 1B illustrates an example of the temperature sensing circuit 115 Fig. 1A. Fig. Figure 2 is a block diagram illustrating an embodiment of a detection block 51-53 of Fig. 1A represents. Fig. Figure 3 shows a configuration of a NAND chain and components for sensing. Fig. 4 illustrates current detection based on a change in voltage in an example implementation of the current detection module 402 in Fig. 3. Fig. 5 illustrates an example implementation of the BLC transistor 404 Fig. 3. Fig. 6 is a perspective view of a memory device 600 showing a set of blocks in a plane in an example 3D configuration of the memory structure 126 of Fig. 1. Fig. 7A illustrates an example cross-sectional view of a portion of one of the blocks Fig. 6. Fig. 7B illustrates an example transistor 500. Fig. Figure 8 shows a close-up view of the area 622 of the stack Fig. 7A. Fig. 9A illustrates an example implementation of the memory structure 126 Fig. 1A, which has NAND chains in sub-blocks in a 3D configuration. Fig. Figure 9B illustrates a perspective view of sub-blocks SB0-SB3 consistent with Fig. 9A is. Fig. Figure 10A illustrates an initial threshold distribution of an example two-pass programming operation involving four data states. Fig. Figure 10B illustrates a threshold distribution resulting from a first pass of the example two-pass programming operation Fig. 10A results. Fig. Figure 10C shows a threshold distribution resulting from a second pass of the example two-pass programming operation Fig. 10A results. Fig. Figure 11A illustrates an initial threshold distribution of an example two-pass programming operation involving eight data states. Fig. Figure 11B illustrates a threshold distribution resulting from a first pass of the example two-pass programming operation Fig. 11A results. Fig. Figure 11C shows a threshold distribution resulting from a second pass of the example two-pass programming operation Fig. 11A results. Fig. Figure 12 illustrates a series of program verification iterations in an example of programming passing for a lower data page, consistent with Fig. 10B and Fig. 11B. Fig. Figure 13 illustrates a series of program verification iterations in an example of programming passing for an upper data page, consistent with Fig. 10C. Fig. Figure 14 shows a graphical representation of example waveforms in a read operation. Fig. Figure 15A illustrates an example process for programming memory cells. Fig. Figure 15B illustrates another example process for programming memory cells. Fig. Figure 15C illustrates an example process for reading memory cells. Fig. 16A illustrates an example block of memory cells having a user data area and a metadata area. Fig. 16B illustrates memory chains and respective BLC transistors in the example block of memory cells Fig. 16A. Fig. Figure 16C illustrates an example column of a memory chain with a channel layer having a relatively small width. Fig. Figure 16D illustrates an example column of a memory chain with a channel layer having a relatively large width. Fig. 17A shows an example of the metadata area Fig. 16A, where the cells are all in the erased (1) state. Fig. Figure 17B shows an example of the metadata area Fig. 16A, where the cells are all in the programmed state (0). Fig. 17C shows an example of the metadata area Fig. 16A, where bytes of erased state data and programmed state data alternate in consecutive rows. Fig. 18 illustrates a set of memory chains in a block, where the channel widths of the memory chains vary according to a repeating pattern due to non-uniformities in the manufacturing process. Fig. Figure 19A illustrates an example process for identifying memory chains that are likely to have memory cells in a high state. Fig. Figure 19B illustrates an example process for identifying memory chains that are likely to experience low current during a read operation. Fig. Figure 19C illustrates an example process for programming a set of memory cells while clamping a bit line voltage. Detailed description

[0007] According to the invention, a memory device and a method having the features of the independent claims are provided; dependent claims relate to preferred embodiments.

[0008] A memory device is provided in which current in channels of memory chains is boosted based on a data pattern or physical non-uniformities such as non-uniform channel widths of the memory chains.

[0009] In some memory devices, memory cells are connected to each other, such as in NAND strings within a block or sub-block. Each NAND string comprises a number of memory cells connected in series between one or more drain-side SG transistors (SGD transistors) on a drain side of the NAND string, which is connected to a bit line, and one or more source-side SG transistors (SGS transistors) on a source side of the NAND string, which is connected to a source line. Furthermore, the memory cells may be arranged with a common control gate line (e.g., word line) acting as a control gate. A set of word lines extends from the source side of a block to the drain side of a block. Memory cells can be connected in other types of strings and in other ways as well.

[0010] In a 3D memory structure, the memory cells can be arranged in vertical chains in a stack, with the stack comprising alternating conductive and dielectric layers. The conductive layers act as word lines connected to the memory cells. The memory chains extend into storage holes formed in the stack.

[0011] The memory cells may include data memory cells suitable for storing user data and dummy or non-data memory cells unsuitable for storing user data. A dummy word line is connected to a dummy memory cell. One or more dummy memory cells may be provided at the drain and / or source ends of a chain of memory cells to provide a gradual transition in the channel voltage gradient.

[0012] During a programming operation, the memory cells are programmed according to a wordline programming sequence. For example, programming may begin at the wordline on the source side of the block and continue to the wordline on the drain side of the block. In one approach, a wordline is fully programmed before a next wordline is programmed. For example, a first wordline WL0 is programmed using one or more program pass operations until programming is complete. Next, a second wordline WL1 is programmed using one or more program pass operations until programming is complete, and so on. A program pass operation may comprise a set of increasing programming voltages applied to the wordline in respective program loops or program verification iterations.Verification operations can be performed after each programming voltage to determine whether the memory cells have completed programming. When programming is completed for a memory cell, it can be excluded from further programming while programming for other memory cells continues in subsequent program loops.

[0013] The memory cells may also be programmed according to a sub-block sequence, where memory cells in one sub-block or a section of a block are programmed before memory cells in another sub-block are programmed.

[0014] Each memory cell can be associated with a data state according to write data in a programming command. Based on its data state, a memory cell will either remain in the erased state or be programmed to a programmed data state. For example, in a one-bit-per-cell memory device, there are two data states, including the erased state and the programmed state. In a two-bit-per-cell memory device, there are four data states and three higher data states, referred to as the A, B, and C data states (see Fig. 10C). In a three-bit-per-cell memory device, there are eight data states including the erased state Er and seven higher data states known as the BG states (see Fig. 11B). In a four-bit-per-cell memory device, there are sixteen data states, including the erased state and fifteen higher data states.

[0015] After the memory cells are programmed, the data can be read back in a read operation. A read operation may involve applying a series of read voltages to a word line while the detection circuit determines whether cells connected to the word line are in a conducting or non-conducting state. When a cell is in a non-conducting state, the threshold voltage (Vth) of the memory cell exceeds the read voltage. The read voltages are set at levels expected to be between the threshold voltage levels of adjacent data states.

[0016] However, during sensing operations, which include read and verify operations, it is difficult to sense low currents in the memory chains. For example, in a 3D memory structure, there is a trend to stack more layers together to improve the density of the memory device. However, this increases the height of the device and therefore the length and resistance of the channel. This results in a lower current in the channel during sensing operations, making sensing more difficult. The sensing threshold current, which is the minimum current representing a cell in a conducting state, is forced to become lower, making the sensing operation more susceptible to various types of sensing noise and, as a result, reducing sensing accuracy. Furthermore, the sensing time is increased because a longer time is needed to stabilize the sensing and minimize sensing noise.This increases the time for a read or verification / programming operation.

[0017] It is desirable to maintain the channel current and threshold sense current at a relatively high level to avoid increasing the duration of sense operations. Increasing the bitline bias during read / verify sense is one way to increase the channel current during a sense operation. However, this increases power consumption. Maintaining a sufficiently high channel current across all memory channels during read / verify operations for higher read / program speeds while minimizing power consumption has become a challenge in boosting overall memory performance.

[0018] The techniques provided herein address the above and other issues. The techniques maintain sufficient channel current in all memory chains during acquisition operations while minimizing power consumption. Over time, noise and accuracy are improved.

[0019] The techniques recognize that the sensing process is limited by channels with the lowest current among all the memory chains being sensed. The techniques maintain a sensing threshold level and sensing speed by improving the channel current in the memory chains most likely to have low current during sensing in the absence of the corrective measures provided herein. In some cases, the low-current memory chains are found at certain fixed physical locations in a block. For example, on each word line, there may be certain byte locations used to store metadata. The metadata may be used, for example, to provide information about the programming condition of data in a user data area of ​​the word line, such asThe program-erase cycle hot count, a program time stamp indicating the time of the last wordline programming, the program temperature indicating the temperature at the time of the last wordline programming, a low-page program flag indicating whether a low page has been programmed into the wordline, and so on. When this metadata is programmed, often the memory cells at the same position on many wordlines of the block will be programmed to the same data state (same Vth level). If that data state is relatively high, the channel current on those memory chains can be quite low, which can reduce performance in terms of acquisition time, noise, and accuracy.

[0020] If a small number of memory chains are likely to have particularly low channel current, a higher bitline bias voltage may be provided during sensing of those memory chains. The sensing circuitry may include a bitline lock (BLC) transistor that sets a voltage on the bitline during sensing. The BLC transistors of the sensing circuitry of a block typically have their control gates connected to each other and to a common voltage source. Accordingly, it is not possible to increase the bitline bias voltage for the low current chains without affecting the remaining chains. One solution is to selectively provide a higher bitline bias voltage for the low current chains. It is proposed that the BLC transistors for the low current chains be fabricated with a lower Vth.In this way, a higher bitline bias is applied to the low current chains, increasing the current, while a normal bitline bias can still be used for the majority of the memory chains to keep power consumption low. A lower Vth of a BLC transistor can be realized, for example, by modifying the physical configuration of the transistor as discussed herein.

[0021] In one aspect, a set of memory chains is connected to respective sensing circuits. A first set of the memory chains includes metadata, which may be non-random. In some cases, the metadata includes cells that are typically in a highly programmed data state. Memory chains with these high state cells will have a relatively low current during sensing operations. To compensate, the sensing circuits for the second set of memory chains may be different than the sensing circuits for the first set of memory chains. In one approach, the sensing circuits for the second set of memory chains include a bitline capturing transistor having a lower threshold voltage compared to the sensing circuits for the first set of memory chains. The lower threshold voltage may be achieved in various ways, such asby at least one of a shorter control gate length, a smaller oxide thickness, a lower oxide dielectric constant, or a larger source and / or drain doping concentration or ion implantation energy / portion. Therefore, the sensing circuits and the bitline lock transistors can be configured according to an expected data pattern in the associated strings of memory cells.

[0022] The lower threshold voltage allows for a higher voltage on the bitline when the bitline lock transistor is configured as a source-follower transistor. That is, the source voltage is approximately equal to the gate voltage minus the threshold voltage.

[0023] In another aspect, memory chains, which are typically expected to store high-state data, are fabricated with a relatively thicker channel and / or higher doping concentration. Therefore, the channel thickness and / or doping concentration is based on an expected data pattern in the associated chains of memory cells. A thicker channel and a higher doping concentration result in a larger current during sensing.

[0024] In another aspect, there is a repeated pattern in the thickness of the channel widths of the memory chains due to non-uniformity in the manufacturing process. The bitline lock transistors can be configured according to the pattern, so that chains with a relatively narrow channel have a relatively lower threshold voltage.

[0025] In another aspect, the location of the high state data in different word lines is varied and alternated with low state data to avoid an excessive number of high state cells and thereby increase the memory chain current.

[0026] The above and other features are discussed herein.

[0027] Fig. 1A is a block diagram of an example memory device. The memory device 100, such as a non-volatile memory system, may include one or more memory chips 108. The memory chip 108 includes a memory structure 126 of memory cells, such as an array of memory cells, a control circuit 110, and read / write circuitry 128. The memory structure 126 is addressable by word lines via a row decoder 124 and by bit lines via a column decoder 132. The read / write circuitry 128 includes a plurality of sense blocks 51, 52, ..., 53 (sense circuitry) and allows a page of memory cells to be read or programmed in parallel. Typically, a control unit 122 is present in the same memory device 100 (e.g., a removable memory card) as the one or more memory chips 108. The control unit may be separate from the memory chips.Commands and data are transferred between the host 140 and the control unit 122 via a data bus 122 and between the control unit and the one or more memory chips 108 via lines 118.

[0028] The memory structure may be 2D or 3D. The memory structure may comprise one or more arrays of memory cells, including a 3D array. The memory structure may comprise a monolithic 3D memory structure in which multiple memory levels are formed above (rather than within) a single substrate, such as a wafer with no intervening substrates. The memory structure may comprise any type of non-volatile memory monolithically formed in one or more physical levels of arrays of memory cells with an active area disposed above a silicon substrate. The memory structure may be present in a non-volatile memory device with circuitry associated with the operation of the memory cells, whether the associated circuitry is above or within the substrate.

[0029] The control circuit 110 cooperates with the read / write circuits 128 to perform memory operations on the memory structure 126 and includes a state machine 112, an on-chip address decoder 114, a temperature sensing circuit 115, and a power control module 116. The state machine 112 provides chip-level control of memory operations. A memory area 113 may be provided, e.g., for operating parameters and software / code. In one embodiment, the state machine is programmable by software. In other embodiments, the state machine uses no software and is implemented entirely in hardware (e.g., electrical circuits).

[0030] The on-chip address decoder 114 provides an address interface between that used by the host or a memory controller and the hardware address used by decoders 124 and 132. A controller may be circuitry configured to vary a position of a subset of memory cells assigned to metadata in different wordlines of a set of wordlines when a temperature is below a threshold. See, for example, Fig. 17C. See Fig. 1B for further details of a temperature sensing circuit.

[0031] The power control module 116 controls the power and voltages supplied to the word lines, select gate lines, bit lines, and source lines during memory operations. It may include drivers for word lines, SGS and SGD transistors, and source lines. The sense blocks may include bit line drivers in one port. An SGS transistor is a select gate transistor at a source end or source side of a NAND string, and an SGD transistor is a select gate transistor at a drain end or drain side of a NAND string.

[0032] In some implementations, some of the components may be combined. In various designations, one or more of the components (alone or in combination), other than memory structure 126, may be considered to be at least one control circuit configured to perform the techniques described herein, including the steps of the processes described herein. For example, a control circuit may include any one or a combination of control circuit 110, state machine 112, decoders 114 and 132, power control module 116, sense blocks 51, 52, ..., 53, read / write circuits 128, control unit 122, and so on.

[0033] The off-chip control unit 122 (which in one embodiment is an electrical circuit) may include a processor 122c, storage devices (memory) such as ROM 122a and RAM 122b, and an error correction code (ECC) engine 245. The ECC engine may correct a number of read errors.

[0034] A memory interface 122d may also be provided. The memory interface, in communication with ROM, RAM, and the processor, is an electrical circuit that provides an electrical interface between the control unit and the memory chip. For example, the memory interface can change the format or timing of signals, provide a buffer, isolate from jerk, latch I / O, and so on. The processor can issue commands to the control circuit 110 (or any other component of the memory chips) via the memory interface 122d.

[0035] The memory device includes code, such as a set of instructions, and the processor is operable to execute the set of instructions to provide the functionality described herein. Alternatively or additionally, the processor may access code from a storage device 126a of the memory structure, such as a reserved area of ​​memory cells in one or more word lines.

[0036] For example, code may be provided by the control unit to access the memory structure, such as for program, read, and erase operations. The code may include boot code and control code (e.g., a set of instructions). The boot code is software that initializes the control unit during a boot or power-up process and allows the control unit to access the memory structure. The code may be used by the control unit to control one or more memory structures. Upon power-up, the processor 122c retrieves the boot code from the ROM 122a or the storage device 126a for execution, and the boot code initializes the system components and loads the control code into the RAM 122b. Once the control code is loaded into the RAM, it is executed by the processor. The control code includes drivers to perform basic tasks such as:Controlling and allocating memory, prioritizing instruction processing, and controlling input and output ports.

[0037] Generally, the control code may include instructions for performing the functions described herein, including the steps of the flowcharts discussed below, and for providing the voltage waveforms, including those discussed below. A control circuit may be configured to execute the instructions to perform the functions described herein.

[0038] In one embodiment, the host is a computing device (e.g., laptop, desktop, smartphone, tablet, digital camera) having one or more processors, one or more processor-readable storage devices (RAM, ROM, flash memory, hard disk drive, solid-state storage) storing processor-readable code (e.g., software) for programming the one or more processors to perform the methods described herein. The host may also include additional system memory, one or more input / output interfaces, and / or one or more input / output devices in communication with the one or more processors.

[0039] Other types of non-volatile memory in addition to NAND flash memory can also be used.

[0040] Semiconductor memory devices include volatile memory devices such as dynamic random access memory (DRAM) or static random access memory (SRAM) devices, non-volatile memory devices such as resistive random access memory (ReRAM), electrically erasable programmable read-only memory (EEPROM), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory (FRAM), and magnetoresistive random access memory (MRAM), and other semiconductor elements capable of storing information. Each type of memory device can have different configurations. For example, flash memory devices can be configured in a NAND or a NOR configuration.

[0041] The memory devices can be formed from passive and / or active elements in any combination. As a non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include a resistive switching memory element such as an anti-fuse or phase-change material, and optionally a guiding element such as a diode or transistor. Furthermore, as a non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements containing a charge storage region, such as a floating gate, conductive nanoparticles, or a charge storage dielectric material.

[0042] Multiple storage elements can be configured to be connected in series or so that each element can be accessed individually. As a non-limiting example, flash memory devices in a NAND configuration (NAND memory) typically include storage elements connected in series. A NAND chain is an example of a set of series-connected transistors comprising memory cells and SG transistors.

[0043] A NAND memory array can be configured so that the array is composed of multiple chains of memory, where each chain consists of multiple memory elements sharing a single bit line and accessed as a group. Alternatively, memory elements can be configured so that each element can be accessed individually, e.g., a NOR memory array. NAND and NOR memory configurations are examples, and memory elements can be configured in other ways.

[0044] The semiconductor memory elements arranged within and / or above a substrate can be arranged in two or three dimensions, such as a 2D memory structure or a 3D memory structure.

[0045] In a 2D memory structure, the semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in a 2D memory structure, memory elements are arranged in a plane (e.g., an xy-direction plane) that extends substantially parallel to a major surface of a substrate that supports the memory elements. The substrate may be a wafer over or in which the layer of memory elements is formed, or it may be a carrier substrate that is attached to the memory elements after they are formed. As a non-limiting example, the substrate may comprise a semiconductor such as silicon.

[0046] The memory elements can be arranged in an ordered array, such as a plurality of rows and / or columns, within the individual memory device level. However, the memory elements can be arranged in non-regular or non-orthogonal configurations. The memory elements can each have two or more electrodes or contact lines, such as bit lines and word lines.

[0047] A 3D memory array is arranged so that memory elements occupy multiple planes or multiple memory device levels, thereby forming a structure in three dimensions (i.e., in the x, y, and z directions, with the z direction being substantially perpendicular and the x and y directions being substantially parallel to the main surface of the substrate).

[0048] As one non-limiting example, a 3D memory structure may be arranged vertically as a stack of multiple 2D memory device levels. As another non-limiting example, a 3D memory array may be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the main surface of the substrate, i.e., in the y-direction), each column having multiple memory elements. The columns may be arranged in a 2D configuration, e.g., an xy-plane, resulting in a 3D array of memory elements, with elements on multiple vertically stacked memory levels. Other configurations of memory elements in three dimensions may also constitute a 3D memory array.

[0049] As a non-limiting example, in a 3D NAND memory array, the storage elements can be coupled together to form a NAND chain within a single horizontal (e.g., xy) memory device level. Alternatively, the storage elements can be coupled together to form a vertical NAND chain spanning multiple horizontal memory device levels. Other 3D configurations can be envisioned, with some NAND chains containing storage elements within a single memory level, while other chains containing storage elements spanning multiple memory levels. 3D memory arrays can also be designed in a NOR configuration and in a ReRAM configuration.

[0050] Typically, in a monolithic 3D memory array, one or more memory device levels are formed above a single substrate. Optionally, the monolithic 3D memory array may also include one or more memory layers at least partially within the single substrate. As a non-limiting example, the substrate may comprise a semiconductor such as silicon. In a monolithic 3D array, the layers constituting each memory device level of the array are typically formed on top of the layers of the underlying memory device levels of the array. However, layers of adjacent memory device levels of a monolithic 3D memory array may be shared or have intermediate layers between memory device levels.

[0051] 2D arrays can be formed separately and then packaged together to form a non-monolithic memory structure with multiple memory layers. For example, non-monolithic stacked memories can be constructed by forming memory levels on separate substrates and then stacking the memory levels on top of each other. The substrates can be thinned or removed from the memory levels before stacking, but because the memory device levels are originally formed over separate substrates, the resulting memory arrays are not monolithic 3D memory arrays. Furthermore, multiple 2D memory arrays or 3D memory arrays (monolithic or non-monolithic) can be formed on separate chips and then packaged together to form a stacked-chip memory device.

[0052] Associated circuitry is typically required for the operation of the memory elements and for communication with the memory elements. As non-limiting examples, memory devices may include circuitry used to control and drive memory elements to achieve functions such as programming and reading. This associated circuitry may be present on the same substrate as the memory elements and / or on a separate substrate. For example, a controller for memory read / write operations may be located on a separate controller chip and / or on the same substrate as the memory elements.

[0053] One of ordinary skill in the art will appreciate that this technology is not limited to the example 2D and 3D structures described, but covers all relevant memory structures within the spirit and scope of the technology as described herein and as understood by one of ordinary skill in the art.

[0054] Fig. 1B illustrates an example of the temperature sensing circuit 115 Fig. 1A. The circuit includes pMOSFETs 131a, 131b, and 134, bipolar transistors 133a and 133b, and resistors R1, R2, and R3. I1, I2, and I3 denote currents. Voutput is a temperature-based output voltage provided by an analog-to-digital (ADC) converter 129. Vbg is a temperature-independent voltage. A voltage level generation circuit 135 uses Vbg to set a number of voltage levels. For example, a reference voltage can be divided down into multiple levels by a resistor divider circuit.

[0055] The ADV compares Voutput with the voltage levels and selects the closest match among the voltage levels, outputting a corresponding digital value (VTemp) to the processor. This is data indicating the temperature of the memory device. The ROM merges 123 memory data that correlates the matched voltage level with a temperature in one input. The processor then uses the temperature to adjust temperature-based parameters in the memory device.

[0056] Vbg is obtained by adding the base-emitter voltage (Vbe) across transistor 131b and the voltage drop across resistor R2. Bipolar transistor 133a has a larger area (by a factor of N) than transistor 133b. PMOS transistors 131a and 131b are equal in size and are arranged in a current mirror configuration, so the currents I1 and I2 are essentially equal. We have Vbg=Vbe+R2×I2 and I1=Ve / R1, so I2=Ve / R1. As a result, Vbg=Vbe+R2×kt In(N) / R1×q, where T is the temperature, k is the Boltzmann constant, and y is a unit of electric charge. The source of transistor 134 is connected to a supply voltage Vdd and the node between the drain of the transistor and the resistor R3 is the output voltage Voutput.The gate of transistor 134 is connected to the same terminal as the gates of transistors 131a and 131b, and the current through transistor 134 mirrors the current through transistors 131a and 131b.

[0057] Fig. Figure 2 is a block diagram illustrating an embodiment of a detection block 51-53 of Fig. 1A. An individual sense block 51 is partitioned into one or more core sections, referred to as sense modules 180 or sense amplifiers, and a common section, referred to as management circuitry 190. In one embodiment, there will be a separate sense module 180 for each bit line and a common management circuitry 190 for a set of multiple, e.g., four or eight, sense modules 180. Each of the sense modules in a group communicates with the associated management circuitry via a data bus 172. Therefore, there will be one or more management circuits that communicate with the sense modules of a set of memory elements.

[0058] The detection module 180 includes a detection circuit 170 that performs the detection by determining whether a power current in a connected bitline is above or below a predetermined threshold level. The detection module 180 also includes a bitline latch 182 used to set a voltage condition on the connected bitline. For example, a predetermined condition latched in the bitline latch 182 will result in the connected bitline being pulled to a state-determining program inhibit (e.g., 1.5-3V). As an example, a flag=0 may disable programming, while a flag=1 does not disable programming.

[0059] The management circuit 190 includes a processor 192, four example sets of data latches 194-197, and an I / O interface 196 coupled between the set of data latches 194 and the data bus 120. One set of data latches may be provided for each capture module, and data latches identified by LDL and UDL may be provided for each set. In some cases, additional data latches may be used. LDL stores one bit for a lower data page, and UDL stores one bit for an upper data page. This is in a four-level or two-bits-per-storage-element memory device. One additional data latch per bit line may be provided for each additional data bit per storage unit.

[0060] Processor 192 performs calculations such as determining the data in the sensed memory element and storing the determined data in the set of data latches. Each set of data latches 194-197 is used to store data bits determined by processor 192 during a read operation and to store data bits imported from data bus 120 during a program operation, which represents write data intended to be programmed into memory. I / O interface 196 provides an interface between data latches 194-197 and data bus 120.

[0061] During reading, the system's operation is under the control of state machine 112, which controls the supply of various control gate voltages to the addressed memory element. As it steps through the various predefined control gate voltages corresponding to the various memory states supported by the memory, the capture module 180 may trip at one of these voltages, and a corresponding output is provided from the capture module 180 to the processor 192 via bus 182. At that point, the processor 192 determines the resulting memory state by considering the capture module's trip event(s) and the applied control gate voltage information from the state machine via input lines 193. It then computes a binary encoding for the memory state and stores the resulting data bits in data latches 194-197.In another embodiment of the management circuit 190, the bitline latch 182 serves dual duty as both a latch for latching the output of the sense module 180 and as a bitline latch as described above.

[0062] Some implementations may include multiple processors 192. In one embodiment, each processor 192 will have an output line (not shown) such that each of the output lines is connected together to a wired-OR line. In some embodiments, the output lines are inverted before being connected to the wired-OR line. This configuration allows for quick determination during the programming verification process of when the programming process has been completed, whereby the state machine receiving the wired-OR can determine when all of the bits being programmed have reached the desired level. For example, when each bit has reached its desired level, a logical zero for the bit is sent to the wired-OR line (or a data one is inverted).If all of the bits output a data 0 (or a data 1 that is inverted), the state machine can terminate the programming process. Because each processor communicates with eight acquisition modules, the state machine requires the wired-OR line to be read eight times, or logic is added to processor 192 to accumulate the results of the associated bit lines so that the state machine only needs to read the wired-OR line once. Similarly, by correctly selecting the logic levels, the global state machine can detect when the first bit changes state and modify the algorithms accordingly.

[0063] During programming or verification operations, the data to be programmed (write data) is stored in the set of data latches 194-197 from the data bus 120 in the LDL and UDL latches in a two-bit-per-storage element implementation. In a three-bit-per-storage element implementation, an additional data latch may be used. The programming operation, under the control of the state machine, includes a series of programming voltage pulses applied to the control gates of the addressed storage elements. Each programming pulse is followed by a readback (verify) to determine whether the storage element has been programmed to the desired storage state. In some cases, the processor 192 observes the readback storage state relative to the desired storage state.If the two match, processor 192 sets bitline latch 182 to cause the bitline to be pulled to a state indicating a program lock. This locks the memory element coupled to the bitline from further programming, even if programming pulses appear on its control gate. In other embodiments, the processor initially loads bitline latch 182, and the detection circuitry sets it to a lock value during the verification process.

[0064] Each set of data latches 194-197 can be implemented as a stack of data latches for each acquisition module. In one embodiment, there are three data latches per acquisition module 180. In some implementations, the data latches are implemented as a shift register so that the parallel data stored therein is converted to serial data for the data bus 120 and vice versa. All of the data latches corresponding to the read / write block of memory elements can be connected together to form a block shift register so that a block of data can be input or output via serial transfer. In particular, the module of read / write modules is adapted so that each of its set of data latches will shift data into or out of the data bus in sequence, as if they were part of a shift register for the entire read / write block.

[0065] The data latches identify when an associated memory element has reached certain milestones in a programming operation. For example, latches can identify that a memory element's Vth is below a certain verification level. The data latches indicate whether a memory element is currently storing one or more bits from a data page. For example, the LDL latches can be used to store a lower page of data. An LDL latch is flipped (e.g., from 0 to 1) when a lower page bit is stored in an associated memory element. A UDL latch is flipped when an upper page bit is stored in an associated memory element. This occurs when an associated memory element completes programming, e.g., when its Vth exceeds a target verification level such as Vva, VvB, or VvC.

[0066] Fig. Figure 3 illustrates a configuration of a NAND chain and components for sensing. In one implementation, sensing circuits 400 in the sensing block 51 are Fig. 1A and a controller 408 is provided by the control circuit 110 of Fig. 1A. In a simplified example, a NAND chain 412 includes four storage elements in communication with word lines WL0, WL1, WL2, and WL3. In practice, additional storage elements and word lines may be used. Further, additional NAND chains are typically arranged adjacent to each other in a block or other set of non-volatile storage elements. The storage elements are coupled to a p-type source region of a substrate. A bit line 410 having a voltage Vbl is shown in addition to the sense circuit 400. In particular, a BLS (bit line sense) transistor 406 is coupled to the bit line 410. The BLS transistor 406 is a high voltage transistor and is opened in response to a controller 408 during sense operations.A BLC (bit line detect) transistor 404 is a low-voltage transistor that is opened in response to controller 408 to allow the bit line to communicate with a current sense module 402. During a sense operation, such as a read or verify operation, a pre-charge operation occurs in which a capacitor in the current sense module 402 is charged. The BLC transistor 404 may be opened to allow pre-charging. Also, during the sense operation, a verification voltage is applied to a word line of one or more memory elements involved in the operation.

[0067] As mentioned at the beginning, the BLC transistor can be configured differently in the sense circuits of different memory chains based on, for example, an expected data pattern and / or a pattern of non-uniformities in the manufacturing process for the memory device.

[0068] On the drain side of NAND chain 412, BLC transistor 406 is turned on, e.g., made conductive or opened. Additionally, a voltage Vbls is applied to BLC transistor 404 to make it conductive. The bitline voltage Vbl is set or determined based on the control gate voltage Vblc minus Vth of the BLC transistor. The bitline is connected to the source terminal of the BLC transistor, and the BLC transistor operates in a source-follower configuration.

[0069] The precharged capacitor in the current detection module 402 discharges through the bit line and into the source, so that the source acts as a current sink. The precharged capacitor at the drain of the NAND chain can be precharged to a potential that exceeds a potential of the source, so that a current flows through the selected non-volatile memory element and sinks into the source when the selected memory element is in the conducting state.

[0070] The precharged capacitor does not discharge noticeably when the memory element is in a non-conductive state. After a discharge period, the resulting data can be transferred to a management / control circuit to monitor and control the programming of each memory element.

[0071] In particular, if the selected storage element is in a conductive state due to the application of Vcgr, a relatively high current will flow. If the selected storage element is in a non-conductive state, no or a relatively small current will flow. The current sensing module 402 may sense the cell / storage element current icell. In one possible approach, the current sensing module determines a voltage drop associated with a fixed current flow through the relationship ΔV=i t / C, where ΔV is the voltage drop, i is the fixed current, t is a discharge time period, and C is the capacitance of the precharge capacitor in the current sensing module. See also Fig. 4, which illustrates current detection based on a change in voltage in an example implementation of the current detection module 402 in Fig. 3. A larger voltage drop represents a higher current. At the end of a given discharge period, since i and C are fixed, ΔV can be determined for a given current. In one approach, a PMOS transistor is used to determine a level of ΔV relative to a demarcation value. In another possible approach, a cell current discriminator serves as a discriminator or comparator of current levels by determining whether the conduction current is higher or lower than a given demarcation current.

[0072] Voltage sensing, in contrast, does not involve sensing a voltage drop associated with a fixed current. Instead, voltage sensing involves determining whether charge sharing occurs between a capacitor in a voltage sensing module and a capacitance of the bit line. The current is not fixed or constant during sensing. Little or no charge sharing occurs when the selected storage element is conducting, in which case the voltage of the capacitor in the voltage sensing module does not drop significantly. Charge sharing occurs when the selected storage element is non-conducting, in which case the voltage of the capacitor in the voltage sensing module drops significantly.

[0073] The current detection module 402 can therefore determine whether the selected memory element is in a conductive or non-conductive state by the current level. Generally, a higher current will flow when the selected memory element is in a conductive state, and a lower current will flow when the selected memory element is in a non-conductive state. A threshold voltage of the selected memory element is above or below a comparison level, such as a verification level or a read level, when it is in a non-conductive state or a conductive state.

[0074] Fig. 5 illustrates an example implementation of the BLC transistor 404 Fig. 3. The transistor can be, for example, an n-MOSFET. The transistor has a lightly doped p-type substrate 510 with a source terminal 511 and a drain terminal that are heavily doped n-type. Metallized contacts 517 and 513 are provided in an oxide layer 514. The substrate surface is covered with a thin oxide film. The gate electrode 515 is above the insulating oxide layer, and the body electrode 516 in the diagram above provides a counter electrode to the gate. The thin oxide film can contain, for example, silicon dioxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (Si2N2O).

[0075] As mentioned, the bitline voltage is equal to the voltage at source terminal 511. This voltage, in turn, is equal to the control gate voltage minus the threshold voltage (Vth) of the transistor. To increase the bitline voltage, Vth can be lowered. At least one of a shorter control gate length (L1), a smaller oxide thickness (L2), a lower dielectric constant (for oxide layer 514), or a higher source and / or drain doping concentration is associated with a reduced Vth.

[0076] The control gate length can be adjusted during the memory device manufacturing process using appropriate masking, deposition, and etching techniques. Therefore, one approach to compensating for low current in a memory chain is to provide a relatively shorter control gate length for the associated BLC transistors in the sense circuits.

[0077] The oxide thickness can be adjusted during the memory device manufacturing process using appropriate masking, deposition, and etching techniques. Therefore, one approach to compensating for low current in a memory chain is to provide a relatively smaller oxide thickness for the associated BLC transistors in the sense circuits.

[0078] Regarding the dielectric constant of the oxide layer, as mentioned, a lower oxide dielectric constant is associated with a reduced Vth. Therefore, one approach to compensating for low current in a memory chain is to provide a gate oxide in the BLC transistor with a relatively lower dielectric constant. For example, silicon dioxide (SiO2), with a dielectric constant of approximately 3.9, can be used instead of silicon oxynitride (SI2N2O), with a dielectric constant of approximately 4.6.

[0079] The doping concentration can be adjusted during the memory device manufacturing process using a suitable doping process, such as ion implantation or diffusion. Ion implantation involves accelerating charged dopants (ions) in an electric field and beaming the dopant onto a wafer. The penetration depth can be adjusted based on the voltage used to accelerate the ions. A higher doping concentration may be associated with a longer ion implantation time.

[0080] Diffusion involves the network transport of molecules from an area of ​​higher concentration to one of lower concentration through random molecular motion. The result of diffusion is a gradual mixing of materials. The rate of the diffusion process depends on several factors, including the dopant, the concentration gradient, the temperature, the substrate, and the crystallographic orientation of the substrate. Diffusion methods include diffusion from a gas phase, a solid source, or a liquid source. For gas-phase diffusion, a carrier gas such as nitrogen or argon is enriched with the desired dopant in gaseous form and provided opposite the silicon wafer. Phosphorus or arsenic are example dopants for providing the n-type source / drain regions 511 and 512.A larger dopant concentration can be associated with a longer diffusion time, a higher concentration of the dopant in the carrier gas and a higher temperature.

[0081] Therefore, one approach to compensating for a low current in a memory chain is to provide a relatively larger doping concentration in the source and / or drain regions of the associated BLC transistors in the sensing circuits.

[0082] The above approaches can just as easily be combined.

[0083] Fig. 6 is a perspective view of a memory device 600 showing a set of blocks in a plane in an example 3D configuration of the memory structure 126 of Fig. 1. On the substrate 601 are example blocks BLK0, BLK1, BLK2, and BLK3 of memory cells (memory elements) and peripheral regions with circuitry for use by the blocks. Peripheral region 604 runs along one edge of each block, while peripheral region 605 is present at one end of the set of blocks.

[0084] The circuit may include voltage drivers that can be connected to the control gate layers, bit lines, and source lines of the blocks. The substrate may also support circuitry beneath the blocks, along with one or more metal layers arranged in conductive paths to carry circuit signals. The blocks are formed in an intermediate region 602 of the memory device. In an upper region 603 of the memory device, one or more upper metal layers are arranged in conductive paths to carry circuit signals. Each block comprises a stacked region of memory cells, with alternating levels of the stack representing word lines. In one possible approach, each block has opposing stepped sides from which vertical contacts extend upward to an upper metal layer to form connections to conductive paths.While four blocks are shown as an example, two or more blocks extending in the x- and / or y-direction can be used. Typically, the length of the blocks is much longer in the x-direction than the width in the y-direction.

[0085] In one possible approach, the blocks are arranged in a plane, and the length of the plane in the x-direction represents a direction in which signal paths to word lines extend in the one or more upper metal layers (a word line or SGD line direction), and the width of the plane in the y-direction represents a direction in which signal paths to bit lines extend in the one or more upper metal layers (a bit line direction). The z-direction represents a height of the memory device. The blocks can also be arranged in multiple planes.

[0086] Fig. Figure 7A illustrates an example cross-sectional view of a portion of one of the blocks Fig. 6. The block comprises a stack 610 of alternating conductive and dielectric layers. The block comprises conductive layers that are vertically spaced from each other, and the conductive layers comprise word lines connected to memory cells and select gate lines connected to SGD and SGS transistors.

[0087] In this example, the conductive layers or plates include two SGD layers, two SGS layers, and four dummy wordline layers (or wordlines) WLD1, WLD2, WLD3, and WLD4, in addition to data wordline layers (or wordlines) WLL0-WLL10. WLD2 is a topmost dummy wordline layer, and WLD1 is another dummy wordline layer located below the topmost dummy wordline layer and above the topmost drain-side data wordline WLL10. WLD3 and WLD4 are source-side dummy wordline layers. The dielectric layers are labeled DL0-DL19. Also shown are regions of the stack containing NAND strings NS1 and NS2. Each NAND string includes a storage hole 618 or 619 filled with materials that form memory cells adjacent to wordlines. An area 622 of the stack is described in more detail in Fig. 8 shown.

[0088] The stack comprises a substrate 611. In one access, a portion of the source line SL comprises an n-type diffusion layer 611a in the substrate, which is in contact with a source end of each chain of memory cells in a block. The n-type diffusion layer 611a is formed in a p-type source region 611b, which in turn is formed in an n-type source region 611c, which in turn is formed in a p-type semiconductor substrate 611d, in one possible implementation. The n-type source diffusion layer can be shared by all of the blocks in a plane in one access.

[0089] NS1 has a source end 613 at a bottom 616b of the stack 616 or the plurality of wordline layers and a drain end 615 at a top 616a of the stack or the plurality of wordline layers. Local interconnects such as interconnect 617 may be provided periodically above the stack. The local interconnects may be metal-filled slots extending through the stack, such as to connect the source line / substrate to a line above the stack. The metal 617d is insulated from the wordline layers by an insulating material 617c. The slots may be used during the formation of the wordlines and subsequently filled with metal. Specifically, a stack may be formed with a sacrificial material such as SiN for the wordline layers alternating with dielectric layers such as oxide.Slots are periodically etched in the stack down to the substrate, exposing portions of the sacrificial material. An etchant, such as hot phosphoric acid, is deposited in the slots to remove the sacrificial material, forming gaps. A metal is then deposited in the gaps over the slots, forming the final wordline layers. Subsequently, the metal in the slots is cleaned away, and insulating material 617c is deposited along the sidewalls of the slots. A hole is etched in the bottom of the insulating layer. The remainder of the slots are filled with metal 617d, which extends through the hole to the substrate and up to the top of the stack, forming a conductive path or local interconnect from the bottom to the top of the stack.

[0090] A portion of a bit line BL0 is also shown. A conductive via connects the drain end of each memory chain to a bit line. For example, a conductive via 621 connects the drain end 615 to BL0. The local interconnect 617 has a top surface 617a and a bottom surface 617b. The bottom surface is etched through to provide contact with the substrate.

[0091] In one approach, the block of memory cells comprises a stack of alternating control gate and dielectric layers, and the memory cells are arranged in vertically extending storage holes in the stack.

[0092] In an access, each block has a terraced edge in which vertical interconnections, e.g., columns or posts, connect to each layer, including the SGS, WL, and SGD layers, and extend upward to horizontal paths to stress sources. See Fig. 15.

[0093] This example includes two SGD transistors, two drain-side dummy memory cells, two source-side dummy memory cells, and two SGS transistors in each chain as an example. Generally, one or more SGD transistors and one or more SGS transistors can be provided in a memory chain.

[0094] An isolation region IR may be provided to separate portions of the SGD layers from each other to provide an independently driven SGD line or layer portion per sub-block. The isolation region comprises an insulating material such as oxide. In one example, the word line layers are common to all sub-blocks in a block. The drain-side dummy word line layers may comprise a separate portion for each sub-block, a portion of which is shared by multiple sub-blocks of a block, a portion of which is shared by multiple sub-blocks of a block but less than all of the sub-blocks of the block, and / or a single portion shared by all sub-blocks of a block.

[0095] Fig. Figure 7B illustrates an example transistor 500. The transistor includes a control gate CG, a drain D, a source S, and a channel CH. During a program operation, the transistor has a positive gate-to-channel voltage. During an erase operation, the transistor has a positive channel-to-gate voltage.

[0096] Fig. Figure 8 shows a close-up view of area 622 of the stack Fig. 7A. Memory cells are formed at various levels of the stack at the intersection of a wordline layer and a memory hole. In this example, SGD transistors 680 and 681 are provided above dummy memory cells 682 and 683 and a data memory cell MC. A number of layers may be deposited along the sidewall (SW) of the memory hole 630 and / or within each wordline layer, e.g., using atomic layer deposition. For example, each pillar 699 or column formed by the materials within a memory hole may include a block oxide 667, a charge trapping layer 663 or a film such as silicon nitride (Si3N4) or other nitride, a tunneling layer 664 (such as an oxide), a channel layer 665 (e.g., containing polysilicon), and a dielectric core 666. A word line layer may include a block high-k material 660, a metal barrier 661 and a conductive material 662 such asTungsten as a control gate. For example, control gates 690, 691, 692, 693, and 694 are provided. Additional pillars are similarly formed in the various memory holes. A pillar may form a column-shaped active area (AA) of a NAND string. The channel layer has a thickness Th. As mentioned herein, the channel thickness may be greater for memory strings expected to have high-state memory cells in one gate. This increased width provides reduced resistance and therefore increased current. See . Fig. 16C and Fig. 16D.

[0097] The channel width can be controlled during the manufacturing process. Memory holes are formed in one access, and channel films are deposited in one part of the stack, e.g., associated with user data, separated from the memory hole formation and deposition of the channel layer in another part of the stack, e.g., associated with metadata. The deposition of the channel layer can occur over a relatively longer period of time to provide a relatively thicker channel layer.

[0098] When a memory cell is programmed, electrons are stored in a portion of the charge-trapping layer associated with the memory cell. These electrons are drawn into the charge-trapping layer from the channel and through the tunnel layer. The Vth of a memory cell increases in proportion to the amount of stored charge. During an erase operation, the electrons return to the channel.

[0099] Each of the memory holes can be filled with a plurality of annular layers including a blocking oxide layer, a charge trapping layer, a tunneling layer, and a channel layer. A core region of each of the memory holes is filled with a body material, and the plurality of annular layers are located between the core region and the word line in each of the memory holes.

[0100] The NAND string can be considered to have a floating body channel because the entire length of the channel is not formed on a substrate. Furthermore, the NAND string is provided by a plurality of wordline layers stacked one above the other and separated from each other by dielectric layers.

[0101] Fig. 9A illustrates an example implementation of the memory structure 126 Fig. 1A, which comprises NAND strings in sub-blocks in a 3D configuration. In one approach, a block BLK of memory cells is formed from a stack of alternating conductive and dielectric layers. The block comprises conductive layers that are vertically spaced apart from each other, and the conductive layers that are vertically spaced apart from each other comprise word lines connected to the memory cells and select gate lines connected to SGD (drain-side select gate) and SGS (source-side select gate) transistors. In this example, the conductive layers comprise two SGD layers, two SGS layers, and four dummy word line layers (or word lines) WLD1, WLD2, WLD3, and WLD4 in addition to the data word line layers (or word lines) WLL0-WLL10. The dielectric layers are referred to as DL0-DL19.Each NAND chain may be formed in a memory hole in the stack and is filled with materials that form memory cells adjacent to the word lines.

[0102] Furthermore, each block can be divided into sub-blocks, and each sub-block includes multiple NAND chains, with an example NAND chain being shown. For example, sub-blocks SB0, SB1, SB2, and SB3 include multiple NAND chains 300n, 310n, 320n, and 330n. The NAND chains include data word lines, dummy word lines, and select gate lines. Each sub-block includes a set of NAND chains extending in the x-direction and sharing a common SGD line. SB0 includes SGD lines or SGD layer sections 810 and 814 in the SGDO and SGD1 layers. SB1 includes SGD layer sections 811 and 815 in the SGDO and SGD1 layers. SB2 has SGD layer sections 812 and 816 in the SGDO and SGD1 layers. SB3 has SGD layer sections 813 and 817 in the SGDO and SGD1 layers. Each of the data word line layers WLL0 to WLL10 and the SGS layers SGS0 and SGS1 is shared by all of the sub-blocks SB0 to SB3.

[0103] NAND chains 300n, 310n, 320n, and 330n are present in sub-blocks SB0, SB1, SB2, and SB3. Programming of the block can occur one sub-block at a time. Within each sub-block, a wordline programming sequence can be followed, e.g., starting at WL0, the source-side wordline, and subsequently one wordline at a time up to WLL10, the drain-side wordline.

[0104] NAND chains 300n, 310n, 320n, and 330n have channels 300a, 310a, 320a, and 330a, respectively. Each channel has a drain end and a source end. For example, channel 300a has a drain end 390 and a source end 391.

[0105] In addition, the NAND chain 300n includes SGS transistors 300 and 301, the dummy memory cells 302 and 303, the data memory cells 304, 305, 306, 307, 308, 309, 310, 311, 312, 313 and 314, the dummy memory cells 315 and 316, and SGD transistors 317 and 318.

[0106] The NAND chain 310n includes SGS transistors 320 and 321, dummy memory cells 322 and 323, data memory cells 324, 325, 326, 327, 328, 329, 330, 331, 332, 333 and 334, dummy memory cells 335 and 336, and SGD transistors 337 and 338.

[0107] NAND chain 320n includes SGS transistors 340 and 341, dummy memory cells 342 and 343, data memory cells 344, 345, 346, 347, 348, 349, 350, 351, 352, 353 and 354, dummy memory cells 355 and 356, and SGD transistors 357 and 358.

[0108] The NAND chain 330n includes SGS transistors 360 and 361, dummy memory cells 362 and 363, data memory cells 364, 365, 366, 367, 368, 369, 370, 371, 372, 373 and 374, dummy memory cells 375 and 376, and SGD transistors 377 and 378.

[0109] Fig. Figure 9B shows a perspective view of sub-blocks SB0-SB3 consistent with Fig. 9A. A sub-block is a section of a block and represents a set of memory chains that are programmed together and share a common SGD line. Each memory chain in a sub-block is also connected to a different bit line in an access.

[0110] Example memory cells are shown extending in the x-direction along word lines in each sub-block. Each memory cell is represented as a cube for simplicity. SB0 has NAND chains 300n, 301n, 302n, and 303n. SB1 has NAND chains 310n, 311n, 312n, and 313n. SB2 has NAND chains 320n, 321n, 322n, and 323n. SB3 has NAND chains 330n, 331n, 332n, and 333n. Bit lines are connected to sets of NAND chains. For example, a bit line BL0 is connected to NAND chains 300n, 310n, 320n, and 330n; a bit line BL1 is connected to NAND chains 301n, 311n, and 321n; a bit line BL2 is connected to NAND chains 302n, 312n, 322n, and 332n; and a bit line BL3 is connected to NAND chains 303n, 313n, 323n, and 333n. A sense circuit can be connected to each bit line. For example, sense circuits 400, 400a, 400b, and 400c are connected to bit lines BL0, BL1, BL2u, and BL3.NAND chains are examples of vertical memory chains that extend upward from a substrate.

[0111] Programming and reading can occur for selected cells of a word line and sub-block at a time. This allows each selected cell to be controlled by a respective bit line. For example, an example set 395 of memory cells (including an example memory cell 380) in SB0 is connected to WLL4. Similarly, sets 396, 397, and 398 have data storage cells in SB1, SB2, and DB3 connected to WLL4.

[0112] Fig. Figure 10 illustrates an initial threshold distribution of an example two-pass programming operation involving four data states. Initially, the cells are all in the erased (Er) state, as represented by threshold (Vth) distribution 900. The vertical axis indicates the number of cells, and the horizontal axis indicates a Vth.

[0113] Fig. Figure 10B illustrates a threshold distribution obtained after a first pass of the example two-pass programming operation from Fig. 10A results. Based on write data as indicated, the cells that are to remain in the Er state or be programmed to the A state are represented by the Vth distribution 900, while cells that are to be programmed to the B and C states are programmed to an intermediate (INT) distribution 902. This programming pass may be referred to as an intermediate pass, in which a verification level of VvINT is used.

[0114] Fig. Figure 10c shows a threshold distribution obtained after a second pass of the example two-pass programming operation from Fig. 10A results. Based on write data as indicated, the cells to remain in the Er state are represented by Vth distribution 900. The cells to be programmed to the A state using a verification voltage of VvV are represented by distribution 910. The cells to be programmed to the B and C states using verification voltages VvB and VvC are represented by distributions 912 and 914. Each data state represents two data bits as shown. In general, a multi-pass programming process can help achieve tighter Vth distributions, especially for the higher states. Read voltages Vr1, VrB, and VrC can be used to read the states of the cells in a read operation.

[0115] Fig. Figure 11A illustrates an initial threshold distribution of an example two-pass programming operation involving eight data states. Initially, the cells are all in the erased (Er) state, as represented by threshold (Vth) distribution 1100. The vertical axis indicates the number of cells, and the horizontal axis indicates a Vth.

[0116] Fig. Figure 11B illustrates a threshold distribution obtained after a first pass of the example two-pass programming operation from Fig. 11A results. Based on write data as indicated, the cells that are to remain in the Er state or are to be programmed to the A, B, and C states are represented by the Vth distribution 1100, while the cells that are to be programmed to the D, E, F, and G states are programmed to an intermediate (INT) distribution 1102. This programming pass operation may be referred to as an intermediate pass operation, in which a verification level of VvINT is used.

[0117] Fig. Figure 11C illustrates a threshold distribution obtained after a second pass of the example two-pass programming operation from Fig. 11A results. Based on the write data as indicated, the cells to remain in the Er state are represented by Vth distribution 1100. The cells to be programmed to the A, B, and C states using verification voltages of Vva, VvB, and VvC are represented by Vth distributions 1110, 1112, and 1114. The cells to be programmed to the D, E, F, and F states using verification voltages of VvD, VvE, VvF, and VvG are represented by Vth distributions 1116, 1118, 1120, and 1122. Each data state represents three data bits as indicated. The read voltages VrA, VrB, and VrC can be used to read the states of the cells in a read operation.

[0118] Other example programming operations may use additional data states and / or programming pass operations. A single-pass programming operation could also be used.

[0119] Fig. Figure 12 illustrates a series of program verification iterations in an example of a programming pass for a lower data page, consistent with Fig. 10B and Fig. 11B. The horizontal axis represents program verification (PV) iteration number or time, and the vertical axis represents a voltage. Pulse train 1300 includes a series of programming pulses 1301-1309. Example verification pulses include an INT state verification pulse 1310 (VvINT). Pulse train 1300 is an example of a first step of incrementally increasing programming voltages. Vpgm_init1 is an example of an initial value of a first set of incrementally increasing programming voltages.

[0120] A pulse train typically comprises programming pulses that gradually increase in amplitude in one or more program verification iterations of a program passing operation using a varying step size. In some cases, the programming pulses increase in each program verification iteration after the first. A new pulse train can be applied in each program passing operation, starting at an initial level and ending at a final level that does not exceed a maximum allowed level. The initial levels can be the same or different in different program passing operations. The final levels can also be the same or different in different program passing operations. The step size can be the same or different in different program passing operations.In some cases, a smaller step size is used in a final programming pass to reduce Vth distribution widths.

[0121] Fig. Figure 13 illustrates a series of programming verification iterations in an example of a programming pass operation for an upper data page, consistent with Fig. 10C. A similar series of programming verification iterations can be used for the programming passing process example from Fig. 11C. The horizontal axis represents a program verification iteration number (PV), and the vertical axis represents a control gate or wordline voltage. Pulse train 1500 comprises a series of program pulses 1501-1515 applied to a wordline selected for programming. Pulse train 1500 is an example of a second or third set of incremental program voltages. Vpgm_init2 is an example of an initial value of a third set of incremental program voltages. One, two, or three verification pulses are provided after each program pulse, as an example, based on the target data states being verified.For example, one or more of an example A-state verification pulse 1520 (VvA), B-state verification pulse 1521 (VvB), and C-state verification pulse 1522 (VvC) may be applied in different programming verification iterations.

[0122] Fig. Figure 14 illustrates a graphical representation of example waveforms in a read operation. A read operation may involve reading a number of data pages—three pages in this example. A control gate read voltage is applied to a selected word line, while a pass voltage, Vpass, is applied to the remaining unselected word lines. A sense circuit is then used to determine whether a cell is in a conducting state. Vpass is ramped up and then ramped back down separately during the read voltages of each of the low, middle, and high pages, as illustrated by plots 970, 971, and 972. This example is for an eight-state memory device, consistent with Fig. 11C. The example can be modified for fewer states (e.g., four states and two sides) or additional states (e.g., sixteen states and four sides).

[0123] For the first page, the A and E states are read using a read voltage waveform 970a with voltages VrA and VrE. For the second page, the B, D, and F states are read using the read voltage waveform 971a with voltages VrB, VrD, and VrF. For the third page, the C and G states are read using the read voltage waveform 972a with voltages VrC and VrG. Optionally, the bit line and / or source line can be charged in a read operation.

[0124] Fig. 15A illustrates an example process for programming memory cells. A two-pass programming operation consistent with Fig. 10A-10C and 11A-11C is shown. Step 1530 begins the first pass of a programming operation. Step 1531 selects a wordline for programming. Step 1532 sets an initial programming voltage (Vpgm). Step 1533 involves applying a programming voltage to the selected wordline. Pass voltages may be applied to the unselected and dummy wordlines. Step 1534 involves performing verification tests, e.g., by applying verification voltages. A decision step 1535 determines whether programming of the selected wordline is terminated, e.g., whether the verification tests are passed. If decision step 1535 is true, a decision step 1537 determines whether the first pass is performed for all wordlines, e.g., in a sub-block or a block.If decision step 1537 is true, step 1538 begins the second pass of the programming operation.

[0125] If step 1535 is false, step 1536 increments the programming voltage, and step 1533 begins the next program verification iteration or loop. If step 1537 is false, step 1531 selects another wordline for programming.

[0126] In the second pass of the programming operation, step 1539 selects a wordline for programming. Step 1540 sets an initial programming voltage (Vpgm). Step 1541 involves applying a programming voltage to the selected wordline. The pass voltages may be applied to the unselected and dummy wordlines. Step 1542 involves performing verification tests. A decision step 1543 determines whether programming of the selected wordline is terminated, e.g., whether the verification tests have been passed. If decision step 1543 is true, a decision step 1545 determines whether the second pass is performed for all wordlines, e.g., in a subblock or block. If decision step 1545 is true, the programming operation is terminated at step 1546.

[0127] If step 1543 is false, step 1544 increments the programming voltage, and step 1541 begins the next program verification iteration or loop. If step 1545 is false, step 1539 selects another wordline for programming.

[0128] This example process therefore involves programming the memory cells of each wordline in a set of wordlines, one wordline at a time in a program pass. Once the first program pass for all wordlines is complete, the process programs the memory cells of each wordline in the set of wordlines, one wordline at a time, in a second program pass. In this approach, the metaarea of ​​each wordline can be used to indicate whether the cells of the wordline have completed the first program pass. Generally, the cells of a block are initially in the erased state. The internal controller of the memory device can keep track of which wordline it last programmed. However, the controller may not keep track of whether it is in the first or second program pass.In addition, the control unit can interrupt a programming operation to perform other higher priority tasks and then continue programming.

[0129] Accordingly, in one embodiment, some of the cells in the metadata area may be programmed to indicate whether the wordline has completed the first program pass. For example, in the eight-state example, Fig. 11C, the cells in the metadata area are maintained in the erased state to indicate that the cells of the word line have not completed the first program pass operation. This also indicates that the cells of the word line have not completed the second program pass operation. The cells in the metadata area can be programmed to one of the higher states to indicate that the cells of the word line have completed the first program pass operation. It is desirable to use a data state for this that is far from the erased state so that the data can be reliably stored even if the Vth distributions of the cells in the metadata area change significantly due to disturbances, environmental conditions, defects, and other factors. For example, the E, F, or G state could be used because these are separated from the erased state by several other states.

[0130] In another possible approach, the cells in the metadata area are programmed to a mid-range state such as the C or D state to indicate that the user data cells of the word line have completed the first program pass but not the second program pass, and the cells in the metadata area are programmed to a higher state such as the F or G state to indicate that the user data cells of the word line have completed the second program pass.

[0131] In many cases, the cells of a block are in a state where they have completed programming. The cells in the metadata area will therefore be in a high state, potentially leading to a low-power problem in the absence of the corrective measures provided herein.

[0132] The cells in the metadata area can be used to store various other types of information, such as a number of program-erase cycles, a timestamp indicating the time of the last wordline programming operation, and data indicating a temperature at the time of the last wordline programming operation. The timestamp and temperature can be used to adjust a read process (e.g., read voltages) for the wordline, which causes a data storage loss that increases as the time elapsed since the last program operation increases. Temperature can also be a factor in adjusting the read voltages. Depending on the encoding scheme used, these types of metadata could also result in the cells being in a high state.

[0133] Fig. Figure 15B illustrates another example process for programming memory cells. A two-pass programming operation performed with Fig. 10A-10C and 11A-11C is shown. Step 1550 begins the first pass of a program operation. Step 1551 selects a wordline for programming. Step 1552 sets an initial program voltage (Vpgm). Step 1553 involves applying the program voltage to the selected wordline. Step 1554 involves performing verification tests. A decision step 1555 determines whether the verification tests are passed. If decision step 1555 is true, the second pass of the program operation begins at step 1557.

[0134] If step 1555 is false, step 1556 increments the programming voltage and step 1553 begins the next programming verification iteration or loop.

[0135] In the second pass of the programming operation, step 1558 sets an initial programming voltage (Vpgm). Step 1559 involves applying the programming voltage to the selected wordline. Step 1560 involves performing verification tests. A decision step 1561 determines whether the verification tests are passed. If decision step 1561 is true, a decision step 1563 determines whether there is a next wordline to be programmed. If decision step 1563 is true, a wordline is selected at step 1551. If decision step 1563 is false, the programming operation is terminated at step 1564.

[0136] If step 1561 is false, step 1562 increments the programming voltage and step 1559 begins the next programming verification iteration or loop.

[0137] This example process therefore involves programming the memory cells of each word line using a first program pass operation and then a second program pass operation before beginning programming of a next word line.

[0138] Some of the cells in the metadata area may be programmed to indicate whether the word line has completed the first program pass or the first or second program pass, as previously discussed.

[0139] Fig. Figure 15C illustrates an example process for reading memory cells. Step 1570 begins a read operation. Step 1571 selects a wordline for reading. Step 1572 involves applying a control gate read voltage to the selected wordline. Pass voltages may be applied to the unselected and dummy wordlines. Step 1573 involves sensing a conducting state of the selected cells, e.g., whether the cells are conducting or non-conducting. This may be performed using a sensing circuit connected to the memory strings via bitlines.

[0140] A decision step 1574 determines whether the reading of the selected wordline is complete, e.g., whether all of the control gate read voltages have been applied. If decision step 1574 is true, a decision step 1576 determines whether there is a next wordline to read. If decision step 1576 is false, the read operation is completed at step 1577. If decision step 1576 is true, a next wordline is selected for reading at step 1571. If decision step 1574 is false, step 1575 sets the next control gate read voltage, and step 1572 applies the next control gate read voltage and other voltages.

[0141] Fig. 16A illustrates an example block 1600 of memory cells including a user data area 1601 and a metadata area 1602. The data is typically arranged in units of pages. A page is a unit of reading or writing in the memory device. A page may comprise, in one access, a set of cells connected to a common control line, such as a word line. A data page may comprise a user data portion and an auxiliary or metadata portion, as mentioned. The user data portion may be an area addressable by a host device. In one example, the page length is 2112 bytes and includes 2048 bytes allocated for user data and 64 bytes allocated for metadata. The metadata may include various types of information, such as error correction code (ECC) data obtained by encoding the associated user data.Another type of metadata identifies the program pass that the cells of the associated word line have completed in a multi-pass operation.

[0142] A set of detection circuits 1610 is associated with the block. For example, a respective detection circuit may be connected to each respective memory chain in the block. The set of detection circuits may include a first set of detection circuits 1611 of a first type (Type 1) associated with the cells in the user data area and a second set of detection circuits 1612 of a second type (Type 2) associated with the cells in the metadata area. In one embodiment, the Type 2 detection circuits include a BLC transistor with a lower Vth than the BLC transistors of the Type 1 detection circuits to compensate for the presence of high state data in the metadata area.

[0143] The user data typically comprises random data. That is, the user data is stored relatively uniformly across the various data states. The metadata may comprise data that tends to be non-random and is likely to be represented by cells in high data states in some situations. The storage chains with high-state metadata may comprise a subset of the storage chains assigned to the metadata.

[0144] Fig. 16B illustrates memory chains and respective BLC transistors in the example block of memory cells Fig. 16A. This view illustrates memory chains 1640-1641 in the user data area 1601 and memory chains 1642-1643 in the metadata area 1602. The memory chains 1640-1643 include example memory cells 1644-1647.

[0145] The Type 1 sense circuits 1611 include BLC transistors 1613-1614 in a first set of transistors 1615 and in the sense circuits 1613a-1614a. The BLC transistors 1613-1614 include control gates 1613g-1614g and source terminals 1613s-1614s connected to the memory chains 1640-1641 via bit lines 1613b-1614b. The Type 2 sense circuits 1612 include BLC transistors 1616-1617 in a second set of transistors 1619 in the sense circuits 1616a-1617a. BLC transistors 1616-1617 have control gates 1616g-1617g and source terminals 1616s-1617s connected to memory chains 1642-1643 via bit lines 1616b-1617b. A BLC control line 1618 receives a voltage Vblc from a voltage source 1648 and is connected to the control gates of each of the BLC transistors for the block in one access.

[0146] Each of the detection circuits may be similar to the detection circuit 400 of Fig. 3 for example.

[0147] This example involves a plurality of memory chains, each chain having a set of series-connected memory cells among a set of memory cells.Furthermore, there are a plurality of detection circuits 1613a-1614a and 1616a-1616a, wherein each detection circuit comprises a transistor 1613-1614 and 1616-1617 with a source terminal 1613s-1614s and 1616s-1617s, each connected to a memory chain 1640-1643 of a plurality of memory chains, wherein control gates 1613g-1614g and 1616g-1617g of the transistors are connected to a common voltage source 1648, wherein the transistors comprise a first set of transistors 1613-1614 connected to a first set of memory chains 1640, 1641 and a second set of transistors 1616-1617 connected to a second set of memory chains 1642 and 1643, and wherein the first set of transistors has a higher threshold voltage than the second set of transistors.

[0148] The drain terminals of the BLC transistors can be connected to a voltage source high enough to allow the BLC transistors to operate in a source-follower configuration.

[0149] Fig. 16C illustrates an example column 1660 of a memory chain with a channel layer 1662 having a relatively small width or thickness Th1. A dielectric core and other layers 1661, e.g., a block oxide, a charge-trapping layer, and a tunneling layer, are also provided. As mentioned, a memory chain with a relatively small channel width will have a relatively small current.

[0150] One option is to make the channel width wider for memory chains where cells are expected to be in a high state for a significant portion of the memory device's lifetime. This is an example of manufacturing the channel width based on a data pattern.

[0151] Fig. 16D illustrates an example column 1670 of a memory chain having a channel layer 1672 with a relatively large width or thickness Th2>Th1. A dielectric core 1673 and other layers 1671, e.g., a block oxide, a charge trapping layer, and a tunneling layer, are also provided.

[0152] Fig. 17A illustrates an example of metadata area 1602 Fig. 16A, where the cells are all in the erased (1) state. In Fig. In Figures 17A-18, each memory cell is represented by a rectangle. The cells are arranged in sixteen memory chains and eleven word lines. In this case, sixteen bits or two bytes of metadata can be stored on each word line. The memory chains comprise one set of memory chains 1602a and another set of memory chains 1602b.

[0153] The sixteen cells in each wordline can store data indicating whether the wordline has completed a particular programming pass in a multi-pass programming operation. For reliability, the data can be stored redundantly in each of the sixteen bits. When the data is needed, each cell is read, and the results are evaluated using a majority voting process.

[0154] Fig. Figure 17B illustrates an example of metadata area 1602 Fig. 16A, where the cells are all in the programmed (0) state. The cells are all in a relatively high state, so the current in the strings during sensing will be small unless a countermeasure is taken, such as adjusting the BLC transistors to have a higher sensing voltage (via a lower Vth), increasing the channel width, and / or increasing the channel doping concentration.

[0155] Fig. Figure 17C shows an example of metadata area 1602 Fig. 16A, where bytes of erased state data (1) and programmed state data (0) alternate in consecutive rows. For example, the row of WLL0 has a set of eight cells 1710 in the set of memory chains 1602a in the 1 state and a set of eight cells 1711 in the set of memory chains 1602b in the 0 state. The next row of WLL1 has a set of eight cells 1712 in the set of memory chains 1602a in the 0 state and a set of eight cells 1713 in the set of memory chains 1602b in the 1 state. In this approach, the cells in the 1 (erased) state are not used to store data. The cells in the 0 (high) state are used to store data, but their relative position is varied on the different word lines. This reduces the number of high state cells in a given storage chain so that the current does not become too low.

[0156] Another option is to vary the sets of cells across more than two possible sets of memory chains. Another option is to vary the sets of cells across different word lines, but not necessarily on alternating word lines. For example, in the set of memory chains 1602a, a byte of 1s may be provided in WLL0 and WLL1, followed by a byte of 0s in WLL2 and WLL3, and so on. In the set of memory chains 1602b, a byte of 0s may be provided in WLL0 and WLL1, followed by bytes of 1s in WLL2 and WLL3, and so on.

[0157] In an access, a control circuit may be configured to change the position of a subset of memory cells assigned to metadata on different wordlines of a set of wordlines when a temperature is below a threshold. As the temperature decreases, the Vth of the BLC transistors increases, resulting in a lower detection voltage on the low-current memory chains. To counteract this effect and avoid problems associated with excessively low chain current during sensing, the locations of the cells assigned to metadata on different wordlines may be varied to reduce the number of high-state cells in a given chain. This reduces the chain resistance and increases the chain current. This variation may be triggered based on a temperature in an access, so that the variation is not used when the temperature is above a threshold.The variation is implemented at the time of programming. This technique is useful when a detection operation occurs when the temperature is below the threshold.

[0158] The subset of memory cells assigned to metadata may store data indicating whether a respective wordline of a set of wordlines has completed programming. The subset of memory cells assigned to metadata is in a relatively high threshold voltage state when programming has completed for the respective wordline and in a relatively low threshold voltage state when programming has not completed for the respective wordline.

[0159] In another approach, the subset of memory cells assigned to metadata is in the relatively low threshold voltage state when at least one program pass, but less than all program passes of a multi-pass program operation for the respective word line has been completed.

[0160] In another approach, a position of the subset of memory cells assigned to metadata differs in different word lines of the set of word lines

[0161] In another approach, a control circuit is configured to vary a position of the subset of memory cells assigned to metadata in different wordlines of the set of wordlines when a temperature is below a threshold.

[0162] A programming process can be modified to check the temperature. If the temperature is below a threshold, the programming of the metadata cells can be modified as discussed. In one approach, the modification reduces metadata redundancy. For example, in Fig. 17C uses one data byte instead of two bytes, so the redundancy is reduced by half. However, sufficient redundancy can still be achieved if each cell stores the same bit, and a read result is obtained by a majority voting process.

[0163] Fig. Figure 18 illustrates a set of memory chains in a block, where the channel widths of the memory chains vary according to a repeating pattern due to non-uniformities in the manufacturing process. The memory chains are numbered 0-31 at the bottom, while a BLC transistor type (either T1, Type 1, or T2, Type 2) is shown at the top for each memory chain. In this pattern, every fourth transistor is of Type T2, and the remaining transistors are of Type T1. For example, Type T1 transistors are associated with the memory chains numbered 0-2, 4-6, 8-10, 12-14, 16-18, 20-22, 24-26, and 28-30, and Type T2 transistors are associated with the memory chains numbered 3, 7, 11, 15, 19, 23, 27, and 31.The type T2 transistors can have a lower Vth, for example, to compensate for associated memory chains with reduced channel widths due to non-uniformities in the manufacturing process. Another option is to have transistors of more than two types to compensate for associated memory chains with reduced channel widths of two or more types.

[0164] In another example, every other transistor is configured to be of one type and the remaining transistors are configured to be of a different type.

[0165] For example, in a 2D memory device, nonuniformities can be introduced by multiple patterning lithography techniques, such as spacer-based double patterning or quadruple spacer patterning. These techniques can result in systematic variations in the channel width and the corresponding memory chain resistance. The variations can be caused by wafer-level trends and layout pattern dependencies. Factors can include chemical and mechanical polishing variations that cause film thickness variations, variations in line width due to optical refraction and interference, mask or lens distortions in the photolithography system, or plasma etch microcharge effects. Nonuniformities can also be present in a 3D memory device.

[0166] Fig. 19A illustrates an example process for identifying memory chains likely to have memory cells in a high state. Step 1900 includes programming a block of memory cells in a memory device. For example, this may include typically programming the user data area and the metadata area. Step 1901 includes reading memory cells to identify memory chains with high data states. A high data state may be a data state above a specified data state or a Vth level above a specified Vth, for example. Step 1902 includes storing data identifying a portion of the memory cells with a high data state in each memory chain. Step 1903 includes determining a probability that a memory chain will have more than a threshold portion of cells in a high state.For example, assume that there are five passes through steps 1900-1903 and that the high-state cell interval is 80%, 70%, 60%, 90%, and 70%. The probability of this is (.8 + .7 + .6 + .9 + .7) / 5 = .74.

[0167] Step 1904 involves fabricating a new memory device with a modification to the channels and / or sensing circuitry to compensate for strings with high-state memory cells. For example, these may be strings for which the probability exceeds a specified level. The data collection of steps 1900-1903 may occur in one or more memory devices. One useful option is to collect the data for a population of end users of a set of memory devices under real-world conditions over a period of time, such as weeks or months. This helps provide a representative view of memory device usage. This approach predicts the data pattern on a per-string basis to identify potential low-power strings. The strings may be present in the metadata area, as mentioned.It is also possible that patterns are detected in the user data area that identify chains that are likely to have low current due to many of their cells being in a high data state.

[0168] Fig. Figure 19B illustrates an example process for identifying memory chains likely to experience low current during a read operation. For example, step 1910 involves programming a block of memory cells in a memory device to a data state. Or, the cells in each memory chain may be programmed to different states, but the pattern should be the same in each chain. One goal is to provide each chain in a similar configuration so that the current in each chain would be the same under ideal conditions where there are no physical non-uniformities in the chains. Step 1911 involves reading the memory cells while measuring the current in each chain. One approach uses a current measurement device to measure the current in a test environment rather than when the memory device is in the hands of the end user.Step 1912 includes storing data identifying memory chains with a current below a threshold. Step 1913 includes fabricating a new memory device with a modification to the channels and / or sensing circuitry to compensate for low-current memory chains.

[0169] One theory of this process is that non-uniformities in the manufacturing process will result in some chains exhibiting lower current. For example, this could be due to the channel being thinner than other channels, so the resistance is higher and the current is therefore lower. These non-uniformities in the tested devices are expected to be repeated in the new memory devices.

[0170] Fig. 19C illustrates an example process for programming a set of memory cells while sensing a bitline voltage. Step 1920 includes applying a control gate voltage to a set of memory cells connected to a wordline and to respective bitlines. Step 1921 includes detecting, during the control gate voltage, whether each memory cell is in a conductive or non-conductive state while sensing a first set of the respective bitlines at a first level and sensing a second set of the respective bitlines at a second level greater than the first level.

[0171] For example, in Fig. 16B assumes that WLL10 is the selected word line. The set of memory cells includes cells 1644, 1645, 1646, and 1647. The first set of respective bit lines includes bit lines 1613b-1614b, and the second set of respective bit lines includes bit lines 1616b-1617b. The process may be used in conjunction with a multi-pass programming operation, such as in Fig. 15A or Fig. 15B or in a single-pass programming operation.

[0172] The memory cells connected to the second set of the respective bit lines are more likely to be in a higher state than memory cells connected to the second set of the respective bit lines.

[0173] Furthermore, memory cells connected to the second set of respective bit lines may include metadata tracking a program pass operation in a multi-pass program operation and having a relatively high threshold voltage when the program pass operation is a final program pass operation in the multi-pass program operation compared to when the program pass operation is a previous program pass operation in the multi-pass program operation.

[0174] The memory cells connected to the first set of the respective bit lines can be reserved for storing user data in N data states (e.g. N=4 in Fig. 10C and N=8 in Fig. 11C); and memory cells connected to the second set of respective bit lines store the metadata in fewer than N data states.

[0175] Sensing includes allowing the sense nodes of the sense circuits to communicate with the respective bit lines while detecting the first set of the respective bit lines at the first level and clamping the second set of the respective bit lines at the second level.

[0176] Detecting the first set of respective bit lines at the first level and detecting the second set of respective bit lines at the second level comprises applying a common control gate voltage to a transistor in each detection circuit connected to one of the respective bit lines, the transistors comprising a first set of transistors connected to the first set of respective bit lines and a second set of transistors connected to the second set of respective bit lines, the first set of transistors having a higher threshold voltage than the second set of transistors.

[0177] Each transistor may have a source terminal connected to one of the respective bit lines and configured as a source follower to apply a voltage to one of the respective bit lines based on a difference between the common control gate voltage and the threshold voltage of the transistor.

[0178] In one embodiment, a device comprises: means for providing a first voltage to a first set of bitlines during a sense operation; means for providing a second voltage, lower than the first voltage, to a second set of bitlines during the sense operation; and a common control gate voltage connected to the means for providing the first voltage and the means for providing the second voltage.

[0179] The means for providing the first and second voltages may comprise the control circuits such as the power control module 116 and the column decoder 132 Fig. 1A, the acquisition block 51 from Fig. 1A and Fig. 2 and the detection circuit 400 Fig. 3 or other logical hardware and / or other executable code stored on a computer-readable storage medium. The means for providing the common control gate voltage may comprise the control circuits such as the power control module 116 and the row decoder 124 of Fig. 1A or other logical hardware and / or other executable code stored on a computer-readable storage medium. Other embodiments may include similar or equivalent means.

[0180] The foregoing detailed description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teachings. The described embodiments were chosen in order to best explain the principles of the invention and their practical application, to thereby enable others skilled in the art to best utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto.

Claims

[1] A storage device (100) comprising: a plurality of NAND chains (300n-303n, 310n-313n, 320n-323n, 330n-333n, 412, 1640, 1641, 1642, 1643), each NAND chain having a set of series-connected memory cells among a set of memory cells and one or more select gate transistors at a drain end (390) of the NAND chain; a plurality of bit lines (BL0, BL1, BL2, BL3, 410, 1613b-1614b, 1616b-1617b), each bit line connected to the drain ends of one or more NAND chains of the plurality of NAND chains; a plurality of detection circuits (400, 400a, 400b, 400c, 1611, 1612), each detection circuit being connected to a respective bit line of the plurality of bit lines, each detection circuit comprising a bit line detection, BLC, transistor (404, 1613-1614, 1616-1617) with a source terminal (511, 1613s-1614s, 1616s-1617s) connected to the respective bit line, and by means of the detection circuits it is detectable whether a power current in the respective connected bit line is above or below a predetermined threshold level, wherein control gates (1613g-1614g, 1616g-1617g) of the BLC transistors (1613-1614, 1616-1617) are connected to a common voltage source (1648); wherein the BLC transistors comprise a first set and a second set of BLC transistors, wherein the first set of BLC transistors (1615) includes the BLC transistors (404, 1613-1614) of detection circuits (1611) connected to bit lines connected to the drain ends of a first set of NAND chains (1640, 1641), wherein the second set of BLC transistors (1619) includes the BLC transistors (404, 1616-1617) of detection circuits connected to bit lines connected to the drain ends of a second set of NAND chains (1642, 1643), and wherein the first set of BLC transistors (1615) has a higher threshold voltage than the second set of BLC transistors (1619). [2] A storage device according to claim 1, wherein: Channels (1662) of the first set of NAND chains are wider and / or have a higher doping concentration than channels (1672) of the second set of NAND chains. [3] A storage device according to claim 1 or 2, wherein: the first set of NAND chains (1640, 1641) comprises memory cells assigned to user data; and the second set of memory cells (1642, 1643) comprises memory cells assigned to metadata. [4] A storage device according to claim 3, wherein: the set of memory cells is connected to a set of word lines (WLL0-WLL10); a subset of the memory cells is assigned metadata storage data indicating whether a respective word line of the set of word lines (WLL0-WLL10) has completed programming; wherein the subset of memory cells assigned to metadata are in a relatively high threshold voltage state when programming for the respective word line is completed, and in a relatively low threshold voltage state when programming for the respective word line is not completed. [5] A storage device according to claim 4, wherein: a position of the subset of memory cells assigned to metadata is different in different word lines of the set of word lines (WLL0-WLL10). [6] The storage device of claim 4, further comprising: a control circuit configured to vary a position of the subset of memory cells assigned to the metadata in different wordlines of the set of wordlines (WLL0-WLL10) when a temperature is below a threshold. [7] A storage device according to any one of claims 1 to 6, wherein: the second set of BLC transistors (404, 1616-1617) has a shorter control gate length (L1) and / or a smaller oxide thickness (L2) and / or a smaller oxide dielectric constant and / or a larger source and / or drain doping concentration compared to the first set of BLC transistors (404, 1613-1614). [8] A storage device according to any one of claims 1 to 7, wherein: each BLC transistor (404, 1613-1614, 1616-1617) is configured as a source follower to provide a voltage on a respective NAND chain during a sense operation; and a voltage provided on the respective NAND chains (1642, 1643) of the second set of BLC transistors (1616-1617) is greater than a voltage provided on the respective NAND chains (1640, 1641) of the first set of BLC transistors (1613-1614). [9] Procedure comprising: Applying (1572) a control gate voltage to a set of memory cells connected to a word line (WLL0-WLL10), each memory cell being in a NAND chain of a plurality of NAND chains (300n-303n, 310n-313n, 320n-323n, 330n-333n, 412, 1640, 1641, 1642, 1643), each NAND chain having a drain end (390) and having one or more select gate transistors at the drain end, the drain end (390) of each NAND chain being connected to a respective bit line of a plurality of bit lines (BL0, BL1, BL2, BL3, 410, 1613b-1614b, 1616b-1617b), and wherein detection circuits (400, 400a, 400b, 400c, 1611, 1612) are connected to the bit lines, wherein each detection circuit comprises a bit line detection, BLC, transistor (404, 1613-1614, 1616-1617) with a source terminal (511, 1613s-1614s, 1616s-1617s) connected to the respective bit line and detectable by means of the detection circuits,whether a power current in the respective connected bit line is above or below a predetermined threshold level, wherein control gates (1613g-1614g, 1616g-1617g) of the BLC transistors (1613-1614, 1616-1617) are connected to a common voltage source (1648); and, during the application of the control gate voltage to the set of memory cells, detecting (1573), by the detection circuits (1611, 1612), whether each memory cell is in a conductive or non-conductive state, wherein a first set of the bit lines (1613b-1614b) is detected at a first level and wherein a second set of bit lines (1616b-1617b) is detected at a second level that is greater than the first level, wherein the detecting of the first set of the bit lines (1613b-1614b) at the first level and detecting the second set of bit lines (1616b-1617b) at the second level comprises applying a common control gate voltage to the control gates (1613g-1614g, 1616g-1617g) of the BLC transistors, wherein the BLC transistors comprise a first set of BLC transistors (1613-1614) connected to the first set of bit lines (1613b-1614b) and a second set of BLC transistors (1616-1617) connected to the second set of bit lines (1616b-1617b), and wherein the first set of BLC transistors (1613-1614) has a higher threshold voltage than the second set of BLC transistors (1616-1617). [10] The method of claim 9, wherein: Memory cells connected to the second set of bit lines (1616b-1617b) have metadata that tracks a program pass in a multi-pass program operation and have a relatively high threshold voltage, when the program pass operation in the multi-pass program operation is a final program pass operation, as compared to when the program pass operation is a previous program pass operation in the multi-pass program operation.

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