BANDWIDTH ADJUSTMENT IN A PHASE-LOCKED LOOP OF A LOCAL OSCILLATOR

Abstract

An RF circuit that has the following: a charge pump (68) configured to generate current pulses having a first current amplitude (i CP0 ) and a predetermined duration (T ON ) to generate a capacitive element (C) coupled to the charge pump (68) and configured to receive the current pulses and, depending thereon, to generate a tuning voltage (V TUNE ) to generate an RF oscillator (61) coupled to the capacitive element (C) and configured to generate an RF signal (s LO (t)) with a frequency (f LO ) which is dependent on the tuning voltage (V FINE ) depends; a measuring circuit (63; 71) which is designed to generate a measuring signal (V1, V2, V 2A , V 2B , f1, f2) which determines the tuning voltage (V FINE ) or the frequency (f LO ) of the RF signal (s LO (t)) represents; a controller circuit (50) coupled to the charge pump (68) and the measuring circuit (63; 71) and configured to: to control the charge pump (68) in such a way as to obtain the first amplitude (i CP0 ) of a current pulse by a current difference (Δi; Δi A , Δi B ) and a first change (ΔV1; Δf1) of the measurement signal, which is a reaction to a first current pulse of the current pulses with the first current amplitude (i CP0 ) and a second change (ΔV2; ΔV 2A , ΔV 2B ; Δf2) of the measurement signal, which is a reaction to a second current pulse of the current pulses with changed current amplitude (i CP0 +Δi) is to be determined, and based on the first change (ΔV1; Δf1) of the measurement signal and the second change (ΔV2; ΔV 2A , ΔV 2B ; Δf2) of the measuring signal and the current difference (Δi) a measured value for the first amplitude (i CP0 ) to calculate.

Description

TECHNICAL FIELD

[0001] The present description relates to the field of radar sensors, in particular to a phase-locked loop with a voltage-controlled oscillator (VCO) for generating an RF oscillator signal. BACKGROUND

[0002] Radio frequency (RF) transmitters and receivers are found in a wide variety of applications, particularly in wireless communications and radar sensors. In the automotive sector, there is a growing demand for radar sensors, which can be used in, among other things, advanced driver assistance systems (ADAS) such as adaptive cruise control (ACC, or radar cruise control) systems. Such systems can automatically adjust the speed of a vehicle in order to maintain a safe distance from other vehicles ahead (as well as from other objects and pedestrians). Other applications in the automotive sector include blind spot detection, lane change assist, and the like.

[0003] Modern radar systems use highly integrated RF circuits that can contain all core functions of a radar transceiver's RF front end in a single chip package (single-chip transceiver). Such RF front ends can include, among other components, an RF local oscillator (LO), power amplifiers, low-noise amplifiers (LNA), or mixers.

[0004] Frequency-modulated continuous-wave (FMCW) radar systems use radar signals containing sequences of so-called chirps. To generate such chirps, the radar device may include a local oscillator comprising a VCO arranged in a phase-locked loop (PLL). The frequency of the VCO is adjusted via a control voltage, which can be tuned by adjusting the frequency division ratio of a frequency divider in the PLL's feedback loop. An example of such a VCO connected in a phase-locked loop and a method for calibrating its bandwidth are described in publication US20070247235A1, wherein the calibration of the bandwidth is performed by adjusting the current of a charge pump included in the phase-locked loop.To keep the phase noise of the local oscillator output signal within specified limits, the PLL bandwidth can be designed according to these specified limits. However, this PLL bandwidth generally depends on parameters that are subject to some variation due to tolerances in the manufacturing process. SUMMARY

[0005] An RF circuit is described below. According to one embodiment, the RF circuit comprises a charge pump configured to generate current pulses with a first current amplitude and a predetermined duration. The RF circuit further comprises a capacitive element coupled to the charge pump and configured to receive the current pulses and, depending thereon, to generate a tuning voltage. An RF oscillator is coupled to the capacitive element and configured to generate an RF signal with a frequency that depends on the tuning voltage. The RF circuit further comprises a measuring circuit configured to generate a measurement signal that represents the tuning voltage or the frequency of the RF signal.A controller circuit is coupled to the charge pump and the measuring circuit and is configured to control the charge pump to change the first amplitude of a current pulse by a current difference. The controller circuit is further configured to determine a first change in the measurement signal, which is a reaction to a first current pulse of the current pulses with the first current amplitude, as well as a second change in the measurement signal, which is a reaction to a second current pulse of the current pulses with a changed current amplitude. Based on the first change in the measurement signal and the second change in the measurement signal, and based on the current difference, a measured value for the first amplitude can be calculated.

[0006] Furthermore, a method is described which, according to one embodiment, comprises the following: generating current pulses with an adjustable current amplitude and a predetermined, defined duration by means of a charge pump, wherein the generation of current pulses comprises generating a first current pulse with a first amplitude and generating a second current pulse with a second amplitude that differs from the first amplitude by a current difference; and converting the current pulses into a tuning voltage for an RF oscillator such that the tuning voltage changes in response to each current pulse depending on its amplitude. The frequency of the RF oscillator depends on the tuning voltage.The method further comprises generating a measurement signal representing the tuning voltage or the frequency of the RF oscillator; determining a first change in the measurement signal in response to the first current pulse and a second change in the measurement signal in response to the second current pulse; and calculating the first amplitude based on the current difference as well as the first change in the measurement signal and the second change in the measurement signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The following examples are explained in more detail using illustrations. The illustrations are not necessarily to scale, and the examples are not limited to the aspects shown. Rather, emphasis is placed on illustrating the principles underlying the examples. The illustrations show: Fig. Figure 1 is a sketch illustrating the operating principle of an FMCW radar system for distance and / or speed measurement. Fig. Figure 2 includes two timing diagrams illustrating the frequency modulation (FM) of the RF signal generated by the FMCW system. Fig. Figure 3 is a block diagram illustrating the basic structure of an FMCW radar system. Fig. Figure 4 is a block diagram illustrating an example of an integrated RF front-end circuit of a radar chip including analog baseband signal processing. Fig. Figure 5 is a block diagram illustrating a first example of a local oscillator with a VCO connected in a phase-locked loop. Fig. 6 is a block diagram illustrating a second example of a local oscillator with a VCO connected in a phase-locked loop. Fig. Figure 7 shows an exemplary timing diagram of a concept for iteratively adjusting the voltage for coarse tuning of the VCO. Fig. 8 illustrates an exemplary implementation of the phase-locked loop from Fig. 5 in more detail, where the bandwidth of the phase-locked loop can be adjusted by changing the magnitude of the output current of the charge pump. Fig. Figure 9 illustrates an exemplary implementation of a charge pump used in the phase-locked loop according to Fig. 8 can be used. Fig. Figure 10 shows a part of the phase-locked loop (open loop) used to measure the output current of the phase-locked loop charge pump. Fig. Figure 11 shows exemplary timing diagrams of the response of the input voltage at the VCO to a current pulse of the charge pump of the phase-locked loop for different peak values ​​of the current pulses. Fig. 12 is an exemplary timing diagram showing an alternative approach to Fig. 11 illustrated. Fig. 13 and Fig. 14 show an alternative to Fig. 10 or 11. Fig. Figure 15 shows exemplary timing diagrams of the responses of the input voltage at the VCO to several current pulses of the charge pump of the phase-locked loop for different peak values ​​of the current pulses. Fig. 16 is a flowchart illustrating an example of the method described herein. Fig. 17 is a flowchart illustrating another example of the method described herein. DETAILED DESCRIPTION

[0008] Fig. Figure 1 illustrates, in a schematic diagram, the application of an FMCW radar system as a sensor for measuring distances and speeds of objects, commonly referred to as radar targets. In the present example, the radar device 10 has separate transmitting (TX) and receiving (RX) antennas 5 and 6, respectively (bistatic or pseudo-monostatic radar configuration). However, it should be noted that a single antenna can also be used, serving simultaneously as a transmitting antenna and a receiving antenna (monostatic radar configuration). The transmitting antenna 5 radiates a continuous RF signal s RF (t), which is frequency-modulated, for example, with a type of sawtooth signal (periodic, linear frequency ramp). The emitted signal s RF (t) is backscattered at the radar target T and the backscattered / reflected signal y RF (t) is received by the receiving antenna 6. Fig. 1 shows a simplified example; in practice, radar sensors are systems with multiple transmit (TX) and receive (RX) channels to also determine the angle of arrival (Direction of Arrival, DoA) of the backscattered / reflected signal y RF (t) and thus to be able to locate the radar target T more precisely.

[0009] Fig. 2 illustrates the mentioned frequency modulation of the signal s RF (t). As in Fig. 2 (upper diagram), the radiated RF signal s RF (t) is composed of a set of “chirps”, ie the signal s RF (t) comprises a sequence of sinusoidal waveforms with increasing frequency (up-chirp) or decreasing frequency (down-chirp). In this example, the instantaneous frequency f(t) of a chirp increases starting from a starting frequency f START within a time period T RAMP linear to a stop frequency f STOP(see diagram below in Fig. 2). Such chirps are also called linear frequency ramps. Fig. 2 shows three identical linear frequency ramps. However, it should be noted that the parameters f START , F STOP , T RAMP and the pause between the individual frequency ramps can vary. The frequency variation does not necessarily have to be linear (linear chirp). Depending on the implementation, transmit signals with exponential or hyperbolic frequency variation (exponential or hyperbolic chirps, respectively) can also be used.

[0010] Fig. Figure 3 is a block diagram illustrating an exemplary possible structure of a radar device 1 (radar sensor). Accordingly, at least one transmitting antenna 5 (TX antenna) and at least one receiving antenna 6 (RX antenna) are connected to a chip-integrated RF frontend 10, which may contain all the circuit components required for RF signal processing. These circuit components include, for example, a local oscillator (LO), RF power amplifiers, low-noise amplifiers (LNAs), directional couplers (e.g., rat-race couplers, circulators, etc.), and mixers for downconverting the RF signals to the baseband or an intermediate frequency band (IF band). The RF frontend 10 may be integrated—possibly together with other circuit components—in a chip, which is typically referred to as a monolithically integrated microwave circuit (MMIC).

[0011] The example shown shows a bistatic (or pseudo-monostatic) radar system with separate RX and TX antennas. In a monostatic radar system, a single antenna would be used for both transmitting and receiving the electromagnetic (radar) signals. In this case, a directional coupler (e.g., a circulator) can be used to separate the radiated RF signals from the received RF signals (radar return signals). As mentioned above, radar systems in practice usually have multiple transmit and receive channels (TX / RX channels) with multiple TX and RX antennas, which, among other things, enables measurement of the direction of arrival (DoA) from which the radar returns are received. In such MIMO systems, the individual TX channels and RX channels are usually identical or similar in design.

[0012] In the case of an FMCW radar system, the RF signals radiated via the TX antenna 5 can, for example, be in the range of approximately 20 GHz to 100 GHz (e.g., around 77 GHz in some applications). As mentioned, the RF signal received by the RX antenna 6 includes the radar echoes (chirp echo signals), i.e., those signal components that are backscattered by one or more radar targets. The received RF signal y RF (t) is, for example, down-converted to the baseband (or an IF band) and further processed in the baseband using analog signal processing (see Fig. 3, analog baseband signal processing chain 20). The analog signal processing essentially comprises filtering and, if necessary, amplification of the baseband signal. The baseband signal is finally digitized (see Fig. 3, analog-to-digital converter 30) and further processed in the digital domain. The digital signal processing chain can be implemented at least partially as software, which is executed on a processor, for example a microcontroller or a digital signal processor (see Fig. 3, DSP 40). The overall system is typically controlled by a system controller 50, which may also be implemented at least partially as software executing on a processor such as a microcontroller. The RF frontend 10 and the analog baseband signal processing chain 20 (optionally also the analog-to-digital converter 30) may be integrated together in a single MMIC (i.e., an RF semiconductor chip). Alternatively, the individual components may also be distributed across multiple integrated circuits.

[0013] Fig. 4 illustrates an exemplary implementation of a radar transceiver 1 according to the example of Fig. 3 in more detail. In the present example, the RF frontend 10 of the radar transceiver 1 and the subsequent signal processing in the baseband are shown. It should be noted that Fig. Figure 4 illustrates a simplified circuit diagram to show the basic structure of the RF front-end 10 with one TX channel and one RX channel. Actual implementations, which may depend heavily on the specific application, can of course be more complex and typically feature multiple TX and / or RX channels.

[0014] The RF frontend 10 comprises a local oscillator 101 (LO) which generates an RF oscillator signal s LO (t). The RF oscillator signal s LO (t) is in radar operation, as described above with reference to Fig. 2, is frequency-modulated and is also referred to as an LO signal. In radar applications, the frequency f LO of the LO signal s LO (t) usually in the SHF (Super High Frequency, centimeter wave) or EHF (Extremely High Frequency, millimeter wave) band, e.g., in the interval from 76 GHz to 81 GHz in some automotive applications. The LO signal s LO (t) is processed in both the transmit signal path TX01 (in the TX channel) and the receive signal path RX01 (in the RX channel). The local oscillator 101 typically includes a VCO (see also Fig. 5), which is connected in a phase-locked loop (PLL).

[0015] The transmission signal s RF (t) (cf. Fig. 2), which is radiated by the TX antenna 5, is generated by amplifying the LO signal s LO (t), for example by means of the RF power amplifier 102, and is thus merely an amplified version of the LO signal s LO(t). The output of amplifier 102 can be coupled to the TX antenna 5 (in the case of a bistatic or pseudo-monostatic radar configuration). The received signal y RF (t), which is received by the RX antenna 6, is fed to the receiver circuit in the RX channel and thus directly or indirectly to the RF port of the mixer 104. In the present example, the RF reception signal y RF (t) (antenna signal) is pre-amplified by amplifier 103 (gain g). The mixer 104 receives the amplified RF reception signal g·y RF (t). The amplifier 103 can be an LNA, for example. The reference port of the mixer 104 is connected to the LO signal s LO (t) so that the mixer 104 receives the (pre-amplified) RF signal y RF (t) into the baseband. The down-converted baseband signal (mixer output signal) is BB (t). This baseband signal y BB(t) is first processed in analog form, with the analog baseband signal processing chain 20 essentially providing amplification and (e.g., bandpass or lowpass) filtering to suppress unwanted sidebands and image frequencies. The resulting analog output signal, which is fed to an analog-to-digital converter (see Fig. 3, ADC 30) is denoted by y(t). Methods for the digital processing of the digitized output signal (digital radar signal y[n]) for the detection of radar targets are known per se (e.g., range Doppler analysis) and will therefore not be discussed further here.

[0016] In the present example, the mixer 104 mixes the pre-amplified RF reception signal g y RF(t) (i.e., the amplified antenna signal) down to the baseband. The mixing can be performed in one stage (i.e., from the RF band directly to the baseband) or via one or more intermediate stages (i.e., from the RF band to an intermediate frequency band and further to the baseband). In this case, the receive mixer 104 effectively comprises several individual mixer stages connected in series. Given the Fig. 4 shows that the quality of a radar measurement strongly depends on the quality of the LO signal s LO (t), among other things, by the LO signal s LO (t). This noise is quantitatively determined by the phase noise of the local oscillator 101 and consequently by the bandwidth of the phase-locked loop.

[0017] Fig. 5 shows a block diagram of an exemplary implementation of a local oscillator, which is used, for example, in the RF frontend 10 of Fig. 4 can be used. According to Fig. 5, the local oscillator 101 comprises a VCO 61 which is designed to generate an RF oscillator signal s LO (t) (ie the LO signal) whose frequency f LO depends on one or more input voltages (tuning voltages). The frequency f LO is typically a non-linear function of the input voltage(s). In the example shown, the VCO 61 has a first input for supplying a first voltage V COARSE for coarse tuning of the VCO 61 and a second input for supplying a second voltage V FINE for fine tuning the VCO 61. In the example shown, the first voltage V COARSE (coarse tuning voltage) from a digital-to-analog converter 62 (DAC) according to a digital word x COARSE generated, whereas the second voltage V FINE(Fine-tuning voltage) is output by the feedback network 60 (phase / frequency feedback of the PLL). The fine-tuning voltage V FINE is therefore an output of the feedback network 60 and simultaneously an input voltage of the VCO 61. The VCO 61 and the feedback network 60 together form the closed phase-locked loop (PLL). It should also be noted that the DAC 62 is used to generate the coarse tuning voltage V COARSE is optional and can be omitted in some embodiments. In these cases, coarse tuning of the VCO is not necessary or is implemented in a different way, and the VCO only has one input for the fine tuning voltage V FINE on (cf. Fig. 12 and associated description).

[0018] For each of the input voltages V FINE , V COARSE can be an associated VCO gain (VCO gain) f LO / V FINE or f LO / V FINE The derivatives ∂f LO / ∂V FINE or ∂f LO / ∂V FINE are called differential VCO gains. In the following discussion, the ratio f LO / V FINE as VCO gain K VCO and the derivative ∂f LO / ∂V FINE is called differential VCO gain kvco. Both values ​​K VCO and kvco are generally frequency dependent. Furthermore, the VCO gain K VCO and the differential VCO gain kvco are temperature dependent and can also be influenced by aging effects.

[0019] The one in the example from Fig. 5 used VCO 61 has two VCO gains f LO / V COARSE and f LO / V FINEIn this example, the VCO 61 contains two different varactor diodes, whose characteristics determine the VCO gain. Various suitable implementations of the VCO 61 are known per se and therefore will not be discussed in detail here. Fig. Figure 6 illustrates another example of a local oscillator 101 with a phase-locked loop. Unlike the previous example, in this example the VCO 61 has only one input, to which the voltage V CTL which corresponds to the sum V COARSE +V FINE In this case, the VCO only has a VCO gain f LO / V CTL For the corresponding differential VCO gain ∂f LO / ∂V CTL applies k VCO = ∂f LO / ∂V CTL = ∂f LO / ∂V FINE = ∂f LO / ∂V COARSE . Apart from the implementation of the VCO, the example from Fig. 6 identical to the previous example from Fig. 5 and reference is made to the above description.

[0020] In the examples from Fig. 5 and Fig. 6 is the setpoint for the frequency f LO on the one hand by the frequency f REF a reference signal s REF (t) and on the other hand by adjusting the division ratio of a frequency divider in the feedback path 60 of the phase-locked loop, this division ratio being dependent on the digital signal x TUNE This mechanism will be discussed later in relation to Fig. 8. The reference signal s REF (t) can be generated, for example, by means of a clock generator (not shown), which can, for example, contain a crystal that determines the frequency f REF The frequency f REF a reference signal s REF (t) can be in the range of several hundred MHz (e.g. 200 MHz).

[0021] The digital signal x COARSE, which is fed to the DAC 62, can be, for example, from the system controller 50 (cf. Fig. 3) or another controller circuit. The feedback network 60 of the phase-locked loop is designed to provide the fine-tuning voltage V FINE so that the frequency f LO of the LO signal s LO (t) the (from the digital signal x TUNE dependent) setpoint. The fine-tuning voltage V FINE can only be varied within a specific interval (e.g. 0 to 3V). The size of this interval depends on the implementation of the VCO 61 and the feedback network 60. According to the (frequency-dependent) differential VCO gain k VCO =∂f LO / ∂V FINE This interval corresponds to a frequency range of e.g. 1500 MHz (frequency ramps over e.g. 200MHz-4000MHz are also possible), within which the frequency f LO of the LO signal s LO(t) by varying the fine-tuning voltage V FINE can be adjusted. That is, the frequency f LO of the LO signal s LO (t) can (with appropriate setting of the coarse tuning voltage V COARSE ) can be fine-tuned, for example, in the range from 76 GHz to 77.5 GHz. If a different tuning range is desired (e.g. 79 GHz to 80.4 GHz), the coarse tuning voltage V COARSE The numerical values ​​provided are for illustrative purposes only and depend heavily on the actual implementation.

[0022] As mentioned, the VCO gain K VCO and the differential VCO gain kvco also depends on the temperature. To generate a specific sequence of frequency ramps (chirps) with a start frequency f1 and a stop frequency f2, the coarse tuning voltage V COARSE set and then the frequency f LO by changing the fine-tuning voltage V FINEfrom a first value V FINE = V1 to a second value V FINE = V2. The latter is achieved with the help of the phase-locked loop. The frequency f generated by the VCO 61 LO changes from the start frequency f1 to the stop frequency f2. The modulation of the frequency f LO is not directly affected by a change in the fine-tuning voltage V FINE The controller 50 can change the (digital) signal x TUNE [n] the effective division ratio of the frequency divider 66 (see also Fig. 8), which in turn causes a change in the frequency f fed back into the phase-locked loop PLL This change can be compensated by feedback by adjusting (using a phase detector, charge pump and loop filter) the fine-tuning voltage V FINE In the steady state of the PLL, the frequency f LOonly from the usually constant reference frequency f REF and the effective division ratio of the frequency divider 66 (see also Fig. 8), which is transmitted via the signal x TUNE [n] can be set. The current value of the fine-tuning voltage V FINE is generated “automatically” as the output signal of the PLL and also depends on the temperature-dependent VCO gain and the currently set value of the coarse tuning voltage V COARSE away.

[0023] When coarse tuning the VCO, the temperature dependence of the VCO gain K VCO must be taken into account to ensure that the voltage range from V1 to V2 required for a desired frequency ramp (from f1 to f2) does not leave the interval (e.g. 0 to 3V) within which the voltage V FINE can be varied. For example, for a given value of the coarse tuning voltage V COARSEand a desired frequency ramp (e.g. f1=76 GHz and f2=77.5 GHz) may be necessary, the fine-tuning voltage V FINE from V1=0.6 V to V2=2.7 V. A temperature change can shift V1 and V2 by, for example, 0.5 V. However, the voltage value V2 = 2.7 V + 0.5 V is outside the fine-tuning range. Consequently, an adjustment of the coarse tuning voltage V COARSE necessary.

[0024] To adjust the coarse tuning voltage V COARSE during operation, the coarse tuning can be done in such a way that for the starting frequency f1 of a frequency ramp the fine tuning voltage V FINE assumes a predefined setpoint (independent of the current temperature). In the case of a frequency ramp with increasing frequency (up-chirp), for example, during a tuning phase, the coarse tuning voltage V COARSE be varied until the fine-tuning voltage V FINEa defined setpoint of e.g. V1=0.6 V. The fine-tuning voltage V FINE measured by an ADC 63 and the resulting digital value is fed to the controller 50. For a frequency ramp with a falling frequency, the setpoint for the fine-tuning voltage V FINE be higher, e.g. V2=2.4 V.

[0025] Varying the coarse tuning voltage V COARSE can be done using known iteration methods, e.g. successive approximation (see Fig. 7). While the coarse tuning voltage V COARSE is iteratively adjusted, the phase-locked loop 60 is active; the feedback network 60 of the phase-locked loop controls the fine-tuning voltage V FINE so that during this tuning phase the LO frequency f LO remains essentially constant (apart from short, transient variations).

[0026] According to the Fig. In the example shown in Figure 7, the voltage VCOARSE initially set to an initial value of, for example, 0.8 V. The feedback network 60 then regulates the voltage V FINE to a value (e.g. 0.9 V) so that the frequency f LO corresponds to the desired frequency f1. This value of the voltage V FINE is greater than the desired setpoint V1, which is why the voltage V COARSE is gradually increased. Due to the feedback in the phase-locked loop, the voltage V FINE below the setpoint V1, which is why the voltage V COARSE is reduced again (by a reduced voltage swing) until the voltage V FINE rises above the setpoint V1 again, etc. The voltage V FINE thus gradually approaches the setpoint V1. The corresponding coarse tuning voltage V COARSE is obtained “automatically” as a result of the successive approximation. At the end of the tuning phase, V FINE≈V1, where the setpoint V1 no longer depends (or only very weakly) on the temperature. The temperature dependence and other cross-sensitivities are compensated by iteratively adjusting the coarse tuning voltage V COARSE compensated. Successive approximation is a well-known iteration method and will therefore not be discussed further here. Other methods for setting the coarse tuning voltage V COARSE possible.

[0027] Fig. Figure 8 shows an example of an implementation of the phase-locked loop (PLL) in more detail. In the illustrated example, the feedback network 60 of the phase-locked loop comprises a frequency divider 65 with a fixed division ratio M and a multi-modulus divider 66 (multi-modulus divider, MMD) with an adjustable (integer) division ratio N. The overall division ratio is therefore N*M. This division ratio N can be varied, for example, by means of a sigma-delta modulator 64, so that effectively a non-integer division ratio R is achieved, which essentially depends on the digital signal x TUNEwhich is fed to the sigma-delta modulator 64 as the input signal. The combination of multi-modulus divider 66 and sigma-delta modulator 64 is known as a "fractional-N divider" and will therefore not be explained in detail here. It should be noted that the frequency divider 65 with a fixed division ratio is optional (i.e., the fixed division ratio M can be 1). Furthermore, the order of the frequency dividers 65 and 66 can be reversed.

[0028] In the example shown, the output signal of the MMD 66 is s PLL (t). This output signal s PLL (t) has a frequency f PLL and the ratio f LO / f PLL corresponds to the effective division ratio R=M·x TUNE [n] of the two frequency dividers 65 and 66. The frequency f PLL is detected in a phase detector (also called phase-frequency detector) 67 with the frequency f REF a reference signal sREF (t) (clock signal). The output signal of the phase-frequency detector 67 depends on the comparison result and drives a charge pump 68, whose output current i CP depends on whether the frequency and phase of the signal s PLL (t) and the reference signal s REF (t) differ from each other (see Fig. 9 and the corresponding description). The output current i CP is fed to the so-called loop filter 69, which finally produces the fine-tuning voltage V FINE according to a transfer function H(s). The structure and operation of a phase-locked loop for generating a frequency-modulated RF signal is known per se and will therefore not be explained in detail here. Unlike conventional implementations, however, the bandwidth of the phase-locked loop can be changed, for example, by adjusting the magnitude of the output current i CP the charge pump 68.

[0029] For the following discussion, the coarse tuning voltage V COARSE is assumed to be constant and the differential VCO gain kvco is given as ∂f LO / ∂V FINE The open-loop transfer function L(s) of the phase-locked loop can be given as follows: L(s)=1skVCO⋅iCP0RH(s) where i CP is the magnitude of the output current of the charge pump 68. For example, the output current i CP depending on the output signal of the phase-frequency detector 67 equal to +i CP0 or -i CP0 be (cf. Fig. 9).

[0030] The closed-loop transfer function G(s) of the phase-locked loop can be calculated as follows: G(s)=L(s)1+L(s).

[0031] The bandwidth of the closed-loop transfer function G(s) depends on the parameters kvco (differential VCO gain), i CP0(magnitude of the charge pump output current) and R (real division ratio f PLL / f LO ) and the transfer function H(s) of the loop filter 68.

[0032] Fig. Figure 9 shows a simple example of a charge pump 68. This comprises a current source Q1 and a second current sink Q2, as well as a first switch SW1 and a second switch SW2. The switch SW1 connects the current source Q1 to an output node of the charge pump 68, and the switch SW2 connects the current sink Q2 to the output node. A capacitor C is coupled to the output node and is configured to store the charge supplied by the current source Q1 or the current sink Q2. The voltage V CP across the capacitor C is proportional to the stored charge. The switches SW1 and SW2 of the charge pump 68 are controlled by the output signals UP, DOWN, which are generated, for example, by the phase detector 67 (see Fig. 8) are generated as output signals or derived from its output signal. If the phase of the signal s PLL (t) is smaller than the phase of the reference signal s REF (t), then the switch SW1 is switched on by the signal UP (generated by the phase detector 67) (for a certain switch-on time T ON1 ) and the output current i CP the charge pump is +i CP0 ; the corresponding charge is i CP0 ·T ON1 . Similarly, if the phase of the signal s PLL (t) is greater than the phase of the reference signal s REF (t), the switch SW2 is switched on by the signal DOWN (generated by the phase detector 67) (for a certain switch-on time T ON2 ) and the output current i CP the charge pump is -i CP0 ; the corresponding charge is -i CP0 ·T ON2 . The switching times T ON1 and T ON2 can be proportional to the respective phase difference (between sPLL (t) and s REF (t)). The loop filter 69 filters the resulting voltage signal V CP ; the filtered signal is the fine-tuning voltage V FINE .

[0033] The structure and function of the charge pump 68 is known per se and will therefore not be explained further here. Unlike conventional implementations, the current source Q1 and the current sink Q2 are controllable, ie, the amount i CP0 of the output current is adjustable. As explained above, the bandwidth of the phase-locked loop depends on the amount i CP0 of the output current of the charge pump. As mentioned, the bandwidth of the phase-locked loop, which is included in the LO signal s LO(t) contains phase noise, which influences the radar system's background noise and thus also the detectability of radar targets and the detection reliability. Typically, a radar sensor must meet certain specifications regarding phase noise. However, the actual current value i CP0 may deviate from a desired setpoint due to tolerances in the manufacturing of the integrated charge pump circuit. Furthermore, the current value i CP0 fluctuate due to temperature changes.

[0034] In the following, a concept is explained that allows the current amount i to be adjusted in the chip in which the local oscillator 101 is integrated (e.g. in the MMIC in which the RF front end of the radar transceiver is integrated). CP0 to be determined through measurements and calibrated based on these measurements. Fig. 10 illustrates that part of the feedback network 60 of the phase-locked loop from Fig. 8, which is used for the measurement. The control loop is open during the measurement, ie there is no feedback of the LO frequency f LO to the phase detector 67, and the charge pump 68 is controlled directly by the controller 50 (and the output of the phase detector is ignored). The operation of the circuit from Fig. 10 in the trade fair operation is explained below using the time diagrams from Fig. 11. First, the coarse tuning voltage V COARSE - with a closed phase-locked loop - be adjusted so that the fine-tuning voltage V FINE assumes a defined initial value V0. This can be done by referring to Fig. 7 can be used. However, the actual value of V0 is not important for the subsequent steps and therefore the (e.g. iterative) adjustment of the coarse tuning voltage V COARSE also be omitted and the coarse tuning voltage V COARSEbe set to a predefined value.

[0035] In the next step, the controller 50 - ie with the phase locked loop open - causes the charge pump 68 to output i CP (t) a first current pulse with a defined pulse length T ON =t2-t1 and a defined first amplitude i CP0 Such a current pulse is shown in the right diagram of the Fig. 11 (dashed line, current amplitude i CP0 ). In response to the first current pulse, the fine-tuning voltage V FINE by a first voltage difference ΔV1 (V1=V0+ΔV1). This voltage difference ΔV1 can be calculated (for a steady state) as follows ΔV1=1C∫t1t2iCP(t)dt=1CiCP0TON, where C is the effective capacitance at the output of the charge pump 68 (and thus also at the input of the loop filter 69). The response of the fine-tuning voltage V FINEto the first current pulse, the left diagram shows the Fig. 10 (dashed signal waveform). The effective capacitance C is any capacitance that the charge pump 68 "sees" at its output. In the steady state (i.e., after all transient events have subsided), the loop filter 68 behaves like a capacitive element and can therefore be considered as a capacitance C representing the sum of all individual capacitances in the loop filter (i.e., between the charge pump and the VCO).

[0036] A second measurement is then carried out, whereby the charge pump 68 is controlled in such a way that the output signal i CP (t) a second current pulse with the defined pulse length T ON and a defined second amplitude i CP0 +Δi is output. In the Fig. 11, the fine-tuning voltage V FINE by adjusting the coarse tuning voltage VCOARSE back to the value V FINE =V0 (cf. Fig. 7), which is not necessary (cf. Fig. 12). In response to the second current pulse, the fine-tuning voltage V FINE by a second voltage difference ΔV2 (V2=V0+ΔV2). This voltage difference ΔV2 can be calculated as follows ΔV2=1C∫t1t2iCP(t)dt=1C(iCP0+Δi)TON.

[0037] The response of the fine-tuning voltage V FINE The diagram on the left shows the second current pulse. Fig. 10 (solid signal curve). For both measurements, the response of the voltage V FINE e.g., measured by means of the analog-to-digital converter 63. The controller 50 can, based on the change in the (digitized) voltage V FINE determine the voltage differences ΔV1 and ΔV2.

[0038] From the voltage differences ΔV1 and ΔV2 - with a known amplitude difference Δi - the first amplitude i CP0The ratio ΔV2 / ΔV1 can be calculated: ΔV2ΔV1=(iCP0+Δi) / iCP0=1+Δi / iCP0, and from the ratio ΔV2 / ΔV1 follows the transformation of equation 5 Δi=iCP0(ΔV2ΔV1−1), and iCP0=ΔiΔV2ΔV1−1=Δi⋅ΔV1ΔV2−ΔV1.

[0039] The calculations necessary for the evaluation of equation 7 can be carried out, for example, by a computing unit contained in the controller 50 (e.g., a processor, a microcontroller, a CPU, etc.).

[0040] Optionally, the effective capacitance C can be determined from the voltage differences ΔV1 and ΔV2. The capacitance C follows directly from the difference ΔV2-ΔV1, according to the following equations ΔV2−ΔV1=1CTONΔi C=TONΔiΔV2−ΔV1.

[0041] The example from Fig. 12 differs from the example in Fig. 11 only in that the fine-tuning voltage is not reset to V0 before the second current pulse. In this example, the coarse tuning of the VCO, i.e., the adjustment of the VCO's operating point, can be omitted. However, the voltage differences ΔV1 and ΔV2 do not depend significantly on the output voltage V0, so the determination of the first amplitude i CP0 in the example of Fig. 12 does not change. For the pulse length of the current pulses from Fig. 12 Ton=t2-t2=t4-t3.

[0042] The Fig. 13 and Fig. 14 show an alternative to the example according to Fig. 10 and Fig. 11. The circuit according to the example from Fig. 13 is essentially the same as the circuit according to the example from Fig. 10 except that the voltage measurement using the ADC 63 is replaced by a frequency measurement (see Fig. 13, frequency measuring circuit 71). Since a change in the voltage V FINEat the VCO input and a change in frequency f LO directly related to the differential VCO gain kvco, the functions of the circuits are Fig. 10 and Fig. 13 is essentially equivalent. The following approximation applies to the differential VCO gain kVCO=∂fLO∂VFINE≈Δf1ΔV1≈Δf2ΔV2, and consequently, the voltage differences ΔV1 and ΔV2 in equations 7 and 9 can be expressed as follows: ΔV1=Δf1 / kVCO and ΔV2=Δf2 / kVCO.

[0043] A substitution of ΔV1 and ΔV2 (according to equation 11) in equation 7 results in (constant k VCO shortens away) iCP0=ΔiΔf2Δf1−1=Δi⋅Δf1Δf2−Δf1, and a substitution of ΔV1 and ΔV2 in equation 9 gives C=kVCOTONΔiΔf2−Δf1

[0044] To calculate the capacity (equation 13), the VCO gain k VCOin the frequency range under consideration must be known or also measured. The calculation of the desired first amplitude i CP0 (Equation 12) the VCO gain k flows VCO However, the right diagram in Fig. 14 shows the same current pulses as Fig. 11. The left diagram in Fig. 14 shows the response of the LO frequency f LO to the first current pulse; ie the LO frequency f LO increases in response to the first current pulse with amplitude i CP0 by a first frequency difference Δf1 (f1=f0+Δf1) and in response to the second current pulse with amplitude i CP0 +Δi by a second frequency difference Δf2 (f2=f0+Δf2). Between measurements, the output frequency f LO of the VCO can be regulated back to the output value f0 (frequency f0 corresponds to a voltage V FINE =V0, cf. Fig. 7). Alternatively, the frequency can be adjusted - analogous to the example from Fig. 12. This is possible as long as the VCO gain kvco does not change significantly between the values ​​f0 and f2. In practice, this is usually the case, since only small frequency changes are considered. Furthermore, the measurement can be performed in a frequency range in which the change ∂k VCO / ∂f of the VCO gain kvco is comparatively small. The frequency measurement can be carried out, for example, using a counter that counts the periods of the LO signal (e.g., after a frequency division of 65, see Fig. 13) within a specific time window. These and other frequency measurement techniques are well known and therefore will not be discussed in detail here.

[0045] The measurement of the first amplitude i CP0 allows offset correction. Assume the measured value for i CP0 deviates by an offset i OF from a desired setpoint i CP,D from (i CP0 = i CP,D +iOF ), then the controller 50 can control the charge pump so that the amplitude of the current pulses is increased by the value i OF is smaller than in the previous measurement, which corrects the offset error (i OF can also be negative).

[0046] Fig. 15 shows, using exemplary time diagrams, the repeated execution of measurements from Fig. 11. In a first measurement, the charge pump is again supplied with a current amplitude i CP0 operated; in a second measurement, a (changed) current amplitude i CP0 +Δi A and in a third measurement a current amplitude i CP0 +Δi B The resulting voltage changes are expressed as ΔV1 (at a current amplitude i CP0 ), ΔV 2A (at a current amplitude i CP0 +Δi A ) and ΔV 2B (at a current amplitude i CP0 +Δi B). Analogous to equation (7) one obtains (with Δi=Δi A and ΔV2=ΔV 2A ) iCP0=ΔiAΔV2AΔV1−1=ΔiA⋅ΔV1ΔV2A−ΔV1, and iCP0=ΔiBΔV2BΔV1−1=ΔiB⋅ΔV1ΔV2B−ΔV1.

[0047] Since both equations 14 and 15 must yield the same result, the following applies: ΔiAΔV1ΔV2A−ΔV1=ΔiBΔV1ΔV2B−ΔV1.

[0048] Assuming error-prone amplitude differences Δi A and Δi B (constant error Δi ERR ) ΔiA=ΔiAD+ΔiERR, and ΔiB=ΔiBD+ΔiERR, ie the amplitude differences Δi A and Δi B each by an error Δi ERR from the corresponding setpoints Δi AD and Δi BD deviate, follows from equation 16: (ΔiAD+ΔiERR)KA=(ΔiBD+ΔiERR)KB, where KA=ΔV1ΔV2A−ΔV1 and KB=ΔV1ΔV2B−ΔV1.

[0049] The parameters K A and K Brepresent the measured values ​​ΔV1, ΔV 2A and ΔV 2B . The error Δi ERR follows from equation 18: ΔiERR=(ΔiBDKB−ΔiADKA) / (KA−KB).

[0050] An additional measurement with a changed amplitude difference (Δi B instead of Δi A ) allows a determination of the current error (differential error) Δi ERR . As an alternative to the above calculation from Equation 18, a constant percentage error can also be assumed. In this case, the following relationship is obtained instead of Equation 18: (ΔiAD(1+p / 100))KA=(ΔiBD(1+p / 100))KA, with the percentage error p. Rearranging equation 21 leads to p=100(ΔiBDKB−ΔiADKA)(ΔiADKA−ΔiBDKB).

[0051] For small (percentage) errors, Δi ERR ≈ Δi AD (1 + p / 100) ≈ Δi BD(1 + p / 100) and both approaches lead to virtually the same results. The measured differential error Δi ERR also allows a correction of the output current of the charge pump 68 (see Fig. 10), e.g. by suitable control of the charge pump 68 by the controller 50.

[0052] Finally, it should be noted that the determination of the actual values ​​of the current amplitude i CP0 , the differential current error Δi ERRand / or the effective capacitance C (cf. Equation 13) also allows conclusions to be drawn regarding other components that were manufactured in the same manufacturing process. For example, it is possible to determine at which end of the tolerance range a specific MMIC lies, which can be important information with regard to the functional safety of the MMIC. In particular, the calculation of the effective capacitance C according to Equation 13 also allows the determination of the actual absolute error ΔC (or the relative error ΔC / C0) with respect to a nominal value C0 of the effective capacitance C. The information about the error ΔC (or ΔC / C0) also allows conclusions to be drawn about the actual absolute or relative error of other components in the same MMIC. In some embodiments, these errors can, for example, be partially compensated.For example, the loop filter 69 can have switchable capacitor groups whose total capacitance can be adjusted using a digital signal. In this case, a measured error ΔC can be at least partially calibrated, for example, by controlling one or more digital capacitor groups. Furthermore, the current error of the current sources Q1 and Q2 of the charge pump 68 can correlate with the error ΔC. This error can also be at least partially compensated based on the measured error ΔC, for example by tuning resistors on which the current of the current sources Q1 and Q2 depends. For example, due to characteristics of the manufacturing process, it can be known that an error ΔC / C0 of -10 percent results in a corresponding error in the current source current of +10 percent, which can be at least partially compensated by appropriate tuning of the current sources Q1 and Q2.

[0053] In the following, some of the embodiments described here are summarized using flowcharts. This is not a complete list, but merely an exemplary summary of important aspects. According to the flowchart from Fig. 16 comprises an embodiment of the method described above (see e.g. Fig. 10 to 14) the generation of current pulses with adjustable current amplitude and a defined duration T ON by means of a charge pump (see e.g. Fig. 10 and Fig. 13, charge pump 68). The generation of current pulses comprises generating a first current pulse with a first current amplitude i CP0 and generating a second current pulse with a second current amplitude i CP0 +Δi (see. Fig. 16, step 91). The difference between the first and the second amplitude is therefore Δi (see also Fig. 11, right diagram). The process further includes converting (see Fig. 16, step 92) of the current pulses into a tuning voltage V FINE for an RF oscillator (see e.g. Fig. 10 and Fig. 13, VCO 61). The tuning voltage V FINE (e.g. starting from an adjustable initial value V0) in response to the current pulses depending on its amplitude (see e.g. Fig. 11, left diagram). In this example, the RF oscillator is a VCO whose frequency f LO from the tuning voltage V FINE depends.

[0054] According to Fig. 16, the method further comprises generating a measurement signal that represents the tuning voltage V FINE or the frequency f LO of the RF oscillator (see Fig. 16, step 93). The measurement signal can be, for example, the digital output signal of the ADC 63 from Fig. 10. In Fig. 11 the measured values ​​are labelled with V1 and V2, for example, in Fig. 14 with f1 and f2. Furthermore, a first change ΔV1 or Δf1 of the measurement signal is determined as a reaction to the first current pulse (with current amplitude i CP0 ) and a second change ΔV2 or Δf2 of the measurement signal in response to the second current pulse (with current amplitude i CP0 +Δi) (see Fig. 16, step 94). The determination of the changes can be done, for example, digitally in a computing unit contained in the controller 50. Based on the current amplitude difference Δi as well as the first change ΔV1 or Δf1 and the second change ΔV2 or Δf2, the first current amplitude iCP0 can be calculated (see Fig. 16, step 95). This calculation can be performed, for example, according to equation 7 or 11.

[0055] According to one embodiment, the mentioned RF oscillator and the charge pump are part of a phase-locked loop (see e.g. Fig. 10 or Fig. 13), whereby this phase-locked loop is used during the Fig. 16 is inactive (ie the control loop is open), so that the charge pump operates independently of the frequency f LO of the RF signal (no feedback).

[0056] Before generating a current pulse, the tuning voltage V FINE to an initial value V0. The operating point of the RF oscillator is set using a further tuning voltage V COARSE adjusted so that the tuning voltage V FINE takes on the desired value (cf. Fig. 7). During this operating point adjustment, the phase-locked loop is closed, i.e., in closed-loop operation.

[0057] The mentioned conversion of the current pulses into the tuning voltage V FINE For the RF oscillator, according to one embodiment, the current pulses can be fed to an input of a loop filter (see e.g. Fig. 10, loop filter 69), which has a total capacity (cf. Fig. 9, capacity C) and transferring the charges transported with the current pulses to the total capacity.

[0058] The flow chart according to Fig. 17 shows an example of an extension of the example from Fig. 16, which in addition to the determination of the first amplitude i CP0 (or its deviation from a setpoint) also the determination of the (differential) current error Δi ERR which allows the amplitude differences Δi and Δi A , Δi B (see equation 17). According to Fig. 17 is additionally (compared to step 91 of Fig. 16) a third current pulse with a third amplitude is generated. In step 94', additionally (compared to step 94' from Fig. 16) a third change in the measurement signal is determined in response to the third current pulse. Based on two of the determined changes in the measurement signal, the first amplitude i CP0 be calculated (see step 95 of Fig. 16) and, based on the three changes ΔV1, ΔV 2A , ΔV 2B of the measurement signal, the mentioned differential error Δi ERR be calculated (see Fig. 17, step 96). This error can be calculated, for example, according to equation 20 or using equation 22.

[0059] At this point it should be noted that the sequence in the flow charts from Fig. 16 and Fig. 17 represents a logical sequence of the individual steps, but not a mandatory chronological order. For example, the second current pulse ( Fig. 17, step 91') after the first change in the measurement signal has been determined in response to the first current pulse. Even if step 95 (see Fig. 16) in the example from Fig. 17 is not explicitly shown, it can still be carried out (before or after step 96).

Claims

[1] An RF circuit comprising: a charge pump (68) configured to generate current pulses having a first current amplitude (i CP0 ) and a predetermined duration (T ON ) to generate a capacitive element (C) coupled to the charge pump (68) and configured to receive the current pulses and, depending thereon, to generate a tuning voltage (V TUNE ) to generate an RF oscillator (61) coupled to the capacitive element (C) and configured to generate an RF signal (s LO (t)) with a frequency (f LO ) which is dependent on the tuning voltage (V FINE ) depends; a measuring circuit (63; 71) which is designed to generate a measuring signal (V1, V2, V 2A , V 2B , f1, f2) which determines the tuning voltage (V FINE ) or the frequency (f LO ) of the RF signal (s LO (t)) represents; a controller circuit (50) coupled to the charge pump (68) and the measuring circuit (63; 71) and configured to: to control the charge pump (68) in such a way as to obtain the first amplitude (i CP0 ) of a current pulse by a current difference (Δi; Δi A , Δi B ) and a first change (ΔV1; Δf1) of the measurement signal, which is a reaction to a first current pulse of the current pulses with the first current amplitude (i CP0 ) and a second change (ΔV2; ΔV 2A , ΔV 2B ; Δf2) of the measurement signal, which is a reaction to a second current pulse of the current pulses with changed current amplitude (i CP0 +Δi) is to be determined, and based on the first change (ΔV1; Δf1) of the measurement signal and the second change (ΔV2; ΔV 2A , ΔV 2B ; Δf2) of the measuring signal and the current difference (Δi) a measured value for the first amplitude (i CP0 ) to calculate. [2] The RF circuit according to claim 1, wherein the charge pump (68), the capacitive element (C) and the RF oscillator (61) are part of a phase-locked loop where the phase-locked loop is at least temporarily inactive, so that the charge pump operates independently of the frequency of the (f LO ) of the RF signal (s LO (t)). [3] The RF circuit according to claim 2, wherein the operating point of the RF oscillator (61) is adjustable such that it generates a desired frequency when the phase-locked loop is active, if the tuning voltage (V FINE ) assumes a reference value (V0). [4] The RF circuit according to claim 3, wherein the controller circuit (50) is further configured to: another tuning voltage (V COARSE ) which determines the operating point of the RF oscillator (61), before the generation of a current pulse by the charge pump (68) with the phase-locked loop active, the further tuning voltage (VCOARSE ) so that the tuning voltage (V FINE ) assumes a reference value (V0). [5] The RF circuit according to any one of claims 1 to 4, wherein the capacitive element comprises a loop filter (69) connected downstream of the charge pump (68). [6] The RF circuit according to any one of claims 1 to 5, wherein the controller circuit (50) is further configured to: to control the charge pump (68) so that the first amplitude (i CP0 ) depending on the calculated measured value for the first amplitude (i CP0 ) is adjusted. [7] The RF circuit according to any one of claims 1 to 6, wherein the controller circuit (50) is further configured to: to calculate a component parameter of the charge pump (68) and / or the capacitive element based on the changes in the measurement signal and the current difference (Δi). [8] The RF circuit according to claim 7, wherein the capacitive element (C) is a loop filter (69) and the device parameter is a total capacitance of the loop filter. [9] A method comprising: Generation of current pulses with adjustable current amplitude and a predetermined duration (T ON ) by means of a charge pump (68), wherein the generation of current pulses comprises the generation of a first current pulse having a first amplitude (i CP0 ) and generating a second current pulse with a second amplitude (i CP0 +Δ i ) which differs by a current difference (Δi) from the first amplitude (i CP0 ) differs; Converting the current pulses into a tuning voltage (V FINE ) for an RF oscillator such that the tuning voltage (V FINE ) in response to each current pulse depending on its amplitude (i CP0 , i CP0 +Δi) is changed, whereby a frequency (fLO ) of the RF oscillator from the tuning voltage (V TUNE ) depends; Generating a measurement signal (V1, V2, V 2A , V 2B ; f1, f2) which is the tuning voltage (V FINE ) or the frequency (f LO ) of the RF oscillator; Determining a first change (ΔV1; Δf1) of the measurement signal in response to the first current pulse and a second change (ΔV2; Δf2) of the measurement signal in response to the second current pulse; Calculate the first amplitude (i CP0 ) based on the current difference (Δi) and the first change (ΔV1; Δf1) of the measuring signal and the second change (ΔV2; Δf2) of the measuring signal. [10] The method according to claim 9, further comprising: Setting the operating point of the RF oscillator (61) so that it generates a target frequency when the tuning voltage (V FINE ) assumes a reference value (V0), wherein during the setting of the operating point the charge pump (68) and the RF oscillator are part of an active phase-locked loop. [11] The method according to claim 10, wherein for generating the first and the second current pulse, the phase-locked loop is not active, so that the charge pump (68) operates independently of the frequency (f LO ) of the RF signal (s LO (t)). [12] The method according to any one of claims 9 to 11, wherein converting the current pulses into the tuning voltage (V FINE ) for the RF oscillator includes: Supplying the current pulses to an input of a loop filter (69) having a total capacitance, and Transferring the charges transported by the current pulses to the total capacity. [13] The method according to any one of claims 9 to 12, wherein the generation of current pulses additionally comprises the generation of a third current pulse having a third amplitude (iCP0 +Δi B ), and the method further comprising: Determining a third change (ΔV 2B ; Δf 2B ) of the measurement signal in response to the third current pulse; and Calculating a current error (Δi ERR ) of the current difference between the second amplitude (i CP0 +Δi A ) and the first amplitude (i CP0 ) and / or the current difference between the third amplitude (i CP0 +Δi B ) and the first amplitude (i CP0 ) based on the first change, the second change and the third change of the measurement signal. [14] The method according to any one of claims 9 to 13, further comprising: Calculating a component parameter of the charge pump (68) and / or the capacitive element based on the changes in the measurement signal and the current difference (Δi). [15] The method according to claim 14, wherein the capacitive element (C) is a loop filter (69) and the device parameter is a total capacitance of the loop filter (69). [16] The method according to claim 15, further comprising: Adjusting the total capacity of the loop filter (69) based on the calculated total capacity of the loop filter (69) and a target value for the total capacity.

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