Semiconductor design

Abstract

Semiconductor design (10) which includes the following: an insulating encapsulation material (210), a first semiconductor die (110) embedded in the insulating encapsulation material, wherein the first semiconductor die has a first active area (110a) accessible from the insulating encapsulation material and a first conductor terminal (112) wired to the first active area, a second semiconductor die (120) embedded in the insulating encapsulation material and separated from the first semiconductor die (110), the second semiconductor die having a second active area (120a) accessible from the insulating encapsulation material and a second conductor terminal (122) wired to the second active area (120a), and a rewiring layer (310) arranged on the first active area (110a) of the first semiconductor die (110), the second active area (120a) of the second semiconductor die (120) and the insulating encapsulation material (210), wherein the rewiring layer comprises a conductor track (312, 416, 516) electrically connected to the first semiconductor die (110) and winding towards the second semiconductor die (120), and the ratio of the total length of the conductor track (312, 416, 516) to the top width (W) of the insulating encapsulation material (210) between the first and second semiconductor dies ranges from 3 to 10. wherein the conductor track (312, 416, 516) of the rewiring layer (310) comprises at least one turning segment (312a) located above the insulating encapsulation material (210) and the at least one turning segment (312a) of the conductor track (312, 416, 516) is located on a plane that is substantially perpendicular to the first active area (110a) of the first semiconductor die (110) and to the second active area (120a) of the second semiconductor die (120).

Description

GENERAL STATE OF THE ART

[0001] In one aspect of conventional semiconductor packaging technologies such as Integrated Fan-out Wafer Level Packaging (InFO-WLP), redistribution layers (RDLs) can be formed on a die and electrically connected to active components within a die. Additionally, a mold compound can be formed around the die to provide the surface that supports the fan-out trace structures. For example, RDLs with interconnect layers are typically formed on both the die and the mold compound.

[0002] In such semiconductor package designs, heat causes both the die and the molding compound to expand during operation at their respective coefficients of thermal expansion (CTE). Due to the discrepancy in the CTE between the die and the molding compound, a tensile stress concentration arises. However, such stress can potentially damage the interconnect layer. For example, thermal stress can cause the interconnect layer to crack or break, leading to circuit failure. Accordingly, there is a need for semiconductor package designs that are more reliable and in which the interconnect layer is protected from tensile stress.

[0003] US 9 773 753 B1 relates to a semiconductor device comprising a first chip having a first surface and a second surface opposite the first surface, wherein the first chip comprises at least one first pad arranged adjacent to the first surface of the first chip.

[0004] US 2013 / 0 087 921 A1 relates to a semiconductor arrangement for galvanically isolated signal transmission comprising an artificial chip which contains a semiconductor chip and an electrically insulating potting compound, wherein the semiconductor chip has circuit structures and is embedded in the potting compound on all sides except on a base area of ​​the semiconductor chip in such a way that a base area of ​​the artificial chip is enlarged by the potting compound relative to the base area of ​​the semiconductor chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Aspects of the present disclosure can best be understood by studying the following detailed description in conjunction with the accompanying figures. It should be noted that, consistent with industry practice, various features are not drawn to scale. Rather, the dimensions of the various features may be exaggerated or decreased for purposes of illustration. Fig. 1 is a schematic cross-sectional view illustrating an integrated fan-out package according to exemplary embodiments of the present disclosure. Fig. 2A is the schematic top view illustrating a semiconductor structure according to example embodiments of the present disclosure. Fig. Figure 2B is the schematic cross-sectional view along the line AA in the semiconductor construction of Fig. 2A. Fig. 3A is a schematic top view illustrating a semiconductor structure according to some embodiments of the present disclosure. Fig. Figure 3B is the schematic cross-sectional view along line BB of the semiconductor structure of Fig. 3A. Fig. 4 is a schematic perspective view illustrating a semiconductor structure according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0006] The invention is as defined in the independent claims. The dependent claims relate to corresponding developments. The following disclosure provides many different embodiments or examples of implementing various features of the respective subject matter. Certain example components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not intended to be limiting. In the following description, the formation of a first feature on or at a second feature may include, for example, embodiments in which the first and second features are formed in direct contact, as well as embodiments in which additional features are formed between the first and second features such that the first and second features are not in direct contact.Additionally, reference numbers and / or reference symbols may be repeated throughout the various examples in the present disclosure. This repetition is for clarity and convenience and does not, in itself, dictate any relationship between the various embodiments and / or configurations discussed.

[0007] Spatially relatable terms such as "beneath," "under," "lower," "above," "above," "above," "upper," and the like may also be used herein for convenience in describing the relationship of one element or feature to one or more other elements or features, as illustrated in the figures. The spatially relatable terms are intended to encompass various orientations of the device in use or operation, in addition to the orientation depicted in the figures. The device may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relatable descriptors used herein may be interpreted accordingly.

[0008] Other features and processes may also be included. For example, they may include test structures involved in verification testing of the 3D packaging or 3DIC devices. Test structures may include, for example, test pads formed in a redistribution layer or on a substrate that enables testing of the 3D packaging or 3DIC, the use of probes and / or probe cards, and the like. Verification testing may be performed on semi-finished designs as well as on the final design. In addition, the designs and methods disclosed herein may be used in conjunction with test methodologies that include intermediate verification of known "good" die to increase production and reduce costs.

[0009] Fig. 1 is a schematic cross-sectional view illustrating a semiconductor package according to exemplary embodiments of the present disclosure. Referring to Fig. 1, an integrated fan-out package 50 may, in some embodiments, include a circuit substrate 2, external terminals 4 attached to a lower surface of the circuit substrate 2 and electrically connected to the circuit substrate 2, and a semiconductor structure 6 disposed on an upper surface of the circuit substrate 2. The upper surface is opposite the lower surface. In other words, the external terminals 4 and the semiconductor structure 6 are disposed on opposite sides of the circuit substrate 2. In some embodiments, the circuit substrate 2 may be a printed circuit board with patterned conductive layers and patterned dielectric layers alternately stacked on top of one another, and the external terminals 4 attached to the lower surface of the circuit substrate 2 may be solder balls arranged in a grid pattern.For example, the semiconductor structure 6 can be first formed and then attached to the circuit substrate 2 and electrically connected thereto via contact bumps 3. The integrated fan-out package 50 can comprise a plurality of semiconductor dies and is electrically connected to the circuit substrate 2 via the contact bumps 3 (e.g., controlled collapse chip connection bumps, ie, C4 contact bumps). Details of the embodiments of the semiconductor structure 6 are described below.

[0010] Fig. 2A is the schematic top view illustrating a semiconductor structure according to exemplary embodiments of the present disclosure, and Fig. 2B shows the schematic cross-sectional view along the line AA in the semiconductor construction in Fig. 2A. In some exemplary embodiments, a semiconductor structure 10 in Fig. 2A and Fig. 2B, a plurality of semiconductor dies 100 (e.g., a first semiconductor die 110 and a second semiconductor die 120), an insulating encapsulant 210, and a redistribution layer 310 electrically connected to the semiconductor dies 100. In some embodiments, each of the semiconductor dies 100 includes an active area and a conductive terminal wired to the active area. For example, the first semiconductor die 110 includes a first active area 110a and at least one first conductive terminal 112 wired to the first active area 110a, and the second semiconductor die 120 includes a second active area 120a and at least one second conductive terminal 122 wired to the second active area 120a. It should be noted that the number of semiconductor dies 100 in the figures is merely illustrative by way of example, and the disclosure is not limited thereto.In some alternative embodiments, more semiconductor dies 110 may be configured to form the semiconductor structure 10.

[0011] In some embodiments, the insulating encapsulant 210 may laterally encapsulate sidewalls of the semiconductor dies 100 such that the semiconductor dies 100 may be spaced apart from each other by the insulating encapsulant. For example, there may be a gap G between the first semiconductor die 110 and the second semiconductor die 120, and the insulating encapsulant 210 may be located in and fill the gap G such that the first semiconductor die 110 and the second semiconductor die 120 are spatially separated from each other. In other words, the first semiconductor die 110 and the second semiconductor die 120 may be separately embedded in the insulating encapsulant. The insulating encapsulant 210 may, for example, include an insulating material or polymer composite material formed by compression molding, transfer molding, or another suitable molding process.In some embodiments, the first active area 110a of the first semiconductor die 110 and the second active area 120a of the second semiconductor die 120 may be accessibly exposed from the insulating encapsulant 210 such that the first lead terminal 112 and the second lead terminal 122 are accessibly exposed from the insulating encapsulant 210 for further electrical connection.

[0012] As in Fig. 2A, the first lead terminal 112 of the first semiconductor die 110 and the second lead terminal 122 of the second semiconductor die 120 may have two parallel tangents L1 in an X-direction and two parallel tangents L2 in a Y-direction perpendicular to the X-direction. In other words, the parallel tangents L1 may be substantially perpendicular to the parallel tangents L2. In some embodiments, the closest distance D between the first lead terminal 112 of the first semiconductor die 110 and the second lead terminal 122 of the second semiconductor die 120 may be measured between the parallel tangents L2. The closest distance D may be greater than a top width W of the insulating encapsulant 210 between the first semiconductor die 110 and the second semiconductor die 120 and less than three times the top width of the insulating encapsulant 210.In some cases, the upper width W of the insulating encapsulant 210 between the first semiconductor die 110 and the second semiconductor die 120 is greater than a distance D' between the sidewall of the first semiconductor die 110 facing the second semiconductor die 120 and the sidewall of the second semiconductor die 120 facing the first semiconductor die 110. For example, an upper portion (not shown) of the insulating encapsulant 210 between the first lead terminal 112 and the second lead terminal 122 may have a wide upper part and a narrow lower part in the cross-sectional view.

[0013] In some embodiments, the first active area 110a of the first semiconductor die 110 and the second active area 120a of the second semiconductor die 120 may be substantially coplanar with a top surface 210a of the insulating encapsulant 210. The redistribution layer 310 may be arranged on the first active area 110a, the second active area 120a, and the top surface 210a of the insulating encapsulant 210. For example, the redistribution layer 310 may extend laterally beyond the outer perimeter of line terminals, thus providing fan-out conductive trace structures. The line terminals (e.g., the first line terminal 112 and the second line terminal 122) may, for example, comprise copper vias. In some embodiments, the redistribution layer 310 may comprise at least one conductive trace 312.The conductive trace 312 may be electrically connected to the first conduction terminal 112 of the first semiconductor die 110 and may wind toward the second conduction terminal 122 of the second semiconductor die 120. The conductive trace 312 winding toward the second conduction terminal 122 may comprise any current path that is longer than the shortest distance between the conduction terminals it connects, or long enough to maintain electrical conductivity. The current path of the conductive trace 312 winding from the first conduction terminal 112 to the second conduction terminal 122 may be configured in the form of traces with successive bends, curves, or the like. In other words, the conductive trace 312 may be electrically connected to the semiconductor dies 100 and reroute electrical signals, thus enabling further electrical connection.A total length of the conductive line 312 can, for example, range from approximately 50 µm to 500 µm. In some embodiments, the total length of the conductive line 312 can be greater than the shortest distance D and at least three times greater than the upper width W of the insulating encapsulant 210. A ratio of the total length of the conductive line 312 to the upper width W of the insulating encapsulant 210 ranges, for example, from approximately 3 to approximately 10. In some cases, the shortest distance D is less than three times the upper width W of the insulating encapsulant 210. If the current path of the conductive line 312 connected between the first line terminal 112 and the second line terminals 122 is linear in these cases, the tensile stress resulting from the discrepancy in the CTE can have a negative effect on the conductive line 312; for example, the conductive line 312 can tend to tear.Since the conductive trace 312 winds between the semiconductor dies 100, so that the overall length of the conductive trace 312 increases, the tolerance of the conductive trace 312 to the tensile stress resulting from the discrepancy in the CTE is improved.

[0014] In some embodiments, the conductive line 312 of the redistribution layer 310 may include at least one turning segment 312a corresponding to the insulating encapsulant 210. For example, as shown in Fig. 2A, the turn segments 312a are located above the insulating encapsulant 210. In some embodiments, the turn segments 312a may be located above the first semiconductor die 110 and / or the second semiconductor die 120. In some other embodiments, depending on the design requirements, the turn segments 312a may be located above the interface between the semiconductor dies 100 and the insulating encapsulant 210 in plan view. The turn segments 312a may lie on a plane P1 that is substantially parallel to the first active area 110a of the first semiconductor die 110 and the second active area 120a of the second semiconductor die 120. The plane P1 may be, for example, the XY plane.

[0015] In some embodiments, the conductive track 312 may be formed as a zigzag-shaped conductive structure corresponding to the insulating encapsulant. In some other embodiments, the current path of the turning segments 312a of the conductive track 312 may be formed as an angled path. For example, an angle θ of the current path of the turning segments 312a may include an acute angle, a right angle, or an obtuse angle. Multiple turning segments 312a may be connected to one another and form a winding structure. In some embodiments, the current path of the turning segments 312a may be a curved path. The winding structure may, for example, be wired sinusoidally between the first line terminal 112 and the second line terminal 122 of the second semiconductor die 120. In some embodiments, the zigzag-shaped conductive structure may be formed as a regular structure.For example, the zigzag-shaped conductive structure may be symmetrical with respect to the center of the insulating encapsulant 210. In some other embodiments, the zigzag-shaped conductive structure may be formed as an irregular structure depending on the routing design requirements.

[0016] In some other embodiments, the conductive trace 312 may include conductive pads 312b formed on the first conductive terminal 112 and the second conductive terminal 122. In some embodiments, the layout area of ​​the conductive trace 312 may be located between the parallel tangents L1 of the first conductive terminal 112 and the second conductive terminal 122. In some other embodiments, the layout area of ​​the conductive trace 312 may be located between and / or outside the parallel tangents L1 of the first conductive terminal 112 and the second conductive terminal 122, depending on the routing design requirements.

[0017] The redistribution layer 310 may, for example, include a dielectric layer 314 formed on the first active area 110a, the second active area 120a, and the top surface 210a of the insulating encapsulant 210. In some embodiments, the dielectric layer may include photopatternable insulating materials such as polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), and the like, or a combination thereof, and may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), a spin-coating process, and the like, or a combination thereof.

[0018] In some embodiments, the dielectric layer 314 may be patterned to form a plurality of openings (not shown) that expose at least the surface of the lead terminals of the semiconductor dies 100, e.g., using a photolithography technique or other suitable process. In some other embodiments, the conductive line 312 may be formed by depositing a seed layer (not shown) on the dielectric layer 314 and in the openings. The seed layer may include conductive materials such as copper, titanium, nickel, gold, and the like, or a combination thereof. Next, a photoresist material (not shown) may be deposited on the seed layer and patterned to define the desired structure, such as the zigzag-shaped conductive structure.A conductive line material, such as copper, aluminum, silver, gold, and the like, or a combination thereof, may be formed on the seed layer using an electrochemical plating process, an electroless plating process, PVD, ALD, and the like, or a combination thereof. Thereafter, the photoresist material may be removed using the appropriate photoresist removal process. In some embodiments, the conductive line 312 may be formed before the dielectric layer 314. The order in which the conductive line 312 and the dielectric layer 314 are formed does not limit the disclosure.

[0019] In some embodiments, the exposed portions of the seed layer on the dielectric layer 314 may be removed, for example, using an etching process or other suitable process. In some other embodiments, a passivation layer (not shown) may be formed on the conductive line 312 to protect against damage. Other possible shapes for the conductive line 312 may be used, as long as a ratio of a total length of the conductive line 312 to the top width W of the insulating encapsulant 210 may range, for example, from about 3 to about 10. The semiconductor structure 10 itself may withstand the tensile stress resulting from the discrepancy in the CTE of the semiconductor dies 100 and the insulating encapsulant 210 and eliminate the negative effect caused by tearing of the redistribution layer 310, thus improving the functionality of the semiconductor structure 10.

[0020] Fig. 3A is the schematic perspective view illustrating a semiconductor structure according to some embodiments of the present disclosure, and Fig. 3B shows the schematic cross-sectional view along the line BB in the semiconductor construction in Fig. 3A. A semiconductor structure 20 according to the present embodiment in Fig. 3A and Fig. 3B is similar to the semiconductor structure 10 of Fig. 2A. The same or similar reference numerals designate the same or similar elements throughout the drawings, and details thereof are not repeated. The difference between the semiconductor structure 20 and the semiconductor structure 10 in Fig. 2A is that the redistribution layer 410 may include more than one conductive structural element (e.g., conductive traces and / or conductive vias).

[0021] In some embodiments, the redistribution layer 410 may include a first dielectric layer 412 and a second dielectric layer 414. For example, the first dielectric layer 412 may be formed and patterned to form openings on the first semiconductor die 110, the second semiconductor die 120, and the top surface 210a of the insulating encapsulant 210 (not shown). The openings in the first dielectric layer 412 may expose a portion of the lead terminals (e.g., 112 and 122) of the semiconductor dies 100. Next, a first step 416a' of the first trace 416a of the conductive trace 416 may be formed on the first dielectric layer 412 and in the openings. The formation methods and materials for the first dielectric layer 412 and the conductive line 416 may be similar to those for the dielectric layer 314 and the conductive line 312. A detailed description is omitted.Thereafter, the second dielectric layer 414 may be formed on the first dielectric layer 412 and patterned to include openings exposing a portion of the first trace 416a. Next, a plurality of conductive vias 416b may be formed in the openings of the second dielectric layer 414, and a second step 416a'' of the first trace 416a may be formed on the conductive vias 416b and the second dielectric layer 414. In other words, the first step 416a' and the second step 416a'' of the first trace 416a may be electrically connected via the conductive vias 416b. In some embodiments, the conductive vias 416b and the second step 416a'' of the first trace 416a may be formed in the same process.The formation processes for the second step 416a'' may be similar to those for the first trace 416a and the conductive trace 310, so the detailed description is omitted. In some embodiments, the first trace 416a may be located with the first step 416a' and the second step 416a'' on a first plane (not shown) that is substantially parallel to the first active area 110a and the second active area 120a.

[0022] In some embodiments, when a portion of the first stage 416a' and the second stage 416a'' of the first trace 416a is connected to the conductive vias 416b, the conductive vias 416b may be referred to as a second trace 416c. The second trace 416c may be formed as a zigzag-shaped conductive structure (as a hatched area in the circle Z in Fig. 3B) and are referred to in the cross-sectional view as turning segments of the conductive trace 416. In some embodiments, the second trace 416c may be formed over the insulating encapsulant 210. In some other embodiments, the second trace 416c may be on a second plane (such as the cross-sectional plane along line BB in Fig. 3A) that is substantially perpendicular to the first active area 110a of the first semiconductor die 110 and to the second active area 120a of the second semiconductor die 120. In some embodiments, the total length of the second step 416a'' of the first trace 416a of the conductive line 416 may be between the shortest distance D and the upper width W of the insulating encapsulant 210. In some other embodiments, the total length of the second trace 416c of the conductive line 416 may be greater than the shortest distance D between the first conduction terminal 112 and the second conduction terminal 122.

[0023] In some embodiments, the turnaround segments of the conductive line 416 may be formed symmetrically with respect to the insulating encapsulant 210 above the active areas (e.g., the first active area 110a and the second active area 110b) of the semiconductor dies 100. In some embodiments, the turnaround segments of the conductive line 416 may correspond to the first active area 110a and / or the second active area 120a and / or the top surface 210a of the insulating encapsulant 210. In some embodiments, the turnaround segments of the conductive line 416 may be located above the interface between the semiconductor dies 100 and the insulating encapsulant 210 in cross-sectional view. In some embodiments, the conductive vias 416b may have a conical sidewall. In some other embodiments, the conductive vias 416b may have vertical sidewalls.By alternately repeating the above steps, the formation of the redistribution layer 410 is completed.

[0024] In the semiconductor structure 20, the conductive vias 416b can provide a connection path between the first section 416a and the second section 416c. The conductive vias 416b can contribute an extension path to the conductive path of the conductive line 416. The semiconductor structure 20 itself can withstand the tensile stress resulting from the CTE discrepancy between the semiconductor dies 100 and the insulating encapsulant 210 and eliminate the adverse effect caused by tearing of the redistribution layer 410, thus improving the functionality of the semiconductor structure 20.

[0025] Fig. 4 is a schematic perspective view illustrating a semiconductor structure according to some embodiments of the present disclosure. A semiconductor structure 30 according to the present embodiment in Fig. 4 is similar to the combination of the semiconductor construction 10 of the Fig. 2A and Fig. 2B and the semiconductor structure 20 of the embodiment shown in Fig. 3A and Fig. 3B. The same or similar numerals designate the same or similar elements throughout the drawings, and details thereof are not repeated. The difference between semiconductor structure 30, semiconductor structure 10, and semiconductor structure 20 is the routing of the conductive trace 516 of the redistribution layer 510.

[0026] The first track 516a of the conductive track 516 (also referred to as a zigzag-shaped conductive structure) with a first step 516a' and / or a second step 516a'' can be used as the turning segments (as a hatched area in the circle Z1 in Fig. 4) be formed according to the insulating encapsulant 210. The formation processes for the first track 516a may be Fig. 2A and Fig. 2B, and the detailed description is simplified. For example, the first dielectric layer 512 may be formed and patterned to include openings (not shown) on the semiconductor dies 100 and the insulating encapsulant 210. Thereafter, the first step 516a' of the first trace 516a may be formed in the openings and on the first dielectric layer 512 to include the turnaround segments in a top view. In some other embodiments, the second step 516a'' of the first trace 516a may include the turnaround segments (also referred to as a zigzag-shaped conductive structure) in a top view. For example, the second dielectric layer 514 may be formed and patterned on the first dielectric layer 512 to include openings (not shown) that expose a portion of the conductive vias 516b.The second step 516a'' of the first trace 516a can be formed in the openings so that it is electrically connected to the conductive vias 516b, and formed on the second dielectric layer 514 such that the second step 516a'' can include the turnaround segments in plan view. The overall length of the conductive trace 516 itself can be increased.

[0027] In some embodiments, the turning segments of the conductor track 516 (as a hatched area in the circle Z2 in Fig. 4) have the conductive vias 516b, wherein a part of the first step 516a' and the second step 516a'' of the first track 516a is connected to the conductive vias 516b, and the turning segments can also be referred to as a zigzag-shaped conductive structure. The formation processes for the turning segments (as a hatched area in the circle Z2 in Fig. 4) can be assigned to the hatched area of ​​circle Z in Fig. 3B, and a detailed description is omitted. In some embodiments, the first trace 516a may be located on a first plane (not shown) that is substantially parallel to the active areas (e.g., 110a and 110b) of the semiconductor dies 100, and the second trace 516c with the conductive vias 516b may be located on a second plane (not shown) that is substantially perpendicular to the active areas (e.g., 110a and 110b) of the semiconductor dies 100.

[0028] Since the conductive line 516 includes turning segments to increase its overall length, the semiconductor structure 30 can withstand the tensile stress resulting from the discrepancy in the CTE of the semiconductor dies 100 and the insulating encapsulant 210 and eliminate the adverse effect caused by tearing of the redistribution layer 510, so that the functionality of the semiconductor structure 30 can be improved.

[0029] According to some embodiments, a semiconductor structure is provided including an insulating encapsulant, a first semiconductor die, a second semiconductor die, and a redistribution layer. The first semiconductor die is embedded in the insulating encapsulant. The first semiconductor die has a first active area accessibly exposed from the insulating encapsulant and a first lead terminal wired to the first active area. The second semiconductor die is embedded in the insulating encapsulant and separated from the first semiconductor die. The second semiconductor die has a second active area accessibly exposed from the insulating encapsulant and a second lead terminal wired to the second active area.The redistribution layer is arranged on the first active area of ​​the first semiconductor die, the second active area of ​​the second semiconductor die, and the insulating encapsulant. The redistribution layer includes a conductive trace. The conductive trace is electrically connected to the first semiconductor die and winds up to the second semiconductor die. A ratio of a total length of the conductive trace 312 to the upper width of the insulating encapsulant ranges, for example, from about 3 to about 10.

[0030] According to some alternative embodiments, a semiconductor structure is provided including an insulating encapsulant, a first semiconductor die, a second semiconductor die, and a conductive trace. The first semiconductor die is embedded in the insulating encapsulant. The first semiconductor die has a first active area accessibly exposed from the insulating encapsulant and a first conductive terminal wired to the first active area. The second semiconductor die is embedded in the insulating encapsulant and separated from the first semiconductor die. The second semiconductor die has a second active area accessibly exposed from the insulating encapsulant and a second conductive terminal wired to the second active area.The conductive trace extends from the first to the second lead terminal and is thus electrically connected between the first and second semiconductor dies. A total length of the conductive trace is greater than a minimum distance between the first semiconductor lead terminal and the second semiconductor lead terminal, and the total length of the conductive trace is at least three times greater than the upper width of the insulating encapsulant.

[0031] According to some alternative embodiments, a semiconductor structure is provided comprising a plurality of semiconductor dies, an insulating encapsulant, and a redistribution layer. Each of the semiconductor dies comprises an active area. The insulating encapsulant laterally encapsulates the semiconductor dies. The semiconductor dies are spaced apart from each other by the insulating encapsulant. The redistribution layer is arranged on the active areas of the semiconductor dies and the insulating encapsulant. The redistribution layer has a zigzag-shaped conductive structure corresponding to the insulating encapsulant, which is electrically connected between the semiconductor dies.

Claims

[1] Semiconductor construction (10) comprising: an insulating encapsulant (210), a first semiconductor die (110) embedded in the insulating encapsulant, the first semiconductor die having a first active area (110a) accessible from the insulating encapsulant and a first lead terminal (112) wired to the first active area, a second semiconductor die (120) embedded in the insulating encapsulant and separated from the first semiconductor die (110), the second semiconductor die having a second active area (120a) accessible from the insulating encapsulant and a second lead terminal (122) wired to the second active area (120a), and a redistribution layer (310) arranged on the first active area (110a) of the first semiconductor die (110), the second active area (120a) of the second semiconductor die (120), and the insulating encapsulant (210), wherein the redistribution layer comprises a conductive trace (312, 416, 516), the conductive trace (312, 416, 516) being electrically connected to the first semiconductor die (110) and winding toward the second semiconductor die (120), and a ratio of a total length of the conductive trace (312, 416, 516) to the upper width (W) of the insulating encapsulant (210) between the first and second semiconductor dies ranging from 3 to 10, wherein the conductor track (312, 416, 516) of the redistribution layer (310) comprises at least one turning segment (312a) located above the insulating encapsulant (210), and the at least one turning segment (312a) of the conductor track (312, 416, 516) is located on a plane that is substantially perpendicular to the first active area (110a) of the first semiconductor die (110) and to the second active area (120a) of the second semiconductor die (120). [2] The semiconductor structure of claim 1, wherein a minimum distance (D) between the first and second lead terminals (112, 122) is greater than the upper width (W) of the insulating encapsulant (210). [3] The semiconductor structure of claim 1 or 2, wherein the conductive trace (312, 416, 516) is electrically connected between the first conduction terminal (112) of the first semiconductor die (110) and the second conduction terminal (122) of the second semiconductor die (120). [4] A semiconductor structure according to any one of the preceding claims, wherein there is a gap (G) between the first and second semiconductor die (110, 120) and the insulating encapsulant (210) fills the gap. [5] A semiconductor structure according to any one of the preceding claims, wherein the conductive trace (312, 416, 516) comprises at least one turning segment (312a) located on a plane substantially parallel to the first active area (110a) of the first semiconductor die (110a) and to the second active area (120a) of the second semiconductor die (120). [6] A semiconductor structure according to any one of the preceding claims, wherein the at least one turning segment (312a) of the conductive trace (312a, 416, 516) comprises a first trace (416a, 516a) and a second trace (416c, 516c) connected to the first trace (416a, 516a), the first trace (416a, 516a) being located on a first plane substantially parallel to the first and second active (110a, 120a) surfaces, and the second trace (416c, 516c) being located on a second plane substantially perpendicular to the first active surface of the first semiconductor die and to the second active surface of the second semiconductor die. [7] Semiconductor construction comprising: an insulating encapsulant (210), a first semiconductor die (110) embedded in the insulating encapsulant, the first semiconductor die having a first active area (110a) accessible from the insulating encapsulant (210) and a first lead terminal (112) wired to the first active area (110a), a second semiconductor die (120) embedded in the insulating encapsulant (210) and separated from the first semiconductor die, the second semiconductor die having a second active area (120a) accessible from the insulating encapsulant and a second lead terminal (122) wired to the second active area (120a), and a conductor track (312, 416, 516) winding from the first to the second lead terminal and thus connected between the first and second semiconductor dies, wherein a total length of the conductor track (312, 416, 516) is greater than a minimum distance (D) between the first and second lead terminals (112, 122) and the total length of the conductor track (312, 416, 516) is at least three times greater than the upper width (W) of the insulating encapsulant (210) between the first and second semiconductor dies, wherein the conductive track (312, 416, 516) comprises at least one turning segment (312a) located on a plane substantially perpendicular to the first active area (110a) of the first semiconductor die and to the second active area (120a) of the second semiconductor die. [8] The semiconductor structure of claim 7, wherein the smallest distance (D) between the first and second lead terminals (112, 122) is less than three times the upper width of the insulating encapsulant (210). [9] A semiconductor structure according to claim 7 or 8, wherein a gap (G) is located between the first and second semiconductor dies and the insulating encapsulant (210) fills the gap. [10] A semiconductor structure according to any one of the preceding claims 7 to 9, wherein the conductive trace (312, 416, 516) comprises at least one turning segment (312a) located on a plane substantially parallel to the first active area (110a) of the first semiconductor die and to the second active area (120a) of the second semiconductor die. [11] A semiconductor structure according to any one of the preceding claims 7 to 10, wherein the conductive trace (312a, 416, 516) comprises a first trace (416a, 516a) and a second trace (416c, 516c) connected to the first trace (416a, 516a), the first trace (416a, 516a) being located on a first plane substantially parallel to the first and second active areas (120a), and the second trace (416c, 516c) being located on a second plane substantially perpendicular to the first active area of ​​the first semiconductor die and to the second active area of ​​the second semiconductor die. [12] Semiconductor construction comprising: a plurality of semiconductor dies (110, 120), each of the semiconductor dies comprising an active area (110a, 120a), an insulating encapsulant (210) laterally encapsulating the semiconductor dies (110, 120), the semiconductor dies being spaced apart from one another by the insulating encapsulant (210), and a rewiring layer (310) arranged on the active areas of the semiconductor dies and the insulating encapsulant, wherein the rewiring layer (310) comprises a zigzag-shaped conductive structure (312a) corresponding to the insulating encapsulant (210) and electrically connected between the semiconductor dies; wherein the zigzag-shaped conductive structure (312a) of the rewiring layer (310) is located on a plane that is substantially perpendicular to the active areas (110a, 120a) of the semiconductor dies (110, 120). [13] The semiconductor structure of claim 12, wherein a minimum distance (D) between two adjacent semiconductor dies (110, 120) is greater than an upper width (W) of the insulating encapsulant (210) filling a gap (G) between the two adjacent semiconductor dies (110, 120). [14] The semiconductor construction of claim 12 or 13, wherein the zigzag-shaped conductive structure (312a) comprises a first trace (516a) and a second trace (516c) connected to the first trace (516a), the first trace (516a) being located on a first plane substantially parallel to the active areas (110a, 120a) of the semiconductor dies (110, 120), and the second trace (516c) being located on a second plane substantially perpendicular to the active areas of the semiconductor dies. [15] A semiconductor structure according to any one of the preceding claims 12 to 14, wherein each of the semiconductor dies (110, 120) comprises a lead terminal (112, 122) wired to its active area, and the zigzag-shaped conductive structure (312a) of the redistribution layer (310) is electrically connected to the lead terminals of the semiconductor dies.

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