Induction coil structure for integrated circuit

Abstract

Integrated circuit (500) comprising the following: several conductive layers (106, 108) comprising conductive wires (106) and conductive vias (108) arranged within one or more dielectric structures that are in contact with the first substrate (102); wherein the multiple conductive layers (106, 108) define an induction coil (110) having one or more turns (112) each comprising a vertically extending segment arranged along a plane intersecting the first substrate (102); and wherein the vertically extending segment includes several of the conductive wires (106) and the conductive vias (108), wherein the multiple conductive interconnect layers (106, 108) comprise a first plurality of conductive interconnect layers (306) arranged within a first ILD structure (304) comprising multiple stacked ILD layers, the integrated circuit (500) further comprises the following: a second substrate (406); and a second ILD structure (408) arranged between the second substrate (406) and the first ILD structure (304) and surrounding a second plurality of conductive interconnect layers (410), wherein the multiple conductive interconnect layers (106, 108) further comprise the second plurality of conductive interconnect layers, the vertically extending segment comprises the following: a first conductive interconnect via (324a) having first sidewalls angled such that the first width of the first conductive interconnect via (324a) increases as its distance from the first substrate (102) increases; and a second conductive interconnect via (324b) having second side walls angled such that the width of the second conductive interconnect via (324b) decreases as its distance from the first substrate (102) increases.

Description

BACKGROUND

[0001] Semiconductor devices are used in a wide variety of electronic applications, such as personal computers, mobile phones, digital cameras, etc. To provide different functionalities for different applications, integrated chips have circuits that employ a wide range of active and passive components. A commonly used passive component is an inductor. An inductor is a conductive coil that has one or more turns and is configured to store electrical energy in a magnetic field when an electric current flows through it. Inductors are widely used in filters (e.g., RL filters), harmonic oscillators, and many other circuit components. The inductance L of an inductor can be calculated as: L=μN2Al, where L is the inductance; µ is the magnetic permeability; N is a number of turns of the induction coil; A is the surface area of ​​the turns; and l is the length of the coil.

[0002] From US 2008 / 0 297 299 A1, a spiral inductor is known which is arranged vertically in a plurality of insulating layers formed on a substrate, with a plurality of first conductive lines arranged in the insulating layers and through holes formed vertically in the insulating layers to electrically connect the plurality of first conductive lines.

[0003] DE 10 2008 010 070 A1 describes a device with a planar coil arranged in a metallization above and perpendicular to a substrate. Some described embodiments include multiple planar coils arranged in the metallization above and perpendicular to the substrate, which can be electrically connected or only inductively coupled.

[0004] US 2012 / 0 268 229 A1 discloses a device comprising a substrate and a vertical inductor above the substrate. The vertical inductor comprises a plurality of parts formed from metal, each of the parts extending in one of a plurality of planes perpendicular to a major surface of the substrate. Metal lines interconnect adjacent parts of the plurality of parts of the vertical inductor.

[0005] DE 10 2015 105 952 A1 describes a device comprising a first semiconductor die and a second semiconductor die, an encapsulant that encapsulates the first semiconductor die and the second semiconductor die, and a first connecting device that electrically connects the first semiconductor die and the second semiconductor die, wherein the first connecting device extends over the first semiconductor die, the second semiconductor die and the encapsulant.

[0006] US 2015 / 0 302 975 A1 discloses a spiral inductor formed in a vertical plane relative to a planar surface of a substrate. It comprises a plurality of through holes arranged in the vertical plane and spaced apart from each other, a metal interconnect structure on the upper surface, and a redistribution layer on the lower surface comprising at least one lower metal layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying figures. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. Rather, the dimensions of the various features may be arbitrarily exaggerated or reduced to facilitate discussion. Fig. 1 illustrates a cross-sectional view of a non-claimed embodiment of an integrated circuit with an inductor. Fig. 2 illustrates a three-dimensional view of a non-claimed embodiment of an integrated circuit with an induction coil. Fig. 3A-3C illustrate cross-sectional views of some further unclaimed embodiments of integrated circuits with an inductor. Fig. 4 illustrates a cross-sectional view of a non-claimed embodiment of a stacked integrated circuit structure with an inductor. Fig. 5 illustrates a cross-sectional view of an embodiment of a stacked integrated circuit structure with an inductor according to the invention. Fig. 6 illustrates a cross-sectional view of an embodiment of a stacked integrated circuit structure with an inductor according to the invention. Fig. 7 illustrates a cross-sectional view of an embodiment of a stacked integrated circuit structure with an inductor according to the invention. Fig. 8-10 illustrate cross-sectional views of some embodiments of a method for forming an integrated circuit with an inductor. Fig. 11 illustrates a flowchart of some embodiments of a method for forming an integrated circuit with an inductor. Fig. 12-17 illustrate cross-sectional views of some embodiments of a method for forming a stacked integrated circuit structure with an inductor. Fig. 18 illustrates a flow diagram of some embodiments of a method for forming a stacked integrated circuit structure with an inductor. DETAILED DESCRIPTION

[0008] The following disclosure provides many different embodiments or examples for implementing various features of the subject matter discussed herein. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not limiting. For example, the formation of a first structural element over or on a second structural element in the following description may include embodiments in which the first and second structural elements are formed in direct contact, and may also include embodiments in which additional structural elements may be formed between the first and second structural elements such that the first and second structural elements are not necessarily in direct contact.Furthermore, the present disclosure may repeat reference numbers and / or letters throughout the various examples. This repetition is for the purpose of simplicity and clarity and does not automatically establish a relationship between the various embodiments and / or configurations discussed.

[0009] Furthermore, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein to simplify description and to describe the relationship of one element or structural element to one or more other elements or structural elements, as illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the device during use or operation in addition to the orientation shown in the figures. The device may also be oriented differently (rotated 90 degrees or oriented differently), and the spatially relative descriptors used herein can be interpreted accordingly.

[0010] In the semiconductor industry, consumer demands have led to a continuous increase in integrated circuit densities. To achieve higher circuit densities, the semiconductor industry has continuously reduced the minimum feature sizes of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) so that more components can be formed within a given area of ​​an integrated chip. However, inductors present a number of difficulties with such scaling.

[0011] Generally, inductors are formed within back-end-of-line (BEOL) metal interconnect layers over a substrate. An inductor comprises one or more turns, each disposed within a metal interconnect wire layer. For example, an inductor may comprise a first turn disposed within a first metal interconnect wire layer and a second turn disposed on top of the first metal wire layer and surrounding the first turn. Because the inductance of an inductor is directly proportional to the surface area of ​​the inductor's turns, the inductor can occupy a relatively large amount of space to achieve a desired inductance.

[0012] In addition, inductors in integrated circuits have also been found to suffer from planarization problems due to chemical mechanical planarization (CMP) processes used to form the metal interconnect wire layers. For example, a CMP process can cause dishing along the top surface of a metal interconnect wire layer (because the metal can be removed at a faster rate than the surrounding dielectric). Dishing can change the resistance of a metal interconnect wire layer, thereby altering the current flowing through an inductor and the resulting response of the inductor.

[0013] The present disclosure, in some embodiments, relates to an integrated circuit having an inductor comprising one or more turns arranged along vertical planes that intersect an underlying substrate. In some embodiments, the integrated circuit has a plurality of conductive routing layers comprising conductive wires and conductive vias arranged within one or more dielectric structures adjacent to the first substrate. The plurality of conductive routing layers define an inductor having one or more turns, each comprising a vertically extending segment arranged along a plane that intersects the first substrate. The vertically extending segment includes a plurality of the conductive wires and the conductive vias.By orienting the induction coil to have turns arranged along vertical planes that intersect an underlying substrate, the size of the induction coil can be reduced and cupping problems that affect induction coil performance can be alleviated.

[0014] Fig. 1 illustrates a cross-sectional view of an unclaimed embodiment of an integrated circuit 100 including an inductor.

[0015] The integrated circuit 100 includes an inductor 110 defined by conductive routing layers 106 and 108 disposed within one or more dielectric structures disposed along one or more surfaces of a first substrate 102. In some embodiments, the one or more dielectric structures may include a first dielectric structure 104 disposed along a first surface 102a of the first substrate 102. In other embodiments (not shown), the one or more dielectric structures may further include a second dielectric structure disposed along a second surface of the first substrate 102 opposite the first surface 102a.

[0016] The induction coil 110 has one or more turns 112 (in Fig. 1, a single turn is shown) that wind around an axis 113. The axis 113 extends along a line that does not intersect a surface of the first substrate 102 that lies directly beneath the inductor 110. For example, in some embodiments, the axis 113 may extend parallel to a first surface 102a of the first substrate 102. The one or more turns 112 each comprise a plurality of the conductive routing layers 106 and 108. In some embodiments, the conductive routing layers 106 and 108 may comprise alternating layers of conductive vias 108 (configured to provide vertical connections) and conductive wires 106 (configured to provide lateral connections). The conductive wires 106 extend past one or more sides of the conductive vias 108.For example, in some embodiments, the conductive wires 106 may extend past opposite sides of the conductive vias 108.

[0017] The one or more turns 112 of the induction coil 110 each include one or more vertically extending segments 114a-114b coupled to one or more horizontally extending segments 116a-116b. The vertically extending segments 114a-114b are aligned to be disposed along planes that intersect the first substrate 102. The vertically extending segments 114a-114b each include a plurality of conductive wires 106 and conductive vias 108. For example, in some embodiments, the vertically extending segments 114a-114b may have two or more conductive wires 106 and two or more conductive vias 108. The horizontally extending segments 116a-116b extend parallel to the first surface 102a of the first substrate 102 and include a conductive wire 106 coupled to one or more of the vertically extending segments 114a-114b.

[0018] By orienting the inductor 110 so that it winds around the axis 113, which does not intersect the first surface 102a of the first substrate 102, which lies directly beneath the inductor 110, the turns 112 of the inductor 110 can have a relatively large surface area without causing the inductor 110 to occupy much space of the first substrate 102. Because the turns 112 can have a relatively large surface area, the inductor can provide a relatively large inductance, allowing the inductor 110 to meet design specifications while conserving valuable space on the integrated circuit 100.Furthermore, because the turns 112 of the inductor extend in a vertical direction, the effects of CMP-induced cupping are reduced compared to conventional inductors (e.g., cupping does not occur along an entire length of the turns 112 and therefore does not cause large deviation of the turns 112 from their intended design).

[0019] Fig. 2 illustrates a three-dimensional (3D) view of an unclaimed integrated circuit 200 with an induction coil.

[0020] The integrated circuit 200 includes a plurality of conductive routing layers 106 and 108 disposed within a first dielectric structure 104 over a first substrate 102. The first substrate 102 may be any type of semiconductor body (e.g., silicon, SiGe, SOI, etc.), as well as any other type of semiconductor and / or epitaxial layers connected thereto. For example, in some embodiments, the first substrate 102 may include a base substrate and an epitaxial layer. The plurality of conductive routing layers 106 and 108 include alternating layers of conductive wires 106 and conductive vias 108.

[0021] The plurality of conductive layers 106 and 108 define an induction coil 110. The induction coil 110 has a first terminal 202 and a second terminal 204. During operation, a current is configured to flow from the first terminal 202 to the second terminal 204, or vice versa. As the current flows through the induction coil 110, a magnetic field is generated along an axis 113. As the current flowing through the induction coil 110 changes, the time-varying magnetic field induces a voltage according to Faraday's law of induction.

[0022] The induction coil 110 has a plurality of turns 112a-112c that wind around the axis 113. For example, the induction coil 110 may include a first turn 112a, a second turn 112b, and a third turn 112c that wind around the axis 113. The axis 113 extends along a line that does not intersect a region of the first substrate 102 directly beneath the induction coil 110. The plurality of turns 112a-112c include vertically extending segments coupled together by horizontally extending segments. The vertically extending segments each include a plurality of conductive wires 106 and conductive vias 108, while the horizontally extending segments include conductive wires 106.In some embodiments, the horizontally extending segments may have a connecting shoulder that allows the horizontally extending segments to be connected to adjacent ones of the plurality of turns 112a-112c. In some alternative embodiments, the vertically extending segments may also extend in a horizontal direction (e.g., the vertically extending segments may have vias that are horizontally offset along a horizontal direction). In such embodiments, the vertically extending segments may be connected to a horizontal segment that is substantially straight.

[0023] In some embodiments, the plurality of turns 112a-112c are interconnected by a lower one of the conductive wires 106. In other embodiments (not shown), the plurality of turns 112a-112c may be interconnected by other ones of the conductive wires 106. For example, in some embodiments, the first turn 112a may be coupled to the second turn 112b by an upper one of the conductive wires 106. In other embodiments, the first turn 112a may be coupled to the second turn 112b by one of the conductive wires 106 that is located between the upper and lower conductive wires.In further embodiments, the first turn 112a may be coupled to the second turn 112b by means of a first of the conductive wires 106, and the second turn 112b may be coupled to the third turn 112c by means of a second of the plurality of conductive wires 106 that is at a different height from the first substrate 102 than the first of the conductive wires 106.

[0024] The multiple turns 112a-112c of the inductor 110 may be arranged along vertically extending planes that intersect the first substrate 102. Because the turns 112a-112c of the inductor 110 are arranged along vertically extending planes, the turns 112a-112c of the inductor 110 may have a relatively large surface area while occupying a relatively small area of ​​the first substrate 102. Therefore, the inductor 110 may provide high inductance with a minimal footprint. For example, the multiple turns 112a-112c may extend along a length (L) of 99.5 µm and each have a width (W) of 200 µm and a height (H) of 300 µm, resulting in the inductor 110 having a footprint of approximately 19990 µm. 2In comparison, an induction coil having the same dimensions but oriented around an axis intersecting the first substrate 102 would require a significantly larger footprint of approximately 60,000 µm 2 .

[0025] Fig. 3A-3C illustrate cross-sectional views of some further unclaimed embodiments of integrated circuit structures with an inductor.

[0026] Fig. 3A illustrates a cross-sectional view of an unclaimed embodiment of an integrated circuit structure 300 having an inductor disposed within conductive interconnect layers.

[0027] The integrated circuit structure 300 includes a first interlayer dielectric (ILD) structure 304 disposed along a front side 102f of a first substrate 102 having a plurality of transistor devices 302. A second dielectric structure 310 is disposed along a back side 102b of the first substrate 102 opposite the front side 102f. The first ILD structure 304 surrounds a first plurality of conductive interconnect layers 306 comprising alternating layers of conductive interconnect wires 322 and conductive interconnect vias 324.

[0028] The second dielectric structure 310 surrounds a plurality of redistribution layers 312 configured to couple the first plurality of conductive interconnect layers 306 to a bond pad 318 disposed along the backside 102b of the first substrate 102. The bond pad 318 comprises a conductive material (e.g., a metal such as aluminum or the like) and has an exposed top surface. The bond pad 318 is configured to provide an electrical connection between the integrated circuit structure 300 and an external device. For example, a solder bump (not shown) may be formed on the bond pad 318 to connect the bond pad 318 to an external I / O pin of an integrated chip package. In some embodiments, the second dielectric structure 310 may be separated from the first substrate 102 by a passivation layer 320.In such embodiments, the plurality of redistribution layers 312 extend through the passivation layer 320. In some embodiments, the passivation layer 320 may comprise an oxide, a nitride (e.g., silicon nitride), or the like.

[0029] The first plurality of conductive interconnect layers 306 defines an inductor 110 comprising a plurality of turns 112 wound around an axis 113 extending along a line that does not intersect a surface of the first substrate 102 directly underlying the inductor 110. The plurality of turns 112 each comprise a plurality of the conductive interconnect wires 322 and a plurality of the conductive interconnect vias 324. For example, a first turn comprises a vertically extending segment comprising a plurality of conductive interconnect wires 322 and conductive interconnect vias 324.

[0030] In some embodiments, a diffusion barrier layer 326 extends continuously along an outer boundary of a conductive interconnect wire 322 and a conductive interconnect via 324 between the conductive interconnect wire 322 and the first substrate 102. In such embodiments, a metal of the conductive interconnect wire 322 may directly contact a metal of the conductive interconnect via 324. In various embodiments, the diffusion barrier layer 326 may comprise tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), cobalt tungsten (CoW), or the like.

[0031] Fig. 3B illustrates a cross-sectional view of an unclaimed embodiment of an integrated circuit structure 328 having an inductor disposed within redistribution layers.

[0032] The integrated circuit structure 328 includes a first ILD structure 304 disposed along a front side 102f of a first substrate 102 and a second dielectric structure 310 disposed along a back side 102b of the first substrate 102. The first ILD structure 304 surrounds a first plurality of conductive interconnect layers 306. The second dielectric structure 310 surrounds a plurality of redistribution layers 312 configured to couple the first plurality of conductive interconnect layers 306 to a bond pad 318 disposed along the back side 102b of the first substrate 102.

[0033] The plurality of redistribution layers 312 include alternating layers of redistribution vias 314 and redistribution wires 316. In some embodiments, the plurality of redistribution layers 312 are coupled to the first plurality of conductive interconnect layers 306 by means of one or more through-substrate vias (TSVs) 308 that extend through the first substrate 102. The plurality of redistribution layers 312 define an inductor 110 that includes a plurality of turns 112 wound around an axis 113 that extends along a line that does not intersect a region of the first substrate 102 directly underlying the inductor 110. The plurality of turns 112 each include a plurality of redistribution vias 314 and a plurality of redistribution wires 316.

[0034] In some embodiments, the plurality of redistribution layers 312 are larger than the plurality of conductive interconnect layers. In some embodiments, the redistribution layers 312 may have layers with a height ranging between approximately 1 µm and approximately 50 µm. The relatively large size of the plurality of redistribution layers 312 allows the inductor 110 to have turns with a relatively large surface area, allowing the inductor 110 to have a smaller footprint while meeting device specifications.

[0035] Fig. 3C illustrates a cross-sectional view of another unclaimed embodiment of an integrated circuit structure 330 having an inductor extending through a first substrate.

[0036] The integrated circuit structure 300 includes a first ILD structure 304 disposed along a front side 102f of a first substrate 102 and a second dielectric structure 310 disposed along a back side 102b of the first substrate 102. The first ILD structure 304 surrounds a first plurality of conductive interconnect layers 306. The second dielectric structure 310 surrounds a plurality of redistribution layers 312 configured to couple the first plurality of conductive interconnect layers 306 to a bond pad 318 disposed along the back side 102b of the first substrate 102. A plurality of TSVs 308 extend through the first substrate 102 from one of the first plurality of conductive interconnect layers 306 to one of the plurality of redistribution layers 312.

[0037] An inductor 110 is defined by one or more of the first plurality of conductive interconnect layers 306, the TSVs 308, and one or more of the plurality of redistribution layers 312. The inductor 110 includes a plurality of turns 112 wound around an axis 113 that extends along a line that does not intersect a surface of the first substrate 102 directly beneath the inductor 110. In some embodiments, the substrate 102 has a thickness in a range between approximately 50 µm and approximately 200 µm, allowing the inductor 110 to have turns with a relatively large surface area.

[0038] Fig. 4 illustrates a cross-sectional view of a non-claimed embodiment of a stacked integrated circuit structure 400 with an inductor.

[0039] The stacked integrated circuit structure 400 includes a first integrated chip die 402 and a second integrated chip die 404. The first integrated chip die 402 includes a first substrate 102 and a first ILD structure 304 disposed along a front side 102f of the first substrate 102. The first ILD structure 304 surrounds a first plurality of conductive interconnect layers 306. In some embodiments, the first substrate 102 may include one or more transistor devices 302. In other embodiments, the first substrate 102 may alternatively and / or additionally include, for example, imaging devices or MEMS devices. The second integrated chip die 404 includes a second substrate 406 and a second ILD structure 408 between the first ILD structure 404 and the second substrate 406. The second ILD structure 408 surrounds a second plurality of conductive interconnect layers 410.In some embodiments, the second substrate 406 may include one or more transistor devices 412.

[0040] The first ILD structure 304 and the second ILD structure 408 each comprise a plurality of stacked ILD layers. In various embodiments, the plurality of stacked ILD layers may comprise one or more of an oxide (e.g., SiO2, SiCO, etc.), a fluorosilicate glass, a phosphate glass (e.g., borophosphate silicate glass), or the like. The first plurality of conductive interconnect layers 306 and the second plurality of conductive interconnect layers 410 each comprise a plurality of alternating conductive interconnect via and conductive interconnect wire layers. In various embodiments, the plurality of alternating conductive interconnect via and conductive interconnect wire layers may comprise aluminum, copper, tungsten, or the like.

[0041] The first integrated chip die 402 is vertically stacked on the second integrated chip die 404 in a face-to-face (F2F) hybrid bonding configuration. Within the F2F hybrid bonding configuration, the first ILD structure 304 contacts the second ILD structure 408 along a bonding interface 414. Furthermore, first conductive contact pads 416a within the first ILD structure 304 contact second conductive contact pads 416b within the second ILD structure 408 along the bonding interface 414. In some embodiments, the first conductive contact pads 416a are coupled to the first plurality of conductive interconnect layers 306 via a first conductive via 418a, and the second conductive contact pads 416b are coupled to the second plurality of conductive interconnect layers 410 via a second conductive via 418b.In some embodiments, the conductive contact pads 416a-416b and the conductive vias 418a-418b may comprise a metal such as copper.

[0042] In some embodiments, the first plurality of conductive interconnect layers 306 is coupled to a plurality of redistribution layers 312 disposed along a backside 102b of the first substrate 102 via a TSV 308 extending through the first substrate 102. The plurality of redistribution layers 312 couple the first plurality of conductive interconnect layers 306 to a bond pad 318 disposed along the backside 102b of the first substrate 102. The plurality of redistribution layers 312 define an inductor 110 comprising a plurality of turns 112 wound around an axis 113 extending along a line that does not intersect a surface of the first substrate 102 directly underlying the inductor 110. The plurality of turns 112 each include a plurality of redistribution vias 314 and a plurality of redistribution wires 316.

[0043] Fig. 5 illustrates a cross-sectional view of an embodiment of a stacked integrated circuit structure 500 with an inductor according to the invention.

[0044] The stacked integrated circuit structure 500 includes a first integrated chip die 402 stacked on the second integrated chip die 404 in a face-to-face (F2F) hybrid bond configuration. The first integrated chip die 402 includes a first substrate 102 and a first ILD structure 304 disposed along a front side 102f of the first substrate 102. The first ILD structure 304 surrounds a first plurality of conductive interconnect layers 306. The second integrated chip die 404 includes a second substrate 406 and a second ILD structure 408 disposed between the first ILD structure 304 and the second substrate 406. The second ILD structure 408 surrounds a second plurality of conductive interconnect layers 410.

[0045] The first plurality of conductive interconnect layers 306 and the second plurality of conductive interconnect layers 410 collectively define an inductor 110 comprising a plurality of turns 112 wound around an axis 113 extending along a line that does not intersect a surface of the first substrate 102 directly underlying the inductor 110. The plurality of turns 112 each comprise a first plurality of conductive interconnect wires and conductive interconnect vias of the first plurality of conductive interconnect layers 306 and a second plurality of conductive interconnect wires and conductive interconnect vias of the second plurality of conductive interconnect layers 410.

[0046] In some embodiments, the first plurality of conductive interconnect layers 306 has a size that increases as a distance from the first substrate 102 increases. For example, a first conductive interconnect wire 322a may have a smaller size than a second conductive interconnect wire 322b, which is separated from the first substrate 102 by the first conductive interconnect wire 322a. Similarly, the second plurality of conductive interconnect layers 410 may also have a size that increases as a distance from the second substrate 406 increases.Because the sizes of the first plurality of conductive interconnect layers 306 and the second plurality of conductive interconnect layers 410 increase as a distance from an associated substrate increases, the inductor 110 may have a vertically extending segment including conductive interconnect wires that increase in size from a first width to a second width and decrease in size from the second width to a third width (e.g., substantially equal to the first width) along a line extending in a direction intersecting the front side 102f of the first substrate 102.

[0047] In some embodiments, the conductive interconnect vias and the conductive interconnect wires within the first plurality of conductive interconnect layers 306 have angled sidewalls that cause a size of respective ones of the first plurality of conductive interconnect layers 306 to increase as a distance from the first substrate 102 increases. For example, the first plurality of conductive interconnect layers 306 may include a first conductive interconnect via 324a whose sidewalls are angled at an angle θ1 such that a width of the first conductive interconnect via 324a increases as a distance from the first substrate 102 increases.Likewise, the conductive interconnect vias and conductive interconnect wires within the second plurality of conductive interconnect layers 410 have angled sidewalls that cause a size of respective ones of the second plurality of conductive interconnect layers 410 to increase as a distance from the second substrate 406 increases. For example, the second plurality of conductive interconnect layers 410 may include a second conductive interconnect via 324b whose sidewalls are angled at an angle θ2 such that a width of the second conductive interconnect via 324b increases as a distance from the second substrate 406 increases.Because the inductor 110 is defined by the first plurality of conductive interconnect layers 306 and the second plurality of conductive interconnect layers 410, the vertically extending segment of the inductor 110 has a first conductive interconnect via 324a with a width that increases as a distance from the first substrate 102 increases and a second conductive interconnect via 324b with a width that decreases as a distance from the first substrate 102 increases.

[0048] Fig. 6 illustrates a cross-sectional view of an embodiment of a stacked integrated chip structure 600 with an inductor according to the invention.

[0049] The stacked integrated chip structure 600 includes an inductor 110 defined by one or more of a first plurality of conductive interconnect layers 306, TSVs 308a-308b, and one or more of a plurality of redistribution layers 312. The inductor 110 includes a plurality of turns 112, each extending through the first substrate 102. For example, the inductor 110 may include a turn each having a first vertically extending segment including a first TSV 308a extending through the first substrate 102 and a second vertically extending segment including a second TSV 308b extending through the first substrate 102. The plurality of turns 112 wind around an axis 113 that extends along a line that does not intersect a surface of the first substrate 102 that lies directly beneath the induction coil 110.

[0050] Fig. 7 illustrates a cross-sectional view of an embodiment of a stacked integrated chip structure 700 with an inductor according to the invention.

[0051] The stacked integrated chip structure 700 includes an inductor 110 defined by a first plurality of conductive interconnect layers 306, a second plurality of conductive interconnect layers 410, a plurality of TSVs 308a-308b, and one or more of a plurality of redistribution layers 312. The inductor 110 includes a plurality of turns 112, each extending through the first substrate 102. For example, the inductor 110 may include a turn each having a first vertically extending segment including a first TSV 308a extending through the first substrate 102 and a second vertically extending segment including a second TSV 308b extending through the first substrate 102.The induction coil 110 comprises a plurality of turns 112 wound around an axis 113 extending along a line that does not intersect a surface of the first substrate 102 directly beneath the induction coil 110.

[0052] In some embodiments, one or more of the plurality of TSVs 308, the first plurality of conductive interconnect layers 306, the second plurality of conductive interconnect layers 410, and / or the plurality of redistribution layers 312 may comprise different materials, such that the vertically extending segments of the inductor 110 include components having different materials. For example, the first plurality of conductive interconnect layers 306 may comprise copper, the plurality of TSVs 308 may comprise copper, and the plurality of redistribution layers 312 may comprise aluminum.

[0053] Fig. 8-10 illustrate cross-sectional views 800-1000 of some unclaimed embodiments of a method for forming an integrated circuit with an inductor. Although the Fig. 8-10 are described in relation to a method, it is understood that the Fig. 8-10 are not limited to such a method, but instead can also exist independently as structures independent of the method.

[0054] As shown in cross-sectional view 800 of Fig. 8, a first conductive wire 106a defining a first horizontal segment 116a of an inductor coil is formed within a first dielectric structure 104 disposed along a first surface of a first substrate 102.

[0055] As shown in cross-sectional view 900 of Fig. 9, one or more conductive wires 106b and / or conductive vias 108a-108b are formed to define a first vertical segment 114a and a second vertical segment 114b of the inductor. In some embodiments, the one or more conductive wires 106b and / or conductive vias 108a-108b may be formed within the first dielectric structure 104. In other embodiments (not shown), the one or more conductive wires 106b and / or conductive vias 108a-108b may be formed within a second dielectric structure disposed along a backside 102b of the first substrate 102 opposite the first surface 102a.In further embodiments (not shown), the one or more conductive wires 106b and / or conductive vias 108a-108b may comprise substrate vias (TSVs) formed within the first substrate 102.

[0056] As shown in the cross-sectional view 1000 of Fig. 10, a second conductive wire 106c, defining a second horizontal segment 116b of the inductor 110, is formed within the first dielectric structure 104 or the second dielectric structure (not shown). The second horizontal segment 116b of the inductor 110 completes a turn 112 of the inductor 110, which winds around an axis 113 extending along a line that does not intersect a surface of the first substrate 102 directly underlying the inductor 110.

[0057] Fig. 11 illustrates a flowchart of some unclaimed embodiments of a method 1100 for forming an integrated circuit with an inductor.

[0058] Although the disclosed methods (e.g., methods 1100 and 1800) are illustrated and described below as a series of actions or events, it should be understood that the illustrated order of such actions or events should not be construed in a limiting sense. For example, some actions may be performed in different orders and / or concurrently with other actions or events than those illustrated and / or described herein. Moreover, not all of the illustrated actions may be required to implement one or more aspects or embodiments of the description herein, and one or more of the actions shown herein may be performed in one or more separate actions and / or phases.

[0059] At 1102, a first conductive wire is formed within a first dielectric structure disposed along a first surface of a first substrate to define a first horizontal segment of an inductor. Fig. 8 illustrates a cross-sectional view 800 of some embodiments corresponding to action 1102.

[0060] At 1104, one or more conductive wires and / or conductive vias are formed to define a vertical segment of the inductor coupled to the first horizontal segment. Fig. 9 illustrates a cross-sectional view 900 of some embodiments corresponding to action 1104.

[0061] At 1106, a second conductive wire is formed within a second dielectric structure disposed along a second surface of the first substrate to define a second horizontal segment of an inductor. In some embodiments, the first dielectric structure may be the same as the second dielectric structure, while in other embodiments, the first and second dielectric structures may comprise different dielectric structures separated by the first substrate. Fig. 10 illustrates a cross-sectional view 1000 of some embodiments corresponding to action 1106.

[0062] Fig. 12-17 illustrate cross-sectional views 1200-1700 of some embodiments of a method for forming a stacked integrated chip structure with an inductor. Although the Fig. 12-17 in relation to a method, it is understood that the Fig. 12-17 are not limited to such a process, but instead can also exist independently as structures independent of the process.

[0063] As shown in the cross-sectional view 1200 of Fig. 12, a first integrated chip die 402 is formed by forming a first plurality of conductive interconnect layers 306 within a first ILD structure 304 comprising a first plurality of stacked ILD layers over a first substrate 102. In some embodiments, the first plurality of conductive interconnect layers 306 may be formed using a damascene process (e.g., a single damascene process or a dual damascene process). The damascene process is performed by: forming an ILD layer over the first substrate 102, etching the ILD layer to form a via hole and / or a metal trench, and filling the via hole and / or the metal trench with a conductive material. In some embodiments, the ILD layer may be deposited by a physical vapor deposition technique (e.g., PVD, CVD, PE-CVD, ALD, etc.).), and the conductive material may be formed using a deposition process and / or a plating process (e.g., electroplating, chemical plating, etc.). In various embodiments, the first plurality of conductive interconnect layers 306 may comprise tungsten, copper, aluminum-copper, or the like.

[0064] In some embodiments, first conductive contact pads 416a may be formed within the first ILD structure 304 over the first plurality of conductive interconnect layers 306. The first conductive contact pads 416a may be coupled to the first plurality of conductive interconnect layers 306 via first conductive vias 418a. In some embodiments, the first conductive contact pads 416a and the first conductive vias 418a may comprise a metal, such as copper.

[0065] As shown in cross-sectional view 1300 of Fig. 13, a second integrated chip die 404 is formed by forming a second plurality of conductive interconnect layers 410 within a second ILD structure 408 comprising a second plurality of stacked ILD layers over a second substrate 406. In some embodiments, the second plurality of conductive interconnect layers 410 may be formed using a damascene process (e.g., a single damascene process or a dual damascene process), as described above. In some embodiments, second conductive contact pads 416b may be formed within the second ILD structure 408 over the second plurality of conductive interconnect layers 410. The second conductive contact pads 416b may be coupled to the second plurality of conductive interconnect layers 410 by means of second conductive vias 418b.In some embodiments, the second conductive contact pads 416b and the second conductive vias 418b may comprise a metal such as copper.

[0066] As shown in the cross-sectional view 1400 of Fig. As shown in Figure 14, the first integrated chip die 402 is bonded to the second integrated chip die 404 along a bonding interface 414. Along the bonding interface 414, the first ILD structure 304 abuts the second ILD structure 408, and the first conductive contact pads 416a abut the second conductive contact pads 416b. In some embodiments, bonding is performed by aligning the first conductive contact pads 416a and the second conductive contact pads 416b, and then applying pressure and heat. The pressure may be a maximum of approximately 30 MPa, and the heat may range between approximately 100°C and 500°C. The hybrid bonding process results in the formation of a bond between dielectric and conductive materials.

[0067] As shown in the cross-sectional view 1500 of Fig. As shown in Figure 15, the first substrate 102 is thinned to reduce a thickness of the first substrate 102 (e.g., from a thickness t to a thickness t-δ). The first substrate 102 may be thinned using an etching process and / or a physical grinding process. In some embodiments, the first substrate 102 may have a thickness reduced from a first thickness t in a range between approximately 700 μm and approximately 1000 μm to a second thickness t-δ in a range between approximately 50 μm and approximately 200 μm.

[0068] As shown in the cross-sectional view 1600 of Fig. 16, a plurality of TSVs 308 are formed to extend through the first substrate 102. The plurality of TSVs 308 extend from the first plurality of conductive interconnect layers 306 to a backside of the first substrate 102. In some embodiments, the plurality of TSVs 308 are formed by forming a masking layer on the backside 102b of the first substrate 102. In various embodiments, the masking layer may comprise a dielectric material, such as silicon dioxide, silicon nitride, or the like. After the masking layer is formed, the first substrate 102 is selectively treated with one or more etchants configured to form sidewalls defining TSV openings 1602 that extend through the first substrate 102. In various embodiments, the one or more etchants may comprise dry and / or wet etchants.After the TSV openings 1602 are defined, a conductive material is formed within the TSV openings 1602 to form the plurality of TSVs 308. The conductive material may be formed by depositing a barrier layer and / or a seed layer within the TSV openings 1602 and then performing a plating process (e.g., an electroplating process or a chemical plating process) to fill the TSV openings 1602 with the conductive material.

[0069] In some embodiments, the conductive material may comprise a metal such as copper. In some embodiments, the barrier layer may comprise tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), cobalt tungsten (CoW), or the like. In some embodiments, the conductive material may be separated from the first substrate 102 by a dielectric separation layer. In various embodiments, the dielectric separation layer may comprise an oxide, a nitride, or the like. For example, the dielectric separation layer may comprise silicon oxide deposited by plasma-enhanced chemical vapor deposition (PECVD) using silane or TEOS as the silicon source. An etch process may be performed to remove the dielectric separation layer from the bottom of the TSV openings 1602 before the barrier layer and the seed layer are formed.

[0070] As shown in the cross-sectional view 1700 of Fig. As shown in Figure 17, a plurality of redistribution layers 312 are formed over the TSVs 308. The plurality of redistribution layers 312 may be formed by depositing a metal and then patterning the metal to define a redistribution layer. A dielectric layer is then formed over the redistribution layer. In various embodiments, the plurality of redistribution layers 312 may comprise a metal, such as aluminum, copper, or the like. In various embodiments, the dielectric layer may comprise an epoxy, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), or the like.

[0071] As shown in cross-sectional view 1700, the plurality of redistribution layers 312, the TSVs 308, the first plurality of conductive interconnect layers 306, and the second plurality of conductive interconnect layers 410 define an inductor 110 including a plurality of turns 112, each extending through the first substrate 102. In other embodiments illustrated above, the inductor 110 may be defined by one or more of the plurality of redistribution layers 312, the TSVs 308, the first plurality of conductive interconnect layers 306, and the second plurality of conductive interconnect layers 410.

[0072] Fig. 18 illustrates a flowchart of some unclaimed embodiments of a method 1800 for forming an integrated chip with an inductor.

[0073] At 1802, a first integrated chip die is formed by forming a first plurality of conductive interconnect layers within a first dielectric structure on a front side of a first substrate. In some embodiments, the first plurality of conductive interconnect layers defines a portion of an inductor. In other embodiments, the first plurality of conductive interconnect layers does not define a portion of an inductor. Fig. 12 illustrates a cross-sectional view 1200 of some embodiments corresponding to action 1802.

[0074] At 1804, a second integrated chip die is formed by forming a second plurality of conductive interconnect layers within a second dielectric structure on a second substrate. In some embodiments, the second plurality of conductive interconnect layers defines a portion of an inductor. In other embodiments, the second plurality of conductive interconnect layers does not define a portion of an inductor. Fig. 13 illustrates a cross-sectional view 1300 of some embodiments corresponding to action 1804.

[0075] At 1806, the first integrated chip die is bonded to the second integrated chip die along a hybrid bonding interface comprising dielectric and conductive materials. Fig. 14 illustrates a cross-sectional view 1400 of some embodiments corresponding to action 1806.

[0076] At 1808, the first substrate is thinned. Thinning the first substrate reduces a thickness of the first substrate. Fig. 15 illustrates a cross-sectional view 1500 of some embodiments corresponding to action 1808.

[0077] At 1810, TSVs are formed that extend through the first substrate to the first plurality of conductive interconnect layers. In some embodiments, the TSVs define a portion of an inductor. In other embodiments, the TSVs do not define a portion of an inductor. Fig. 16 illustrates a cross-sectional view 1600 of some embodiments corresponding to action 1810.

[0078] At 1812, one or more redistribution layers are formed along a backside of the first substrate. The one or more redistribution layers are disposed within a dielectric structure disposed on a side of the first substrate opposite the first ILD structure. In some embodiments, the one or more redistribution layers define a portion of an inductor. In other embodiments, the one or more redistribution layers do not define a portion of an inductor. Fig. 17 illustrates a cross-sectional view 1700 of some embodiments corresponding to action 1812.

[0079] At 1814, a bond pad is formed over the one or more redistribution layers. The bond pad is coupled to the first plurality of conductive interconnect layers through the one or more redistribution layers. Fig.17 illustrates a cross-sectional view 1700 of some embodiments corresponding to action 1814.

[0080] Therefore, the present disclosure relates to an integrated chip having an inductor oriented to wrap around an axis that does not intersect a region of the substrate directly beneath the inductor. According to the invention, the present disclosure relates to an integrated circuit according to claim 1 and a semiconductor device according to claim 6.

[0081] In further unclaimed embodiments, the present disclosure relates to a method of forming an integrated circuit. The method includes forming a first conductive wire defining a first horizontal segment of an inductor within a first dielectric structure along a first surface of a first substrate. The method further includes forming one or more conductive wires or conductive vias defining vertical segments of the inductor. The method further includes forming a second conductive wire defining a second horizontal segment of the inductor within a second dielectric structure along a second surface of the first substrate.

Claims

[1] Integrated circuit (500) comprising: a plurality of conductive routing layers (106, 108) comprising conductive wires (106) and conductive vias (108) disposed within one or more dielectric structures adjacent to the first substrate (102); wherein the plurality of conductive routing layers (106, 108) define an induction coil (110) having one or more turns (112) each comprising a vertically extending segment disposed along a plane intersecting the first substrate (102); and wherein the vertically extending segment comprises a plurality of the conductive wires (106) and the conductive vias (108), wherein the plurality of conductive routing layers (106, 108) comprise a first plurality of conductive interconnect layers (306) disposed within a first ILD structure (304) comprising a plurality of stacked ILD layers, wherein the integrated circuit (500) further comprises: a second substrate (406); and a second ILD structure (408) disposed between the second substrate (406) and the first ILD structure (304) and surrounding a second plurality of conductive interconnect layers (410), wherein the plurality of conductive routing layers (106, 108) further comprise the second plurality of conductive interconnect layers, wherein the vertically extending segment comprises: a first conductive interconnect via (324a) having first sidewalls angled such that a first width of the first conductive interconnect via (324a) increases as its distance from the first substrate (102) increases; and a second conductive interconnect via (324b) having second sidewalls angled such that a second width of the second conductive interconnect via (324b) decreases as its distance from the first substrate (102) increases. [2] The integrated circuit (500) of claim 1, wherein the one or more turns (112) each wind around an axis (113) extending along a line that does not intersect a first surface of the first substrate (102) facing one of the one or more dielectric structures. [3] The integrated circuit (500) of claim 1 or 2, further comprising: a first ILD structure (304) arranged along a first surface of the first substrate; a first plurality of conductive interconnect layers (306) surrounded by the first ILD structure (304); and a plurality of redistribution layers (312) disposed along a second surface of the first substrate (102) and configured to couple the first plurality of conductive interconnect layers (306) to a bond pad (318), the plurality of redistribution layers (312) comprising the plurality of conductive routing layers (106, 108). [4] The integrated circuit (500) of any preceding claim, wherein the vertically extending segment comprises a substrate via (308) extending through the first substrate (102). [5] Integrated circuit (500) according to one of the preceding claims, further comprising: a first ILD structure (304) disposed along a first surface of the first substrate (102), the first ILD structure (304) surrounding a first plurality of conductive interconnect layers (306); Substrate vias (308) extending through the first substrate (102); a dielectric structure disposed along a second surface of the first substrate (102) opposite the first surface, the dielectric structure surrounding a plurality of redistribution layers (312) coupled to the first plurality of conductive interconnect layers (306) through the substrate vias (308); and wherein the vertically extending segment is defined by the first plurality of conductive interconnect layers (306), the substrate vias (308), and the plurality of redistribution layers (312). [6] A semiconductor device (500) comprising: a first substrate (102); a plurality of conductive routing layers (106, 108) within one or more dielectric structures adjacent to the first substrate (102); and wherein the plurality of conductive routing layers (106, 108) define an induction coil (110) having one or more turns (112) winding around an axis (113) extending parallel to a first surface of the first substrate (102) facing one of the one or more dielectric structures, wherein the semiconductor device (500) further comprises: a first plurality of conductive interconnect layers (306) disposed within a first ILD structure (304) comprising a plurality of stacked ILD layers disposed along the first surface of the first substrate (102), wherein the plurality of conductive routing layers (106, 108) comprise the first plurality of conductive interconnect layers (306), and wherein the semiconductor device (500) further comprises: a second substrate (406); a second ILD structure (408) between the second substrate (406) and the first ILD structure (304); and a second plurality of conductive interconnect layers (410) within the second ILD structure (408), wherein the plurality of conductive routing layers (106, 108) further comprise the second plurality of conductive interconnect layers (410), and wherein the semiconductor device (500) further comprises: Substrate vias (308) extending through the first substrate (102); and one or more redistribution layers (312) disposed on a second surface of the first substrate (102) opposite the first surface, wherein the plurality of conductive routing layers (106, 108) comprises the first plurality of conductive interconnect layers (306), the substrate vias (308), and the one or more redistribution layers (312). [7] The semiconductor device (500) of claim 6, wherein the one or more turns (112) comprise: a first turn (112a) including a first pair of vertically extending segments each comprising a first plurality of conductive wires (106) and conductive vias (108); a second turn (112b) including a second pair of vertically extending segments each comprising a second plurality of conductive wires (106) and conductive vias (108); and wherein a segment of the first pair of vertically extending segments is coupled to a segment of the second pair of vertically extending segments by a horizontally extending segment comprising a conductive wire (106). [8] The semiconductor device (500) of claim 7, wherein the first turn (112a) and the second turn (112b) each extend through the first substrate (102).

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