Storage device configured to store and output an address in response to an internal command

Abstract

Storage device including: a first memory bank group (340_1; 440_1); a second memory bank group (340_2; 440_2), wherein each of the first and second memory bank groups (340_1, 340_2; 440_2440_1, 440_2) contains a plurality of memory banks (340_11-3401k, 34_21-340_2k; 440_11, 440_12, 440_22, 440_22); an internal instruction generator (220A; 316; 416) for generating a first internal instruction (INTN_WR1_a) and a second internal instruction (INTN_WR1_b) based on a first instruction (WR1) from a memory controller (100A), wherein the first instruction (WR1) controls a memory operation of a first target memory bank (440_11) in the first memory bank group (340_1; 440_1), wherein the internal instruction generator (220A; 316; 416) outputs the first internal instruction (WR1) and the second internal instruction (WR2) to the first target memory bank (440_11); and an address input / output circuit (I / O circuit) (420; 500) which receives a first address (ADDR1) corresponding to the first instruction (WR1) to select a memory path of the first address (ADDR1) based on whether a bubble interval (B_INTV) is present in a data burst operation interval corresponding to the first instruction (WR1), to control the output of the first address (ADDR1) according to a time at which the first internal instruction (WR1) and the second internal instruction (WR2) are respectively issued, and to store the first address (ADDR1) in the address I / O circuit (320; 420; 500).

Description

BACKGROUND 1. Area

[0001] One or more embodiments described here relate to a storage device for controlling the storage and output of an address in response to an internal command. 2. Description of the state of the art

[0002] Semiconductor memory devices are widely used in high-performance electronic systems. One example is dynamic random-access memory, which is a volatile memory that determines data values ​​based on charges stored in capacitors. Furthermore, a variety of memory systems have been proposed for writing and reading large amounts of data at high speeds. These memory systems can operate based on a reference clock frequency, which differs from a data clock frequency used to transfer data between memory devices and a memory controller. However, the use of reference and data clock frequencies can have drawbacks.

[0003] From US patent 2017 / 0270987A1, a semiconductor storage device is known which comprises: a first bank containing a first memory cell group and writing data to the first memory cell group upon receiving a first instruction; a second bank containing a second memory cell group and writing data to the second memory cell group upon receiving the first instruction; and a delay controller that issues the first instruction for the first bank upon receiving a second instruction and issues the first instruction for the second bank after an interval of at least one first period.

[0004] From US patent 2013 / 0294174A1, a storage device is known in which a burst length "b" is used, which performs "k" core accesses per instruction and receives an instruction, where "b" is an integer of at least 2 and "k" is an integer of at least 2 and at most "b". The storage device includes a memory cell array comprising a plurality of bank groups, a plurality of bank group control units corresponding to each plurality of bank groups, each bank group control unit configured to generate a multiplexer control signal for selecting a portion of the data read from a corresponding bank group, and a multiplexer configured to sequentially output data read from the plurality of bank groups according to the multiplexer control signal output by the plurality of bank group control units.Data elements contained in the multiplexer's output data have the same time range. SUMMARY

[0005] The object of the invention is to overcome disadvantages in the prior art. This object is achieved by a storage device according to the main claim, by a storage device according to dependent claim 16, and by a non-volatile, computer-readable medium according to dependent claim 20. Further developments of the invention are specified in the dependent claims.

[0006] According to one or a plurality of embodiments, a storage device comprises a first memory bank group; a second memory bank group, wherein each of the first and second memory bank groups comprises a plurality of memory banks; an internal instruction generator for generating a first internal instruction and a second internal instruction based on a first instruction from a memory controller, wherein the first instruction controls a memory operation of a first target memory bank in the first memory bank group and the internal instruction generator outputs the first internal instruction and the second internal instruction to the first target memory bank;and an address input / output circuit (I / O circuit) for receiving a first address corresponding to the first instruction, for selecting a memory path for the first address based on whether a bubble interval exists within a data burst operation interval corresponding to the first instruction, for controlling the output of the first address according to a time at which both the first internal instruction and the second internal instruction are respectively issued, and for storing the first address in the address I / O circuit.

[0007] According to one or a plurality of other embodiments, a storage device comprises a first memory bank group; a second memory bank group, each of the first and second memory bank groups comprising a plurality of memory banks; an internal instruction generator for generating a first internal instruction and a second internal instruction based on a first instruction received from a memory controller, wherein the first instruction is intended to control a memory operation of a first target memory bank of the first memory bank group, to generate a third internal instruction based on a second instruction received from the memory controller to control a memory operation of a second target memory bank of the second memory bank group following the first instruction, and to output the first to third internal instructions;and an address input / output circuit (I / O circuit) for receiving the first to third internal instructions, receiving a first address corresponding to the first instruction and a second address corresponding to the second instruction from the memory controller, and storing the first address and the second address, wherein the second address uses a memory path selected based on whether the third internal instruction is received, within a first clock cycle from a time at which the first internal instruction is received.

[0008] According to one or a plurality of other embodiments, a storage device comprises a first memory bank group; a second memory bank group, each of the first and second memory bank groups containing a plurality of memory banks; an internal instruction generator for generating a first internal read instruction and a second internal read instruction based on a first read instruction received from a memory controller, and outputting the first and second internal read instructions to a first destination memory bank of the first memory bank group; and an address input / output (I / O) circuit comprising a first latch and a second latch, wherein the address I / O circuit receives a first address from the memory controller according to the first read instruction and stores the first address in the first latch based on the first internal read instruction.The address I / O circuit is used to select the first latch in which the first address is stored, based on whether a bubble interval is captured in a data burst operation interval according to the first read instruction, and outputs the first address stored in the first latch of the first target memory bank according to a time at which the internal instruction generator issues the second internal read instruction to the first target memory bank.

[0009] According to one or a variety of other embodiments, a non-volatile, computer-readable medium comprises code which, when executed by a processor, causes the processor to: generate, through an internal instruction generator, a first internal instruction and a second internal instruction based on an instruction from a memory controller, the instruction to control a memory operation of a first target memory bank in a first memory bank group; receive, through an address input / output (I / O) circuit, a first address corresponding to the instruction; select a memory path of the first address based on whether a bubble interval exists in a data burst operation interval corresponding to the instruction; and control the output of the first address according to a time at which the first internal instruction and the second internal instruction are issued to the first target memory bank.and storing the first address in the address I / O circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Features become apparent to a person skilled in the art through the detailed description of exemplary embodiments with reference to the accompanying drawings, in which: Fig. 1 illustrates an embodiment of a storage system; Fig. 2 illustrates another embodiment of a storage system; Fig. 3 illustrates an embodiment of a storage device; Fig. 4 illustrates an embodiment that includes first and second memory bank groups; Fig. 5A illustrates an embodiment of signals for controlling a storage device, and Fig. Figure 5B illustrates an embodiment of the storage device which is controlled by the signals from Fig. 5A can be controlled; Fig. 6A illustrates an embodiment of a storage operation of a storage device, and Fig. Figure 6B illustrates an embodiment of a storage device that performs the storage operation of Fig. 6A executes; Fig. Figure 7 illustrates an embodiment of an address input / output circuit (I / O circuit); Fig. Figure 8 illustrates an embodiment of a bubble interval detector; Fig. 9 illustrates an embodiment of a depth address output circuit; Fig. Figure 10A illustrates an embodiment for controlling the storage and output of a first address of a depth-based address output unit when a bubble interval is present in a data burst interval corresponding to a first instruction, and Fig. 10B an embodiment of a timing diagram for operating the depth-based address output unit of the Fig. 10A illustrates; Fig. Figure 11A illustrates an embodiment for controlling the storage and output of a first address of a depth-based address output unit when a bubble interval is not present in a data burst interval corresponding to a first instruction, and Fig. 11B an embodiment of a timing diagram for operating the depth-based address output unit of Fig. 11A illustrates; Fig. 12A and Fig. 12B Illustrate embodiments of timing diagrams for operating a storage device during a read operation; Fig. Figure 13 illustrates an embodiment of an address I / O circuit which operates taking into account a read operation which has no read latency; Fig. 14 illustrates another embodiment of a bubble interval detector; Fig. 15 illustrates an embodiment of a depth-based address output unit; Fig. 16 illustrates another embodiment of a depth-based address output unit; Fig. 17 illustrates another embodiment of a storage system; Fig. 18 illustrates an embodiment of a semiconductor package; and Fig. Figure 19 illustrates another embodiment of a semiconductor package. DETAILED DESCRIPTION

[0011] Fig. Figure 1 illustrates an embodiment of a memory system 10A, which may include a memory controller 100A and a memory device 200A. The memory controller 100A may include a memory interface 110A. The memory controller 100A can provide various signals to the memory device 200A via the memory interface 110A and control memory operations, such as write and read operations. For example, the memory controller 100A can provide commands CMD and addresses ADDR to the memory device 200A and access data DATA in the memory area 210A. The memory device 200A can also transfer data DATA through a DQ contact point or DQ pin between the memory controller 100A and the memory device 200A.

[0012] The 100A storage controller can access the 200A storage device upon request from a host. The 100A storage controller can communicate with the host using various protocols. For example, the 100A storage controller can communicate with the host using an interface protocol such as Peripheral Component Interface Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), or Serial SCSI (SAS). Alternatively, one of several interface standards, such as Universal Serial Bus (USB), Multi-Media Card (MMC), Extended Small Disk Interface (ESDI), or Integrated Device Intelligence (IDE), can be used to establish the interface between the host and the 100A storage controller.

[0013] The memory device 200A can include a memory area 210A, an internal instruction generator 220A, and an address I / O circuit 230A. The memory area 210A can contain a plurality of memory bank groups BG. Each of the memory bank groups BG can contain a plurality of memory banks. In one embodiment, each of the memory banks can contain a memory cell array, a row decoder, a column decoder, and a read amplifier. The memory device 200A can be a dynamic random-access memory (DRAM), such as a synchronous double data rate DRAM (DDR-SDRAM), a low-power, low-data-rate SDRAM (LPDDR), a graphics double data rate (GDDR) SDRAM, and a Rambus DRAM (RDRAM).

[0014] The frequency of a reference clock used as the basis for a memory operation of the 200A storage device can be lower than the frequency of a data clock used as the basis for a data burst operation of the 200A storage device. Specifications of the 10A storage system can, for example, conform to standard protocols established by the Joint Electron Device Engineering Council (JEDEC).

[0015] Due to a frequency difference between the reference clock and the data clock, an interval (e.g., a bubble interval) during which data DATA is not transferred to and from a DQ pad can occur during a memory operation (e.g., a data burst operation corresponding to an instruction) of the memory device 200A. To improve the efficiency of the memory operation and the performance of the memory system 10A, the memory system 10A can perform a memory operation to reduce or minimize a bubble interval. For example, the memory device 20A can perform the memory operation at each of a multitude of memory bank groups BG. The address I / O circuit 230A can store an address ADDR to perform the memory operation at each of the memory bank groups BG and can perform a FIFO (first-in, first-out) control operation to output the stored address ADDR at a suitable time.

[0016] The internal instruction generator 220A can generate internal instructions based on a CMD instruction from the memory controller 100A. In one embodiment, if the burst length of a data burst operation performed by the memory device 200A based on the CMD instruction is a predetermined number of reference bits or more, the internal instruction generator 220A can generate at least two internal instructions. For example, the internal instruction generator 220A can generate a first internal instruction and a second internal instruction if the burst length of the data burst operation corresponding to the CMD instruction is 2n bits (where n is an integer equal to or greater than 2) equal to or greater than the reference bits.

[0017] The burst length of a data burst operation, corresponding to the first and second internal instructions respectively, can be n bits. As described above, by generating the internal instructions using the internal instruction generator 220A, if a data burst operation with a burst length of a predetermined number of reference bits or more is to be performed, the storage device 200A can divide the burst length into bursts with a prescribed number of reference bits or less and execute the data burst operation. Furthermore, the storage device 200A can operate in an on-the-fly (OTF) mode and perform the data burst operation by varying the burst length.

[0018] Assuming that the internal instruction generator 220A receives the CMD instruction and generates the first internal instruction and the second internal instruction, the address ADDR corresponding to the CMD instruction can be output twice to the memory bank group BG, according to a time at which the first internal instruction is output to the memory bank group BG and a time at which the second internal instruction is output to the memory bank group BG.

[0019] To control the output of address ADDR, the address I / O circuit 230A, according to one embodiment, can store address ADDR from memory controller 100A and output address ADDR to memory bank group BG at a time when an internal instruction generated by internal instruction generator 220A is output to memory bank group BG. Address I / O circuit 230A can select a memory path for address ADDR based on whether a data burst interval corresponding to the received CMD instruction contains a data burst operation interval.

[0020] The 230A address I / O circuit can control a circuit that stores an address ADDR when the data burst interval is present according to the received CMD command. This differs from a circuit that stores the address ADDR when the data burst interval is absent. The 230A address I / O circuit can output the stored address ADDR to the memory bank group BG at the same time as the internal command is issued to the memory bank group BG. Due to the operations of the 230A address I / O circuit described above, the data burst interval can be reduced. Consequently, the 200A storage device can perform efficient memory operations.

[0021] Fig. Figure 2 illustrates an embodiment of a memory system 10B, which may include an application processor (AP) 100B and a memory device 200B. A memory control module 110B in which the AP 100B and the memory device 200B can form a memory system. The memory device 200B may also include a memory area 210B, an internal instruction generator 220B, and an address I / O circuit 230B.

[0022] The AP 100B can be used as a host of Fig. 1. The AP 100B can also be implemented by a system-on-a-chip (SoC), which may include a system bus to which predefined standard bus protocols are applied, and various intellectual properties (IPs) connected to the system bus. An Advanced Microcontroller Bus Architecture (AMBA) protocol available from Advanced RISC Machine (ARM) Ltd. can be used as the standard system bus protocol. Examples of bus types to which the AMBA protocol is applied include AHB (Advanced High Performance Bus), APB (Advanced Peripheral Bus), AXI (Advanced eXtensible Interface), AXI4, and AXI Coherency Extensions (ACE). In addition, other protocol types such as uNetwork from SONICs Inc., CoreConnect from IBM, and an OCP-IP Open Core protocol can be applied.

[0023] The memory control module 110B can perform the same function as the memory controller of the previous embodiment. The memory device 200B can also perform a memory operation to reduce or minimize a burst interval that may occur due to a difference between the frequency of a reference clock (used for the memory operation) and the frequency of a data clock (used for a data burst operation). The address I / O circuit 230B can store the address ADDR and output the address ADDR at a suitable time to support the memory operation.

[0024] The Fig. Figure 3 illustrates an embodiment of a storage device 300, which may include a control logic 310, an address I / O circuit 320, a bank control logic 330, a plurality of memory bank groups 340_1 to 340_n, and a data I / O buffer 350. The storage device 300 of Fig. Figure 3 is only one example. In one embodiment, the storage device 300 may further include various types of circuitry for performing write, read and / or other storage operations.

[0025] The control logic 310 can contain an instruction decoder 312, a mode register 314, and an internal instruction generator 316. The control logic 310 can control all operations of the storage device 300. The instruction decoder 312 can decode an externally applied instruction CMD and internally generate a decoded instruction signal. For example, the instruction decoder 312 can decode a chip select signal / CS, a row address pulse signal / RAS, a column address pulse signal / CAS, a write enable signal / WE, and a clock enable signal CKE. Furthermore, the control logic 310 can decode an address ADDR and generate control signals associated with a write or read instruction. The mode register 314 can set an internal register based on a mode register signal to determine an operating mode of the storage device 300 and the address ADDR.

[0026] The internal instruction generator 316 can generate an internal instruction INTN_CMD based on the decoding result of the instruction decoder 312. In one embodiment, the internal instruction generator 316 can generate at least one internal instruction INTN_CMD based on the burst length of a data burst operation based on the CMD instruction. The control logic 310 can output the internal instruction INTN_CMD to the memory bank groups 340_1 to 340_n and the address I / O circuit 320.

[0027] The address I / O circuit 320 can include a bubble interval detector 322 and a depth-based address output unit 324. The bubble interval detector 322 can detect a bubble interval within a data burst operation interval according to the CMD instruction. Within the first clock cycle from the time the storage device 300 receives a CMD instruction to control a memory operation of a target memory bank of any memory bank group (e.g., a first memory bank group 340_1), the bubble interval detector 322 can detect a bubble interval based on whether the storage device 300 receives another instruction to control a memory operation of a target memory bank of a different memory bank group (e.g., a second memory bank group 340_2).

[0028] For example, if the instruction to control the memory operation of the target memory bank of the second memory bank group 340_2 is received within the first clock cycle after the instruction CMD to control the memory operation of the target memory bank of the first memory bank group 340_1 is received, the bubble interval detector 322 can generate a detection signal indicating that the bubble interval is not being detected. If the instruction to control the memory operation of the target memory bank of the second memory bank group 340_2 is received after the first clock cycle, the bubble interval detector 322 can generate a detection signal indicating that the bubble interval is being detected.

[0029] The bubble interval detector 322 can directly receive the CMD command and detect a bubble interval based on a pattern from the CMD command. In another embodiment, the bubble interval detector 322 can receive the internal INTN_CMD command and determine the bubble interval based on a pattern from the internal INTN_CMD command.

[0030] The depth-based address output unit 324 can select and store a memory path for the address ADDR based on the detection signal generated by the bubble interval detector 322. The depth-based address output unit 324 can include multiple depth address output circuits for storing different addresses and sequentially outputting the respective stored addresses. For example, the depth-based address output unit 324 can include first through third depth address output circuits, which can sequentially output their respective stored addresses. The depth-based address output unit 324 can store the first address received in the first depth address output circuit, store the second address received subsequently in the second depth address output circuit, and output the first address before the second address.

[0031] However, since, as described above, the storage device 300 generates at least two internal INTN_CMD instructions based on the CMD instruction, which corresponds to a data burst operation with a burst length of reference bits or more, and performs a memory operation based on these at least two internal INTN_CMD instructions, the address I / O circuit 320 can output address ADDR at least twice and control the output of address ADDR according to the timing of the internal INTN_CMD instructions being issued. Since, as described above, the storage device 300 can perform a memory operation that can reduce or minimize the bubble interval, the depth-based address output unit 324 can control a memory path of address ADDR based on an instruction pattern or an internal instruction pattern to support the memory operation.

[0032] The address I / O circuit 320 can output a row address X_ADDR, a column address Y_ADDR, and a bank address BA_ADDR at a time when the internal instruction INTN_CMD is issued to the memory bank groups 340_1 to 340_n of the control logic 310. In one embodiment, the bank address BA_ADDR can contain addresses of memory bank groups 340_1 to 340_n and addresses of target memory banks of memory bank groups 340_1 to 340_n. The bank control logic 330 can receive the bank address BA_ADDR and generate a bank control signal BA_CS. Memory banks in each of memory bank groups 340_2 to 340_n can receive an internal instruction INTN_CMD, a row address X_ADDR, a column address Y_ADDR, and a bank control signal BA_CS in a similar manner to memory banks 340_11 to 340_1k in the first memory bank group 340_1. A target memory bank in one of memory bank groups 340_1 to 340_n can be activated based on the bank control signal BA_CS.

[0033] A memory operation based on the internal INTN_CMD instruction can be performed on memory cells in a target memory bank that correspond to the row address X_ADDR and the column address Y_ADDR.

[0034] The data I / O buffer 350 can read data DATA from the target memory bank and transfer the data DATA to an external location (e.g., the memory controller 100A in the Fig. 1) provide the storage device 300. In one embodiment, the data I / O buffer 350 can receive data DATA from outside (e.g., from the storage controller 100A in Fig. 1) and provide the DATA data to the target memory bank. The DATA data can be transferred to or from the outside via a DQ pad. The Data I / O Buffer 350 can also perform a data burst operation and transfer the DATA data based on an externally received data clock.

[0035] Fig. Figure 4 illustrates an embodiment of the first memory bank group 340_1 and the second memory bank group 340_2 of Fig. 3. With reference to Fig. 4 The first memory bank group 340_1 can contain the first to kth memory banks 340_11 to 340_1k, and the second memory bank group 340_2 can contain the first to kth memory banks 340_21 to 340_2k. A first memory bank 340_11 of the first memory bank group 340_1 can contain a memory bank array 341 in which a plurality of memory cells are arranged in rows and columns, a row decoder 342, a read amplifier 343, and a column decoder 344.

[0036] Both the row decoder 342 and the column decoder 344 can receive and activate a memory bank control signal BA_CS. The row decoder 342 and the column decoder 344 can receive a row address X_ADDR and a column address Y_ADDR, respectively, and access at least one memory cell selected for a memory operation based on the row address X_ADDR and the column address Y_ADDR. For example, a memory bank from memory banks in one of the memory bank groups 340_1 to 340_k can be selected based on the bank address BA_ADDR of Fig. 3 can be selected, and memory cells of the selected memory bank can be addressed based on the row address X_ADDR and the column address Y_ADDR. The configuration of the first memory bank 340_11 of the Fig. 4 can also be applied to other memory banks 340_12 to 340_2k.

[0037] In at least one embodiment, a storage unit containing at least one memory bank can be considered a memory bank group. A data I / O line can be shared by memory banks of a memory bank group. As in Fig. As shown in Figure 4, an I / O line for inputting and outputting data from multiple memory banks within a memory bank group can be shared. Memory banks 340_11 to 340_1k of the first memory bank group 340_1 can be connected to a first data I / O line DIOL_1, and memory banks 340_21 to 340_2k of the second memory bank group 340_2 can be connected to a second data I / O line DIOL_2. Thus, by connecting another data I / O line to each memory bank group, the memory device 300 can be expanded. Fig. 3. Perform a memory operation on each memory bank group.

[0038] A time interval based on a core cycle for the storage device 300 of Fig. 3. The execution of a memory operation based on an internal instruction can, in at least one embodiment, correspond to a first clock cycle. For example, a first internal instruction and a second internal instruction, generated based on an instruction received to control a memory operation of a target memory bank of the first memory bank group 340_1, can be issued to the target memory bank, taking into account the first clock cycle. Alternatively, a time interval of a bubble interval (or a data burst operation interval corresponding to an internal instruction) can correspond to the second clock cycle. However, the first clock cycle and the second clock cycle can be set to different clock durations, taking into account delays of internal signals of the storage device 300.

[0039] Fig. Figure 5A illustrates an embodiment of a timing diagram for operating a storage device 400, illustrating a bubble interval B_INTV. Fig. 5B is a block diagram of the storage device 400, which represents the operation of an address I / O circuit 420 when a bubble interval is detected.

[0040] According to one embodiment, the frequency of a data clock WCK can be twice the frequency of a reference clock CLK, a first clock cycle can be four clock cycles, and a second clock cycle can be two clock cycles. An output time interval (hereinafter referred to as a time interval INTV_tCCD from time_CAS to CAS delay (tCCD)) between internal instructions generated based on an instruction can be the first clock cycle. In one embodiment, a write latency 'WR latency' can be two clock cycles. The frequencies and / or clock cycles can differ in other embodiments.

[0041] Referring to Fig. 5A and Fig. At time t1, the storage device 400 (5B) can receive a first write instruction WR1 and a first address ADDR1 to control a memory operation of a first destination memory bank 440_11 of a first memory bank group 440_1. The burst length BL_32 of a data burst operation corresponding to the first write instruction WR1 can be 32 bits. The first address ADDR1 can contain a first bank address BA1, corresponding to the first destination memory bank 440_11 of the first memory bank group 440_1, a first row address X1, and a first column address Y1. The internal instruction generator 416 can generate a first internal write instruction INTN_WR1_a and a second internal write instruction INTN_WR1_b based on the first write instruction WR1. A burst length BL_16 of a data burst operation, corresponding to each of the first internal write instruction INTN_WR1_a and the second internal write instruction INTN_WR1_b, can be 16 bits.

[0042] The internal instruction generator 416 can issue the first internal write instruction INTN_WR1_a to the first target memory bank 440_11 at time t3, taking into account the write latency 'WR-Latency', and issue the second internal write instruction INTN_WR1_b to the first target memory bank 440_11 at time t7, which is a tCCD interval INTV_tCCD after time t7. In this case, the address I / O circuit 420 can output the first address ADDR1 to the first target memory bank 440_11 at any time t3 and t7 according to the times at which the internal instruction generator 416 issues the first internal write instruction INTN_WR1_a and the second internal write instruction INTN_WR1_b to the first target memory bank 440_11.

[0043] Storage device 400 can perform a data burst operation BL 16A_1, corresponding to the first internal write instruction INTN_WR1_a, between time t3 and time t5. Subsequently, storage device 400 can perform a data burst operation BL 16A_2, corresponding to the second internal write instruction INTN_WR1_b, between time t7 and time t9. During a time interval between t3 and t9, which is a data burst operation interval corresponding to the first write instruction WR1, the bubble interval B_INTV can occur as a result for a time interval between t5 and t7 and a time interval between t9 and t11, during which no data burst operation is performed.

[0044] In one embodiment, the address I / O circuit 420 can detect the bubble interval B_INTV and store and output the first address ADDR1 based on a detection result. The address I / O circuit 420 can detect the bubble interval B_INTV based on whether another internal write instruction is received within a first clock cycle (or after a second clock cycle) from the time at which the first internal write instruction INTN_WR1_a is received. When the address I / O circuit 420 detects the bubble interval B_INTV, the address I / O circuit 420 can store the first address ADDR1 in a circuit corresponding to a first depth Dep1 in order to output the first address ADDR1 at time t3, which is a write latency 'WR latency' after time t1, and store the first address ADDR1 in a circuit corresponding to a second depth Dep2 in order to output the first address ADDR1 again at time t7.The address I / O circuit 420 can first output the first address ADDR1 via a circuit corresponding to the first depth Dep1 and then output the first address ADDR1 via a circuit corresponding to the second depth Dep2.

[0045] Fig. Figure 6A illustrates an embodiment of a timing diagram for a storage operation of a storage device 400. Fig. Figure 6B illustrates an embodiment of the storage device 400, illustrating an operation of an address I / O circuit 420 when a bubble interval is not detected.

[0046] With reference to Fig. 6A and Fig. 6B The storage device 400 can receive a first write instruction WR1 and a first address ADDR1 to control a memory operation of a first target memory bank 440_11 of a first memory bank group 440_1 at time t1, and a second write instruction WR2 and a second address ADDR2 to control a memory operation of a second target memory bank 440_22 of a second memory bank group 440_2 at time t3. For example, if the storage device 400 can receive the second write instruction WR2 within one clock cycle from the time at which the first write instruction WR1 is received. The first write instruction WR1 and the first address ADDR1 can be used as above with reference to Fig. 5A should be described.

[0047] A burst length BL_32 of a data burst operation corresponding to the second write instruction WR2 can be 32 bits. According to one embodiment, the burst length BL_32 of the data burst operation corresponding to the second write instruction WR2 can be 16 bits or another number of bits.

[0048] The internal instruction generator 416, taking into account a write latency 'WR latency', can issue a third internal write instruction INTN_WR2_a to the second target memory bank 440_22 at time t5 and a fourth internal write instruction INTN_WR2_b to the second target memory bank 440_22 at time t9, which is a tCCD interval INTV_tCCD after time t5. In this case, the address I / O circuit 420 can output the second address ADDR2 to the second target memory bank 440_22 at any time t5 and t9, according to the times at which the internal instruction generator 416 issues the third internal write instruction INTN_WR2_a and the fourth internal write instruction INTN_WR2_b to the second target memory bank 440_22.

[0049] Storage device 400 can execute a data burst operation BL 16B_1, corresponding to the third internal write instruction INTN_WR2_a, between time t5 and time t7. Afterwards, storage device 400 can execute a data burst operation, corresponding to the fourth internal write instruction INTN_WR2_b, between time t9 and time t11. As a result, the data in the Fig. 5A captured bubble interval B_INTV is filled with data burst operations BL 16B_1 and BL 16B_2, which correspond to the third internal write command INTN_WR2_a and the fourth internal write command INTN_WR2_b, respectively.

[0050] In one embodiment, for example, the address I / O circuit 420 receives the third internal write instruction INTN_WR2_a within a first clock cycle from a time at which the address I / O circuit 420 receives the first internal write instruction INTN_WR1_a, in which the bubble interval B_INTN may not be detected. If the bubble interval B_INTV is not detected as described above, the address I / O circuit 420 can store the first address ADDR1 in a circuit corresponding to a first depth Dep1 in order to output the first address ADDR1 at time t3, which is after the write latency 'WR latency' from time t1, and store the second address ADDR2 in a circuit corresponding to a second depth Dep2 in order to output the second address ADDR2 at time t5, which is after the write latency 'WR latency' from time t3.

[0051] The address I / O circuit 420 can also store the first address ADDR1 in a circuit corresponding to a third depth Dep3, in order to output the first address ADDR1 again at time t7, and store the second address ADDR2 in a circuit corresponding to a fourth depth Dep4, in order to output the second address ADDR2 again at time t9. The address I / O circuit 420 can output the first address ADDR1 via the circuit corresponding to the first depth Dep1, the second address ADDR2 via the circuit corresponding to the second depth Dep2, the first address ADDR1 via the circuit corresponding to the third depth Dep3, and the second address ADDR2 via the circuit corresponding to the fourth depth Dep4.

[0052] Fig. Figures 5A to 6B show only the operations of the storage device 400 based on the first and second write commands WR1 and WR2. In one embodiment, the storage device 400 can operate based on a read command.

[0053] Fig. Figure 7 illustrates an embodiment of an address I / O circuit 500, which may include a bubble interval detector 510, a depth-based address output unit 530, and an activation / reset signal generator 550. The bubble interval detector 510 can receive internal commands INTN_CMDs and detect bubble intervals based on patterns in the internal commands INTN_CMDs. The bubble interval detector 510 can generate a detection signal BD_RS based on the detection result of the bubble intervals and provide the detection signal BD_RS to the depth-based address output unit 530.

[0054] The depth-based address output unit 530 can contain first to nth depth address output circuits 530_1 to 530_n. Each of the depth address output circuits 530_1 to 530_n can store one of the addresses ADDRs. The respective depth address output circuits 530_1 to 530_n can also correspond to different depths and output addresses, which are stored sequentially as depth address output signals Dep_ADDR_out based on the depths. For example, the first to nth depth address output circuits 530_1 to 530_n can each correspond to the first to nth depths and thus output sequentially stored addresses.

[0055] The activation / reset signal generator 550 can provide an activation signal ENS to each of the first to nth depth address output circuits 530_1 to 530_n, so that the respective first to nth depth address output circuits 530_1 to 530_n sequentially store and output addresses. In one embodiment, the activation / reset signal generator 550 can generate the activation signal ENS based on the internal INTN_CMDs instructions. Thus, if a storage device is switched off or receives a reset signal from outside, the activation / reset signal generator 550 can provide a reset signal RST to reset an address stored in each of the first to nth depth address output circuits 530_1 to 530_n.

[0056] Fig. Figure 8 illustrates an embodiment of the bubble interval detector 510 from Fig. 7, and Fig. Figure 9 illustrates an embodiment of the depth address output circuit 530_m from Fig. 7. Here, a first internal instruction INTN_CMD1_a and a second internal instruction INTN_CMD2_a can each be a signal generated based on a first instruction to control a memory operation of a target memory bank of a first memory bank group, where a burst length signal BLS is a signal indicating whether the first instruction is an instruction to perform a data burst operation with a burst length of reference bits or more, and a third internal instruction INTN_CMD2_a is a signal generated in response to a second instruction to control a memory operation of a target memory bank of a second memory bank group.

[0057] With reference to Fig. The bubble interval detector 510 can include a bubble interval detection start unit 511, delay units 512a to 512d, a signal detector 513, drivers 514a to 514d, and a latch 515. The drivers 514a to 514d can be circuits configured to enhance the characteristics of the respective signals and align their edges. Each of the delay units 512a to 512d can also delay a signal by up to a second clock cycle (e.g., 2 clock cycles).

[0058] The process of setting a capture signal BD_RS is now described. The bubble interval capture starter unit 511 can receive the first internal instruction INTN_CMD1_a and the burst length signal BLS and begin capturing a bubble interval. For example, if the burst length signal BLS is a high-level signal indicating that the first instruction is to perform a data burst operation with a burst length of reference bits or more, the bubble interval capture starter unit 511 can provide the first internal instruction INTN_CMD1_a to the delay unit 512a. The delay unit 512a can delay the first internal instruction INTN_CMD1_a by up to the second clock cycle and provide the delayed first internal instruction INTN_CMD1_a to the signal detector 513.

[0059] If the bubble interval detection start unit 511 receives the third internal instruction INTN_CMD2_a after the second clock cycle from a time at which the bubble interval detection start unit 511 receives the first internal instruction INTN_CMD1_a, the signal detector 513 can provide the delayed first internal instruction INTN_CMD1_a to the delay unit 512b, and the delay unit 512b can delay the delayed first internal instruction INTN_CMD2_a until the second clock cycle and provide the delayed first internal instruction INTN_CMD2_a to the latch 515.

[0060] In this case, the latch 515 can output a high-level BD_RS detection signal, indicating that no bubble interval is being detected. In another case, if the bubble interval detection start unit 511 does not receive the third internal instruction INTN_CMD2_a after the second clock cycle from the time the first internal instruction INTN_CMD1_a is received, the signal detector 513 cannot provide the delayed first internal instruction INTN_CMD1_a to the delay unit 512b, and the latch 515 can output a low-level BD_RS detection signal, indicating that the bubble interval is being detected.

[0061] The process of resetting the detection signal BD_RS is now described. After an initial clock cycle from the point at which the bubble interval detection start unit 511 receives the first internal command INTN_CMD1_a, the second internal command INTN_CMD1_b, received by the bubble interval detector 510, can be delayed by the delay units 512c and 512d up to the first clock cycle, and the delay unit 512d can provide the delayed second internal command INTN_CMD1_b to the latch 515. In this case, the latch 515 can reset the detection signal BD_RS to an initial level (e.g., a low level). The bubble interval detector 510 can be configured differently in another embodiment.

[0062] In relation to Fig. 9. The depth-based address output unit 530 can contain a plurality of depth address output circuits 530_1 to 530_n. An m-th depth address output circuit 530_m can contain a memory path selector 532_m and an address storage unit 534_m. The m-th memory path selector 532_m can contain first to third selection circuits SC1 to SC3. In one embodiment, the memory path selector 532_m can be activated based on an m-th activation signal ENS [m] and receive a first internal instruction INTN_CMD1_a or a second internal instruction INTN_CMD2_b together with a capture signal BD_RS and an inverted capture signal / BD_RS. The m-th address storage unit 534_m can contain a multiplexer MUX, which includes a plurality of switching elements, for example, switching elements SW1 to SW3, and a latch LAT.The multiplexer MUX can select a memory path based on a selection signal output by the memory path selector 532_m. The latch LAT can store an address via the selected memory path. The latch LAT can then output the stored address to an m-th depth address output signal Dep_ADDR_out [m]. The configuration of the m-th depth address output circuit 530_m can be applied to other depth address output circuits 530_1 through 530_n.

[0063] In one embodiment, when the memory path selector 532_m receives the first internal instruction INTN_CMD1_a, the first selector circuit SC1 can generate a first select signal A at a high level, and the second selector circuit SC2 and the third selector circuit SC3 can each generate a second select signal C at a low level and a third select signal E at a low level, respectively. The address memory unit 534_m can store an externally received address ADDR in the latch LAT based on the first select signal A and output the stored address ADDR as the depth address output signal Dep_ADDR_out [m].

[0064] When the memory path selector 532_m receives the second internal command INTN_CMD1_b and a low-level capture signal BD_RS, the second selector circuit SC2 can generate a high-level second select signal C, and the first selector circuit SC1 and the third selector circuit SC3 can generate a low-level first select signal A and a low-level third select signal E, respectively.

[0065] The address storage unit 534_m can store an m-1-th depth address output signal Dep_ADDR_out [m-1], which is output by an m-1 depth address output circuit 530_m-1, in the latch LAT in response to the second selection signal C and outputs the stored m-1-th depth address output signal Dep_ADDR_out [m-1] as the depth address output signal Dep_ADDR_out [m].

[0066] When the memory path selector 532_m finally receives the second internal instruction INTN_CMD1_b and a high-level capture signal BD_RS, the third selector circuit SC3 can generate a third high-level select signal E, and the first selector circuit SC1 and the second selector circuit SC2 can generate a first low-level select signal A and a second low-level select signal C, respectively. The address memory unit 534_m can store an m-2th depth address output signal Dep_ADDR_out [m-2], output by an m-2th depth address output circuit 530_m-2, in the latch LAT as a response to the third select signal E and output the stored m-2th depth address output signal Dep_ADDR_out [m-2] as a depth address output signal Dep_ADDR_out [m]. Subsequently, the latch LAT can receive an m-th reset signal RST [m] and be reset.The depth-based address output unit 530 may have a different configuration in another embodiment.

[0067] Fig. Figure 10A illustrates an embodiment for controlling the storage and output of a first address ADDR1 of a depth-based address output unit 530 when a bubble interval is in a data burst interval which, according to one embodiment, corresponds to a first instruction WR1. Fig. Figure 10B illustrates an embodiment of a timing diagram for operating the depth-based address output unit 530 of the Fig. 10A.

[0068] With reference to Fig. 10A, the depth-based address output unit 530 can contain a first to fourth depth address output circuit 530_1 to 530_4. The first write instruction WR1, a first address ADDR1, and internal instructions INTN_WR1_a and INTN_WR1_b are detailed above with reference to... Fig. 5A are described with reference to Fig. 10B, Operations of the depth-based address output unit 530 based on activation signals ENS [1] to ENS [4] are described below.

[0069] Back on Fig. 10A and Fig. Referring to 10B, the first depth address output circuit 530_1 can be activated at times t1 to t5 based on a first activation signal ENS [1] and receive a first internal write instruction INTN_WR1_a at time t3. The depth address output circuit 530_1 can receive the first address ADDR1 from outside based on the first internal write instruction INTN_WR1_a and store the first address ADDR1. The first depth address output circuit 530_1 can output the first address ADDR1 as a first depth address output signal Dep_ADDR_out [1] to activate a memory operation in response to the first internal write instruction INTN_WR1_a.

[0070] After time t5, the first depth address output circuit 530_1 can be deactivated. The second depth address output circuit 530_2 can be activated between time t5 and time t9 based on a second activation signal ENS [2]. The second depth address output circuit 530_2 can receive a second internal write command INTN_WR1_b at time t7. The second depth address output circuit 530_2 can store the first address ADDR1 stored in the first depth address output circuit 530_1 based on the second internal write command INTN_WR1_b and a high-level (H) capture signal BD_RS. The second depth address output circuit 530_2 can output the first address ADDR1 to the second depth address output signal Dep_ADDR_out [2] to activate a memory operation in response to the second internal write command INTN_WR1_b.

[0071] After time t9, the second depth address circuit 530_2 can be deactivated. The third depth address output circuit 530_3 can be activated based on the third activation signal ENS [3], receive the next internal command, and in standby mode store and output an address corresponding to the next internal command.

[0072] Fig. Figure 11A illustrates an embodiment for controlling the storage and output of a first address ADDR1 of a depth-based address output unit 530 when a bubble interval is not within a data burst interval which, according to one embodiment, corresponds to a first instruction WR1. Fig. Figure 11B illustrates an embodiment of a timing diagram of an operation of the depth-based address output unit 530 of the Fig. 11A.

[0073] With reference to Fig. 11A can contain the depth-based address output unit 530, including first to fourth depth address output circuits 530_1 to 530_4. With reference to Fig. 10B are, since the first write command WR1, the first address ADDR1 and the internal commands INTN_WR1_a and INTN_WR1_b are described in detail above with reference to Fig. 5A described below, operations of the depth-based address output unit 530 in response to the activation signals ENS [1] to ENS [4].

[0074] Back on Fig. 11A and Fig. Referring to 11B, the first depth address output circuit 530_1 can be activated based on a first activation signal ENS [1] between time t2 and time t4 and receive a first internal write instruction INTN_WR1_a at time t3. The depth address output circuit 530_1 can receive the first address ADDR1 from outside and store the first address ADDR1 based on the first internal write instruction INTN_WR1_a. The first depth address output circuit 530_1 can output the first address ADDR1 as a first depth address output signal Dep_ADDR_out [1] to activate a memory operation based on the first internal write instruction INTN_WR1_a.

[0075] After time t4, the first depth address output circuit 530_1 can be deactivated. The second depth address output circuit 530_2 can be activated between time t4 and time t6 based on a second activation signal ENS [2]. At time t5, the second depth address output circuit 530_2 can receive a third internal write command INTN_WR2_a. The second depth address output circuit 530_2 can receive a second address ADDR2 from an external source and store the second address ADDR2 based on the third internal write command INTN_WR2_a. The second depth address output circuit 530_2 can output the second address ADDR2 as a second depth address output signal Dep_ADDR_out [2] to activate a memory operation based on the third internal write command INTN_WR2_a.

[0076] After time t6, the second depth address output circuit 530_2 can be deactivated. The third depth address output circuit 530_3 can be activated between time t6 and time t8 based on a third activation signal ENS [3]. The third depth address output circuit 530_3 can receive a second internal write command INTN_WR1_b at time t7. The third depth address output circuit 530_3 can store the first address ADDR1, which is stored in the first depth address output circuit 530_1, based on the second internal write command INTN_WR1_b and a low-level (L) capture signal BD_RS. The third depth address output circuit 530_3 can output the first address ADDR1 as the third depth address output signal Dep_ADDR_out [3] to activate a memory operation based on the second internal write command INTN_WR1_b.

[0077] After time t8, the third depth address output circuit 530_3 can be deactivated. The fourth depth address output circuit 530_4 can be activated between time t8 and time t10 based on a fourth activation signal ENS [4]. The fourth depth address output circuit 530_4 can receive a fourth internal write command INTN_WR2_b at time t9. The fourth depth address output circuit 530_4 can store the second address ADDR2, which is stored in the second depth address output circuit 530_2, based on the fourth internal write command INTN_WR2_b and the low-level (L) capture signal BD_RS. The fourth depth address output circuit 530_4 can output the second address ADDR2 as a fourth depth address output signal Dep_ADDR_out [4] to activate a memory operation based on the fourth internal write command INTN_WR2_b.

[0078] Fig. 12A and Fig. Figure 12B shows embodiments of timing diagrams for operating a storage device in / during a read operation. With reference to Fig. 12A A write latency 'WR latency' may exist in a write operation based on a write command, as in Fig. 5A is shown. In a read operation based on a read command, there may be no read latency.

[0079] An internal instruction generator can thus receive a first read instruction RD1, issue a first internal read instruction INTN_RD1_a to a first target memory bank at time t1, and issue a second internal read instruction INTN_RD1_b to a first target memory bank at time t5, which is a tCCD interval INTV_tCCD after time t1. In this case, an address I / O circuit can output a first address ADDR3 at each of time points t1 and t5, corresponding to the times at which the internal instruction generator issues the first internal read instruction INTN_RD1_a and the second internal read instruction INTN_RD1_b to the first target memory bank. In one embodiment, a data clock WCK can be a signal based on a clock received from an external source (e.g., a memory controller).

[0080] Additionally, the internal command generator can be used with reference to Fig. 12B furthermore receives a second read instruction RD2, issues a third internal read instruction INTN_RD2_a to a second target memory bank at time t3, and issues a fourth internal read instruction INTN_RD2_b to the second target memory bank at time t7, which is one tCCD interval INTV_tCCD after time t3. In this case, the address I / O circuit can issue a second address ADDR4 to the second target memory bank at each of time points t3 and t7, according to the times at which the internal instruction generator issues the third internal read instruction INTN_RD2_a and the fourth internal read instruction INTN_RD2_b to the second target memory bank.

[0081] Fig. Figure 13 illustrates an embodiment of an address I / O circuit 700 configured to operate with zero read latency when considering a read operation.

[0082] With reference to Fig. The address I / O circuit 700 can include a bubble interval detector 710, a depth-based address output unit 730, and an activation / reset signal generator 750. The bubble interval detector 710 can receive internal read commands INTN_RDs and detect a bubble interval based on patterns in the internal read commands INTN_RDs. The bubble interval detector 710 can generate a detection signal BD_RS' based on the detection result of the bubble interval and provide the detection signal BD_RS' to the depth-based address output unit 730. The depth-based address output unit 730 can include a read address latch circuit 731 and a depth-read address output circuit 732.

[0083] The 731 read address latch can store address ADDRs received based on internal INTN_CMD commands. Specifically, the 731 read address latch can change the positions where the address ADDRs are stored based on internal INTN_RD read commands. The 732 deep read address output circuit can select an address required for a read operation from the address ADDRs stored in the 731 read address latch, based on the BD_RS' capture signal, and output the selected address as a deep read address output signal, Dep_RD_ADDR_out.

[0084] When the read operation is performed, the activation / reset signal generator 750 can generate an activation signal ENS' to activate the depth-based address output unit 730. In one embodiment, the activation / reset signal generator 750 can generate the activation signals ENS' based on the internal read commands INTN_RDs. If a storage device is powered off or receives a reset signal from outside, the activation / reset signal generator 750 can provide a reset signal RST to the depth-based address output unit 730 and reset the addresses ADDRs stored in the read address latch circuit 731.

[0085] Fig. Figure 14 illustrates an embodiment of the bubble interval detector 710. Fig. 13, and Fig. Figure 15 illustrates an embodiment of the depth-based address output unit 730. Fig. 13.

[0086] With reference to Fig. 14. The bladder interval detector 710 can contain a bladder interval detection start unit 711, delay units 712a to 712c, a signal detector 713, drivers 714a to 714c, and a latch 715. Since the number of delay units 712a to 712c connected to a reset terminal of the latch 715 in the bladder interval detector 710 is one less than in the bladder interval detector 510 of the Fig. 8, the time at which a detection signal BD_RS' of the latch 715 is set can be adjusted to be up to a second clock cycle earlier than the time at which the detection signal BD_RS' of the latch 515 is set. Fig. 8 is reset. For example, the time at which the detection signal BD_RS' of the bladder interval detector 710 is set can be controlled so that it differs from the time at which the detection signal BD_RS of the bladder interval detector 510 is set. Fig. 8 is postponed. Operations of the bladder interval detector 710 can be performed similarly to operations of the bladder interval detector 510. Fig. 8. The configuration of the bubble interval detector 710 may differ in another embodiment.

[0087] With reference to Fig. The depth-based address output unit 730 can contain a read address latch circuit 731 and a depth-read address output circuit 732. The read address latch circuit 731 can contain a variety of switching elements SW1 to SW4 and a variety of latches LAT1 to LAT4. The read address latch circuit 731 can modify a latch in which an address ADDR is stored, based on an internal read instruction INTN_RD_a. The internal read instruction INTN_RD_a can be the first generated or issued internal read instruction among internal read instructions corresponding to a predetermined read instruction.For example, from a first internal read instruction, a second internal read instruction corresponding to a first read instruction, and a third internal read instruction and a fourth internal read instruction corresponding to a second read instruction, the 731 read address latch circuit can change the latch in which the address ADDR is stored, based on the first internal instruction and the third internal instruction.

[0088] The 732 depth-read address output circuit can include a multiplexer (MUX) and a driver (DRV). As above with reference to Fig. As described in section 1, the deep-read address output circuit 732 can output the address ADDR to memory banks. A specific output method of the deep-read address output circuit 732 according to one embodiment is now described.

[0089] The deep-read address output circuit 732 can be connected to the output terminals of a second latch LAT2 and a fourth latch LAT4 of the read address latch circuit 731 and receive an address ADDR_PRE stored in the second latch LAT2 and an address ADDR_LAT stored in the fourth latch LAT4. The deep-read address output circuit 732 can directly output the received address ADDR as the deep-read address output signal Dep_RD_ADDR_out based on an activation signal ENS, or it can select one of the addresses ADDR_PRE stored in the second latch LAT2 and one of the addresses ADDR_LAT stored in the fourth latch LAT4, based on the activation signal ENS and the acquisition signal BD_RS', and output the selected address as the deep-read address output signal Dep_RD_ADDR_out. The configuration of the depth-based address output unit 730 may differ in another embodiment.

[0090] Fig. Figure 16 illustrates an embodiment of an operation of the depth-based address output unit 730, corresponding to the timing diagram of the Fig. 12B corresponds. Referring to Fig. 12B and 13 to 16: Initially, when the read address latch circuit 731 receives a first address ADDR3 and a first internal read command INTN_RD1_a, the read address latch circuit 731 sequentially stores the first address ADDR3 in a first latch LAT1 and a second latch LAT2. Since the bubble interval detector 710 only receives the first internal read command INTN_RD1_a, the bubble interval detector 710 can output an initial level (e.g., low level) detection signal BD_RS'. The deep read address output circuit 732 can directly select the first address ADDR3 and output the first address ADDR3 as a deep read address output signal Dep_RD_ADDR_out.

[0091] When the read address latch circuit 731 receives a second address ADDR4 and a third internal read instruction INTN_RD2_a, it can sequentially store the second address ADDR4 in the first latch LAT1 and the second latch LAT2, and sequentially store the first address ADDR3 in the third latch LAT3 and the fourth latch LAT4. Since the bubble interval detector 710 receives the third internal read instruction INTN_RD2_a after a second clock cycle from the time it receives the first internal read instruction INTN_RD1_a, it can output a high-level detection signal BD_RS'. The deep-read address output circuit 732 can directly select the second address ADDR4 and output it as the deep-read address output signal Dep_RD_ADDR_out.

[0092] When the read address latch circuit 731 receives the second internal read command INTN_RD1_b, it can maintain a memory state from each of the first four latches, LAT1 to LAT4. Although the bubble interval detector 710 receives the second internal read command INTN_RD1_b, it can output a detection signal BD_RS', which is held at a high level, due to a delay unit 712. The deep read address output circuit 732 can select and output the address ADDR_LAT stored in the fourth latch, LAT4, based on the high-level detection signal BD_RS. This means that the 732 deep-read address output circuit can output the first address ADDR3, which is stored in the fourth latch LAT4, as the deep-read address output signal Dep_RD_ADDR_out in order to perform a read operation in response to the second internal read instruction INTN_RD1_b.

[0093] When the read address latch circuit 731 receives the fourth internal read instruction INTN_RD2_b, it can maintain a memory state from each of the first four latches, LAT1 to LAT4. Since the second clock cycle has elapsed after the bubble interval detector 710 received the second internal read instruction INTN_RD1_b, the read address latch circuit 731 can output a capture signal BD_RS', which is reset to a low level. The deep read address output circuit 732 can select and output the address ADDR_PRE, which is stored in the second latch LAT2 based on the low-level capture signal BD_RS'. That is, the deep read address output circuit 732 can output the second address ADDR4 as the deep read address output signal Dep_RD_ADDR_out to enable a read operation based on the fourth internal read instruction INTN_RD2_b.

[0094] Fig. Figure 17 illustrates an embodiment of a memory system 1000, which may include a memory controller 1200 and a memory module 1400. The memory module 1400 may contain at least one memory chip 1800, each of which may contain a memory cell array, and a buffer chip 1600 for transmitting signals between the at least one memory chip 1800 and the memory controller 1200 or for managing a memory operation on the memory chips 1800. The memory chips 1800 of the memory module 1400 may be subdivided into a first rank R1 and a second rank R2. Each of the at least one memory chip 1800 may contain an address I / O circuit to which the reference to Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15 to Fig. The embodiments described in 16 can be used to perform a memory operation.

[0095] Although Fig. While Figure 17 provides an example in which part of the function of the memory controller 1200 is performed in a memory module of the load-reduced dual inline memory module (LRDIMM) type, the inventive concept is not limited thereto. For example, a fully buffered memory module of the DIMM type (FBDIMM) can be applied to the memory module 1400, and an extended memory buffer chip (AMB chip) can be mounted as a buffer chip on the memory module 1400. Additionally, another type of memory module can be applied to the memory module 1400, and at least part of the function of the memory controller 1200 can be performed in the memory module 1400.

[0096] Fig. Figure 18 illustrates an embodiment of a semiconductor package 2000 with a stacked structure comprising a plurality of layers. With reference to Fig. 18 The semiconductor package 2000 can contain a plurality of layers LA1 to LAn. Each of the first to n-1th layers LA1 to LAn can be a memory layer (or memory chip) containing a plurality of memory bank groups 2100.

[0097] Each of the memory bank groups 2100 can contain a plurality of memory banks, each of which can contain a memory cell array configured to store data, a row decoder, a column decoder, and a read amplifier. The nth layer LAn can be a buffer layer. In the semiconductor package 2000, the stacked layers LA1 to LAn can be interconnected by through-silicon vias (TSVs) 2300. The buffer layer LAn can communicate with an external memory controller and the memory layers LA1 to LAn-1, and relay transfer signals between the memory layers LA1 to LAn-1 and the external memory controller. The buffer layer LAn can contain an address I / O circuit 2200. With reference to Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15 to Fig. The embodiments described in 16 can be applied to the address I / O circuit 2200 to perform a memory operation.

[0098] Fig. Figure 19 illustrates an embodiment of a semiconductor package 3000 with a stacked semiconductor chip. With reference to Fig. 19 The semiconductor package 3000 can be a memory module containing at least one stacked semiconductor chip 3300 and one system-on-a-chip (SoC) 3400 mounted on a package substrate 3100 (e.g., a printed circuit board (PCB)). An interposer 3200 can optionally also be provided on the package substrate 3100.

[0099] The stacked semiconductor chip 3300 can be implemented as a chip-on-chip (CoC). The stacked semiconductor chip 3300 can contain at least one memory chip 3320 stacked on a buffer chip 3310 (e.g., a logic chip). The buffer chip 3310 and the at least one memory chip 3320 can be interconnected by through-silicon vias (TSVs). The buffer chip 3320 can contain an address I / O circuit to which the data referenced in the Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15 to Fig. The embodiments described in Section 16 can be used to perform a memory operation. In one example, the 3300 stack semiconductor chip can be a high-bandwidth memory (HBM) with a bandwidth of about 500 GB / s to about 1 TB / s or more.

[0100] The procedures, processes, and / or operations described herein can be performed by code or instructions executed by a computer, processor, controller, or other signal processing device. The computer, processor, controller, or other signal processing device may be the elements described herein or an additional element. Because the algorithms underlying the procedures (or operations of the computer, processor, controller, or other signal processing device) are described in detail, the code or instructions for implementing the operations of the procedure execution forms can transform the computer or processor, controller, or other signal processing device into a specialized processor for performing the procedures described herein.

[0101] The generators, controllers, outputs, interfaces, modules, detectors, decoders, delays and other units, latch and other signal generation, signal provision and signal processing features of the embodiments disclosed herein may be implemented in non-volatile logic which may include hardware, software or both.In the case of at least partial hardware implementation, the generators, controllers, outputs, interfaces, modules, detectors, decoders, delays and other units, latch and other signal generation, signal provision and signal processing features can be, for example, any of a variety of integrated circuits, including an application-specific integrated circuit, a field-programmable gate array, a combination of logic gates, a system-on-a-chip, a microprocessor or any other type of processing or control circuit, but not limited to.

[0102] If the generators, controllers, outputs, interfaces, modules, detectors, decoders, delays and other units, latches and other signal generation, signal provision and signal processing features are at least partially implemented in software, they may include, for example, memory or other storage devices for storing code or instructions to be executed by, for example, a computer, processor, microprocessor, controller or other signal processing device. The computer, processor, microprocessor, controller or other signal processing device may be those described herein or an additional element.Since the algorithms that form the basis of the methods (or operations of the computer, processor, microprocessor, controller or other signal processing device) are described in detail, the code or instructions for implementing the operations of the embodiments of the method can transform the computer, processor, controller or other signal processing device into a special processor for performing the methods described herein.

[0103] The various operations of the procedures described above can be performed by any suitable means capable of carrying out the operations, such as various hardware and / or software components, circuits and / or modules.

[0104] The software may comprise an ordered list of executable instructions for implementing logical functions and may be executed in any 'processor-readable medium' for use by or in conjunction with a system, device, or instruction-executing apparatus, such as a single-core or multi-core processor or processor-containing system.

[0105] The blocks or steps of a method or algorithm and of functions described in connection with the embodiments disclosed herein can be executed directly in hardware, in a software module executed by a processor, or in a combination of both. When implemented in software, the functions can be stored or transferred in one or a multitude of instructions or code on a tangible, non-volatile, computer-readable medium. A software module can be located in working memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, a hard disk, a removable storage medium, a CD-ROM, or any other form of storage medium known in the prior art.

[0106] According to one or more of the aforementioned embodiments, a frequency difference between the reference clock and the data clock can cause an interval (e.g., a bubble interval) during which data is not transferred to and from a pad during a memory operation (e.g., a data burst operation corresponding to an instruction) of the storage device. To improve the efficiency of the memory operation and the performance of the memory system, the memory system can perform a memory operation to reduce or minimize a bubble interval. For example, an address I / O circuit can control a circuit (which stores an address when a bubble interval is present in the data burst operation interval corresponding to a received instruction) in such a way as to differ from a circuit that stores the address when no bubble interval is present.The address I / O circuit can output the stored address to the memory bank group BG at a time equal to when the internal command to the memory bank group BG is issued. Due to the operations of the address I / O circuit described above, the bubble interval can be reduced. As a result, the storage device can perform efficient memory operations.

Claims

Storage device comprising: a first memory bank group (340_1; 440_1); a second memory bank group (340_2; 440_2), each of the first and second memory bank groups (340_1, 340_2; 440_2) containing a plurality of memory banks (340_11-340_1k, 34_21-340_2k; 440_11, 440_12, 440_22, 440_22); an internal instruction generator (220A; 316; 416) for generating a first internal instruction (INTN_WR1_a) and a second internal instruction (INTN_WR1_b) based on a first instruction (WR1) from a memory controller (100A), the first instruction (WR1) being a memory operation of a first target memory bank (440_11) in the first memory bank group (340_1; 440_1), wherein the internal instruction generator (220A; 316; 416) outputs the first internal instruction (WR1) and the second internal instruction (WR2) to the first destination memory bank (440_11); and an address input / output circuit (I / O circuit) (420;500), which receives a first address (ADDR1) corresponding to the first instruction (WR1) to select a memory path of the first address (ADDR1) based on whether a bubble interval (B_INTV) is present in a data burst operation interval corresponding to the first instruction (WR1), to control the output of the first address (ADDR1) according to a time at which the first internal instruction (WR1) and the second internal instruction (WR2) are respectively issued, and to store the first address (ADDR1) in the address I / O circuit (320; 420; 500).; Storage device according to claim 1, wherein a frequency of data clocks synchronized in a data burst operation is greater than a frequency of reference clocks synchronized in the storage operation. Storage device according to claim 1 or 2, wherein: if a burst length (BL_16) of a data burst operation corresponding to the first instruction (WR1) is 2n bits, where 2n is equal to or greater than a predetermined number of reference bits, each burst length of a data burst operation according to the first internal instruction (INTN_WR1_a) and a burst length of a data burst operation corresponding to the second internal instruction (INTN_WR1_b) is n bits, where n is an integer equal to or greater than 2. Storage device according to one of claims 1 to 3, wherein a burst length of a data burst operation (BL_16) corresponding to the first instruction (WR1) is equal to or different from a burst length (BL_32) of a data burst operation corresponding to a second instruction (WR2) received by the storage device after the storage device receives the first instruction (WR1). Storage device according to one of claims 1 to 4, wherein: the data burst operation interval corresponding to the first instruction (WR1), a first data burst operation interval corresponding to the first internal instruction (INTN_WR1_a) and a second data burst operation interval corresponding to the second internal instruction (INTN_WR1_b), the bubble interval (B_INTV) is an interval for which no data burst operation is performed between the first data burst operation interval and the second data burst operation interval. Storage device according to any one of claims 1 to 5, wherein the address I / O circuit (320; 420; 500) comprises: a bubble interval detector (510; 610; 710) for detecting the bubble interval (B_INTV) based on whether a second instruction (WR2) to control a storage operation of a second target memory bank (440_22) in the second memory bank group (340_2; 440_2) is received within a first clock cycle, from a time at which the storage device receives the first instruction (WR1), wherein the bubble interval detector (510; 610; 710) generates a detection signal (BD_RS). Storage device according to claim 6, wherein: the first clock cycle includes a time interval based on a core cycle for performing a memory operation based on the first internal instruction (INTN_WR1_a), and the internal instruction generator (220A; 316; 416) issues the second internal instruction (INTN_WR1_b) to the first target memory bank (440_11) after the first clock cycle from a time at which the internal instruction generator (220A; 316; 416) issues the first internal instruction (INTN_WR1_a) to the first target memory bank (440_11). Storage device according to claim 6 or 7, wherein: the internal instruction generator (220A; 316; 416) generates a third internal instruction (INTN_WR2_a) based on the second instruction (WR2) at a time when the second instruction (WR2) is received, and when the third internal instruction is received after a second clock cycle from a time when the first internal instruction (INTN_WR1_a) is received, the bubble interval detector (416) sets the detection signal (BD_RS) to a first level indicating that the bubble interval (B_INTV) is detected after the second clock cycle from a time when the third internal instruction (INTN_WR2_a) is received. Storage device according to claim 8, wherein the second clock cycle is a time interval of the bubble interval (B_INTV). Storage device according to claim 9, wherein: when the second internal instruction (INTN_WR1_b) is received, the bubble interval detector (416) resets the detection signal (BD_RS) to a second level, after the first clock cycle from the time at which the second internal instruction (INTN_WR1_b) is received. Storage device according to one of claims 6 to 10, wherein: the address I / O circuit (320; 420; 500) includes a depth-based address output unit (530) which includes the first to third depth address output circuits (530_1-530_3) to store respective addresses therein, and the first to third depth address output circuit (530_1-530_3) outputs the respective addresses stored therein sequentially to one of the memory banks. Storage device according to claim 11, wherein, when the first internal command is received, the depth-based address output unit (530) stores the first address (ADDR1) received from the memory controller (100A) in the first depth address output circuit (530_1), and stores the first address (ADDR1) stored in the first depth address output circuit (530_1) in one of the second depth address output circuits (530_2) and the third depth address output circuit (530_3) based on the acquisition signal (BD_RS). Storage device according to claim 12, wherein when the detection signal (BD_RS) is at a first level indicating that the bubble interval (B_INTV) is being detected, the depth-based address output unit (530) stores the first address (ADDR1) stored in the first depth address output circuit (530_1) in the third depth address output circuit (530_3), and stores a second address (ADDR2) corresponding to the second instruction (WR2) in the second depth address output circuit (530_2). Storage device according to claim 12 or 13, wherein: when the detection signal (BD_RS) is at a second level indicating that the bubble interval (B_INTV) is not detected, the depth-based address output unit (530) stores the first address (ADDR1) stored in the first depth address output circuit (530_1) in the second depth address output circuit (530_2). Storage device according to any one of claims 1 to 14, wherein the storage device operates in an on-the-fly mode to perform a data burst operation with a variable burst length. Storage device comprising: a first memory bank group (340_1; 440_1); a second memory bank group (340_2; 440_2), each of the first and second memory bank groups (340_1, 340_2, 440_1, 440_2) containing a plurality of memory banks (440_11, 440_12, 440_21, 440_22); an internal instruction generator (220A; 316; 416) for generating a first internal instruction (INTN_WR1_a) and a second internal instruction (INTN_WR1_b) based on a first instruction (WR1) received from a memory controller (100A), the first instruction (WR1) being intended to control a memory operation of a first target memory bank (440_11) of the first memory bank group (340_1; 440_1), to generate a third internal instruction (INTN_WR2_a) based on a second instruction (WR2) received from the memory controller (100A) to perform a memory operation of a second target memory bank (440_22) of the second memory bank group (340_2;440_2) to control after the first instruction (WR1), and to output the first to third internal instructions (INTN_WR1_a, INTN_WR1_b, INTN_WR2_a); and an address input / output circuit (I / O circuit) (420; 500) to receive the first to third internal instructions (INTN_WR1_a, INTN_WR1_b, INTN_WR2_a), to obtain a first address (ADDR1) from the memory controller (100A) corresponding to the first instruction (WR1) and a second address (ADDR2) corresponding to the second instruction (WR2), and to store the first address (ADDR1) and the second address (ADDR2) using a memory path selected based on whether the third internal instruction (INTN_WR2_a) is received within the first clock cycle from the time the first internal instruction (INTN_WR1_a) is received.; Storage device according to claim 16, wherein: the address I / O circuit (320; 420; 500) contains first to third depth address output circuits (530_1, -530_3) which store respective addresses (ADDR1-ADDR3) therein, and the first to third depth address output circuits (530_1, -530_3) sequentially output the respective addresses (ADDR1-ADDR3) stored therein to one of the memory banks (440_11, 440_12, 440_21, 440_22). Storage device according to claim 17, wherein: when the third internal instruction (INTN_WR2_a) is received within the first clock cycle from the time at which the first internal instruction (INTN_WR1_a) is received, the address I / O circuit (320; 420; 500) stores the first address (ADDR1) received from the memory controller (100A) in the first depth address output circuit (530_1) and outputs the first address (ADDR1) to the first destination memory bank (440_11) via the first depth address output circuit (530_1), according to a time at which the internal instruction generator (220A; 316; 416) outputs the first internal instruction (INTN_WR1_a) to the first destination memory bank (440_11), the address I / O circuit (320; 420;500) in the second depth address output circuit (530_2) stores the second address (ADDR2) received from the memory controller (100A), and outputs the second address (ADDR2) to the second destination memory bank (440_22) through the second depth address output circuit (530_2), according to a time at which the internal instruction generator (220A; 316; 416) outputs the third internal instruction (INTN_WR2_a) to the second destination memory bank (440_22), and the address I / O circuit (320; 420; 500) stores the first address (ADDR2) stored in the first depth address output circuit (530_2) in the third depth address output circuit (530_3), and outputs the first address to the first destination memory bank (440_11) through the third depth address output circuit. (530_1) outputs according to a time at which the internal instruction generator (220A; 316; 416) sends the second internal instruction (INTN_WR1_b) to the first target memory bank (440_11) of the first memory bank group (340_1;outputs 440_1).; Storage device according to claim 17 or 18, wherein: if the third internal instruction (INTN_WR2_a) is not received within the first clock cycle from the time at which the first internal instruction (INTN_WR1_a) is received, the address I / O circuit (320; 420; 500) stores the first address (ADDR1) received from the memory controller (100A) in the first depth address output circuit (530_1), and outputs the first address (ADDR1) to the first destination memory bank (440_11) via the first depth address output circuit (530_1) according to a time at which the internal instruction generator (220A; 316; 416) outputs the first internal instruction (INTN_WR1_a) to the first destination memory bank (440_11), the address I / O circuit (320; 420;500) stores the first address (ADDR1) stored in the first depth address output circuit (530_1) in the second depth address output circuit (530_2), and outputs the first address (ADDR1) to the first destination memory bank (440_11) through the second depth address output circuit (530_2), according to a time at which the internal instruction generator (220A; 316; 416) outputs the second internal instruction (INTN_WR1_b) to the first destination memory bank (440_1), and the address I / O circuit (320; 420; 500) stores the second address (ADDR2) received from the memory controller (100A) in the third depth address output circuit (530_3) and outputs the second address (ADDR2) to the second destination memory bank (440_22) through the third depth address output circuit. (530_2) outputs at a time when the internal instruction generator (220A; 316; 416) outputs the third internal instruction (INTN_WR2_a) to the second destination memory bank (530_2).; Non-volatile, computer-readable medium comprising code which, when executed by a processor, causes the processor to: generate a first internal instruction (INTN_WR1_a) and a second internal instruction (INTN_WR1_b) by an internal instruction generator (220A; 316; 416), based on an instruction (WR1) from a memory controller (100A), the instruction (100A) to control a memory operation of a first target memory bank (440_11) in a first memory bank group (340_1; 440_1); receive a first address (ADDR1) corresponding to the instruction (WR1) by an address input / output (I / O) circuit (420; 500); select a memory path of the first address (ADDR1) based on whether there is a bubble interval (B_INTV) in a data burst operation interval corresponding to the instruction (WR1);Controlling the output of the first address (ADDR1) according to the time at which the first internal instruction (INTN_WR1_a) and the second internal instruction (INTN_WR1_b) are each issued to the first destination memory bank (440_11); and storing the first address (ADDR1) in the address I / O circuit (320; 420; 500).

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