SEMICONDUCTOR DEVICE

Abstract

Semiconductor device comprising: a - -epitaxial layer (200) formed on a first surface of a substrate (100); a p-region (300) which is on the n - -epitaxial layer (200) is formed; a n + -region (400) formed on the p-region (300); a gate (600) that is on the n - -epitaxial layer (200) is formed, wherein the gate (600) has a pn junction (J); an oxide film (800) formed on the gate (600); a source electrode (900) formed on the oxide film (800) and the n + -area (400); and a drain electrode (950) formed on a second surface of the substrate (100), where: the gate (600) has a first gate (610) and a second gate (620) formed on the first gate (610); the first gate (610) comprises n-polycrystalline silicon; and the second gate (620) comprises p-polycrystalline silicon, wherein the first gate (610) is in contact with the second gate (620), wherein the pn junction (J) is formed at a contact surface between the first gate (610) and the second gate (620), and wherein the second gate (620) covers a side surface of the first gate (610).

Description

TECHNICAL FIELD

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same. BACKGROUND

[0002] In particular, a power semiconductor device requires a low on-resistance or low saturation voltage to allow a very large current to flow and thus reduce energy loss in an electrically conductive state. Furthermore, a high breakdown voltage is required as an essential property of the power semiconductor device, which makes the power semiconductor device resistant to a high reverse voltage of a pn junction applied to both ends of the power semiconductor device in an off-state or at the moment a switch is turned off.

[0003] Among power semiconductor devices, a metal-oxide-semiconductor field-effect transistor (MOSFET) is generally a most commonly used transistor in digital circuits and analog circuits.

[0004] At the same time, in order to reduce the on-resistance and increase a current density, a trench gate MOSFET in which a JFET region of a flat gate MOSFET is removed is developed.

[0005] In the case of a trench-gate MOSFET, after a trench is formed, a gate insulation layer is formed on a bottom surface and a side surface of the trench. In this case, an electric field is concentrated at the gate insulation layer formed at a corner of the trench, which is why the gate insulation layer may break during operation of a semiconductor device.

[0006] The document US 6 566 708 B1 discloses trench-gate field-effect transistors with low gate-drain capacitance and their manufacture.

[0007] The document US 2014 / 0 159 147 A1 discloses a semiconductor device.

[0008] The document US 2016 / 0 064 537 A1 discloses an insulated gate bipolar transistor using a trench gate electrode.

[0009] The document CN 1 06 449 744 A discloses a trench-gate bipolar transistor with an insulated gate electrode, which is provided with a diode embedded in the gate.

[0010] The document US 2008 / 0 061 364 A1 discloses a trench-type MOS transistor. SHORT DESCRIPTION

[0011] The present invention is based on the object of attenuating an electric field concentrated at a gate insulation layer in a trench-gate metal-oxide-semiconductor field-effect transistor (MOSFET). To achieve this object, the present invention provides a semiconductor device according to claim 1. Further embodiments are described in the dependent claims.

[0012] Accordingly, a breakdown voltage of the semiconductor device can be improved.

[0013] Furthermore, durability of the gate insulation layer can be improved due to the attenuation of the electric field concentrated at the gate insulation layer. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a diagram schematically illustrating an example of a cross section of a semiconductor device according to an exemplary embodiment of the present invention. Fig.2 is a diagram schematically showing an off state of the semiconductor device according to Fig. 1 illustrates. Fig. 3 is a diagram schematically showing an on-state of the semiconductor device according to Fig. 1 illustrates. Fig. 4 to 8 are diagrams schematically showing an example of a method for manufacturing the semiconductor device according to Fig. 1 illustrate. Fig. 9 is a diagram schematically illustrating an example of a cross section of a semiconductor device according to another exemplary embodiment of the present invention. Fig. 10 is a diagram schematically showing an example of a method for manufacturing the semiconductor device according to Fig. 9 illustrates. Fig.11 is a diagram schematically illustrating an example of a cross section of a semiconductor device according to another exemplary embodiment of the present invention. Fig. 12 is a diagram schematically illustrating an example of a cross section of a semiconductor device according to another exemplary embodiment of the present invention. DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0014] The drawings should be considered as illustrative and not restrictive, and like reference characters indicate like elements throughout the description.

[0015] Additionally, the sizes and thicknesses of the configurations shown in the drawings are shown arbitrarily for clarity and ease of description, but the present invention is not limited thereto. In the drawings, the thicknesses of layers, films, panels, regions, etc. are exaggerated for clarity. In the drawings, the thicknesses of some layers and regions are exaggerated for clarity and ease of description.

[0016] Further, it should be understood that when an element, such as a layer, film, region, or substrate, is referred to as being "on top of" another element, it may be directly on top of the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly on top of" another element, there are no intervening elements. Further, the word "on top of" or "over" a reference portion means that it is located on top of or below the reference portion, but does not necessarily mean that it is "on top of" or "over" based on a direction opposite the direction of gravity.

[0017] In addition, unless expressly stated otherwise, the words “comprise” and variations thereof, such as “comprises” or “having,” are intended to imply the inclusion of the stated element, but not the exclusion of any other elements.

[0018] Furthermore, throughout the description, "on the plane" means the case where a subject portion is viewed from above, and "cross-sectional view" means the case where a cross-section of a subject portion obtained by vertically cutting the subject portion is viewed from the side.

[0019] Fig. 1 is a diagram schematically illustrating an example of a cross section of a semiconductor device according to an exemplary embodiment of the present invention.

[0020] Referring to Fig.1, a semiconductor device according to an exemplary embodiment of the present invention comprises: a substrate 100, an n - -layer 200, a p-region 300, a trench 350, an n + -area 400, a gate 600, a p + -region 700, a source electrode 900 and a drain electrode 950.

[0021] The substrate 100 may be a n + -silicon carbide substrate.

[0022] The n - -layer 200 is formed on a first surface of the substrate 100 and the p - -Area 300 is on the n - -Layer 200 is formed. The n + -range 400 and the p + -region 700 are formed on the p-region 300. In this case, a thickness of the p + -area 700 greater than a thickness of the n + -range 400.

[0023] The trench 350 penetrates the p-region 300 and the n + -area and is on the n --layer 200. Accordingly, the p-region 300 and the n + -area formed on a side surface of the trench 350. The p + -Area 700 is spaced from the side surface of the trench 350 and the n + -range is between the p + -area 700 and the side surface of the trench 350.

[0024] A gate insulation layer 500 is formed in the trench 350. The gate insulation layer 500 may comprise silicon dioxide (SiO2).

[0025] The gate 600 is formed on the gate insulation layer 500. The trench 350 may be filled with the gate 600, and a portion of the gate 600 may protrude outward from the trench 350.

[0026] The gate 600 includes a first gate 610 and a second gate 620. The first gate 610 is in contact with the gate insulation layer 500 formed on a bottom surface of the trench 350, and the second gate 620 is formed on the first gate 610 and is in contact with the first gate 610. A portion of the second gate 620 may protrude outward from the trench 350. In this case, an extension of an upper surface of the first gate 610 may extend below a lower surface of the p-type region 300 so as not to affect a threshold voltage determined by the p-type region 300, the gate insulation layer 500, and the second gate 620.

[0027] The first gate 610 comprises n-type polycrystalline silicon, and the second gate 620 comprises p-type polycrystalline silicon. Accordingly, the gate 600 includes a pn junction J. The pn junction J is formed in the trench 350 and is formed on a surface where the first gate 610 contacts the second gate 620.

[0028] An oxide film 800 is formed on the gate 600. The oxide film 800 covers a side surface of the protruding gate 600. That is, the oxide film 800 is formed on the second gate 620 and covers a side surface of the second gate 620. The oxide film 800 may comprise silicon dioxide (SiO2).

[0029] A source electrode 900 is on the n + -Area 400, the p +A source electrode 900 and a drain electrode 950 are formed on a second surface of the substrate 100. Here, the second surface of the substrate 100 denotes a surface facing away from the first surface of the substrate 100. The source electrode 900 and the drain electrode 950 may comprise ohmic metal.

[0030] As described above, the gate 600 in the trench 350 includes the pn junction J, so that an electric field is distributed between the gate insulating layer 500 and the pn junction J of the gate 600 in an off-state of the semiconductor device. Accordingly, the electric field at the gate insulating layer 500 is attenuated, so that a breakdown voltage of the semiconductor device can be improved. Furthermore, in accordance with the attenuation of the electric field at the gate insulating layer 500, a durability of the gate insulating layer 500 can be improved.

[0031] Now, a function of the semiconductor device according to Fig. 1 with reference to the Fig. 2 and Fig. 3 described.

[0032] The Fig. 2 and Fig. 3 are diagrams schematically showing a function of the semiconductor device according to Fig. 1 illustrate.

[0033] Fig.2 is a diagram schematically showing an off state of the semiconductor device according to Fig. 1 illustrates. Fig. 3 is a diagram schematically showing an on-state of the semiconductor device according to Fig. 1 illustrates.

[0034] The off state of the semiconductor device exists under a condition described below. VGS <VTH, VDS≥oV

[0035] The on-state of the semiconductor device exists under a condition described below. VGS≥VTH, VDS>oV

[0036] Here V TH a threshold voltage of the MOSFET, and V GS is V G - V S , and V DS is V D - V S . V G is a voltage applied to a gate, V D is a voltage applied to a drain electrode, and V Sis a voltage applied to a source electrode.

[0037] Referring to Fig. 2, in the off state of the semiconductor device, a depleted layer 50 is formed to form the n - Layer 200 is almost completely covered, so that a current path is blocked. The depleted layer 50 surrounds the bottom surface and the corner of the trench 350. In the off-state of the semiconductor device, an electric field is generated in the gate 600 and the p-type region 300 by a voltage applied to the drain electrode 950, and the pn junction J located in the gate 600 disperses the electric field so that a small electric field is applied to the gate insulation layer 500.

[0038] As described above, the electric field applied to the gate insulating layer 500 (e.g., located at the gate insulating layer 500) is weakened, so that a breakdown voltage of the semiconductor device can be improved. Furthermore, according to the weakening of the electric field applied to the gate insulating layer 500 at a voltage lower than the breakdown voltage, the durability of the gate insulating layer 500 can be improved.

[0039] Referring to Fig. 3, in the on-state of the semiconductor device, the depleted layer 50 is in the n - -layer 200 formed under the p-region 300. The depleted layer 50 is not in the n --layer 200 is formed adjacent to the side surface of the trench 350, and a channel is formed in the p-region 300 adjacent to the side surface of the trench 350, so that a current path is formed. That is, in the on-state of the semiconductor device, electrons (e-) emitted from the source electrode 900 move to the drain electrode 950 through the n + -range 400, the p-range 300 and the n - -Shift 200.

[0040] Now, a comparison between the characteristics of the semiconductor device according to the present exemplary embodiment and the characteristics of a conventional semiconductor device will be described with reference to Table 1.

[0041] Table 1 presents simulation results of the semiconductor device according to the present exemplary embodiment and a conventional semiconductor device.

[0042] Comparative Example 1 is a conventional trench gate MOSFET device in which a gate does not have a pn junction. Example 1 is the semiconductor device according to Fig. 1.

[0043] In Table 1, breakdown voltages of the semiconductor device according to Example 1 and the semiconductor device according to Comparative Example 1 at almost the same current density are compared. (Table 1) Breakdown voltage (V) Current density (A / cm 2 ) Comparison example 1 858 875 Example 1 1230 871

[0044] Referring to Table 1, the breakdown voltage of the semiconductor device according to Comparative Example 1 is 858 V and the breakdown voltage of the semiconductor device according to Example 1 is 1230 VDh, it can be seen that the breakdown voltage of the semiconductor device according to Example 1 increased by 43.4% compared to the breakdown voltage of the semiconductor device according to Comparative Example 1.

[0045] Now, a method for manufacturing the semiconductor device according to Fig. 1 with reference to the Fig. 4 and Fig. 8, and Fig. 1 described.

[0046] The Fig. 4 to 8 are diagrams showing an example of a method for manufacturing the semiconductor device according to Fig. 1 illustrate schematically.

[0047] Referring to Fig. 4, the substrate 100 is prepared and the n - -Layer 200 is formed on the first surface of the substrate 100. The n - -Layer 200 is formed on the first surface of the substrate 100 by means of epitaxial growth. Here, the substrate 100 can be an n + -silicon carbide substrate.

[0048] Referring to Fig. 5, the p-region 300 is formed on the n-layer 200 and the n +-region 400 is formed on the p-region 300. The p-region 300 can be formed by injecting p-ions, such as Bohr (B), aluminum (Al), gallium (Ga) and / or indium (In), into the n - -Layer 200 and the n + -Region 400 can be formed by injecting n-ions, such as nitrogen (N), phosphorus (P), arsenic (As) and / or antimony (Sb), into the p-region 300.

[0049] However, the present invention is not limited thereto and the p-region 300 is on the n - -layer 200 is formed by epitaxial growth and the n + -region 400 can also be formed on the p-region 300 by epitaxial growth.

[0050] Referring to Fig. 6, the trench 350 is formed by etching the n + -range 400, the p-range 300 and the n - -layer 200 is formed. The trench 350 penetrates the p-region 300 and the n+ -area and is in the n - -Layer 200 formed.

[0051] Next, the gate insulation layer 500 is formed in the trench 350, and a first gate material layer 610a is formed on the gate insulation layer 500. The trench 350 is filled with the first gate material layer 610a, and the first gate material layer 610a may comprise n-type polycrystalline silicon.

[0052] Referring to Fig. 7, the first gate 610 is formed by etching a portion of the first gate material layer 610a. The first gate 610 is formed on the gate insulation layer 500 formed on the bottom surface of the trench 350. In this case, an extension of the upper surface of the first gate electrode 610 may be below the lower surface of the p-type region 300.

[0053] Referring to Fig.8, the gate 600 is formed by forming the second gate 620 on the first gate 610. The second gate 620 is in contact with the first gate 610 and comprises p-type polycrystalline silicon. Accordingly, the gate 600 includes the pn junction J. The pn junction J is formed in the trench 350 and is formed at a surface where the first gate 610 is in contact with the second gate 620.

[0054] The trench 350 may be filled with the gate 600 and a portion of the gate 600 may protrude outwardly from the trench 350.

[0055] Next, p-ions such as Bohr (B), aluminum (AL), gallium (Ga) and indium (In) are introduced into the n + -area 400 and the p-area 300, so that the p + -area 700 is formed. The p + -region 700 is spaced from the side surface of the trench 300. A concentration of the p-ions present in the p +-region 700 is greater than a concentration of the p-ions contained in the p-region 300.

[0056] Next, an oxide film is formed on the gate 600. The oxide film 800 may cover a side surface of the protruding gate 600.

[0057] Referring to Fig. 1, the source electrode 900 is placed on the n + -Area 400, the p + region 700 and the oxide film 800, and the drain electrode 950 is formed on the second surface of the substrate 100.

[0058] Now, a semiconductor device according to another exemplary embodiment of the present invention will be described with reference to the Fig. 9 to 11 described.

[0059] Fig. 9 is a diagram schematically illustrating an example of a cross section of a semiconductor device according to another exemplary embodiment of the present invention.

[0060] Referring to Fig. 9, the semiconductor device differs from the semiconductor device according to Fig. 1 only in a structure of a gate 600, but the other structures are the same as those in the semiconductor device according to Fig. 1. Accordingly, the description of the same structures is omitted.

[0061] A gate insulating layer 500 is formed in a trench 350, and a gate 600 is formed on the gate insulating layer 500. The trench 350 may be filled with the gate 600, and a portion of the gate 600 may protrude outward from the trench 350.

[0062] The gate 600 includes a first gate 610 and a second gate 620. The first gate 610 is formed to extend from a side surface to a bottom surface of the trench 350, and the second gate 620 is formed on the first gate 610 and is in contact with the first gate 610. A part of the second gate 620 may protrude outward from the trench 350. In this case, the first gate 610 is in contact with the gate insulation layer 500 formed on the bottom surface and the side surface of the trench 350. Furthermore, a part of the first gate 610 may protrude outward from the trench 350 together with the second gate 620.

[0063] The first gate 610 comprises n-type polycrystalline silicon, and the second gate 620 comprises p-type polycrystalline silicon. Accordingly, the gate 600 includes a pn junction J. The pn junction J is formed in the trench 350 and is formed at a surface where the first gate 610 contacts the second gate 620.

[0064] Now, a comparison of the characteristics of the semiconductor device according to the present exemplary embodiment with the characteristics of a conventional semiconductor device will be described with reference to Table 2.

[0065] Table 2 presents simulation results of the semiconductor device according to the present exemplary embodiment and a conventional semiconductor device.

[0066] Comparative Example 1 is a conventional trench-gate MOSFET device in which a gate does not have a pn junction J. Example 2 is the semiconductor device according to Fig. 9.

[0067] In Table 2, breakdown voltages of the semiconductor device according to Example 2 and the semiconductor device according to Comparative Example 1 are compared at almost the same current density. (Table 2) Breakdown voltage (V) Current density (A / cm 2 ) Comparison example 1 858 875 Example 2 1098 871

[0068] Referring to Table 2, the breakdown voltage of the semiconductor device according to Comparative Example 1 is 858 V and the breakdown voltage of the semiconductor device according to Example 2 is 1098 V. That is, it can be seen that the breakdown voltage of the semiconductor device according to Example 2 increases by 28.0% compared to the breakdown voltage of the semiconductor device according to Comparative Example 1.

[0069] Now, with reference to the Fig. 10, Fig. 9 and Fig. 6 a method for manufacturing the semiconductor device according to Fig. 9 described.

[0070] Fig.10 is a diagram showing an example of a method for manufacturing the semiconductor device according to Fig. 9 is illustrated schematically.

[0071] The method for manufacturing the semiconductor device according to Fig. 9 differs from the method of manufacturing the semiconductor device according to Fig. 1 only with respect to the step of forming the gate 600, but the remaining steps are the same as in the method of manufacturing the semiconductor device according to Fig. 1. Accordingly, the description of the same steps is omitted.

[0072] As in Fig. 6 illustrates the trench 350 by etching the n + -range 400, the p-range 300 and the n -Layer 200 is formed, gate insulation layer 500 is formed in trench 350, and then first gate material layer 610a is formed on gate insulation layer 500. Trench 350 is filled with first gate material 610a, and first gate material layer 610a may comprise n-type polycrystalline silicon.

[0073] Referring to Fig. 10, the first gate 610 is formed by etching a portion of the first gate material layer 610a. The first gate 610 is formed to extend from the side surface to the bottom surface of the trench 350. In this case, the first gate is in contact with the gate insulation layer 500 formed on the bottom surface and the side surface of the trench 350.

[0074] Then, as in Fig.9 illustrates the second gate 620 formed on the first gate 610 and the steps for manufacturing the remaining elements are the same as in the method for manufacturing the semiconductor device according to Fig. 1.

[0075] Fig. 11 is a diagram schematically illustrating an example of a cross section of a semiconductor device according to another exemplary embodiment of the present invention.

[0076] The semiconductor device according to the present exemplary embodiment includes a substrate 100, a - -layer 200, a p-region 300, an n + -area 400, a gate 600, a p + -region 700, a source electrode 900 and a drain electrode 950. The substrate 100 may be an n + -silicon carbide substrate.

[0077] Then, the n-layer 200 is formed on a first surface of the substrate 100 and the p-region 300 is formed on the n - -Layer 200 is formed. The n + -range 400 and the p + -area 700 are formed on the p-area 300. Here, the p + -area 700 greater than a thickness of the n + -range 400.

[0078] A gate insulation layer 500 is formed on the n - -layer 200, the p-region 300 and the n + -region 400 is formed and a gate 600 is formed on the gate insulation layer 500.

[0079] The gate 600 includes a first gate 610 and a second gate 620. A bottom surface of the first gate 610 is in contact with the gate insulation layer 500, and the second gate 620 is formed on the first gate 610 and is in contact with the first gate 610. A boundary of a side surface of the first gate 610 may be the same as a boundary of a side surface of the second gate 620.

[0080] The first gate 610 comprises n-type polycrystalline silicon, and the second gate 620 comprises p-type polycrystalline silicon. Accordingly, the gate 600 has a pn junction J. The pn junction J is formed at a surface where the first gate 610 contacts the second gate 620.

[0081] An oxide film 800 is formed on the gate 600. The oxide film 800 covers a side surface of the gate 600. That is, the oxide film 800 is formed on the second gate 620 and covers side surfaces of the first gate 610 and the second gate 620. The oxide film 800 may comprise silicon oxide (SiO2).

[0082] A source electrode 900 is placed on the n + -Area 400, the p + region 700 and the oxide film 800, and a drain electrode 950 is formed on a second surface of the substrate 100. Here, the second surface of the substrate 100 denotes a surface facing away from the first surface of the substrate 100. The source electrode 900 and the drain electrode 950 may comprise ohmic metal.

[0083] As described above, the gate 600 includes the pn junction J, so that in an off-state of the semiconductor device, an electric field is distributed across the gate insulating layer 500 and the pn junction J of the gate 600. Accordingly, the electric field at the gate insulating layer 500 is attenuated, so that a breakdown voltage of the semiconductor device can be improved. Furthermore, in accordance with the attenuation of the electric field at the gate insulating layer 500, a durability of the gate insulating layer 500 is improved.

[0084] Fig. 12 is a diagram illustrating an example of a cross section of a semiconductor device according to another exemplary embodiment of the present invention.

[0085] Referring to Fig. 12, the semiconductor device differs from the semiconductor device according to Fig.11 only with respect to a structure of a gate 600, but the other structures are the same as those of the semiconductor device according to Fig. 11. Accordingly, the description of the same structures is omitted.

[0086] A gate insulation layer 500 is formed on an n - -layer 200, a p-region 300 and an n + -region 400 and a gate 600 is formed on the gate insulation layer 500.

[0087] The gate 600 includes a first gate 610 and a second gate 620. A bottom surface of the first gate 610 is in contact with the gate insulation layer 500, and the second gate 620 is formed on the first gate 610 and is in contact with the first gate 610. Furthermore, the second gate 620 covers a side surface of the first gate 610 and is in contact with the gate insulation layer 500.

[0088] An oxide film 800 is formed on the gate 600. The oxide film 800 covers a side surface of the gate 600. That is, the oxide film 800 is formed on the second gate 620 and covers a side surface of the second gate 620. The oxide film 800 may comprise silicon oxide (SiO2).

Claims

[1] A semiconductor device comprising: a - -epitaxial layer (200) formed on a first surface of a substrate (100); a p-region (300) which is on the n - -epitaxial layer (200) is formed; a n + -region (400) formed on the p-region (300); a gate (600) that is on the n - -epitaxial layer (200) is formed, wherein the gate (600) has a pn junction (J); an oxide film (800) formed on the gate (600); a source electrode (900) formed on the oxide film (800) and the n + -area (400); and a drain electrode (950) formed on a second surface of the substrate (100), where: the gate (600) has a first gate (610) and a second gate (620) formed on the first gate (610); the first gate (610) comprises n-polycrystalline silicon; and the second gate (620) comprises p-polycrystalline silicon, wherein the first gate (610) is in contact with the second gate (620), wherein the pn junction (J) is formed at a contact surface between the first gate (610) and the second gate (620), and wherein the second gate (620) covers a side surface of the first gate (610). [2] A semiconductor device according to claim 1, wherein a gate insulation layer (500) is formed on the n - -epitaxy layer (200), the p-region (300) and the n + -region (400) and the first gate (610) is in contact with the gate insulation layer (500). [3] A semiconductor device according to any one of the preceding claims, further comprising: a p + -region (700) formed on the p-region (300). [4] A semiconductor device according to claim 3, wherein a thickness of the p+ -area (700) is greater than a thickness of the n + -range (400). [5] A semiconductor device according to any preceding claim, wherein the oxide film (800) covers a side surface of the gate (600). [6] The semiconductor device according to claim 5, wherein the oxide film (800) is formed on the second gate (620) and covers a side surface of the second gate (620). [7] A semiconductor device according to any one of the preceding claims, wherein the substrate (100) comprises an n + -silicon carbide substrate.

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