METHOD FOR FORMING AN INTEGRATED CIRCUIT STRUCTURE

Abstract

Method for forming an integrated circuit structure, wherein the method comprises the following: Forming (202) an etch stop layer (32) over a conductive feature (28); Forming (204) a dielectric layer (34) over the etch stop layer (32); Forming (206) an opening (42) in the dielectric layer (34) to expose the etch stop layer (32); Etching (208) of the etch stop layer (32) through the opening (42) using an etchant comprising an inhibitor, wherein an inhibitor film (48) comprising the inhibitor is formed on the conductive feature (28); Deposition (20) of a conductive barrier layer (50) extending into the opening (42); after deposition of the conductive barrier layer (50), performing (212) a treatment to remove the inhibitor film (48); and Deposition (214) of a conductive material (56) to fill a remaining section of the opening (42).

Description

GENERAL STATE OF THE ART

[0001] Integrated circuits feature interconnection structures that include metal traces and vias to serve as three-dimensional wiring structures. The function of these interconnection structures is to properly connect densely packed components.

[0002] Metal traces and vias are formed within the interconnect structure. These are typically created through damascene processes, in which trenches and via openings are formed in dielectric layers. A barrier layer is then deposited, followed by filling the trenches and via openings with copper. After a chemical-mechanical polishing (CMP) process, the top surfaces of the metal traces are smoothed, leaving the metal traces and vias intact.

[0003] Prior art relating to the subject matter of the invention can be found, for example, in US 2017 / 0092580A1, US 6541374B2 and US 6482733B2. The invention is defined by the main claim and the dependent claim. Further embodiments of the invention are described by the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of this disclosure are best understood through the following detailed description, with reference to the accompanying figures. It is emphasized that, in accordance with standard industry practice, various elements may not be drawn to scale. The dimensions of the various features may be arbitrarily enlarged or reduced for the clarity of the discussion. The Fig. Figures 1 to 9 illustrate cross-sectional views of intermediate stages in the formation of a metal conductor and a via in accordance with some embodiments. Fig. Figure 10 illustrates a chemical structure of benzotriazole (BTA) in accordance with some embodiments. Fig. Figure 11 illustrates a chemical structure of bis-triazolyl-indoleamine in accordance with some embodiments. Fig. Figure 12 illustrates a schematic top view of discrete sections of a conductive barrier layer at the base of a via hole in accordance with some embodiments. Fig. Figure 13 illustrates a contact angle of water with a BTA surface in accordance with some embodiments. Fig. Figure 14 illustrates a contact angle of water with a bare copper surface in accordance with some embodiments. Fig. Figure 15 illustrates experimental results showing resistance values ​​of vias formed by a plurality of formation processes in accordance with some embodiments. Fig. Figure 16 illustrates the growth retardation of barrier layers formed in a plurality of formation processes, in accordance with some embodiments. Fig. Figure 17 illustrates the comparison of thicknesses of conductive barrier layers on different surfaces (and formed by different processes) in accordance with some embodiments. Fig. Figure 18 illustrates a process flow for forming a metal conductor and a via in accordance with some embodiments. DETAILED DESCRIPTION

[0005] A method for selectively forming a conductive barrier layer for a conductive feature is provided in accordance with various embodiments. The intermediate steps in forming the conductive feature are illustrated in accordance with some embodiments. Some variations of certain embodiments are discussed. In the various views and illustrative embodiments, the same reference numerals are used throughout to denote the same elements. In accordance with some embodiments of the present disclosure, the formation of the conductive feature includes the selective formation of a conductive barrier layer in an opening, the injection of a metallic material, and the execution of planarization.Selective formation of the conductive barrier layer is achieved by forming an inhibitor film on an underlying metal feature. The conductive barrier layer is then deposited with delayed growth on the inhibitor film, resulting in selective growth of the conductive barrier layer on the sidewalls of the via orifice with very little (if any) conductive barrier layer forming on the inhibitor film. After the conductive barrier layer has formed, a treatment is performed to remove the inhibitor film. The remaining orifice is then filled with a metallic component, such as copper.

[0006] The Fig. Figures 1 to 9 illustrate cross-sectional views of intermediate stages in the formation of a through-hole connection in accordance with some embodiments of the present disclosure. The corresponding processes are also shown schematically in process flow 200, as in Fig. 18 shown, reproduced.

[0007] Fig. Figure 1 illustrates a cross-sectional view of a package component 100. According to some embodiments of the present disclosure, the package component 100 is a component wafer (such as a logic component wafer) comprising active components such as transistors and / or diodes, and possibly passive components such as capacitors, inductors, resistors, or the like. According to alternative embodiments of the present disclosure, the package component 100 is an interposer wafer that may or may not comprise active components and / or passive components. According to still alternative embodiments of the present disclosure, the package component 100 is a package substrate tape that may comprise package substrates with cores or coreless package substrates. In the following discussion, a component wafer is used as an example of the package component 100.The teaching of the present revelation can also be applied to interposer wafers, package substrates, packages, etc.

[0008] In accordance with some embodiments of the present disclosure, the package component 100 comprises semiconductor substrate 20 and features formed on an upper surface of the semiconductor substrate 20. The semiconductor substrate 20 may comprise crystalline silicon, crystalline germanium, silicon-germanium, a III-V compound semiconductor such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or the like. The semiconductor substrate 20 may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. Shallow trench isolation (STI) regions (not shown) may be formed in the semiconductor substrate 20 to isolate the active regions within the semiconductor substrate 20.Although not shown, vias can be formed to extend into the semiconductor substrate 20, with the vias being used to interconnect the features on opposite sides of the package component 100.

[0009] In accordance with some embodiments of the present disclosure, the package component 100 is used to form a device die. In these embodiments, integrated circuit devices 22 are formed on the upper surface of the semiconductor substrate 20. Examples of integrated circuit devices 22 include complementary metal-oxide-semiconductor (CMOS) transistors, resistors, capacitors, diodes, or the like. The details of the integrated circuit devices 22 are not illustrated herein. In accordance with alternative embodiments, the package component 100 is used to form interposers. In accordance with these embodiments, the substrate 20 may also be a dielectric substrate.

[0010] Furthermore, in Fig. Figure 1 illustrates a dielectric layer 24. The dielectric layer 24 can be an interlayer dielectric (ILD) layer or an intermetal dielectric (IMD) layer. In accordance with some embodiments of the present disclosure, the dielectric layer 24 is an ILD in which contact plugs are formed. The corresponding dielectric layer 24 can be formed from phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), a silicon oxide layer (formed using tetraethyl orthosilicate – THEOS), or the like.The dielectric layer 24 can be formed using spin-on coating, atomic layer deposition (ALD), flowable chemical vapor deposition (FCVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), or the like.

[0011] In accordance with some embodiments of the present disclosure, the dielectric layer 24 is an IMD in which metal conductors and / or vias are formed. The corresponding dielectric layer 24 can be formed from a low-θ dielectric carbon-containing material, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), or the like. In accordance with some embodiments of the present disclosure, the formation of the dielectric layer 24 involves the deposition of a pore-forming dielectric material and then performing a curing process to expel the pore-forming agent, such that the remaining dielectric layer 24 is porous.

[0012] A conductive feature 30 is formed in the dielectric layer 24. The conductive feature 30 can be a metal conductor, a conductive via, a contact plug, or the like. In some embodiments, the conductive feature 30 has a diffusion barrier layer 26 and conductive filler material 28 above the diffusion barrier layer 26. The diffusion barrier layer 26 can be formed from a conductive material such as titanium, titanium nitride, tantalum, tantalum nitride, or the like. A conductive area 28 can be formed from copper, a copper alloy, aluminum, or the like. The diffusion barrier layer 26 serves to prevent the diffusion of the material (such as copper) in the conductive area 28 into the dielectric layer 24.In accordance with some embodiments of the present disclosure, the formation of the leading feature 30 can also adopt the methods discussed below, such that the basic section of the diffusion barrier layer is either not formed or is formed discontinuously and having isolated islands.

[0013] As in Fig. As shown in Figure 1, an etch stop layer 32 is formed over the dielectric layer 24 and the conductive feature. The respective process is designated as process 202 in the process sequence as shown in Figure 1. Fig. Figure 18 illustrates this. The etch stop layer 32 is formed from a dielectric material which, without limitation, may be aluminum oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, or the like. The etch stop layer 32 is formed from a material that exhibits high etch selectivity with respect to the overlying dielectric layer 34, and the etch stop layer 32 can therefore be used to stop the etching of the dielectric layer 34.

[0014] The dielectric layer 34 is formed above the etch stop layer 32. The respective process is designated as process 204 in the process sequence, as shown in Fig. Figure 18 illustrates this. In accordance with some embodiments, the dielectric layer 34 is an IMD or an ILD. The dielectric layer 34 may comprise a dielectric material such as an oxide, a nitride, a carbon-containing dielectric material, or the like. The dielectric layer may, for example, be formed from PSG, BSG, BPSG, FSG, TEOS oxide, HSQ, MSQ, or the like. The dielectric layer 34 may also be a low-θ dielectric layer, having a low dielectric constant value, which is lower than about 3.5 or lower than about 3.0.

[0015] The Fig. Figures 2 to 8 illustrate the process for forming a metal conductor and a via in accordance with some embodiments. It is understood that the examples shown in the Fig. Figures 2 to 8 illustrate a dual-damascene process. In accordance with alternative embodiments, a single-damascene process, in which a metal conductor, a via, a contact plug, or the like is formed, is also considered.

[0016] As in the Fig. 2 and Fig. As shown in Figure 3, a through-hole 42 and a trench 44 are formed by etching. The respective process is designated as process 206 in the process flow, as shown in Figure 3. Fig. Figure 18 illustrates this. The via opening 42 and the trench 44 can be formed, for example, using photolithography techniques. In one example of the formation process for the via opening 42 and the trench 44, a metal hard mask 37 is first formed and structured, as shown in Fig. Figure 2 shows that the metal hard mask 37 can be formed from titanium nitride, boron nitride, or the like. The metal hard mask 37 is structured to form an opening 38 therein, the opening 38 defining the structure of the trench to be filled to form a metal conduit. Subsequently, photoresist 40 is formed on the metal hard mask 37 and then structured to form an opening through which the dielectric layer 34 is formed. The dielectric layer 34 is then etched to form an opening 42. In accordance with some embodiments of the present disclosure, the etching of the dielectric layer is carried out using a process gas comprising fluorine and carbon, the fluorine being used for etching, the carbon having the effect of protecting the sidewalls of the resulting opening. With a suitable fluorine-to-carbon ratio, the opening 42 can have a desirable profile.The process gases for etching include, for example, fluorine- and carbon-containing gas(es) such as C4F8, CH2F2, and / or CF4, and a carrier gas such as N2. In one example of the etching process, the flow rate of C4F8 is in the range of approximately 0 sccm to approximately 50 sccm, the flow rate of CF4 is in the range of approximately 0 sccm to approximately 300 sccm (where at least one of C4F8 has a non-zero flow rate), and the flow rate of N2 is in the range of approximately 0 sccm to approximately 200 sccm. In accordance with alternative embodiments, the process gases for etching include CH2F2 and a carrier gas such as N2. In an example of the etching process, the flow rate of CH2F2 is in the range between about 10 sccm and about 200 sccm, and the flow rate of N2 is in the range between about 50 sccm and about 100 sccm.

[0017] During the etching process, the package component can be maintained at a temperature between approximately 30 °C and 60 °C. Plasma can be generated from the etching gases during the etching process. The radio frequency (RF) power of the etching power source can be less than approximately 700 watts, and the pressure of the process gases is in the range of approximately 15 mTorr to approximately 30 mTorr.

[0018] The etching process for forming the opening 42 can be performed using a timed mode. As a result of the etching, the opening 42 is formed to extend to an intermediate level between the upper surface and the bottom surface of the dielectric layer 34. Next, the photoresist 40 is removed, followed by further etching of the dielectric layer 34 using the metal hard mask 37 as an etching mask. In the etching process, which is an anisotropic etching process, the opening 42 extends downwards until the etch stop layer 32 is exposed. Simultaneously, the opening 42 widens downwards, the trench 44 is formed to extend into the dielectric layer 34, and the resulting structure is in Fig. Figure 3 illustrates this. In the resulting structure, the final opening 42 is called a through-hole 42, which lies below and is connected to the trench 44.

[0019] In accordance with alternative embodiments, the via opening 42 and the trench 44 are formed in separate photolithography processes. In a first photolithography process, for example, the via opening 42 is formed, extending down to the etch stop layer 32. In a second lithography process, the trench 44 is formed. The order for forming the via opening 42 and the trench 44 can also be reversed.

[0020] Following, with reference to Fig. 4, the etch stop layer 32 is etched through. The respective process is designated as process 208 in the process flow, as shown in Fig. Figure 18 illustrates this process. The respective process can also be called a wet cleaning process if the etching of the etch-stop layer 32 involves wet etching. In accordance with some embodiments of the present disclosure, the etching solution comprises glycol, dimethyl sulfide, amine, H₂O₂, and the like. Glycol can be used as a surfactant, dimethyl sulfide can be used as a solvent, amine can be used to remove unwanted organic matter from the surface of the package component 100, and H₂O₂ and amine can be used to etch the etch-stop layer 32.

[0021] In addition to the chemicals mentioned above, the etching solution may also contain an inhibitor used to protect the exposed section of conductive filler material 28 (such as copper) from being unintentionally etched once the etch-stop layer 32 has been etched through. In accordance with some embodiments, the inhibitor comprises benzotriazole (BTA). An example of a chemical structure of BTA is shown in Fig. Figure 10 illustrates a benzoic ring with three hydrogen atoms attached to it. The chemical formula of BTA is C6H5N3.

[0022] In accordance with other embodiments, the inhibitor is selected from other chemicals. These candidate inhibitor materials are hydrophobic and preferably possess nonpolar groups. The hydrophobic property and the nonpolar groups desirablely make the candidate inhibitor materials difficult for precursor gas adsorption during subsequent deposition processes. The candidate inhibitor materials also exhibit good chelation stability during and after etching of the etch-stop layer 32 and during the subsequent deposition of the conductive barrier layer. The candidate inhibitor materials can also be removed during the subsequent post-deposition treatment, as discussed. For example, bis-triazolyl-indoleamine can also be used as an inhibitor. An example of the chemical structure of bis-triazolyl-indoleamine is shown in Fig. 11 illustrates. Fig. In section 11, the symbol “R” represents a phenol group. The benzo rings in bis-triazolyl-indoleamine also result in hydrophobic and steric hindrance properties, which are desirable.

[0023] As a result of adding the inhibitor to the etching solution, the inhibitor residue is deposited on the exposed surface of the conductive region 28 (such as copper), resulting in the formation of the inhibitor film 48. The inhibitor film 48 is thin and can have a thickness T1 in the range of approximately 1 nm to approximately 2 nm, although the thickness T1 can be greater or lesser. The thickness T1 depends on the type of inhibitor. The inhibitor film 48 can be a monolayer of the inhibitor, such as a monolayer of BTA. Fig. Figure 5 schematically illustrates a section of the inhibitor film 48 and the underlying conductive region 28. If the conductive region 28 comprises, for example, copper, copper atoms 29 on the surface of the conductive region 28 bond with the nitrogen atoms in the BTA. The benzo rings of the BTA are oriented outwards. Since the benzo rings are unable to bond the other atoms (such as Ta atoms and nitrogen atoms in the subsequently formed conductive barrier layer), steric hindrance results.

[0024] It is desirable that the inhibitor film 48 provides good coverage, for example, 100 percent or at least 90 percent or greater, of the exposed portion of the conductive region 28, so that little (or no) surface area of ​​the conductive region 28 remains exposed after the formation of the inhibitor film 48. Increasing the coverage can be achieved by extending the etching time of the etch stop layer and / or by increasing the concentration of the inhibitor in the etching solution. However, it is found that extending the etching time and increasing the concentration are limited by other factors. For example, excessively extending the etching time can cause underetching in the etch stop layer 32, and excessively increasing the inhibitor concentration can make etching the etch stop layer 32 difficult due to the formation of the inhibitor film on the etch stop layer 32.In accordance with some embodiments of the present disclosure, the etching time is in the range of about 50 seconds to about 100 seconds. The concentration of the inhibitor in the etching solution can be in the range of about 0.5 wt% to about 1.0 wt%.

[0025] In accordance with some embodiments of the present disclosure, additional processes are carried out to increase the coverage of the inhibitor film 48 without causing the problems mentioned above. In one example of the processes, the etch stop layer 32 is first etched. The etching solution may consist of what is discussed in the preceding paragraph, including the inhibitor and other chemicals. The etching time and the concentration of the inhibitor are not excessive. As a result, the coverage of the inhibitor film is less than 100 percent of the exposed surface of the conductive area 28. The coverage may, for example, be less than about 50 percent. Next, the package component 10 is removed from the etching solution, followed by a cleaning process, for example using demineralized water, so that the residual etching solution is removed while the inhibitor film 48 remains.Next, an inhibitor film formation process is carried out using an inhibitor-forming solution. Since this process is used to further grow the inhibitor film 48, but not to etch the etch stop layer 32, the chemicals used to etch the etch stop layer 32 are not included in the inhibitor-forming solution. For example, amines and H₂O₂ cannot be included. However, some chemicals, such as glycol, dimethyl sulfide, etc., may be added to the inhibitor-forming solution. An inhibitor (such as BTA), which may be the same as or different from the inhibitor used in the etching chemical of the etch stop layer 32, is added to the inhibitor-forming solution. The package component 100 is then immersed in the inhibitor-forming solution to continue growing and increase the coverage of the inhibitor film 48.In accordance with some embodiments of the present disclosure, the soaking time is in the range of about 30 seconds to about 60 seconds. The concentration of the inhibitor in the inhibitor-forming solution can be in the range of about 0.5 wt% to about 2.0 wt%. After wetting, the inhibitor film can achieve 100 percent coverage or substantially 100 percent (for example, more than 95 percent or more than 99 percent coverage).

[0026] With further reference to Fig. 2. Simultaneously with the formation of the inhibitor film 48 on the surface of the conductive region 28, the inhibitor film 48 can also be formed on the (sidewall) surface of the etch stop layer 32, the corresponding section of the inhibitor film 48 having a thickness T2 smaller than the thickness T1. The coverage of the corresponding section of the inhibitor film 48 on the sidewalls of the etch stop layer 32 can be less than 100 percent, for example, less than about 50 percent, and is also smaller than the coverage on the conductive region 28. No inhibitor film 48 is grown on the exposed surface of the dielectric layer 34. Inhibitor film 48 may or may not be grown on the metal hard mask 37.When the inhibitor film 48 is grown on the metal hard mask 37, its thickness is also smaller than the thickness T1, and / or the coverage of the sections of the inhibitor film 48 on the metal hard mask 37 is less than 100 percent, for example by about 50 percent.

[0027] With reference to Fig. 6. Subsequently, the conductive barrier layer 50 is deposited over the opening 42 and the trench 44, for example, using atomic layer deposition (ALD). The respective process is designated as process 210 in the process sequence, as shown in Fig. Figure 18 illustrates the conductive barrier layer 50, which can comprise titanium, titanium nitride, tantalum, tantalum nitride, or the like, and serves to prevent copper from leaching into the subsequently deposited copper-containing material 56 ( Fig. 9) diffuses into the dielectric layer 34. In accordance with some embodiments of the present disclosure, the conductive barrier layer 50 comprises TaN formed using ALD. The corresponding ALD cycle involves the introduction of a Ta-containing process gas, such as pentakis dimethylaminotantal (C 10 H 30 The process involves introducing N5Ta into the respective ALD chamber, emptying the Ta-containing process gas, introducing a nitrogen-containing process gas, such as ammonia, into the process chamber, and emptying the nitrogen-containing process gas. There are multiple ALD cycles. After the formation of the conductive barrier layer 50, the thickness T4 of the section of the conductive barrier layer 50 on the side walls of the dielectric layer 34 is large enough to act as a diffusion barrier. The thickness T4 can be, for example, greater than approximately 1.5 nm.

[0028] An example of the reaction equations for the formation of TaN is: Ta(NMe2)5+NH3→Ta(NH2)5+Me2NH xTa(NH2)5→−[Ta−N(H)−Ta]y−+z NH3 outgassing (heating) where “Me” represents methyl groups (CH3). In accordance with other embodiments, the conductive barrier layer 50 can comprise other materials, such as TiN. The corresponding process gases can, for example, contain tetrakis dimethylamidotitanium and ammonia, which can be used in ALD cycles to form TiN.

[0029] The inhibitor film 48 delays the growth of the conductive barrier layer 50. This is due to the steric hindrance of the inhibitor film 48, which is at least partially attributable to its heterocyclic structure. For example, there is a very low probability that a TaN molecule (assuming the conductive barrier layer 50 comprises TaN) grown on it during an ALD cycle will be present on the inhibitor film 48, whereas a complete layer of TaN grows on the dielectric layer 34 during each ALD cycle. Consequently, after an ALD cycle, a very small percentage of the exposed surface of the inhibitor film 48 has grown TaN on it, acting as the seed for subsequent growth. Once the TaN is grown, it grows at the same rate as on the dielectric layer 34.After each cycle, a very small additional area of ​​the inhibitor film 48 is covered with the newly grown TaN. Consequently, a large percentage of the inhibitor film 48 has no TaN grown on it until after several ALD cycles. This effect is called growth retardation (or incubation time retardation) on the inhibitor film 48, while there is no growth retardation on the dielectric layer 34, since no inhibitor film 48 forms on the dielectric layer 34. There is a growth retardation on the conductive barrier layer 50 on the exposed surfaces of the etch stop layer 32 and metal hard mask 37, and this growth retardation is less significant than the growth retardation directly above the conductive area 28.

[0030] Due to the growth retardation and random germination of the conductive barrier layer 50 on the inhibitor film 48, after the formation of the conductive barrier layer is complete, essentially no conductive barrier layer 50 may have grown on the inhibitor film 48. In other words, the conductive barrier layer 50 may not extend to the conductive region 28. It is possible that a small amount of the conductive barrier layer 50 grows on the inhibitor film 48, with a coverage of less than 100 percent and greater than 0 percent. In accordance with some embodiments, the coverage is in the range between about 20 percent and about 80 percent, or in the range between about 40 percent and about 60 percent. The conductive barrier layer 50 also forms discrete islands 50' on the surface of the conductive region 28, which exhibit random and irregular structures. Fig. Figure 12, for example, schematically illustrates a top view of the randomly formed islands 50' of the conductive barrier layer 50, viewed through the via opening 42.

[0031] A post-deposition treatment 52 is performed to remove the inhibitor film 48. This process is designated as process 212 in the process flow, as shown in Fig. Figure 18 illustrates the resulting structure. Fig. Figure 7 illustrates this. The treatment 52 after deposition can be carried out by plasma treatment and / or heat treatment. The process gases can include hydrogen (H2) and a carrier gas, such as argon. In accordance with some embodiments of the present disclosure, plasma treatment is carried out. During the plasma treatment, the temperature of the package component 100 can be greater than about 200 °C, for example, in the range between about 200 °C and about 300 °C. The duration of the treatment can be in the range between about 30 seconds and about 60 seconds. In accordance with alternative embodiments of the present disclosure, heat treatment is carried out (without generating plasma). During the heat treatment, the temperature of the package component 100 can be greater than about 300 °C, for example, in the range between about 300 °C and about 350 °C.The duration of the treatment can range between approximately 30 seconds and approximately 60 seconds.

[0032] As a result of the post-deposition treatment, the inhibitor film 48 is removed. The resulting structure is in Fig. Figure 7 shows that during post-deposition treatment, the inhibitor film 48 decomposes into gases, which are removed. Additionally, any oxide present in the conductive region 28 is reduced back to the elemental metal. After the inhibitor film 48 has been removed, the islands 50' of the conductive barrier layer 50 are deposited on the conductive region 28.

[0033] An advantageous feature of performing the post-deposition treatment after the deposition of the conductive barrier layer 50 is that the conductive barrier layer 50 is condensed by the post-deposition treatment. By increasing the density of the conductive barrier layer 50, its ability to impede the diffusion of the material (such as copper) in the conductive region 56 is increased. Fig. 9) to block into the dielectric layer 34, improved.

[0034] With reference to Fig. 8 Conductive material 56 is deposited to fill the via opening 42 and the trench 44. The respective process is designated as process 214 in the process flow, as shown in Fig. 18 shown, illustrated. The processes that take place in the Fig. 6 and Fig. Figure 7 shows that these can be in-situ processes performed in the same vacuum environment without breaking the vacuum between them. Part or all of the deposition process in Fig. 8 can also be performed in situ in the same vacuum environment as the processes that are used in the Fig. 6 and Fig. 7 are shown, without breaking the vacuum between them. In accordance with some embodiments, the deposition of the conductive material 56 involves performing a full-area deposition to form a metal seed layer (which may be a copper layer) using physical vapor deposition (PVD) and filling the remainder of the via opening 42 and the trench 44, for example, using electroplating, electroless plating, deposition, or the like. A planarization process, such as a chemical-mechanical planarization (CMP) process or a mechanical polishing process, may be performed to remove excess sections of the conductive material 56 and consequently the via 58 and the metal conductor 60, as shown in Fig. Figure 9 shows how to form a via. Each of the via 58 and the metal conductor 60 has a section of the conductive barrier layer 50 and a section of the conductive material 56.

[0035] In the resulting structure, the islands can be 50' ( Fig. 9) are isolated from each other by the conductive area 28 and the conductive material 56, and the islands 50' may be in contact with the conductive area and the conductive material 56. Depending on the materials and the formation processes of the conductive area 28 and the conductive material 56, the interface between the conductive area 28 and the conductive material 56 may or may not be distinguishable. The islands 50' may be in physical contact with the interface.

[0036] As in Fig. As shown in Figure 9, due to the selective formation of the conductive barrier layer 50, the conductive barrier layer 50 has sections that contact the dielectric layer 34 to perform the fusion-blocking function and does not have significant sections to separate the conductive material 56 from the conductive area 28 via the via 58. Since the resistivity of the conductive barrier layer 50 is significantly higher (such as two to four orders of magnitude higher) than the resistivity of the conductive material 56, the absence of the conductive barrier layer 50 on the conductive area 28 can significantly reduce the contact resistance of the via 58.

[0037] Fig. Figure 9 also illustrates the formation of a dielectric etch stop layer 62, which contacts the dielectric layer 34 and the metal conductor 60. The respective process is shown as process 216 in the process sequence, as in Fig. Figure 18 illustrates this. In accordance with some embodiments, the dielectric etch stop layer 62 is formed from a metal oxide, a metal nitride, a metal carbonitride, silicon nitride, combinations thereof and / or multiple layers thereon.

[0038] Fig. Figure 13 describes the hydrophobic property of the inhibitor film 124 when formed from BTA. The layer 120 is a copper layer. The inhibitor film 124 is formed on the copper layer 120 and is made from BTA. A water droplet 122 is deposited onto the inhibitor film 124. The contact angle α1 is approximately 60°, indicating that the inhibitor film 124 is hydrophobic. For comparison, the following is illustrated. Fig. 14, that when the water droplet 122 is deposited directly onto the copper layer 120, the contact angle α2 is approximately 20 degrees. This indicates that the inhibitor film 124 is significantly more hydrophobic than copper. Consequently, the growth retardation of the conductive barrier layer 50 on the inhibitor film 48 is more significant than on bare copper. This proves that the effect of depositing the conductive barrier layer 50 on the inhibitor film 48 results in a more significant growth retardation than on bare copper.

[0039] Fig. Figure 15 illustrates the normalized via resistance values ​​of a plurality of via samples, with the cumulative percentages of the samples shown as a function of the via resistance values. A plurality of samples are formed, with some of the formation processes including pre-cleaning using H₂, resulting in the complete or partial removal of the inhibitor film (if present) in the samples. Data labeled 130 are obtained from the sample vias formed by performing pre-cleaning (to completely remove the inhibitor film) followed by deposition of a TaN layer by PVD.The data marked 132 are obtained from the sample vias formed by performing pre-cleaning (to completely remove the inhibitor film), followed by deposition of a TaN layer by ALD, and then performing a plasma treatment using H₂. The data marked 134 are obtained from the sample vias formed by performing weak pre-cleaning (to partially remove the inhibitor film), followed by deposition of a TaN layer, and then performing a plasma treatment using H₂. The data marked 136 are obtained from the sample vias formed by adopting the embodiments of this disclosure. The results indicate that the embodiments of this disclosure exhibit the lowest resistance values.Furthermore, a comparison of the results for samples 130, 132, 134, and 136 revealed that the via resistance is directly related to the amount of inhibitor film remaining after the TaN layer is deposited. The more inhibitor film remains, the more selective the TaN layer deposition becomes, thus achieving a lower via resistance. This is demonstrated by the low contact resistance values ​​of samples 134 and 136, compared to the high contact resistance values ​​of samples 130 and 132.

[0040] Fig. Figure 16 illustrates the thickness of the TaN layers deposited on different surfaces when ALD is used. The Y-axis represents the thickness of the TaN layers. The X-axis represents the number of ALD cycles. Row 140 shows the results obtained from samples formed by depositing TaN layers onto BTA foils. Row 142 shows the results obtained from samples formed by forming BTA foils, performing pre-cleaning to remove the BTA foils, and then depositing the TaN layers. Row 144 shows the results obtained from samples formed by depositing TaN layers onto bare copper. Line 146 represents the results obtained from the samples formed by depositing the TaN layers on oxidized copper (Cu2O) or bare copper exposed to air (with CuOH on the surface).It has been shown that line 140 corresponds to the greatest thickness, indicating the significant growth retardation of the TaN layers on BTA. Furthermore, line 142 indicates that the remaining BTA affects the growth retardation of the TaN layer.

[0041] Table 1 illustrates the results in a tabular format, with the results also shown in Fig. Figure 16 shows the data. The x's in the "Wet" and "Pre-clean" fields indicate whether wet cleaning (with formed BTA film) is performed, and whether pre-cleaning, in which the BTA film (if formed) is removed, is performed. For the data corresponding to sample 140, BTA films are not formed, and pre-cleaning is not performed. For the data corresponding to sample 142, BTA films are not formed, and pre-cleaning is performed. For the data corresponding to sample 144, the BTA films are formed and not removed when the TaN layer is formed. For the data corresponding to sample 146, BTA films are formed and then removed during pre-cleaning before the TaN layers are formed. The TaN thickness after 17 ALD cycles for line 144 is 0.73 nm, which is half of line 146 where the formed BTA foils are removed before the TaN layers are formed.This demonstrates the effectiveness of the BTA film in delaying / reducing the growth of TaN. The gradient of sample 144 is also significantly lower than that of other samples. This indicates that the growth rate of sample 144 is lower than that of other samples. Table 1 Prozess Daten Nass Vorreinigen Gefälle Dicke (nm) 140 0,589 1,909 142 x 0,577 1,492 144 x 0,262 0,73 146 x x 0,468 1,456

[0042] Fig. Figure 17 illustrates the comparison of the thicknesses of TaN layers on different surfaces with the thicknesses of TaN layers on copper, aluminum oxide and low-θ dielectric. Bar 150 represents the thickness of TaN grown on copper with the BTA film removed by pre-cleaning prior to TaN deposition. Bar 152 represents the thickness of TaN grown on a BTA film formed on copper. Bar 154 represents the thickness of TaN grown on aluminum oxide with the BTA film removed by pre-cleaning prior to TaN deposition. Bar 156 represents the thickness of TaN grown on a BTA film formed on aluminum oxide. Bar 158 represents the thickness of TaN grown on a dielectric low-θ layer without the BTA film removed (since no BTA forms on low-κ).Bar 160 represents the thickness of TaN grown on a dielectric low-κ layer (even without BTA formation). Comparing bar 150 with bar 152, bar 154 with bar 156, and bar 158 with bar 160 shows that inhibitor films significantly delay the growth of TaN layers on copper, the inhibitor film with partial coverage on the aluminum foil causes a slight but lesser delay in the growth of TaN layers on aluminum oxide, and there is no delay in the growth of TaN layers on a dielectric low-κ layer because no BTA film is formed on the dielectric low-θ layer. Fig. 17 explains the different growth retardation behavior on the conductive area 28, the etch stop layer 32 and the dielectric low-θ layer 34 ( Fig. 6).

[0043] The embodiments of the present disclosure have several advantageous features. By forming the conductive barrier layer after the formation of the inhibitor film, since the growth of the inhibitor film is selective on different materials, the resulting conductive barrier layer is selectively formed on the sidewalls of the dielectric low-kκ layer to perform the fusion-blocking function, and is not formed (or substantially not) on the underlying conductive area, thus preventing an undesirable increase in the through-hole resistance. Additionally, by performing the post-deposition treatment after the formation of the conductive barrier layer, not only is the inhibitor film removed, but the conductive barrier layer is also condensed, and the diffusion-blocking capability is improved.In conventional processes, pre-cleaning processes, which can be carried out using H2, are performed before the formation of the conductive barrier layers to reduce oxides, and do not fulfill the function of condensing the conductive barrier layers.

Claims

[1] A method of forming an integrated circuit structure, the method comprising: Forming (202) an etch stop layer (32) over a conductive feature (28); Forming (204) a dielectric layer (34) over the etch stop layer (32); Forming (206) an opening (42) in the dielectric layer (34) to expose the etch stop layer (32); Etching (208) the etch stop layer (32) through the opening (42) using an etchant comprising an inhibitor, wherein an inhibitor film (48) comprising the inhibitor is formed on the conductive feature (28); depositing (20) a conductive barrier layer (50) extending into the opening (42); after depositing the conductive barrier layer (50), performing (212) a treatment to remove the inhibitor film (48); and Depositing (214) a conductive material (56) to fill a remaining portion of the opening (42). [2] The method of claim 1, further comprising, after etching the etch stop layer (32), wetting a respective wafer having the etch stop layer (32) and the inhibitor film (48) with a chemical solution to increase a thickness of the inhibitor film, wherein the etch stop layer is not etched during the wetting. [3] The method of claim 2, wherein the etchant and the chemical solution comprise a same type of inhibitor. [4] A method according to any one of the preceding claims, wherein the treatment comprises a plasma treatment using hydrogen, H2, as a process gas. [5] A method according to any one of the preceding claims, wherein the treatment comprises a heat treatment using hydrogen, H2, as a process gas. [6] A method according to any preceding claim, wherein the inhibitor in the etchant comprises benzotriazole and the conductive feature comprises copper. [7] A method according to any preceding claim, wherein the conductive barrier layer (50) forms isolated islands on the inhibitor film (48). [8] The method of claim 7, wherein after treatment, the isolated islands are in contact with an interface between the conductive feature (28) and the conductive material (56). [9] The method of claim 8, wherein the isolated islands are separated from each other by the conductive material (56). [10] A method of forming an integrated circuit structure, the method comprising: Forming an etch stop layer (32) over a conductive feature (28); Forming a dielectric layer (34) over the etch stop layer (32); Forming an opening (42) in the dielectric layer (34) to expose the etch stop layer (32); Etching the etch stop layer (32); selectively depositing a conductive barrier layer (50) extending into the opening (42), wherein the selective deposition results in the conductive barrier layer (50) having a first thickness on a sidewall of the dielectric layer (34), and the conductive barrier layer (50) is thinner at least at a bottom of the opening (42) than on the sidewall of the dielectric layer (34), wherein etching the etch stop layer (32) results in an inhibitor film (48) being formed on a top surface of the conductive feature (28), and the procedure further comprises the following: after forming the conductive barrier layer (50), removing the inhibitor film (48); and Depositing a conductive material (56) to fill a remaining portion of the opening (42). [11] The method of claim 10, wherein the conductive barrier layer (50) comprises discrete islands at the bottom of the opening. [12] The method of claim 10 or 11, wherein the conductive barrier layer (50) does not extend to the bottom of the opening. [13] The method of any one of claims 10 to 12, wherein removing the inhibitor film (48) comprises a plasma treatment using hydrogen, H2, as a process gas. [14] The method of any one of claims 10 to 12, wherein removing the inhibitor film (48) comprises a heat treatment using hydrogen, H2, as a process gas.

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