MIDDLE-OF-LINE STRUCTURES

Abstract

Structure, comprehensive: a plurality of gate structures (110), each comprising a gate material (112); Source and / or drain metallization features (165); a beveled top layer (140) directly on an upper surface of the gate material (112); Sidewall spacers (115) on sidewalls of the gate structures (110); Liners formed from a first material (155) and a second material (180), wherein the first material (155) directly contacts an entire bottom surface of the source and / or drain metallization features (165), wherein the first material (155) is formed from Ti, TiN, TaN, Ru or Co; Contacts in electrical contact with the source and / or drain metallization features (165), which are separated from the gate structures (110) at least by the side wall spacers (115), wherein the first material (155) directly contacts a side wall of at least one of the side wall spacers (115) and directly contacts two side walls of a conductive filler material (160) of the source and / or drain metallization features (165); and Air gap (175) between the first material (155) and the second material (180), wherein the air gap (175) is located next to the side wall spacers (115) and below the beveled top layer (140) and is formed by a selected aspect ratio of the depressions as a result of constriction phenomena, so that a parasitic capacity is reduced.

Description

AREA OF INVENTION

[0001] The invention relates generally to semiconductor structures and in particular to middle-of-line structures and manufacturing processes. BACKGROUND

[0002] As semiconductor processes continue to scale down, for example through shrinking, the desired spacing between features (especially the pitch) also decreases. Furthermore, at smaller technology nodes, it becomes increasingly difficult to fabricate back-end-of-line (BEOL) and middle-of-line (MOL) metallization features, such as interconnects, due to process characteristics, the scaling of the critical dimension (CD), and the materials used to create these structures.

[0003] For example, when fabricating intermediate interconnect structures for source and drain contacts, it is necessary to remove the dielectric material located on the gate structures. This removal is achieved through an etching process that tends to erode the spacer material of the gate structure. Specifically, the low-k dielectric material used for the spacers or sidewalls of the gate structure can be eroded away in subsequent etching processes used to form the openings for the drain and source contacts. This material loss exposes the metal material of the gate structure, resulting in a short circuit between the metal material of the gate structure and the metal material used to form the contact itself.

[0004] US 2016 / 0315008 A1 mentions a semiconductor device comprising a semiconductor structure, multiple gate structures, at least one source / drain structure, at least one trench, a dielectric pattern and a conductive structure, wherein the conductive structure is arranged in the trench, is electrically connected to the source / drain structure and has a section of smaller width than another section that is connected to the source / drain structure.

[0005] US 2015 / 0380305 A1 discloses a contact structure which provides improved contact resistance and reliability by means of an inner spacer between a contact liner and dielectric layers that laterally surround the contact structure, by the spacer acting as a barrier against the diffusion of metals from the contact liner into the dielectric layers.

[0006] US 2015 / 0255571 A1 discloses a semiconductor device manufacturing process in which a first spacer is formed on a dummy gate, a sacrificial spacer is placed on it, a structure is etched, the sacrificial spacer is removed, and a material is inserted to define a gap. SUMMARY

[0007] In one example, a structure comprises: a plurality of gate structures with source and / or drain metallization features; spacers on side walls of the gate structures, wherein the spacers are formed from a first material and a second material; and contacts in electrical contact with the source and / or drain metallization features, wherein the contacts are separated from the gate structures by spacers.

[0008] In another example, a structure comprises: a plurality of gate structures with source / drain regions, a gate material, sidewall spacers, and a cover material on the gate material and the sidewall spacers; a plurality of source / drain contacts in electrical contact with the source / drain regions; a coating formed from a top material and a bottom material along the sidewall spacers; and contacts extending to the source / drain contacts and separated from the gate metal by the coating.

[0009] In another example, a process comprises: forming a plurality of gate structures with source and / or drain metallization features; forming spacers on sidewalls of the gate structures comprising a first material and a second material; and forming contacts in electrical contact with the source and / or drain metallization features, wherein the contacts are separated from the gate structures by the spacer.

[0010] According to the invention, a structure or a method according to one of the independent claims is provided. BRIEF DESCRIPTION OF THE FIGURES

[0011] The invention is described in detail below with reference to the majority of figures by means of non-limiting examples of exemplary embodiments of the invention. Fig. Figure 1 shows, among other features, gate structures and corresponding manufacturing processes according to aspects of the invention. Fig. Figure 2 shows, among other features, a recessed gate material of the gate structures and corresponding manufacturing processes according to aspects of the invention. Fig. Figure 3 shows, among other features, a cover material on the recessed gate materials and corresponding manufacturing processes according to aspects of the invention. Fig. Figure 4 shows, among other features, source and / or drain metallization features (contacts) and corresponding manufacturing processes according to aspects of the invention. Fig. Figure 5 shows, among other features, a recessed liner material and corresponding manufacturing processes according to aspects of the invention. Fig. Figure 6 shows, among other features, a spacer material in the recesses of the liner material and corresponding manufacturing processes according to aspects of the invention. Fig. Figure 7 shows, among other features, an insulating layer formed in depressions of the source / drain metallization features, and corresponding manufacturing processes according to aspects of the invention. Fig. Figure 8 shows, among other features, contacts that are electrically connected to the source / drain metallization features, and corresponding manufacturing processes according to aspects of the invention. Fig. Figure 9 shows an alternative structure and corresponding manufacturing processes according to additional aspects of the invention. DETAILED DESCRIPTION

[0012] The invention relates generally to semiconductor structures, and in particular to middle-of-line structures and fabrication processes. According to the embodiments herein, the processes and structures provided employ spacers on the sides of the gate structures to prevent short circuits between the source / drain (S / D) contacts and the metallization of the gate structures. Advantageously, the spacers provide additional material to prevent short circuits in fabrication processes, particularly during the formation of intermediate interconnect structures for the source / drain contacts. The structures provided herein offer gate structures with improved low parasitic capacitance.

[0013] The structures of the invention can be fabricated in a variety of ways using a variety of different tools. Generally, however, the methods and tools used are for forming structures with dimensions in the micrometer and nanometer range. The methods, and in particular the technologies, used in the fabrication of the structures of the invention were adopted from the technology of integrated circuits (ICs). The structures are fabricated, for example, on wafers and realized in material films that are structured on the top surface of a wafer by photolithographic processes. In particular, the fabrication of the structures uses three basic building blocks: (i) deposition of thin material films onto a substrate, (ii) application of a structured mask to the top surface of the films by means of photolithographic imaging, and (iii) selective etching of the films with respect to the mask.

[0014] Fig. Figure 1 shows an initial structure and corresponding manufacturing processes according to aspects of the invention. In particular, it shows Fig. 1. A structure 100 comprising a substrate 105 formed from a suitable semiconductor material. The substrate 105 can be formed from any suitable material, including, but not limited to, Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, etc. In embodiments, the substrate 105 can be a fin structure or a planar feature.

[0015] In embodiments, a fin structure can be fabricated using a side-wall image transfer (SIT) technique. According to one example of a SIT technique, a mandrel material, e.g., SiO2, is deposited on substrate 105 using known CVD processes. A resist is formed on the mandrel material and exposed to create a structure (openings). Reactive ion etching is performed through the openings to form the mandrels. In embodiments, the mandrels can have different widths and / or spacings depending on the desired dimensions of the fin structures. Spacers are formed on the sidewalls of the mandrels. These spacers are made of a preferred material that differs from the mandrel material and is formed using known deposition processes known to those skilled in the art. The spacers can have a width that, for example,with the dimensions of the tight FIN structures. The domes are removed or stripped using a known etching process that is selective for the mandrel material. Then, etching is performed within the spacer spacing to form the sub-lithographic features. The sidewall spacers can then be stripped.

[0016] With further reference to Fig. 1. Gate structures 110 are formed on the substrate 105. The gate structures 110 can be planar gate structures or FINFET gate structures. In any case, the gate structures 110 can be fabricated using known gate formation processes, such as exchange gate fabrication processes or gate-first processes known in the prior art. According to embodiments, the gate structures 110 comprise a dielectric gate material and metallization features. The dielectric gate material can, for example, be a high-k gate dielectric, such as a hafnium-based dielectric material. In further embodiments, the high-k dielectric materials can include, without limitation: Al₂O₃, Ta₂O₃, TiO₂, La₂O₃, SrTiO₃, LaAlO₃, ZrO₂, Y₂O₃, Gd₂O₃, and combinations comprising multilayers thereof.The metallization features, in particular the gate material 112, can comprise any exit work metal or combinations of metals, depending on the specific application and the desired parameters. According to embodiments, the gate material 112 can, for example, be a tungsten (W) material.

[0017] With further reference to Fig. 1. Sidewall spacers 115, e.g., a dielectric low-k material, can be deposited on the sidewalls of the gate structures 110. The sidewall spacers 115 can be deposited by known chemical vapor deposition (CVD) processes, followed by a structuring process, e.g., an anisotropic etching process, to remove material from the horizontal surfaces of the structure. Source and drain (S / D) regions 120 can be formed on sides of the gate structures 110, e.g., the sides of the sidewall spacers 115, in the substrate 105 using, e.g., a known method. The S / D regions 120 can be formed, e.g., by an ion implantation process, a doping process, or by means of a diffusion process, as is known in the art, without further explanation being required for understanding the invention.In further embodiments, the S / D areas 120 can represent increased S / D areas formed by epi-growth on the surfaces of the substrate 105 between the gate structures 110.

[0018] Fig. Figure 1 further shows a liner 125 and an insulator material 130, which is deposited within trenches formed between the gate structures 110, and in particular between the sidewall spacers 115. In embodiments, the liner 125 and the insulator material 130 can be deposited by CVD processes. The liner 125 can be formed from any suitable material, e.g., SiN, while the insulator material can be formed from an oxide.

[0019] In Fig. 2. Indentations 135 are formed by back-etching the gate structures 110. The indentations 135 are formed, in particular, by etching the metallization features, especially of the gate material 112, of the gate structures 110, followed by etching the sidewall spacers 115. In embodiments, the gate material 112 and the sidewall spacers 115 are recessed beneath a surface of the liner 125 and the insulator material 130. The gate structures 110 can be etched, for example, by approximately 10% to 50% of their original height, e.g., approximately 30 nm to 40 nm. In embodiments, the gate material 112 and the sidewall spacers 115 can be etched using reactive ion etching (RIE) with a chemistry that is selective with respect to the specific material of this structure. Advantageously, due to the selective chemistry, the etching processes do not require a mask.

[0020] In Fig. 3. A cover material 140 is formed as a layer over the gate structures 110 and the sidewall spacers 115, e.g., in the recesses 135. In this way, the gate structures 110 can comprise a gate material 112, sidewall spacers 115, and the cover material 140. In embodiments, the cover material 140 can be deposited within the recesses 135 by a CVD process, followed by a chemical-mechanical polishing (CMP) process. The cover material 140 can provide protection for the metallization features of the gate structures 110 during subsequent processes for the formation of source / drain contacts or intermediate connections, e.g., prior to etching processes to form the source / drain contacts or intermediate connections. The cover material 140 can, for example, be made of SiN.

[0021] With further reference to Fig. 3. Trenches 150 are formed between the gate structures 110 by removing the liner 125 and the insulator material 130. In embodiments, the liner 125 and the insulator material 130 can be removed by known RIE processes. Etching or removing the liner 125 and the insulator material 130 exposes the S / D areas 120 and forms a chamfer 142 of the cover material 140.

[0022] Fig. Figure 4 shows, among other features, source / drain metallization features and corresponding manufacturing processes according to aspects of the invention. In particular, a liner 155 is formed on the sidewalls of the sidewall spacers 115 using, for example, physical vapor deposition (PVD) or continuous vapor deposition (CVD) processes. The liner 155 can be formed from Ti, TiN, TaN, Ru, and Co, among other examples. In embodiments, the liner 155 can have a thickness in the range of approximately 2 nm to 20 nm, with a desired thickness being in the range of approximately 8 nm to 10 nm; although other dimensions are also possible. In embodiments, the liner 155 directly contacts the S / D areas 120 (silicide of the S / D areas). After the deposition of the liner 155, a metal filling 160 is deposited within the trenches 150 and above the liner 155 to form the source and / or drain metallization features 165.In this way, the majority of gate structures 110 can include the source and / or drain metallization features 165. The metal filling 160 can be deposited by CVD processes and can be any suitable conductive material. The metal filling 160 can, for example, be formed by T, Co, or Cu. In this way, the source and / or drain metallization features 165 include a conductive filling material, in particular the metal filling 160, which is in electrical contact with the source / drain regions 120 of the gate structures 110.

[0023] In Fig. 5. Sections of the liner 155 are removed from the source and / or drain metallization features 165 to form the depressions 170 between the metal filling 160 and the cover material 140. In embodiments, the liner 155 can be deepened by a wet etching process that uses chemicals to remove material from the liner 155 (selectively with respect to the remaining materials), e.g., Ti, TiN, TaN, Ru, and Co, etc. In embodiments, the depressions 170 can have different depths. For example, one depth of the depressions 170 can extend below a surface of the gate structure 110, e.g., below the cover material 140 or a surface of the metal material, in particular the gate material 112, of the gate structures 110. In embodiments, the depressions 170 can also extend within the extent of the cover material 140.

[0024] In Fig. 6. A spacer material 180 is deposited within the recesses 170 to form spacers 182. According to embodiments, the spacer material 180 differs from the material of the liner 155; preferably, it is a more resistant material that can better withstand subsequent etching processes. The second or upper material, in particular the spacer material 180, can be a high-k dielectric material or a low-k dielectric material with a thickness similar to that of the liner 155, e.g., 2 nm to 20 nm. More specifically, the spacer material 180 can be formed from SiN, Al₂O₃, or HfO₂, among other examples. In this way, the second or upper material is SiN, Al₂O₃, or HfO₂, and the first or lower material is Ti, TiN, TaN, Ru, or Co.The spacer material 180 can be deposited by a known CVD process to fill the recesses 170, followed by a CMP process or another etching process, e.g., back etching, wet etching, or dry etching.

[0025] In embodiments, the spacer material 180 and the corresponding spacers 182 further serve to prevent the gate structures 110 from being exposed in subsequent MOL etching processes. In particular, the spacer material 180 efficiently prevents the gate metals of the gate structures 110, especially the gate material 112, from being exposed during etching processes, thereby preventing short circuits between the gate metals and the source / drain contacts or other metallization features, e.g., intermediate connections that are formed in MOL processes. As shown in Fig. 6. The liner material 155 and the spacer material 180 can function as spacers on the sidewall spacers 115 of the gate structures 110 and can be formed from a first material representing the liner 155 and a second material representing the spacer material 180. Alternatively, the liner material 155 together with the spacer material 180 can be considered a thin coating, the coating being formed from a top material, in particular the spacer material 180, and a bottom material, in particular the liner material 155, along the sidewall spacers 115. In embodiments, the spacers 182 formed from the spacer material 180 are in direct contact with the sidewall spacers 115 and the cover material 140 on the gate structures 110 and the source and / or drain metallization features 165.

[0026] Fig. Figure 7 shows an insulator material 195, which, among other features, is formed in recesses 100 of the source and / or drain metallization features 165. In particular, the metal filling 160 is subjected to a selective etching process to form recesses 190 between the spacer material 180, leaving the spacers 182 formed from the spacer material 180. In embodiments, the recesses 190 have a depth that lies within the extent of the spacers 182, e.g., preferably above the metallization features of the gate structures 110, in particular the gate material 112. In this way, the spacers 182 can be protected from erosion of the cover material 140 in subsequent etching processes by maintaining the depth of the recesses 190 within the extent of the spacers 182 formed from the spacer material 180.In particular, the second or upper material, especially the spacer material 180, protects the layer of the cover material 140 from erosion in an etching process. An insulator material 195 can be deposited within the recesses 190. The insulator material 195 can be a dielectric intermediate material, e.g., an oxide deposited by a CVD process.

[0027] In Fig. 8 Metallization structures 200 are formed in the insulator material 195 and these function as contacts that are in direct electrical contact with the metal filling 160 of the S / D regions 120. In particular, the metallization structures 200 constitute contacts that are in direct electrical contact with the source and / or drain metallization features 165 and are separated from the gate structures 110 by the spacer material 180. In this way, the contacts, in particular the metallization structures 200, extend to the S / D regions 120 and are separated from the gate material 112 by the thin coating formed by the liner material 155 and the spacer material 180. According to embodiments, the metallization structures 200 can represent intermediate connection structures formed from a tungsten material that is in electrical contact with the S / D areas 120 (via the metal filling 160).The metallization structures 200, in particular wiring structures or intermediate connection structures, can be formed by known lithography, etching and deposition processes known to the person skilled in the art.

[0028] The metallization structures 200 can be produced by forming a lacquer over the insulator material 195, which is then exposed to energy (light) to form a structure (opening). An etching process using selective chemistry, e.g., RIE, is employed to create at least one trench in the insulator material 195 through the openings in the lacquer. The spacer material 180 prevents the etching process from exposing the materials of the gate structures 110; in particular, the spacer material 180 provides protection during the etching process so that the cover material 140 and / or the sidewall spacer material 115 and / or the gate material 112 are not (or only minimally) subjected to erosion during the etching process. As a result, the conductive material deposited for the metallization structures 200 is not in contact with the metal material, in particular the gate material 112, of the gate structures 110.This prevents a short circuit.

[0029] In embodiments, the lacquer can be removed by a known oxygen ashing process or other known removal agents, followed by the deposition of the conductive material by known deposition processes, e.g., CVD processes. Any remaining conductive material on the surface of the insulator material 195 can be removed by known chemical-mechanical polishing (CMP) processes.

[0030] Fig. Figure 9 shows an alternative structure 100' and corresponding manufacturing processes according to additional aspects of the invention. For example, the liner 155 is in Fig.9 below the cover material 140, and even more preferably significantly below a surface of the metallization feature of the gate structures 110, in particular the gate material 112, as indicated by reference numeral 170'. In embodiments, the recesses 170' are located at such a depth that an air gap 175, which is formed in subsequent deposition processes of the spacer material 180 due to constriction phenomena; in particular, the combination of the depth and width of the recesses 170', especially the aspect ratio of the recesses 170', leads to the formation of air gaps 175 between the side wall spacers 115 and the metal filling 160 during the deposition of the spacer material 180 due to a constriction phenomenon.In this way, the air gaps 175 are located between the first or lower material, in particular the liner 155, and the second or upper material, in particular the spacer material 180. Furthermore, the air gaps 175 are located below a surface of the gate material 112 of the gate structures 110 and are separated from the gate material 112 by the sidewall spacers 115. Specifically, the air gaps 175 are located near the sidewall spacers 115 on the gate structures 110 and below the cover material 140 above the gate material 112. In embodiments, the air gaps 175 serve to increase the parasitic capacity of the structure. The remaining sections of the structure 100' are similar to those described herein.

[0031] The processes and resulting structures described herein serve to further protect the gate metal of the gate structure in MOL processes. The resulting structures, particularly sidewall structures, consequently prevent short circuits that occur when intermediate connections or other wiring structures are present in the source / drain regions. Accordingly, the processes and structures described herein increase the yield.

[0032] The method(s) described above is / are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be marketed by the manufacturer in the form of bare wafers (specifically, a single wafer containing multiple unpackaged chips), as a bare die, or in packaged form. In the latter case, the chip is mounted in a single-chip package (e.g., a plastic substrate with traces attached to a motherboard or other higher-order substrate) or in a multi-chip package (e.g., a ceramic substrate with surface interconnects and / or buried interconnects). In each case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product, e.g., a motherboard, or (b) a final product.The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products with a display, keyboard or other input devices, and a central processing unit.

Claims

[1] Structure, comprehensive: a plurality of gate structures (110), each comprising a gate material (112); Source and / or drain metallization features (165); a beveled top layer (140) directly on an upper surface of the gate material (112); Sidewall spacers (115) on sidewalls of the gate structures (110); Liners formed from a first material (155) and a second material (180), wherein the first material (155) directly contacts an entire bottom surface of the source and / or drain metallization features (165), wherein the first material (155) is formed from Ti, TiN, TaN, Ru or Co; Contacts in electrical contact with the source and / or drain metallization features (165), which are separated from the gate structures (110) at least by the side wall spacers (115), wherein the first material (155) directly contacts a side wall of at least one of the side wall spacers (115) and directly contacts two side walls of a conductive filler material (160) of the source and / or drain metallization features (165); and Air gap (175) between the first material (155) and the second material (180), wherein the air gap (175) is located next to the side wall spacers (115) and below the beveled top layer (140) and is formed by a selected aspect ratio of the depressions as a result of constriction phenomena, so that a parasitic capacity is reduced. [2] Structure according to claim 1, wherein the second material (180) protects the beveled cover layer (140) from erosion in an etching process. [3] Structure according to claim 2, wherein the second material (180) is a dielectric high-k material or a dielectric low-k material. [4] Structure according to claim 3, wherein the second material (180) is made of SiN or Al2O3 or HfO2. [5] Structure according to claim 1, wherein the conductive filling material (160) is in electrical contact with source and drain areas (120). [6] Structure according to claim 1, wherein the side wall spacers (115) are in direct contact with a side wall structure and the chamfered cover layer (140) on the gate structures (110) and the source and / or drain metallization features (165). [7] Structure, comprehensive: a plurality of gate structures (110) with a gate material (112); Source / Drain areas (120); Side wall spacers (115); a beveled top layer (140) on the gate material (112) and the side wall spacers (115); a plurality of source / drain contacts (200) in electrical contact with the source / drain areas (120); Liners comprising an upper material (180) and a lower material (155) along the sidewall spacers (115), the liners extending under the source / drain contacts (200) such that the lower material directly contacts an entire base of the source / drain contacts (200), the source / drain contacts (200) being separated from the gate material (112) by the liners and the sidewall spacers (115), the lower material (155) being made of Ti, TiN, TaN, Ru or Co, wherein the side wall spacers (115) are in direct contact with two side walls of the gate material (112), and the lower material directly contacts a side wall of at least one of the side wall spacers (115) and directly contacts two side walls of a conductive filler material (160) of the source / drain contacts (200); and Air gap (175) between the upper material (180) and the lower material (155), wherein the air gap (175) is located next to the side wall spacers (115) and below the beveled top layer (140) and is formed by a selected aspect ratio of the depressions as a result of constriction phenomena, so that a parasitic capacity is reduced. [8] Structure according to claim 7, wherein the upper material (180) is made of SiN or Al2O3 or HfO2. [9] Structure according to claim 7, wherein the upper material (180) is formed from a dielectric high-k material. [10] Procedures, including: a formation of a plurality of gate structures (110) comprising a gate material (112); forming side wall spacers (115); a formation of source and / or drain metallization features (165); a formation of a beveled top layer (140) over the gate structures (110); forming sidewall spacers (115) on sidewalls of the gate structures (110); a formation of liners comprising a first material (155) and a second material (180), wherein the first material (155) extends below the source and / or drain metallization features (165) and wherein the first material directly contacts and extends over the entire base surface of the source and / or drain metallization features (165), wherein the first material (155) is composed of Ti, TiN, TaN, Ru or Co; a formation of contacts in electrical contact with the source and / or drain metallization features (200) which are separated from the gate structures (110) by the side wall spacers (115), wherein the side wall spacers (115) are in direct contact with two side walls of the gate material (112), and the first material directly contacts a side wall of at least one of the side wall spacers (115) and directly contacts two side walls of a conductive filler material (160) of the source and / or drain metallization features (165); and a formation of air gaps (175) between the first material (155) and the second material (180), wherein the air gaps (175) are located next to the side wall spacers (115) and below the beveled cover material (140) and are formed by a selected aspect ratio of the depressions as a result of constricting phenomena, so that a parasitic capacity is reduced. [11] Method according to claim 10, wherein the second material (180) is formed from SiN or Al2O3 or HfO2.

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