SRAM STORAGE

Abstract

A storage device comprises a matrix array of memory cells, consisting of a first submatrix array and a second submatrix array. Several bit lines are connected to the memory cells, and an input / output (IA) block is located between the first and second submatrix arrays. The bit lines extend directly from the first and second memory submatrix arrays of the storage device to the IIA block. The IIA block also includes input and output ports configured to receive data to be written to the matrix array of memory cells and to output data read from the matrix array of memory cells via the several bit lines.

Description

BACKGROUND

[0001] The present application claims priority over Preliminary US Patent Application No. 62 / 647,422 entitled “FOLDED MEMORY ARCHITECTURE”, filed on March 23, 2018, the disclosure of which is hereby incorporated by reference in its entirety. BACKGROUND

[0002] A common type of memory in an integrated circuit is a static random access memory (SRAM) device. A typical SRAM memory device has a matrix of memory cells. Each memory cell uses six transistors connected, for example, between an upper reference potential and a lower reference potential (typically ground), so that one of two memory nodes can be occupied by the information to be stored, with the complementary information stored at the other memory node.

[0003] SRAM memory is often used for computing applications, such as implementing a cache. A central processing unit (CPU) cache is a hardware cache used by the CPU. CPUs access data from main memory, but this operation is time-consuming and inefficient. A cache is used to provide faster access to frequently used data by storing it locally. A cache provides a smaller storage capacity, but its location near the CPU allows the CPU to significantly speed up requests for frequently used data. In some examples, caches are arranged in a multi-level hierarchy ( L1 , L2 etc.) organized. In a hierarchical cache memory, the level L1The L1 cache is located closest to the CPU. Therefore, its capacity is small, but its access speed is the fastest. Because it provides data or instruction words directly to the CPU, the L1 cache typically operates at the same clock speed as the CPU. List of characters

[0004] Aspects of the present disclosure are best understood from the following detailed description in conjunction with the accompanying figures. It should be noted that, in accordance with common technical practice, various elements are not shown to scale. In fact, the dimensions of the various elements may have been enlarged or reduced as desired for clarity of the description. Furthermore, the drawings are illustrative examples or embodiments of the invention and are not intended to be limiting. Fig. Figure 1 is a block diagram illustrating aspects of an exemplary storage device according to some embodiments. Fig. Figure 2 is a circuit diagram of an example of a cell of a static random access memory (SRAM) according to some embodiments. Fig. 3 is a block diagram which shows further aspects of an example for the in Fig. 1 illustrated storage according to some embodiments. Fig. 4 is a block diagram which shows further aspects of an example for the in Fig. 1 illustrated storage according to some embodiments. Fig. Figure 5 is a block diagram illustrating an example of a memory I / O block according to some embodiments. Fig. Figure 6 is a block diagram illustrating another example of a storage device according to some embodiments. Fig. Figure 7 is a block diagram illustrating another example of a storage device according to some embodiments. Fig. Figure 8 is a block diagram illustrating another example of a memory input / output (I / O) block according to some embodiments. Fig. Figure 9 is a block diagram illustrating another example of a memory I / O block according to some embodiments. Fig. Figure 10 is a block diagram illustrating another example of a memory I / O block according to some embodiments. Fig. Figure 11 is a circuit diagram illustrating another example of a storage device according to some embodiments. Fig. Figure 12 is a flowchart illustrating an example of a storage I / O procedure according to some embodiments. DETAILED DESCRIPTION

[0005] The following disclosure presents many different embodiments or examples of the realization of various features of the subject matter of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature above or on top of a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples in the present disclosure.This repetition serves to simplify and clarify and, as such, does not establish any relationship between the various embodiments and / or configurations described.

[0006] Furthermore, for the sake of simplicity, spatial relationship terms such as "below," "under," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or feature to another element(s) or feature(s), as illustrated in the figures. These spatial relationship terms are intended to encompass orientations of the device in use or operation beyond the orientation depicted in the figures. The device may be oriented differently (rotated by 90 degrees or exhibiting other orientations), and the spatial relationship descriptors used herein may be interpreted accordingly.

[0007] Storage devices, such as static random-access memory (SRAM), have memory cells arranged in a matrix array with rows and columns. The memory cells are connected to a row decoder via word lines. The memory cell matrix also contains bit lines that connect the columns of multiple individual memory cells to an input / output (I / O) block. Thus, the bit lines of each column are connected to multiple memory cells located in that column, and each memory cell in that column is located in a different row and connected to a corresponding word line. Typically, the bit lines extend in one direction (parallel to a first axis), and the word lines extend in a second direction (parallel to a second axis) perpendicular to the first direction. The I / O block is connected to a controller that implements the control logic of the memory architecture.

[0008] SRAM memory is often used to implement various cache memory arrangements, e.g., L1 cache, L2 cache, etc. In a hierarchical cache memory, the level L1 The L1 cache is located closest to the CPU. Therefore, its capacity is small, but its access speed is the fastest. Because it provides data or instruction words directly to the CPU, the L1 cache typically operates at the same clock speed as the CPU.

[0009] Often, CPU space is a limiting factor, so it's sometimes necessary to use long bit lines and long word lines in the L1 cache to minimize the required memory area. These long and heavily loaded bit lines can degrade cache performance. This is because the resistance of each bit line, which increases with its length, introduces a delay in memory cell access time. Reducing the length and number of bits along the bit line improves cache performance.

[0010] Some solutions attempt to reduce bit line lengths while maintaining the same total number of bits by creating subbanks of smaller memory cell matrix arrays, each with shorter bit lines. Local I / O structures with multiplexers aggregate information from the subbanks, which is then sent to global I / O devices using global bit lines. Such structures can introduce additional time delays, potentially diminishing the benefit of shortening the bit lines. Furthermore, the area required to implement this design increases, reducing the CPU footprint and further impacting CPU performance.

[0011] According to some disclosed examples, a "folded architecture" of the memory is used to improve the performance of the storage device. This "folded architecture" shortens the length of the bit lines and eliminates the need for global bit lines, thereby increasing the access speed of the memory, while in implementations such as an L1 cache memory, the CPU area is minimally affected. In some embodiments, the disclosed invention of the memory arrangement is described as being implemented as an SRAM for an L1 cache memory; however, other embodiments are also possible.

[0012] Fig. 1 is a block diagram, which is an example of a storage device 100 illustrated according to aspects of the present disclosure. In the embodiment shown, the Fig. 1 includes the storage device 100 a memory cell matrix field105 , an input / output (I / O) block 130 and a word-lead driver 120 The memory cell matrix field 105 is in two memory submatrix fields 105a , 105b subdivided, located on opposite sides of the EA block 130 are arranged and directly connected to it.

[0013] As stated above, the storage device 100 In some embodiments, an SRAM memory is used, and thus the memory matrix field is 105 a matrix array of SRAM memory cells. Fig. Figure 2 illustrates an example of an SRAM memory cell. 200 of the in Fig. 1 of the depicted memory matrix field 105 The memory cell 200 is with a word line 202 and complementary bit lines BL 204a and BLB 204b connected. As will be described further below, the submatrix fields are 105a , 105bon both sides of the EA block 130 arranged and the bit lines 204a , 204b are directly connected to the EA block 130 connected. The EA block 130 includes a data input port 102 and an output port 104 , which data to write to the memory submatrix fields 105a , 105b receive or output data from the memory submatrix fields 105a , 105b be read out.

[0014] The memory cell 200 includes PMOS transistors 208a up to b and NMOS transistors 206a up to d. The transistors 208a and 206c They are connected to each other and positioned between the supply voltage VDD and ground to form an inverter. Similarly, the transistors are 208b and 206dConnected between VDD and ground to form a second inverter. The two inverters are cross-coupled. An access transistor 206a connects the output of the first inverter to the bit line BL 204a Similarly, the access transistor connects 206b connect the output of the second inverter to the bit bus. 204b The word order 202 is at the gate controls of the access transistors 206a and 206b attached to respond to the word-guiding driver during reading / writing operations 120 , who in Fig. As shown in Figure 1, the outputs of the inverters are selectively connected to the bit lines. 204a , 204b to connect. During a read operation, the inverters drive the complementary voltage levels on the bit lines. 204a , 204b .

[0015] The cross-coupled inverters of the storage cell 200provide two stable voltage states, which are used as logic values 0 and 1 These are referred to as transistors in the memory cell. 200 Metal-oxide-semiconductor field-effect transistors (MOSFETs) are typically used. In some embodiments, more or fewer than 6 transistors can be used to represent the memory cell. 200 to realize.

[0016] Fig. 3 illustrates further aspects of the memory cell 100 In some embodiments, the memory cells comprise submatrix fields. 105a , 105b each of the memory cells 200 , arranged in a column-row configuration, in which each column represents a bit line 204a and a bit bus 204b features and each row has a word line 202 features the bit lines. 204a , 204b Each column is correspondingly populated with several of the memory cells 200connected, which are located in this column, and each memory cell 200 In this column, the entries are arranged in a different row and with a corresponding (different) word order. 202 connected. That means each memory cell 200 of the memory cell matrix field 110 is connected to a bit line 204a a column of the memory cell matrix field 110 , a bit bus 204b the column of the memory cell matrix field 110 and a word lead 202 a series of the memory cell matrix field 110 connected. In some embodiments, the bit lines are 204a and the bit bus 204b arranged parallel vertically and the word lines 202 are parallel horizontally (i.e. perpendicular to the bit lines) 204a , 204b) arranged. The bit lines 204a , 204b the memory cells 200 the submatrix fields 105a , 105bextend directly to the EA block 130 , which is the data input port 102 and an output port 104 includes storing data in the memory cells 200 to write to them or to read from them.

[0017] Referring now to Fig. 4. Further aspects of the storage device will be discussed. 100 illustrated according to disclosed embodiments. The storage device 100 comprises a matrix field of memory cells 105 , which is a first submatrix field 105a and a second submatrix field 105b includes multiple bit lines. 204 are connected to the memory cells 105 connected and an EA block 130 is located between the first submatrix field 105a and the second submatrix field 105bAs stated above, in certain storage applications, such as for an L1 cache, high-speed access to the memory matrix array is desirable. To shorten the bit lines and improve performance, the bit lines are extended 204 from the first and second memory submatrix field 105a , 105b the storage device 100 directly to the EA block 130 The EA block 130 includes a data input port 102 and an output port 104 , which data from the bit lines 204 output and data into the bit lines 204 input.

[0018] The in Fig. 1 to Fig. 4 storage device shown 100 provides a "folded" memory matrix array arrangement by virtue of the position of the EA block 130 , which extends horizontally across the memory matrix field 105extends so that it covers the matrix field 105 into the first and second submatrix fields 105a , 105b subdivided, with the folded storage architecture 100 When divided, essentially a mirror image of the storage structure is created.

[0019] The illustrated “folded” arrangement, in which the EA block 130 directly the bit lines 204 from both memory submatrix fields 105a , 105b receives, enables the length of the bit line to be 204The number of bit lines is reduced to approximately half that of a conventional arrangement, with the bit lines extending to an I / O block at one end of the memory matrix array. In other conventional arrangements, bit lines from memory submatrix arrays have local bit lines that extend to a centrally located local I / O block. However, additional global bit lines are required to send and receive data between the local I / O block and a global I / O block, in order to communicate outside the memory matrix array. Since the bit lines 204 for the entire matrix field 105 , which is the first and second submatrix field 105a , 105b includes, from the EA block 130 be received, which has the input and output connection 102 , 104 Included are the examples of the device disclosed herein. 100No additional components are required, such as the global bit lines and the global I / O block. As further described below, in some embodiments of the folded or mirror-image arrangement, which are described in Fig. 1 to Fig. As shown in Figure 4, the first and second submatrix fields contain corresponding first and second EA blocks, which are arranged between the two submatrix fields. In some examples, the first and second EA blocks may be reserved for the upper submatrix field and the lower submatrix field, respectively. Furthermore, since the first and second EA blocks are arranged side-by-side between the submatrix fields, for additional efficiency and space savings, some components of the EA blocks may be reserved for the upper submatrix field, some components may be reserved for the lower submatrix field, and some components may be shared by both submatrix fields.

[0020] Fig. 5 is a block diagram which shows further aspects of the EA block 130 Illustrated. The EA block 130 has a first or upper side 131 and a second or lower side 132 opposite the first page 131 up. The top side 131 receives several of the bit lines. 204 from the first memory submatrix field 105a and the bottom side 132 The second receives several of the bit lines. 204 from the second memory submatrix field 105b .

[0021] The EA block 130 includes various control blocks for reading and writing data to and from the memory matrix array. 105 The bit lines 204 both submatrix fields 105a , 105b connect to the EA block 130 , which includes, for example, a bit line preloading, multiplexer (MUX) and write driver block 210 , a reading amplifier 220, a write control 230 and an output latch 240 The data input port can include 102 and the data output port 104 receive data from the storage device 100 and output them to components external to it.

[0022] Fig. Figure 6 illustrates another example of the storage device. 100 , where a "butterfly" type design is depicted, wherein a serial decoder 120 and a control system 140 generally parallel to the bit lines 204 (vertically in Fig. 6) extend and center in the memory cell matrix field 105 are arranged to form the matrix field 105 continue into a third submatrix field 105c and a fourth submatrix field 105d to be subdivided. Fig. Figure 7 illustrates another example, where the series decoders 120 and the controls 140on one side of the memory matrix array 105 are arranged. As in the example shown in Fig. As shown in figure 4, the bit lines extend 204 from the opposite sides (top and bottom sides) of the EA block 130 so that the EA components are in the middle of the matrix field 105 are arranged. Various peripheral components can also be accessed from the upper submatrix field(s) 105a, 105c and the lower submatrix field(s). 105b , 105d be used together.

[0023] As already mentioned, various peripheral components of the EA block can 130 from the memory cells of the submatrix fields 105a , 105b can be used jointly. This can be the macro-scale area required for the storage device disclosed herein. 100 to realize, further reduce. The arrangement of EA blocks for the submatrix fields. 105a , 105bside by side between the submatrix fields 105a , 105b enables the shared use of various components of the EA block 130 through the memory submatrix fields 105a , 105b , which shortens the bit lines 240 This allows for better utilization of space without significantly impacting the macro-scale footprint. This optimizes the performance of both the storage device and its associated components, and reduces component redundancy in the EA blocks. As mentioned above, storage applications, such as a lithium cache, may require fast access speeds while minimizing space requirements.

[0024] In some examples, the EA block includes 130 a first and second EA block 130a , 130b , which are connected to the bit lines 204 the first or second submatrix fields 105a, 105b are connected. Fig. Figure 7 illustrates such an arrangement. Furthermore, devices can be used in which the series decoders are used. 120 the memory matrix field further into the third and fourth sub-matrix fields 105c , 105d subdivide, a corresponding third and fourth memory block 130c , 130d used, as in Fig. 6 shown. In the examples of the Fig. 6 and Fig. 7 are all of the control blocks 130 between the upper and lower submatrix fields 105a , 105b (and 105c , 105d ) arranged and are thus centrally located to allow that on the top and bottom sides 131 , 132 the EA blocks 130 shortened bit lines 204 be received.

[0025] In this way, some or all of the EA functions can be assigned to the memory cells and bit lines. 204The corresponding submatrix fields may be reserved. This can affect the performance of the storage device. 100 improve.

[0026] Fig. Figure 8 illustrates aspects of an example for the EA block 130 , where various components of the EA block 130 in a first and second EA block 130a , 130b are provided, which are generally arranged as mirror images of each other. As in Fig. As shown in Figure 8, each of the EA blocks comprises 130a , 130b a bitline preload, read MUX and write driver block 210 , a reading amplifier 220 , a write control 230 and an output latch 240 A data EA layer, which handles data input- 102 and data output port 104 includes, is between the upper and lower control blocks 130a , 130b arranged.

[0027] Fig. Figure 9 shows another example, where the output latch 240 from both EA blocks 130a , 130b is used together. In other words, the individual output latch block 240 functions to store output signals that are on the bit lines 204 both from the first and from the second submatrix fields 105a , 105b to be received. Other EA function blocks are present multiple times, so that the bit lines 204 of the first and second submatrix fields 105a , 105b , a corresponding bitline preload, read MUX and write driver block 210 , a reading amplifier 220 and a write control 230 exhibit. Again, the data EA layer, which handles data input- 102 and data output port 104 includes, between the upper and lower control blocks 130a , 130b arranged.

[0028] Fig. Figure 10 illustrates another example, where further EA functions are derived from the first and second submatrix fields. 105a , 105b can be used together. Specifically, both the output latch function and the output latch function are used together. 240 as well as the write control function 230 from the EA blocks 130a , 130b shared. In other words, the single output latch block 240 and the individual write control 230 received on the bit lines 204 direct signals from both the first and the second submatrix field 105a , 105b Other EA function blocks are located in both the upper and lower EA blocks. 130a , 130b provided so that the bit lines 204 of the first and second submatrix fields 105a , 105b a respective bit line preload, read MUX and write driver block 210 and a respective reading amplifier 220exhibit. Again, the data EA layer, which handles data input- 102 and data output port 104 includes, between the upper and lower control blocks 130a , 130b arranged.

[0029] Fig. 11 is a circuit diagram which shows aspects of another exemplary storage device 100 illustrated, with the EA blocks 130a , 130b between a first and second memory submatrix field 105a , 105b are arranged adjacent to each other and have an output latch 270 share. Fig. 11 shows sections of a single column of memory cells 200 of the first and second memory cell matrix field 105a , 105b , which are between two bit lines 204a , 204b are arranged. The bit lines 204b These are rail-based bit lines that transmit signals complementary to those on the bit lines.204a are. The memory cells 200 are connected with corresponding word lines, which are illustrated in the example that is in Fig. As shown in 11, in horizontal rows perpendicular to the bit lines 204a , 204b extend. The word lines are activated in response to word line selection signals from the word line driver. 120 to be issued, which in Fig. 1 is shown.

[0030] During a reading operation, the word line driver decodes the data. 120 The selected word line is based on a received word line address. This is done at the corresponding gate terminals of the transistors. 310 and 312 Column selection signals ysel_u 320 and / or ysel_d 330 are received to select the desired columns of the memory matrix array. 105 to select. In response to the column selection signals 320 , 330 Data signals are extracted from the selected rows of memory cells200 to appropriate reading amplifiers 220 of the first and second EA blocks 130a , 130b output. In some examples, the word routing driver 120 configured to retrieve only a row from the upper matrix field during a specific read operation 105a or the lower matrix field 105b Select one row, but not both. Accordingly, only a selected row from the upper matrix field is sent. 105a or the lower matrix field 105b Data along the bit lines 204a , 204b to the respective control block 130a , 130b The complementary signals from the selected memory cells 200 on the bit lines 204a , 204b are by the reading amplifiers 220 received, which in response to the read amplifier activation signals sae_u 322 or sae_d 332 the amplified data signals to the shared output latch240 Output the data signals from the shared output latch. 270 output on output pin Q340. In some examples, the outputs of the read amplifiers are 220 configured with a three-state logic, where the output of the read amplifier 220 in addition to the logic levels 0 and 1 It can assume a state of high impedance. This allows the dedicated read amplifier output to be removed from the circuit until new data is available. In this way, the two read amplifier outputs can be connected without the additional delay that would be caused by another layer of multiplexers.

[0031] Fig. Figure 12 is a block diagram illustrating an EA procedure. 400 This illustrates the various embodiments disclosed herein. In the process block 410A matrix array of memory cells is provided, e.g., the one in Fig. 4 matrix fields shown 105 . In the block 412 will be an EA block 130 arranged so that it covers the matrix field 105 from memory cells into a first submatrix field 105a and a second submatrix field 105b subdivided, which are located on opposite sides of the EA block 130 are located in the block 414 bit lines 204 , which are connected to the memory cells of the first submatrix field 105a are connected, on a first page 131 of the EA block 130 received and in block 416 bit lines 204 , which are connected to the memory cells of the second submatrix field 105b are connected, on a second page 132 of the EA block 130 received. Thus, the EA block is 130 between the memory matrix fields 105a , 105barranged. Data signals are thus directly routed from the shortened bit lines, which lead to the centrally located control block. 130 extend, receive, and output directly to these devices, instead of requiring additional global bit lines to send the data signals to a global EA block. The EA block 130 It is operated in such a way that data is read from and written to the memory cells of the first and second submatrix fields, and the data is output via an input and output port. 104 , 102 of the centrally arranged EA block 130 are sent and received as in the block 418 depicted.

[0032] Several examples revealed herein thus provide a memory matrix array with shortened bit lines, which are received directly by an I / O block located between submatrix arrays of the memory matrix array. In this way, the shortened bit lines improve performance. Furthermore, because the centrally located I / O block is directly connected to the bit lines of the memory submatrix arrays, a global I / O block is not required, saving space on a macro scale and further improving performance.

[0033] According to some disclosed embodiments, a storage device, e.g., an SRAM memory, has a matrix array of memory cells comprising a first submatrix array and a second submatrix array. Several bit lines are connected to the memory cells, and an I / O block is arranged between the first and second submatrix arrays. The bit lines extend directly from the first and second memory submatrix arrays of the storage device to the I / O block. The I / O block further comprises a data input and output port configured to receive data to be written to the matrix array of memory cells and to output data read from the matrix array of memory cells via the several bit lines.

[0034] According to further examples, a memory I / O device comprises an I / O block that has a first side and a second side opposite the first side. The first side is configured to receive several bit lines from a first memory submatrix array, and the second side is configured to receive several bit lines from a second memory submatrix array. The I / O block has an output latch that is wired to receive data read from the first and second bit lines. A data input and output port are configured to receive data from and output data to the bit lines.

[0035] According to other examples, a memory I / O method involves providing a matrix array of memory cells. An I / O block is arranged to divide the matrix array of memory cells into a first sub-matrix array and a second sub-matrix array, which are located on opposite sides of the I / O block. Several bit lines, connected to the memory cells of the first sub-matrix array, are received on the first side of the I / O block, and several bit lines, connected to the memory cells of the second sub-matrix array, are received on the second side of the I / O block. The I / O block is operated to read data from and write data to the memory cells of the first and second sub-matrix arrays.

[0036] In this disclosure, various embodiments are outlined in such a way that the person skilled in the art can better understand the aspects of this disclosure. The person skilled in the art recognizes that they can simply use this disclosure as a basis for designing or modifying other methods and structures to achieve the same purposes and / or obtain the same advantages as in the embodiments presented here. The person skilled in the art also realizes that such equivalent constructions do not deviate from the idea and scope of this disclosure and that they can make various changes, substitutions, and modifications to them without deviating from the idea and scope of this disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 62647422

[0001]

Claims

[1] Storage device comprising: a matrix field of memory cells, wherein the matrix field comprises a first submatrix field and a second submatrix field; several bit lines which are connected to the memory cells; an I / O block which is arranged between the first submatrix field and the second submatrix field, wherein the bit lines from the first and second memory submatrix fields of the storage device extend directly to the I / O block, and wherein the I / O block includes a data input and output port which are configured to receive data to be written into the matrix field of memory cells and to output data read from the matrix field of memory cells via the multiple bit lines. [2] Storage device according to claim 1, further comprising an output latch which is connected in such a way that it receives data which is read from the multiple bit lines. [3] Storage device according to claim 1 or 2, wherein: the memory cells of the first and second submatrix fields are arranged in columns and rows; the bit lines extend parallel to the columns; and The EA block is arranged across the columns, perpendicular to the bit lines. [4] Storage device according to claim 2 or 3, further comprising: several word lines which are connected to the memory cells and extend parallel to the rows; and a serial decoder which is connected to the multiple word lines. [5] Storage device according to claim 4, wherein the matrix field further comprises a third submatrix field and a fourth submatrix field, wherein the first submatrix field and the third submatrix field are arranged on a first side of the EA block and the second submatrix field and the fourth submatrix field are arranged on a second side of the EA block opposite the first side, and wherein the first submatrix field and the second submatrix field are arranged on a first side of the serial decoder and the third submatrix field and the fourth submatrix field are arranged on a second side of the serial decoder. [6] Storage device according to one of the preceding claims, further comprising a first and second I / O block comprising the I / O block, wherein the first and second I / O blocks are arranged between the first and second submatrix fields and wherein the first I / O block is connected to the multiple bit lines of the first submatrix field and the second I / O block is connected to the multiple bit lines of the second submatrix field. [7] Storage device according to one of the preceding claims, wherein the EA block comprises a first and second output latch, wherein the first and second output latches are arranged between the first and second submatrix fields and wherein the first output latch is connected to the multiple bit lines of the first submatrix field and the second output latch is connected to the multiple bit lines of the second submatrix field. [8] Storage device according to one of the preceding claims, wherein the EA block comprises a write control which is connected to the multiple bit lines. [9] Storage device according to claim 6, wherein the first and second EA block comprise a first and second read amplifier respectively. [10] Storage device according to claim 9, wherein the first and second read amplifiers are configured with a three-state logic. [11] Memory input / output (I / O) device comprising: an EA block which has a first side and a second side opposite the first side, wherein the first side is configured to receive several bit lines from a first memory submatrix field, wherein the second side is configured to receive several bit lines from a second memory submatrix field; wherein the EA block has an output latch which is connected in such a way that it receives data from the first several and the second several bit lines; and wherein the EA block includes a data input and output port, which are configured to receive data from and output data to the first multiple bit lines and the second multiple bit lines. [12] Storage I / O device according to claim 11, further comprising a first and second I / O block which comprise the I / O block, wherein the first and second I / O blocks are arranged between the first and second submatrix fields and wherein the first I / O block comprises the first side of the I / O block and the second I / O block comprises the second side of the I / O block. [13] Storage I / O device according to claim 11 or 12, wherein the I / O block comprises a first and second output latch, which include the output latch, wherein the first and second output latch are arranged between the first and second submatrix field. [14] Storage device according to any one of the preceding claims 11 to 13, wherein the EA block comprises a write control. [15] Storage device according to any one of the preceding claims 11 to 14, wherein the EA block comprises a read amplifier. [16] Memory input / output (I / O) methods, comprising: Providing a matrix array of memory cells; Arranging an EA block such that it divides the matrix field of memory cells into a first submatrix field and a second submatrix field, which are arranged on opposite sides of the EA block; Receiving the first of several bit lines connected to the memory cells of the first submatrix field on a first page of the I / O block; Receiving the second of several bit lines, which are connected to the memory cells of the second submatrix field, on a second side of the I / O block; Operating the EA block in such a way that data is read from the memory cells of the first and second submatrix fields; and Operating the EA block in such a way that data is written into the memory cells of the first and second submatrix fields. [17] Method according to claim 16, further comprising storing an output signal by means of a common output latch which is configured to receive signals from the first and second bit lines. [18] Method according to claim 16 or 17, wherein the memory cells of the first and second submatrix field are arranged in columns and rows and wherein the bit lines extend parallel to the columns and wherein the method further comprises arranging the EA block transversely across the columns, perpendicular to the bit lines. [19] Method according to claim 18, further comprising arranging a series decoder parallel to the word lines such that a third submatrix field and a fourth submatrix field are formed on opposite sides of the series decoder. [20] Method according to any one of the preceding claims 16 to 19, wherein arranging the EA block in such a way that it divides the matrix field of memory cells into the first submatrix field and the second submatrix field comprises arranging a first and second EA block comprising the EA block in such a way that the matrix field of memory cells is divided into the first submatrix field and the second submatrix field.