System and method for compensating reference noise for unbalanced serial connections

Abstract

Unbalanced signal transmission system, including: a transmitter circuit configured to: Transmitting a reference signal on a first channel; and Transmitting an asymmetrical signal on a second channel; a receiver circuit configured to: Receiving the reference signal combined with initial noise on the first channel; Receiving the asymmetrical signal combined with second noise on the second channel; Sampling the reference signal combined with the first noise, to determine the first noise; and combining the first noise and the unbalanced signal combined with the second noise to reconstruct the unbalanced signal, the reference signal being a DC balanced signal.

Description

AREA OF INVENTION

[0001] The invention relates to high-speed data connections and in particular to systems and methods for compensating reference noise for unbalanced serial connections. BACKGROUND

[0002] In modern data processing systems, high-speed data links provide data transmission paths between central processing units (CPUs), graphics processing units (GPUs), memory modules, peripheral interfaces, network interfaces, and other system components. A high-speed data link can serialize a wide parallel data path into a smaller number of serial connections. High-speed data links typically implement differential signaling, which encodes a logical state for a data signal as a voltage difference between a pair of physical signals. A high-speed data link can include any number of data signals, each consisting of two physical signals to form a differential pair.While differential signaling is very insensitive to noise, two physical signals (wires, pins, bumps, etc.) are required for each data signal along the entire path from transmitter to receiver, which limits area and energy efficiency.

[0003] Single-ended (unbalanced) signaling encodes a data signal onto a single physical signal that includes an implicit reference, such as a local ground reference. A transmitting circuit can send a physical signal referenced to a local transmitting ground, while a receiving circuit can receive the physical signal as a voltage signal referenced to a local receiving ground. At the receiving circuit, the voltage signal may contain relative noise between the local transmitting ground and the local receiving ground, as well as noise coupled to the physical signal during transmission. At relevant high speeds, such noise can significantly impair signal integrity for many useful applications of high-speed single-ended signaling. US 2007 / 0046389 A1 discloses a signaling system between two circuits that generates a reference signal.There is a need to address these questions and / or other issues related to the state of the art and to reduce noise. SHORT DESCRIPTION

[0004] This need is met by the features of claim 1.

[0005] In one embodiment, the transmitter circuit is configured to transmit a reference signal on a first channel and an unbalanced signal on a second channel. Furthermore, the receiver circuit is configured to receive the reference signal combined with the first noise on the first channel, to receive the unbalanced signal combined with the second noise on the second channel, to sample the reference signal combined with the first noise to determine the first noise, and to combine the first noise and the unbalanced signal combined with the second noise to reconstruct the unbalanced signal.

[0006] A circuit and a system for asymmetric signal transmission are disclosed. The asymmetric signal transmission system, or system for transmitting asymmetric signals, comprises at least one instance of the transmitter circuit and at least one instance of the receiver circuit. The system may include a processing unit, such as a graphics processing unit (GPU). BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1A illustrates a transmitter circuit and a receiver circuit configured to provide a reference forwarding function, according to one embodiment; Fig. 1B is a flowchart of a method for transmitting data as an asymmetric signal according to an embodiment; Fig. Figure 1C illustrates a transmitter circuit and a receiver circuit configured to provide a reference forwarding with feedback correction, according to one embodiment; Fig. Figure 1D illustrates a transmitter circuit and a receiver circuit configured to provide compensation for reference noise embedded in a DC balanced signal, according to one embodiment; Fig. Figure 1E illustrates a transmitter circuit and a receiver circuit comprising a digital loop for compensating reference noise with individual track offset control, according to an exemplary embodiment; Fig. Figure 1F illustrates a digital signal generator circuit for compensating reference noise according to one embodiment; Fig. 1G is a flowchart of a method for transmitting data as an asymmetric signal according to an embodiment; Fig. Figure 2 illustrates an exemplary reference forwarding circuit according to one embodiment; Fig. Figure 3A illustrates a receiver output signal with and without reference forwarding according to an exemplary embodiment; Fig. 3B illustrates a receiver output diagram with and without reference forwarding according to an exemplary embodiment; Fig. Figure 4A illustrates a receiver output signal with and without digital control loop compensation using a reference track according to an exemplary embodiment; Fig. 4B illustrates a receiver output diagram with and without digital control loop compensation using a reference track according to an embodiment; Fig. Figure 5A illustrates a system comprising an integrated circuit and a transition link according to one embodiment; Fig. 5B illustrates a cross-section of an integrated circuit and a transition connection according to an exemplary embodiment; Fig. Figure 5C illustrates a system comprising a multi-chip module with an interposer connection configured to couple a first integrated circuit with a second integrated circuit, according to one embodiment; Fig. Figure 5D illustrates a cross-section of a multi-chip module and an interposer connection according to an exemplary embodiment; Fig. Figure 5E illustrates a printed circuit board (PCB) with a first integrated circuit configured to communicate with a second integrated circuit via a set of PCB traces, according to one embodiment; and Fig. Figure 6 illustrates an exemplary system in which the different architecture and / or functionality of the various previous embodiments may be implemented. DETAILED DESCRIPTION

[0007] Embodiments of the invention include a receiver circuit configured to compensate for noise introduced into an unbalanced (single-ended) signal transmitted along a channel to the receiver circuit. The channel can be provided by an electrically conductive path from a transmitter circuit to the receiver circuit. An unbalanced signal is transmitted from the transmitter circuit to the receiver circuit. In one practical setup, a noise signal is introduced into the unbalanced signal, causing the unbalanced signal to become noisy. In various embodiments, the introduced noise signal is extracted from the noisy unbalanced signal to generate a compensation signal (e.g., ground noise compensation), and the compensation signal is used to reduce noise (e.g.,to remove the noisy unbalanced signal (by subtraction) and restore (i.e. replicate) the originally transmitted unbalanced signal.

[0008] In one embodiment, a separate reference signal is transmitted over a dedicated channel along with one or more data tracks in a data bus. In such a configuration, a noise signal introduced into the data bus tracks and the reference signal can be essentially identical, so that the noise signal in the separate reference signal is representative of the noise in each data bus track. The noise signal can be extracted from the reference signal and used to generate the compensation signal for removing noise from the data bus signals. In one embodiment, the reference signal is a fixed voltage signal. In another embodiment, the reference signal is a clock signal. In yet another embodiment, an imbalance in a DC-balanced signal provides the compensation signal.In such an embodiment, no separate reference signal needs to be transmitted. A DC-balanced symmetrical signal transmits an equal number of logic highs and logic lows (i.e., ones and zeros) over time, so that the average signal level lies halfway between the logic high and the logic low. For example, a clock signal with a 50 / 50 duty cycle is a DC-balanced signal.

[0009] Several different embodiments are disclosed for sampling a transmitted reference signal and / or a DC-balanced signal to generate the compensation signal (or signals). A given compensation signal can be combined with a data bus signal to remove noise and restore the data signal to better represent an originally transmitted signal. Various embodiments advantageously allow a larger distance (or a lower amplitude for reduced power consumption) for an unbalanced signal to be transmitted from a transmitter circuit to a receiver circuit without incurring a bit error rate penalty compared to conventional solutions.

[0010] In certain scenarios, the noise signal has a frequency range lower than the clock frequency of the data signal(s). For example, the data signals might have a clock frequency above 10 GHz, while the noise signal may contain energy that primarily falls well below 1 GHz. As such, a given noise signal causes an incoming signal at the receiver circuit to have a potentially large superimposed envelope that tracks the noise signal. This can severely degrade the signal integrity of the data signals.

[0011] In the context of the following description, the term "signal" is not limited to a physical signal or waveform transmitted over a physical connection, such as a conductor or trace on a printed circuit board, a multi-chip substrate, or within an integrated circuit. In one embodiment, a signal may be embedded or encoded with a clock or data signal transmitted over a physical connection. For example, a compensation signal may be a voltage signal or a digital representation of a voltage signal.

[0012] Fig. Figure 1A illustrates a transmitter circuit 110 and a receiver circuit 130 configured to provide reference forwarding, according to an exemplary embodiment. As shown, a single-ended or unbalanced signal transmission system 100 comprises the transmitter circuit 110 coupled to the receiver circuit 130 via a set of connections 120. Each connection 120 can include a bond pad, a bond bump, a conductor wire (e.g., a printed circuit board trace), and any other technically feasible elements for electrically transmitting a signal from the transmitter circuit 110 to the receiver circuit 130.

[0013] As shown, input data signals Din0, Din1, Din2, and Din3 (a four-track data bus) are transmitted from the transmitter circuit 110 to the receiver circuit 130, which generates corresponding output data signals Dout0, Dout1, Dout2, and Dout3. The transmitter circuit 110 includes one or more output buffers 112 configured to drive an output signal voltage relative to a transmitter reference signal 118. A given output buffer 112 receives a data input signal (e.g., Din0, Din1, Din2, and Din3) and drives the logical state of the data input signal in the form of a transmitted data signal. Each transmitted data signal is passed via an associated connection 120 to an input buffer 132. The input buffer 132 reconstructs the data input signal to generate a data output signal (e.g., Dout0, Dout1, Dout2, and Dout3). The in Fig. The reference forwarding approach shown in 1A requires N+1 connections 120 for N data channels.

[0014] The transmitter reference signal 118 is generated by a reference circuit 116. In a simple implementation, the transmitter reference signal 118 is a local transmitter ground node or a local AC ground node. An output buffer 114 transmits the transmitter reference signal 118 to an input buffer 136 within the receiver circuit 130.

[0015] The input buffer 136 receives the reference signal 118 combined with a first noise associated with the transmission of the reference signal 118 to the input buffer 136 (reference noise). The receiver circuit 130 samples the reference signal 118 combined with the first noise as an output of the input buffer 136 to determine the first noise. Based on the sampling of the reference signal 118 combined with the first noise, the receiver circuit 130 generates a compensation signal 134 that can track the transmitter reference signal 118 together with the first noise. In one embodiment, the compensation signal 134 is an analog voltage signal.Because the introduced noise is generally uniform for each of the transmitted data signals and the transmitted reference signal, the compensation signal 134 can be used to remove the introduced noise from the transmitted data signals (a second noise) arriving at the receiver circuit 130 (e.g., by voltage subtraction). That is, the receiver circuit 130 combines the first noise and an unbalanced data signal, which is in turn combined with the second noise to reconstruct the unbalanced data signal. Any technically feasible circuit arrangement can be used to implement the various circuit elements of an unbalanced signal transmission system 100.

[0016] While the introduced noise is generally uniform, noise at a particular input buffer 136 is, strictly speaking, unique to that input buffer 136. As such, a noise signal passed from the output buffer 114 represents a first noise signal, while noise passed from any other output buffer 112 represents a correspondingly different noise signal (second noise). While the noise signals are not strictly equivalent, the first noise signal and each other noise signal are substantially correlated and sufficiently similar to be used as a representation of each other. Furthermore, the representation of the first noise can be in the form of an analog signal (e.g., a voltage), a differential analog signal, or a digital signal (e.g., a digital code).

[0017] Fig. 1B is a flowchart of a method 101 for transmitting data as an asymmetric signal according to an embodiment. Although the method 101 in conjunction with the systems of Fig. As described in Figures 1A, 5A-5D, and 6, any system implementing method 101 is within the scope of protection and the framework of the exemplary embodiments of the invention. In one exemplary embodiment, method 101 is implemented by a transmitter circuit, such as transmitter circuit 110. Fig. 1A, implemented. Data can be received from a receiver circuit, such as the data receiver circuit 130. Fig. 1A, to be received. In general, the transmitter circuit 110 is configured to drive a reference signal via a first channel, comprising a set of connections 120, and a data signal via a second channel for transmission to a receiver circuit 130. The receiver circuit 130 is configured to reconstruct the data signal based on the reference signal.

[0018] In step 141, the transmitter circuit 110 sends a reference signal on a first channel. In one embodiment, the reference signal is transmitted via an output buffer 114 over the first channel, which includes connection 120(A). In step 142, the transmitter circuit 110 sends an unbalanced signal on a second channel. In one embodiment, the unbalanced signal is transmitted via an output buffer 112(0) over the second channel, which includes connection 120(0).

[0019] In step 143, the receiver circuit 130 receives the reference signal combined with the first noise on the first channel. In step 144, the receiver circuit 130 receives the unbalanced signal combined with the second noise on the second channel. In step 145, the receiver circuit 130 samples the reference signal combined with the first noise to determine the first noise. In step 146, the receiver circuit 130 combines the first noise and the unbalanced signal combined with the second noise to reconstruct the unbalanced signal.

[0020] Fig. Figure 1C illustrates a transmitter circuit 110 and a receiver circuit 130 configured to provide reference forwarding with feedback correction, according to an exemplary embodiment. As shown, an unbalanced signal transmission system 102 comprises the transmitter circuit 110, which is coupled to the receiver circuit 130 via a set of links 120. In the unbalanced signal transmission system 102, the transmitter circuit 110 is, with respect to the unbalanced signal transmission system 100, Fig. 1A is modified. More precisely, the transmitter circuit 110 is modified to include the output buffer 115, which can comprise an instance of an output buffer 112. In one embodiment, the output buffer 115 can be configured in an off state, during which time no signal is transmitted. Although the output buffer 115 is off, it exhibits a similar impedance to connection 120 as output buffers 112(0)-112(3) each exhibit to connections 120(0)-120(3), thus maintaining the similarity of noise across all connections 120.

[0021] Furthermore, the receiver circuit 130 is modified to include input buffers 150 and 152 configured to receive a digital compensation signal 157, rather than input buffer 132 configured to receive the analog compensation signal 134. The digital compensation signal 157 provides a digital encoding of a noise compensation signal. In one embodiment, the encoding implements a "thermometer" code, also known in the prior art as a "unary" code. Such codes are robust against the bridging of asynchronous boundaries and produce noise-free value changes. The output of input buffer 152 is sampled by a sampler circuit 156 and filtered by a filter 158.

[0022] In one embodiment, the filter 158 is a low-pass filter (as shown). Furthermore, the filter 158 can include an integrator function, which may be implemented in either an analog or digital domain. In one embodiment, the filter 158 can provide a programmable cutoff frequency. For example, the filter 158 can provide a programmable cutoff frequency in the range of 50 MHz to 1 GHz. The output of the filter 158 is a digital representation of the noise introduced into the reference signal transmitted by the output buffer 115. The introduced noise and the transmitted noise include reference noise. The reference noise is processed before being combined with a second noise signal associated with the asymmetric data signals at the input buffers 150. In this example, the reference noise is processed according to a transfer function of the filter 158.Furthermore, the transfer function can be programmable.

[0023] A set of sampling circuits 154 is configured to synchronously acquire data at the outputs of the input buffers 150 in order to generate data output signals (e.g., Dout0, Dout1, Dout2, and Dout3). In one embodiment, the sampling circuits 154 are flip-flop circuits. In another embodiment, the sampling circuit 156 uses a clock that is uncorrelated with respect to the sampling circuits 154. For example, the sampling circuit 156 can operate with a clock whose frequency differs by about ten percent from the clock used by the sampling circuits 154.

[0024] In the absence of reference noise, the output of the input buffer 152, i.e., the voltage whose resolution by the sampler 156 should be metastable, should be zero; or, after metastability resolution, its output should result in an equal number of ones and zeros. In this scenario, the correction signal 157 is equal to or nearly equal to zero and thus makes no or almost no contribution to the buffers 150, and the connection operates as if the reference noise compensation were missing or disabled. In the presence of reference noise, the output of the input buffer 152 can be used as an error signal to drive a control loop comprising the input buffer 152, the sampler 156, and the filter 158.The control loop modulates the input buffer 152-frontend to reduce the error signal to zero, or more generally, to attenuate the error signal by the amount corresponding to the control gain, which can be made arbitrarily large over a frequency range. The same digital compensation signal 157 is distributed to all other input buffers 150, thereby compensating the input buffers 150 according to the reference noise signal. This control loop can be configured to have a high bandwidth and enable a wide noise reduction band.

[0025] In connections where some or all of the transmitted signals do not occupy part of the frequency spectrum, a more resource-efficient technique for communicating the transmitter reference signal 118 can be implemented. For example, in clock-passing systems, the clock signal has no significant energy below the fundamental frequency of the clock. Furthermore, in certain DC-balanced data coding systems, each data track must not contain any components below a fraction of the Nyquist rate. One example of such a coding system uses 8B / 10B per data track.

[0026] On the receiver side of such systems, data content can be filtered out (e.g., with a low-pass filter), and the remaining signal represents a noise signal that can be used for local data recovery. Extracting a given noise signal and a corresponding compensation signal can be performed for each data track if the data is DC-balanced. Alternatively, noise can be extracted from a reference signal (e.g., a clock signal), with the resulting compensation signal being used for the corresponding data tracks.

[0027] In this way, the reference noise can be traced to the bandwidth of the filter used for receiver reference extraction without additional channel or interconnect costs (e.g., pin / bump / wire). The spectrum of the signal from which the reference noise is extracted determines the achievable reference loop bandwidth and thus the performance of the reference noise suppression, because the higher the lower cutoff frequency of this signal, the greater the loop bandwidth can be. For this reason, using the clock track for reference noise extraction and distributing the error signal across data tracks is preferable to a per-track solution. Examples of using the clock track for reference noise extraction are found in the Fig. 1D and Fig. 1E is shown.

[0028] Fig. Figure 1D illustrates a transmitter circuit 110 and a receiver circuit 130 configured to provide compensation for reference noise embedded in a DC-balanced signal, according to an exemplary embodiment. As shown, an unbalanced signal transmission system 104 comprises the transmitter circuit 110, which is coupled to the receiver circuit 130 via a set of links 120. In the unbalanced signal transmission system 104, the transmitter circuit 110 is, with respect to the unbalanced signal transmission system 102, Fig. 1C is modified. More precisely, the output buffer 115 is enabled and configured to receive a reference signal (clock signal CLK). In one embodiment, the clock signal CLK is a source clock for a data bus comprising Din0, Din1, Din2, and Din3. It is noted that a periodic clock signal such as the clock signal CLK should be a DC-balanced signal (assuming a correctly set 50 / 50 duty cycle). More generally, in other embodiments, the output buffer 115 can be configured to transmit any DC-balanced signal.

[0029] Furthermore, the receiver circuit 130 is modified to include the filter 160, which is configured to generate the digital compensation signal 157 by filtering the output of the input buffer 152. In one embodiment, the filter 160 is a low-pass filter (as shown). The filter 160 may also include an integrator function, which can be implemented in either an analog or digital domain. The filter 160 may also include a circuit arrangement for increasing loop stability; for example, the filter 160 may include a circuit arrangement for generating a suitable zero-frequency response. In one embodiment, the filter 160 may provide a programmable cutoff frequency. For example, the filter 160 may provide a programmable cutoff frequency in the range of 50 MHz to 1 GHz. The output of the filter 160 is a digital representation of reference noise.Filter 160 should largely filter out (attenuate) the fundamental frequency and harmonics of a clock signal for the DC-balanced symmetrical signal (e.g., the clock signal CLK). In the context of the unbalanced signal transmission system 104, any DC imbalance (existing over a certain number of clock cycles) detected by filter 160 in what should be a DC-balanced signal is actually a reference noise signal (the difference between the transmitter reference and the receiver reference). A control loop formed by filter 160 and input buffer 152 can compensate for noise, as the noise signal is modified by restoring a DC imbalance to a balanced or symmetrical state. The digital compensation signal 157 generated by filter 160 is passed to input buffer 152 to close the control loop.Furthermore, the digital compensation signal 157 can be transmitted to the input buffers 150 to compensate for the noise signal at the input buffers 150.

[0030] In one embodiment, a clock buffer 162 is configured to receive the output of the input buffer 152 and generate a source clock 164 (passed-through clock). The source clock (e.g., with phase alignment) can be used as a clock for detection circuits 154.

[0031] Fig. Figure 1E illustrates a transmitter circuit 110 and a receiver circuit 130 with a digital reference noise compensation loop with individual track offset control according to an exemplary embodiment. As shown, an unbalanced signal transmission system 106 comprises the transmitter circuit 110, which is coupled to the receiver circuit 130 via a set of connections 120. In the unbalanced signal transmission system 106, the transmitter circuit 110 is derived from the unbalanced signal transmission system 104. Fig. 1C replicated. However, the receiver circuit 130 is modified with respect to the unbalanced signal transmission system 104. More precisely, the input buffer 152 is replaced by an input buffer 153, which is configured to provide a differential clock signal 172. The differential clock signal 172 is fed to a clock buffer 174, which generates a source clock 176. Furthermore, the differential clock signal 172 is fed to a digital reference noise compensation signal generator circuit 170, which is configured to generate a digital compensation signal 159 and a digital compensation signal 177 based on the differential clock signal 172. More precisely, the compensation signal generator circuit 170 detects a DC imbalance in the differential clock signal 172 and generates a corresponding error signal, which can be used as a compensation signal to compensate for the noise received by the input buffer 153.In one embodiment, the digital compensation signal 159 encodes a noise compensation signal that is transmitted to the input buffer 153 (similar to the digital compensation signal 157) to compensate for noise received by the input buffer 153. The digital compensation signal set 177 includes individual digital compensation signals for compensating different input buffers 150.

[0032] A control loop is formed by the input buffer 153 and the compensation signal generator circuit 170, with the digital compensation signal 159 closing the control loop. The control loop is configured to reduce a noise signal received by the input buffer 153 to zero using the digital compensation signal 159. Based on the digital compensation signal 159, individualized compensation signals are generated for the various input buffers 150. The individualized compensation signals together form the digital compensation signal set 177. The individualized compensation signals provide, without limitation, separately calibrated compensation for DC offsets of the various input buffers 150 prior to the normal connection process. Furthermore, the input buffers 150 may not respond identically and linearly with respect to the same compensation signal.Therefore, the individualized compensation signals enable further decoupling of different transfer functions of different input buffers 150 in order to better track the intended noise compensation effect of the control loop. In one embodiment, a DC offset and a nonlinearity associated with the input buffers 150 can be pre-characterized before normal operation.

[0033] Fig. Figure 1F illustrates a digital signal generator circuit for compensating reference noise 170 according to an exemplary embodiment. The compensation signal generator circuit 170 is configured to detect a DC imbalance in the differential clock signal 172 and generate a corresponding digital compensation signal 159 together with the digital compensation signal set 177. A low-pass differential buffer 180 receives the differential clock signal 172 and transmits a buffered version of the differential clock signal 172 to a read-amplifier-based flip-flop (SA FF) 182. The SA FF 182 should be clocked with an uncorrelated clock relative to the differential clock signal 172. As shown, an output of the SA FF 182 is used to clock a counter 184. The counter 184 provides a set of LSBs (Least Significant Bits) and a set of MSBs (Most Significant Bits).A large number of samples can be taken from the SA FF 182 at a suitable sampling frequency to obtain a scaled number of samples. One scaling technique involves discarding one or more LSBs from the counter. In any given sampling interval, the counter 184 can increment based on a total number of LSBs and MSBs up to a fixed number. If a noise signal exceeds the count for a sampling interval, the counter should reach a maximum value, and the control loop will respond accordingly; however, the control loop will be limited in its slew rate (e.g., bandwidth). In one embodiment, the counter 184 is an up / down counter, and the up / down direction is determined by the state of the differential clock signal 172. The output of the counter 184 is transferred to a set of lookup tables (LUTs) 186.Each LUT 186 can be configured to account for a DC offset and / or nonlinearity for an associated input buffer 150. Such a DC offset and / or nonlinearity can be characterized prior to normal operation. In this way, each LUT 186 implements a transfer function for a corresponding input buffer 150 or input buffer 153. In one embodiment, the LUTs 186 are programmable.

[0034] Conceptually, the output of each LUT 186 is coupled to the input of a binary thermometer converter (BinToTherm) 188. In one embodiment, the LUTs 186 and the BinToTherm converters 188 are implemented as separate circuits. In alternative embodiments, the function of the LUTs 186 and the BinToTherm converters 188 can be combined. In one embodiment, the thermometer code encodes at least sixteen levels.

[0035] While one implementation of the compensation signal generator circuit 170 is shown here, other implementations may be applicable in other embodiments. For example, a microcontroller or a programmable signal processor can be used to implement the compensation signal generator circuit 170. The programmable signal processor can provide programmable transfer functions. Furthermore, alternative logic can be implemented to detect a DC imbalance in the differential clock signal 172 and generate a corresponding digital compensation signal 159 and / or a digital compensation signal set 177.

[0036] Fig. Figure 1G is a flowchart of a method 107 for transmitting data as an asymmetric signal according to an embodiment. Although the method 107 in conjunction with the systems of Fig. As described in Figures 1C-1F, 5A-5D, and 6, any system implementing method 107 is within the scope and protection of the embodiments of the invention. In one embodiment, method 107 is implemented by a transmitter circuit, such as transmitter circuit 110 of the Fig. 1E-1F, implemented. Data can be received from a receiver circuit, such as the data receiver circuit 130 of the Fig. 1E-1F, are received. In general, the transmitter circuit 110 is configured to drive a reference signal via a first channel, comprising a set of connections 120, and a data signal via a second channel for transmission to a receiver circuit 130. The receiver circuit 130 is configured to reconstruct the data signal based on the reference signal.

[0037] In step 191, the transmitter circuit 110 transmits an asymmetrical DC balanced signal on a first channel. In one embodiment, the asymmetrical DC balanced signal includes a clock signal.

[0038] In step 192, the receiver circuit 130 receives the unbalanced DC-balanced signal combined with reference noise on the first channel. In step 193, the receiver circuit 130 samples the unbalanced DC-balanced signal combined with the reference noise to extract the reference noise. In step 193, the receiver circuit 130 combines the reference noise and the unbalanced DC-balanced signal combined with the reference noise to reconstruct the unbalanced DC-balanced signal.

[0039] Fig. Figure 2 illustrates an exemplary reference passthrough circuit 200 according to an embodiment. The reference passthrough circuit 200 represents an approach for implementing the input buffers 132 and 136 of Fig. 1A. The reference pass-through circuit 200 includes input buffers 210(0) to 210(n), which function similarly to input buffer 136 and input buffer 132, respectively. Input buffer 210(0) is configured to generate a differential output signal 212 based on the reference input signal RXref. Input buffer 210(0) also generates a pseudodifferential compensation signal comprising the signals refp and refn, corresponding to compensation signal 134. The pseudodifferential compensation signal represents an extracted noise signal from RXref. The pseudodifferential compensation signal is passed to input buffers 210(1) to 210(n) via a set of associated current mirrors.

[0040] Fig. Figure 3A illustrates a receiver output signal 300 with (lower waveform) and without (upper waveform) reference forwarding according to an exemplary embodiment. The waveforms represent simulated results of a Fig. Figure 1A shows the reference relay system. The simulation included a 75 mV 100 MHz noise signal, modeled as relative noise between a local transmitter circuit ground at transmitter circuit 110 and a local receiver circuit ground at receiver circuit 130. Without reference relay, the noise signal 310 is visible. With reference relay, however, the noise signal is largely eliminated.

[0041] Fig. Figure 3B illustrates a receiver output eye diagram 302 with reference propagation (right eye diagram) and without reference propagation (left eye diagram) according to an exemplary embodiment. While the output signal 300 of Fig. Figure 3A illustrates an overall noise envelope imprinted on a multitude of signal transitions along a linear timeline. Eye diagram 302 illustrates an accumulated effect of a multitude of signal transitions superimposed within the same time window. The bit rate shown here is 25 Gbps, with each bit time occupying 40 ps. As demonstrated, the eye diagram without reference forwarding offers little hope for reliable data transmission, whereas the eye diagram with reference forwarding is a very clean pattern for highly reliable data transmission.

[0042] Fig. Figure 4A illustrates a receiver output signal 400 with digital control loop compensation (lower waveform) and without digital control loop compensation (upper waveform) using a reference track according to an exemplary embodiment. The waveforms represent simulated results of a Fig. Figure 1C depicts the reference relay system. The simulation included a 75 mV 100 MHz noise signal, modeled as relative noise between a local transmitter circuit ground at transmitter circuit 110 and a local receiver circuit ground at receiver circuit 130. Without digital control loop compensation, the noise signal is clearly visible. However, with digital control loop compensation, the noise signal is attenuated.

[0043] Fig. Figure 4B illustrates a receiver output eye diagram 402 with digital control loop compensation (right eye diagram) and without digital control loop compensation (left eye diagram) using a reference track according to an embodiment.

[0044] While the output signal 400 of Fig. Figure 4A illustrates an overall noise envelope imprinted on a multitude of signal transitions along a linear timeline. Eye diagram 402 illustrates an accumulated effect of a multitude of signal transitions superimposed within the same time window. The bit rate shown here is 25 Gbps, with each bit time occupying 40 ps. As demonstrated, the eye diagram without digital loop compensation offers little hope for reliable data transmission, whereas the eye diagram with reference forwarding is a relatively clean pattern for reliable data transmission. The simulation uses a 3.125 GHz sampling clock, and the sampler output is used as a step-up / step-down input. A seventeen-state thermometer-coded output controls a coarse offset adjustment of the receiver with an LSB step of approximately 10 mV.

[0045] Fig. Figure 5A illustrates a system comprising an integrated circuit 510 and a transition link 524 according to an exemplary embodiment. As shown, the integrated circuit 510 includes circuit modules 520, 522, and 526, each of which is manufactured within a local area of ​​a single die in which the integrated circuit 510 is manufactured. The circuit module 520 can be an instance of the transmitter circuit 110 of the Fig. 1A, Fig. 1C, Fig. 1D or Fig. The circuit module 526 includes a connection 1E, which is coupled to the transfer connection 524. The circuit module 526 can include an instance of the receiver circuit 130, which is also coupled to the transfer connection 524. In one embodiment, the transfer connection 524 includes the connections 120 and is configured to transmit unbalanced signals from the transmitter circuit 110 to the receiver circuit 130. Certain circuit modules within the integrated circuit 510 can also include local connections, such as the local connection 542, which can implement any technically feasible signaling technique.

[0046] Fig. Figure 5B illustrates a cross-sectional view of an integrated circuit 510 and a transition connection 524 according to one embodiment. As shown, the integrated circuit 510 comprises a substrate 512, active circuit layers 514, and upper metal layers 516. In one embodiment, the upper metal layers 516 are configured to implement the transition connection 524. In alternative embodiments, any metal layers or any other conductive layers fabricated in association with the integrated circuit 510 can implement the transition connection 524. Active circuit layers 514 can include diffusion layers fabricated within the substrate 512, as well as layers fabricated on the surface of the substrate 512 (metal layers, polysilicon, dielectric layers, and other layers).In one embodiment, the transmitter circuit 110 and the receiver circuit 130 are arranged at opposite ends of the overpass connection 524.

[0047] Fig. Figure 5C illustrates a system comprising a multi-chip module 540 with an interposer link 544 configured to couple a first integrated circuit 550 with a second integrated circuit 560, according to one embodiment. The interposer link 544 can be made of two or more conductive layers (e.g., wires) of an interposer substrate 542. For example, the interposer link 544 can be made of two different metal layers of the interposer substrate 542. Each integrated circuit 550, 560, and the interposer substrate 542 can be made of a common material (e.g., silicon) or materials with substantially identical coefficients of thermal expansion.The multi-chip module 540 can further include a ball-grid array (BGA) package comprising a ceramic substrate, an organic substrate, a silicon substrate, an epoxy or plastic package, or any technically feasible combination thereof. In one embodiment, the interposer substrate 542 is coupled to the BGA package. Certain electrical signals can be coupled from the interposer substrate 542 to input / output pins on the BGA package.

[0048] The integrated circuit 550 includes circuit modules 552, and the integrated circuit 560 includes circuit modules 562. The circuit module 552(1) can include a first instance of the transmitter circuit 110 coupled to the interposer connection 544, and a second instance of the transmitter circuit 110 coupled to an interposer connection 546. Each instance of the transmitter circuit 110 can be coupled to a corresponding instance of the receiver circuit 130 via an interposer connection (e.g., the interposer connection 544, 546). Electrical connections between each integrated circuit 550, 560, and the interposer substrate 542 can be implemented as connectors or connections (C-4) for controlled collapsing chip connections (e.g., conductive spheres).The instances of the transmitter circuit 110, the instances of the receiver circuit 130 and the interposer connections 544, 546 together provide fast chip-to-chip data communication between the integrated circuit 550 and the integrated circuit 560.

[0049] Fig. Figure 5D illustrates a cross-section of the multi-chip module 540 and the interposer connection 544 according to an exemplary embodiment. The interposer substrate 542 can include a set of metal interconnect layers 543, including associated via layers for the metal layers. In one exemplary embodiment, the metal layers 543 are configured to implement an interposer connection 544 and / or an interposer connection 546.

[0050] Fig. Figure 5E illustrates a printed circuit board (PCB) 570 with a first integrated circuit 572 configured to communicate with a second integrated circuit 576 via a set of PCB traces 574, according to an exemplary embodiment. The PCB 570 is designed to include the set of PCB traces 574. The first integrated circuit 572 and the second integrated circuit 576 can be coupled (e.g., soldered, clipped) to the PCB 570, with pins or solder bumps forming electrical connections with the respective PCB traces 574. The integrated circuit 572 can include a first instance of the transmitter circuit 110 coupled to the PCB traces 574, and the integrated circuit 576 can include a first instance of the receiver circuit 130 coupled to corresponding PCB traces 574.In one embodiment, the PCB tracks 574 comprise connections 120, and the PCB tracks 574 are configured to transmit unbalanced signals from the transmitter circuit 110 to the receiver circuit 130. Integrated circuits 572, 576 can include a substrate. The substrate can comprise an organic package or a silicon interposer package, such as the interposer substrate 542 of [reference missing]. Fig. 5C-5D.

[0051] A circuit, a method, and a system embodiment are disclosed which, compared to known solutions, allow for a greater distance between an asymmetrical signal transmitted from a transmitter circuit and a receiver circuit. Such a greater distance can be a fundamental requirement for asymmetrical chip-to-chip signaling via PCB connections. Furthermore, a compromise between greater distance and reduced signal amplitude (to reduce power consumption) is provided.

[0052] Fig.Figure 6 illustrates an exemplary System 600 in which the various architectures and / or functionalities of the various previous embodiments can be implemented. As shown, a System 600 is provided that includes at least one central processor 601 connected to a communication bus 602. The communication bus 602 can be implemented using any suitable protocol, such as PCI (Peripheral Component Interconnect), PCI Express, AGP (Accelerated Graphics Port), HyperTransport, or any other bus or point-to-point communication protocol(s). The System 600 also includes a main memory 604. Control logic (software) and data are stored in the main memory 604, which can be implemented as random-access memory (RAM).

[0053] The system 600 further includes input devices 612, a graphics processor 606, and a display 608, i.e., a conventional CRT (cathode ray tube), LCD (liquid crystal display), LED (light-emitting diode), plasma display, or the like. User input can be received by the input devices 612, e.g., a keyboard, mouse, touchpad, microphone, and the like. In one embodiment, the graphics processor 606 can include a variety of shader modules, a rasterization module, etc. Each of the aforementioned modules can even be located on a single semiconductor platform to form a graphics processing unit (GPU).

[0054] In this description, a single semiconductor platform can refer to a single, unified semiconductor-based integrated circuit or chip. It should be noted that the term "single semiconductor platform" can also refer to multi-chip modules with enhanced connectivity that simulate on-chip operation and offer significant improvements over the use of a conventional central processing unit (CPU) and bus implementation. Naturally, the various modules can also be placed individually or in various combinations of semiconductor platforms, according to the user's requirements.

[0055] The System 600 can also include a Secondary Storage Unit 610. The Secondary Storage Unit 610 includes, for example, a hard disk drive and / or a removable storage drive, which can be a floppy disk drive, a magnetic tape drive, a compact disc drive, a digital versatile disk (DVD) drive, a recording device, or a flash memory for the Universal Serial Bus (USB). The removable storage drive reads from and / or writes to a removable storage device in a well-known manner.

[0056] Computer programs or logic algorithms of the computer control system can be stored in the main memory 604 and / or in the secondary memory 610. Such computer programs enable the System 600 to perform various functions when executed. Memory 604, memory 610, and / or any other memory are possible examples of computer-readable media.

[0057] In one embodiment, the architecture and / or functionality of the various preceding figures can be implemented in the context of the central processing unit 601, the graphics processing unit 606, an integrated circuit (not shown) capable of at least some of the capabilities of both the central processing unit 601 and the graphics processing unit 606, a chipset (i.e., a group of integrated circuits designed to operate as a unit for performing related functions and thus sold, etc.), and / or any other integrated circuit.

[0058] Furthermore, the architecture and / or functionality of the various preceding figures can be implemented in the context of a general-purpose computer system, a circuit board system, a game console system for entertainment purposes, an application-specific system, and / or any other desired system. For example, System 600 can take the form of a desktop computer, a laptop, a server, a workstation, game consoles, an embedded system, and / or some other type of logic. Additionally, System 600 can take the form of various other devices, including, but not limited to, a PDA (Personal Digital Assistant), a mobile phone, a television, and so on.

[0059] Furthermore, although not shown, the System 600 can be coupled to a network (e.g., a telecommunications network, a local area network (LAN), a wireless network, a wide area network (WAN) such as the Internet, a peer-to-peer network, a cable network, or the like) for communication purposes.

[0060] The exemplary System 600 can be configured to include one or more instances of the Unbalanced Signal Transmission System 100, the Unbalanced Signal Transmission System 102, the Unbalanced Signal Transmission System 104, or the Unbalanced Signal Transmission System 106. For example, the Graphics Processor 606 can include the one or more instances configured to provide chip-to-chip and / or module-to-module communication within the system.

Claims

[1] Unbalanced signal transmission system, comprising: a transmitter circuit configured to: Transmitting a reference signal on a first channel; and Transmitting an unbalanced signal on a second channel; a receiver circuit configured to: Receiving the reference signal combined with first noise on the first channel; Receiving the unbalanced signal combined with second noise on the second channel; Sampling the reference signal combined with the first noise, to determine the first noise; and combining the first noise and the unbalanced signal combined with the second noise to recover the unbalanced signal, wherein the reference signal is a DC balanced signal. [2] The unbalanced signal transmission system of claim 1, wherein the reference signal is a reference voltage level. [3] An unbalanced signal transmission system according to claim 1 or 2, wherein the reference signal is a clock signal. [4] An unbalanced signal transmission system according to any one of the preceding claims, wherein sampling comprises generating an analog signal representing the first noise. [5] An unbalanced signal transmission system according to any one of the preceding claims, wherein the sampling comprises generating a digital signal representing the first noise. [6] An unbalanced signal transmission system according to any one of the preceding claims, wherein the sampling comprises generating a difference signal representing the first noise. [7] An unbalanced signal transmission system according to any one of the preceding claims, wherein the sampling comprises sampling the reference signal combined with the first noise at a frequency that is not correlated with a switching frequency of the unbalanced signal. [8] An unbalanced signal transmission system according to any preceding claim, wherein the first noise is processed before being combined with the unbalanced signal combined with the second noise. [9] The unbalanced signal transmission system of claim 8, wherein a transfer function used to process the first noise is programmable. [10] An asymmetrical signal transmission system according to any one of the preceding claims, further comprising additional channels, wherein the transmitter circuit is further configured to transmit additional unbalanced signals on the additional channels, and the receiver circuit is further configured to: Receiving the additional unbalanced signals combined with additional noise on the additional channels; and Combining the first noise and each of the additional unbalanced signals combined with the additional noise to recover the additional unbalanced signals. [11] An unbalanced signal transmission system according to claim 10, wherein the first noise is processed before being combined with the additional unbalanced signals combined with the additional noise. [12] The single-ended signal transmission system of claim 11, wherein additional transfer functions used to process the first noise are programmable for each of the additional single-ended signals. [13] An unbalanced signal transmission system according to any one of the preceding claims, wherein the first channel is provided by a line. [14] An unbalanced signal transmission system according to any one of the preceding claims, wherein the reference signal is an unbalanced signal. [15] Method for reference noise compensation, comprising: Transmitting a reference signal on a first channel by a transmitter circuit; Transmitting an unbalanced signal on a second channel through the transmitter circuit; Receiving the reference signal combined with first noise on the first channel by a receiver circuit; Receiving the unbalanced signal combined with second noise on the second channel by the receiver circuit; Sampling the reference signal combined with the first noise by the receiver circuit to determine the first noise; and Combining the first noise and the unbalanced signal combined with the second noise to recover the unbalanced signal, wherein the reference signal is a DC balanced signal. [16] The method of claim 15, wherein the reference signal is a reference voltage level. [17] A method according to claim 15 or 16, wherein the reference signal is a clock signal. [18] The method of any one of claims 15 to 17, wherein sampling comprises sampling the reference signal combined with the first noise at a frequency that is not correlated with a switching frequency of the single-ended signal. [19] A method according to any one of claims 15 to 18, wherein the first noise is processed before being combined with the unbalanced signal combined with the second noise.

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