Controlgate strap layout to improve a word-lead etching process window

Abstract

Integrated chip with: a storage matrix (500A) with a plurality of cells (502, 504) in a plurality of rows (R) and a plurality of columns (C), wherein the plurality of rows includes a first row (Rm); a delete gate (106a) and a first word line (108a) running along the first row of the memory matrix (500A); and a first control gate (102a) running along the first line, wherein the first control gate is located between and adjacent to the delete gate (106a) and the first word line (108a), and the first control gate has a first pad area (104A) extending towards the delete gate and the first word line, wherein the first word line (108a) adapts to the first pad area (104a) in such a way that it encloses parts of the first pad area (104a).

Description

Background of the invention

[0001] Numerous modern electronic devices contain flash memory. Flash memory is a non-volatile electronic storage medium that can be electrically erased and reprogrammed. To store information, flash memory has an addressable array of memory cells, usually consisting of floating-gate transistors. Common types of flash memory cells are stacked-gate flash memory cells and split-gate flash memory cells, such as a third-generation SUPERFLASH (ESF3) memory cell. Split-gate flash memory cells have lower power consumption, higher injection performance, less susceptibility to short-channel effects, and better over-erase immunity than stacked-gate flash memory cells.

[0002] US 2009 / 0 098 721 A1 relates to a method for producing a flash memory, comprising providing a semiconductor substrate having a plurality of shallow trench isolations (STIs), wherein a region between two adjacent STIs along a first direction is defined as an active region.

[0003] US 2016 / 0 163 876 A1 relates to a semiconductor device structure comprising a semiconductor substrate, a first gate stack above the semiconductor substrate, a second gate stack above the semiconductor substrate and an erase gate between the first gate stack and the second gate stack.

[0004] The patent US 8 513 728 B2 relates to an array of non-volatile memory cells. Short description of the drawings

[0005] Aspects of the present invention can best be understood from the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various elements are not drawn to scale. Rather, for the sake of clarity of discussion, the dimensions of various elements may be exaggerated or reduced as desired. The Fig. 1A and Fig. 1B show various illustrations of embodiments of an integrated chip having control gates with pad regions protruding on wordline sides of the control gates and on erase gate sides of the control gates. Fig. 2 is a plan view of some embodiments of the integrated chip of the Fig. 1A and Fig. 1B, in which a component area is shown. The Fig. 3A to 3C show top views of some alternative embodiments of the integrated chip of Fig. 2, in which the pad areas are modified. The Fig. 4A and Fig. 4B show sectional views of some alternative embodiments of the integrated chip of the Fig. 1A and Fig. 1B, in which an insulation structure is modified. The Fig. 5A and Fig. 5B show top views of some embodiments of an integrated chip with a memory array in which control gates have pad regions protruding on wordline sides of the control gates and on erase gate sides of the control gates. Fig. Figure 6 shows a top view of some embodiments of the integrated chip of the Fig. 5A and Fig. 5B, in which a plurality of wires and a plurality of vias connect the pad areas to each other. Fig. Figure 7 shows a sectional view of some embodiments of the integrated chip of the Fig. 5A, Fig. 5B and Fig. 6 in a strap cell. The Fig. 8 to 20 show a series of cross-sectional views of some embodiments of a method for manufacturing an integrated chip having control gates with pad regions protruding on wordline sides of the control gates and on erase gate sides of the control gates. Fig. 21 shows a block diagram of some embodiments of the method of Fig. 8 to 20. Detailed description

[0006] The present invention provides many different embodiments or examples for implementing various features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. For example, the fabrication of a first element over or on top of a second element in the description below may include embodiments in which the first and second elements are fabricated in direct contact, and may also include embodiments in which additional elements may be fabricated between the first and second elements such that the first and second elements are not in direct contact. Furthermore, in the present invention, reference numerals and / or letters may be repeated in the various examples.This repetition is for simplicity and clarity and does not, in itself, prescribe any relationship between the various embodiments and / or configurations discussed.

[0007] Furthermore, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein to conveniently describe the relationship of one element or structure to one or more other elements or structures illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation, in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relative descriptors used herein may be interpreted accordingly.

[0008] For example, a memory array may include a first control gate and a second control gate; a first word line and a second word line; and a source / drain region. The first and second word lines are disposed between and adjacent to the first and second control gates, respectively, and the source / drain region is disposed between and adjacent to the first and second word lines. The first and second control gates, as well as the first and second word lines, run along respective rows of the memory array and extend across multiple columns of the memory array. Furthermore, the first and second control gates include a plurality of first pad regions and a plurality of second pad regions, respectively. The first pad regions protrude through the first word line from only one side of the first control gate, and the second pad regions protrude through the second word line from only one side of the second control gate.In addition, the first pad regions are offset from the second pad regions along the rows. One problem with the memory matrix is ​​that the distance between the first and second control gates in the first and second pad regions is small. This small distance, in turn, causes problems when manufacturing the first and second word lines.

[0009] When forming the first and second word lines, a conductive layer is formed to cover a gap between the first and second control gates and to include a recess between the first and second control gates. A hard mask layer is also formed to cover the conductive layer. The hard mask layer is patterned with a layout of the first and second word lines, and an etch is performed into the conductive layer when the hard mask layer is in place. One challenge is that the recess has a narrow width in the first and second pad regions due to the small distance between the first and second control gates. As a result, the hard mask layer fuses in the recess and therefore has a greater thickness.The increased thickness prevents the layout from being precisely transferred to the hard mask layer and thus to the conductive layer, thus reducing the process window (e.g., compliance) of the etch and reducing the mass production yield. For example, etch residues from the etch can define a creepage path between the first and second word lines. As another example, the first and second word lines can be formed with non-uniform widths (e.g., tapered widths) from top to bottom. These non-uniform widths can alter the operating parameters of components in the memory array and lead to component failures.

[0010] Various embodiments of the present application are directed to a control gate layout for improving an etch process window for word lines. In some embodiments, an integrated chip includes a memory array, an erase gate, a word line, and a control gate. The memory array includes a plurality of cells in a plurality of rows and a plurality of columns, and the plurality of rows includes a row. The erase gate and the word line run parallel along the row of the memory array. The control gate runs along the row and is disposed between and adjacent to the erase gate and the word line. Furthermore, the control gate includes a pad region projecting toward the erase gate and the word line.

[0011] Since the pad region protrudes toward the erase gate and the word line, a width of the pad region extends between the erase gate side and the word line side of the control gate. Due to this, the distance between the control gate and an adjacent control gate on the word line side in the pad region can be large. Furthermore, hard mask fusion during formation of the word line and other word lines can be avoided. Since hard mask fusion can be avoided, the mass production yield can be increased. For example, the probability that an etch residue defines creepage paths between adjacent word lines can be reduced, and thus an etch process window (e.g., compliance) for the word lines can be increased. As another example, sidewall profiles of the word lines can be vertical or substantially vertical.The vertical or substantially vertical sidewall profiles can, in turn, reduce the likelihood of changes in the operating parameters of components in the memory array and reduce the risk of component failure.

[0012] In Fig. 1A shows a top view 100A of some embodiments of an integrated chip having a first control gate 102a and a second control gate 102b, in which the first and second control gates 102a and 102b include a first pad region 104a and a second pad region 104b, respectively. The first pad region 104a projects from an erase gate side of the first control gate 102a to a first erase gate 106a and also projects from a wordline side of the first control gate 102a to a first wordline 108a. The second pad region 104b projects from an erase gate side of the second control gate 102b to a second erase gate 106b and also projects from a wordline side of the second control gate 102b to a second wordline 108b.

[0013] The first and second control gates 102a and 102b, the first and second erase gates 106a and 106b, and the first and second word lines 108a and 108b run parallel along a first direction (e.g., the x-direction), and the first and second pad regions 104a and 104b are offset from each other in the first direction. Furthermore, the first and second control gates 102a and 102b, the first and second erase gates 106a and 106b, and the first and second word lines 108a and 108b are spaced apart from each other in a second direction (e.g., the y-direction) that is transverse to the first direction. The first and second control gates 102a and 102b are respectively disposed between and adjacent to the first and second erase gates 106a and 106b, and the first and second word lines 108a and 108b are respectively disposed between and adjacent to the first and second control gates 102a and 102b.The first and second control gates 102a and 102b, the first and second erase gates 106a and 106b, and the first and second word lines 108a and 108b, or a combination thereof, may comprise, for example, doped polysilicon and / or one or more other suitable conductive materials.

[0014] Since the first and second pad regions 104a and 104b protrude from the erase gate sides and the word line sides, the first and second pad regions 104a and 104b have respective pad widths W p , which extend between the erase gate sides and the word line sides. It should be noted that only one of the pad widths W p with W p Since the pad widths W pextending between the erase gate sides and the word line sides, a distance S between the first and second control gates 102a and 102b at the first and second pad regions 104a and 104b is large. Due to the large distance S, hard mask fusion is avoided during formation of the first and second word lines 108a and 108b. For example, during formation of the first and second word lines 108a and 108b, a conductive layer may be deposited to cover the gap between the first and second control gates 102a and 102b and to have a recess between the first and second control gates 102a and 102b. In addition, a hard mask layer may be deposited to cover the conductive layer. Due to the large distance S, the recess may be so large that the hard mask layer does not fuse in the recess.In addition, a thickness of the hard mask layer from the first control gate 102a to the second control gate 102b may be constant or substantially constant.

[0015] Since hard mask fusion is avoided, an etch for forming the first and second word lines 108a and 108b can have a large process window (e.g., high compliance). Sticking with the previous example, in which a word line structure can be created in the hard mask layer, and the etching can be performed into the conductive layer when the hard mask layer is in the correct location, the word line structure can be precisely created in the hard mask layer and precisely transferred from the hard mask layer to the conductive layer. This minimizes the likelihood of an etch residue defining creepage paths between the first and second word lines 108a and 108b, and thus, the process window (e.g., compliance) of the etch is large. Furthermore, the mass production yield is high.

[0016] In some embodiments, the distance S is greater than about 0.30, 0.35, or 0.39 µm, it is about 0.3 to 0.5 µm, about 0.3 to 0.4 µm, or about 0.4 to 0.5 µm, or it has another suitable value. If the distance S is too small (e.g., less than 0.3 µm or the like), the hard mask fusion discussed above may occur. If the distance S is too large (e.g., greater than about 0.5 µm or the like), a distance between devices along the first control gate 102a and devices along the second control gate 102b is large, and chip area is wasted.

[0017] The first and second pad regions 104a and 104b protrude toward the first and second word lines 108a and 108b by a respective first amount P1 and protrude away from the first and second word lines 108a and 108b by a respective second amount P2. Note that only one of the first amounts P1 is denoted by P1 and only one of the second amounts P2 is denoted by P2. In some embodiments, the first amounts P1 are the same and / or the second amounts P2 are the same. In some embodiments, the first amounts P1 are different and / or the second amounts P2 are different. In some embodiments, the first and second amounts P1 and P2 are the same for the first pad region 104a and / or the first and second amounts P1 and P2 are the same for the second pad region 104b.In some embodiments, the first and second amounts P1 and P2 are different for the first pad region 104a and / or the first and second amounts P1 and P2 are different for the second pad region 104b. In some embodiments, the first and second pad regions 104a and 104b are square, rectangular, or circular, or have another suitable shape. In some embodiments, the first and second pad regions 104a and 104b have the same shape and / or size. In some embodiments, the first and second pad regions 104a and 104b have different shapes and / or sizes.

[0018] The first and second control gates 102a and 102b have respective control gate widths W cg to sides of the first and second pad areas 104a and 104b. It should be noted that only one of the control gate widths W cg with W cg In some embodiments, the control gate widths Wcg constant or substantially constant, and / or the pad widths W p are constant or substantially constant. In some embodiments, the control gate widths W cg the same size, and / or the pad widths W p are equal. In some embodiments, the control gate widths W cg different, and / or the pad widths W p are different. In some embodiments, the first and second control gates 102a and 102b are symmetric about respective axes that define the control gate widths W cg evenly bisecting and along which the first and second control gates 102a and 102b extend. In other embodiments, the first control gate 102a is asymmetric about a respective one of the axes, and / or the second control gate 102b is asymmetric about a respective one of the axes.

[0019] The first and second erase gates 106a and 106b have respective erase gate widths Weg up to sides of the first and second pad areas 104a and 104b, and the first and second word lines 108a and 108b have respective word line widths W wl to sides of the first and second pad areas 104a and 104b. It should be noted that only one of the erase gate widths W eg with W eg and only one of the word line widths W wl with W wl In some embodiments, the erase gate widths W eg and / or the word line widths W wl constant or substantially constant. In some embodiments, the wordline widths W wl equal size, and / or the erase gate widths W eg are equal. In some embodiments, the wordline widths W wl different, and / or the erase gate widths W egare different. In some embodiments, the first and second erase gates 106a and 106b are recessed at the first and second pad regions 104a and 104b, respectively, and / or they mate with the first and second pad regions 104a and 104b, respectively. In some embodiments, the first and second word lines 108a and 108b are recessed at the first and second pad regions 104a and 104b, respectively, and / or they mate with the first and second pad regions 104a and 104b, respectively.

[0020] A plurality of vias 110 are arranged on the first and second control gates 102a and 102b and on the first and second wordlines 108a and 108b. Note that only one of the vias 110 is labeled 110. The vias 110 are conductive and may, for example, comprise tungsten or another suitable conductive material. In some embodiments, the vias 110 electrically connect the first and second control gates 102a and 102b to respective control gate straplines (not shown), and / or they electrically connect the first and second wordlines 108a and 108b to respective wordline straplines (not shown). Thus, the first control gate 102a and / or the first word line 108a may correspond, for example, to a first strap cell, while the second control gate 102b and / or the second word line 108b may correspond, for example, to a second strap cell.

[0021] The control gate and wordline straplines run parallel to the first and second control gates 102a and 102b and the first and second wordlines 108a and 108b. Furthermore, the control gate straplines are or comprise a material with a lower resistance than that of the first and second control gates 102a and 102b, and the wordline straplines are or comprise a material with a lower resistance than that of the first and second wordlines 108a and 108b. In some embodiments, the first and second control gates 102a and 102b and / or the first and second wordlines 108a and 108b are or comprise doped polysilicon, while the control gate straplines and / or the wordline straplines are or comprise a metal. However, other materials are also possible.By electrically connecting the control gate and word line strap lines to the first and second control gates 102a and 102b and the first and second word lines 108a and 108b, respectively, voltage drops along the first and second control gates 102a and 102b and the first and second word lines 108a and 108b are reduced due to the lower resistances.

[0022] In Fig. 1B is a sectional view 100B of some embodiments of the integrated chip of Fig. 1A. The sectional view 100B can be taken, for example, along the line A of Fig. 1A. The first and second control gates 102a and 102b and the first and second word lines 108a and 108b are covered by a word line hard mask layer 112 and a dielectric interconnect layer 114. The word line hard mask layer 112 may, for example, be or include silicon oxide and / or one or more other suitable dielectrics, and / or the dielectric interconnect layer 114 may, for example, be or include a low-k dielectric and / or one or more other suitable dielectrics. Furthermore, the first and second control gates 102a and 102b and the first and second word lines 108a and 108b are arranged above a substrate 116 and an isolation structure 118.

[0023] The isolation structure 118 protrudes into a top side of the substrate 116 to define a device region 116d of the substrate 116, and a source / drain region 120a is located in the device region 116d, between the first and second word lines 108a and 108b. The device region 116d may, for example, have a top view that is the negative of a top view of the isolation structure 118, such that the device region 116d may, for example, correspond to upper parts of the substrate 116 up to sides of the isolation structure 118. The isolation structure 118 may, for example, be or include silicon oxide and / or one or more other suitable dielectrics and / or may, for example, be or include an STI (shallow trench isolation) structure or another suitable isolation structure. The substrate 116 may, for example, be a bulk silicon substrate or another semiconductor substrate.

[0024] As explained above, the distance S between the first and second control gates 102a and 102b is large at the first and second pad regions 104a and 104b. It should be noted that the second pad region 104b in Fig. 1B is not shown, but in Fig. 1A. Since the distance S is large, hard mask fusion in the word line hard mask layer 112 is avoided during the formation of the first and second word lines 108a and 108b. Since the hard mask fusion is avoided, a word line pattern can be accurately formed in the word line hard mask layer 112. Furthermore, the word line pattern can be accurately transferred from the word line hard mask layer 112 to a conductive layer by etching to form the first and second word lines 108a and 108b. Thereby, the first and second word lines 108a and 108b may have substantially vertical sidewall profiles SW at the source / drain region 120a.The substantially vertical sidewall profiles SW may increase the uniformity along and / or between the first and second word lines 108a and 108b and may also increase the uniformity of operating parameters for devices partially defined by the first and second word lines 108a and 108b. The increased uniformity of operating parameters may reduce the likelihood of device failure and may therefore increase the yield of mass production.

[0025] The first and second control gates 102a and 102b are also disposed over respective floating gates 122 and are covered by respective control gate hard masks 124. The floating gates 122 are spaced from the substrate 116 by respective floating gate dielectric layers 126 and are spaced from the first and second control gates 102a and 102b by respective control gate dielectric layers 128. Note that only one of the floating gate dielectric layers 126 is labeled 126 and only one of the control gate dielectric layers 128 is labeled 128. The floating gates 122 may be or include, for example, doped polysilicon and / or one or more other suitable conductive materials. The floating gate dielectric layers 126 may be or include, for example, silicon oxide and / or one or more other suitable dielectrics.The control gate hard masks 124 and / or the control gate dielectric layers 128 may be or include, for example, silicon oxide, silicon nitride, one or more other suitable dielectrics, or a combination thereof.

[0026] The first and second control gates 102a and 102b are covered by respective control gate sidewall spacers 130. In addition, the first and second erase gates 106a and 106b (not shown; see Fig. 1A) are covered by respective erase gate dielectric layers 132, and the first and second word lines 108a and 108b are covered by respective word line dielectric layers 134. Note that only one of the word line dielectric layers 134 is labeled. The erase gate dielectric layers 132 separate the first and second erase gates 106a and 106b from the floating gates 122, the control gate sidewall spacers 130, and the substrate 116. The word line dielectric layers 134 separate the first and second word lines 108a and 108b from the substrate 116, the isolation structure 118, and the control gate sidewall spacers 130. The control gate sidewall spacers 130 may be or include, for example, silicon oxide, silicon nitride, one or more other suitable dielectrics, or a combination thereof.The erase gate dielectric layers 132 and / or the word line dielectric layers 134 may be or include, for example, silicon oxide or one or more other suitable dielectrics.

[0027] In Fig. 2 is a more detailed top view 200 of some embodiments of the integrated chip of Fig. 1A, in which the device region 116d is shown. The device region 116d is a region of a substrate that is active during operation of the integrated chip. The device region 116d may, for example, be active in that it is depleted and / or enriched during operation of the integrated chip, and / or it may, for example, be active in that current flows through the device region 116d during operation of the integrated chip. The device region 116d is surrounded by the isolation structure 118 (see Fig. 1B) and may, for example, have a layout that is the negative of a layout of the isolation structure 118. Thus, the isolation structure 118 may, for example, be located where or substantially where the device region 116d is not located.

[0028] In Fig. 3A is a top view 300A of some alternative embodiments of the integrated chip of Fig. 2, in which the first and second pad regions 104a and 104b are circular. However, other suitable shapes are also possible.

[0029] In Fig. 3B is a top view 300B of some alternative embodiments of the integrated chip of Fig. 2, in which the first and second pad regions 104a and 104b protrude further away from the first and second word lines 108b than toward the first and second word lines 108a and 108b. Therefore, the first and second control gates 102a and 102b are asymmetric about respective axes defining the control gate widths W cg evenly bisecting and along which the first and second control gates 102a and 102b extend. In alternative embodiments, the first and second pad regions 104a and 104b may extend further toward the first and second word lines 108b than away from the first and second word lines 108a and 108b.

[0030] In Fig. 3C is a top view 300C of some alternative embodiments of the integrated chip of Fig. 2, in which the first and second control gates 102a and 102b have different layouts at the first and second pad regions 104a and 104b. The first pad region 104a protrudes further away from the first and second word lines 108a and 108b than toward the first and second word lines 108a and 108b, while the second pad region 104b protrudes the same amount away from and toward the first word line 108a and the second word line 108b. In some embodiments, the first pad region 104a is asymmetric about an axis defining the control gate width W cg of the first control gate 102a is evenly halved, while the second pad region 104b is symmetrical about an axis defining the control gate width W cg of the second control gate 102b is evenly halved. In alternative embodiments, the first and second pad regions 104a and 104b may have other shapes, other sizes, other orientations, or a combination thereof.

[0031] In Fig. 4A is a sectional view 400A of some alternative embodiment of the integrated chip of Fig. 1B, in which a top surface of the isolation structure 118 is recessed below the top surfaces of the floating gates 122. As a result, the first and second control gates 102a and 102b are recessed at the isolation structure 118. Furthermore, portions of the isolation structure 118 located below the first and second word lines 108a and 108b are recessed below a top surface of the substrate 116. As a result, the first and second word lines 108a and 108b protrude downward at these recessed portions of the isolation structure 118.

[0032] In Fig. 4B is a sectional view 400B of some alternative embodiments of the integrated chip of Fig. 1B, in which the floating gates 122 are arranged above the isolation structure 118.

[0033] In Fig. 5A shows a top view 500A of some embodiments of an integrated chip with a memory array, in which the memory array includes control gates 102 with pad regions 104 extending from the wordline sides of the control gates 102 and from the erase gate sides of the control gates 102. Note that only some of the pad regions 104 are labeled 104. The memory array further includes erase gates 106 and wordlines 108 adjacent to the control gates 102.

[0034] The control gates 102, the erase gates 106, and the word lines 108 partially define a plurality of strap cells 502 and a plurality of memory cells 504. Note that only some of the memory cells 504 are labeled 504. The strap cells 502 and the memory cells 504 are arranged in a plurality of rows and a plurality of columns, and the strap cells 502 extend across two rows. For clarity, the rows are labeled Rm , R m+1 , R m+2 or R m+3 and the columns are labeled C x , C x+1 , C x+2 , C y-1 or C y The indices of the row labels indicate corresponding row numbers, and the indices of the column labels indicate corresponding column numbers, where m is an integer representing a row number in the memory matrix, and x and y are integers representing column numbers in the memory matrix.

[0035] The control gates 102, the erase gates 106 and the word lines 108 run along the rows (e.g. R m to R m+3 ) and are arranged along the columns (e.g. C x to C y ) spaced apart. In addition, the pad regions 104 are repeated along the control gates 102 on the strap cell 502. In some embodiments, the pad regions 104 are in the rows R m and R m+2in each case as the second pad area 104b in the Fig. 1A and Fig. 1B, and / or the pad areas 104 in the rows R m+1 and R m+3 are each as the first pad area 104a in the Fig. 1A and Fig. 1B. In alternative embodiments, the pad areas 104 in rows R m and R m+2 in each case as the second pad area 104b in one of the Fig. 3A to 3C, and / or the pad areas 104 in the rows R m+1 and R m+3 are each as the first pad area 104a in each of the Fig. 3A to 3C, 4A and 4B. In some embodiments, a portion of the memory array in column C x and the lines R m+1 and R m+2 as he did in the Fig. 1A and Fig. 1B, and part of the memory matrix in column C y and the lines R m+1 and R m+2 is as he is in the Fig. 1A and Fig. 1B is shown and described. For example, Fig. 1B along line A. In alternative embodiments, part of the memory matrix in column C x and the lines R m+1 and R m+2 as he does in each of the Fig. 2, 3A to 3C, 4A and 4B, and / or a part of the memory matrix in column C y and the lines R m+1 and R m+2 is as he is in each of the Fig. 2, 3A to 3C, 4A and 4B. For example, the Fig. 4A and Fig. 4B should be created along line A.

[0036] A plurality of vias 110 are arranged on the control gates 102 and the word lines 108 in the strap cells 502. Note that only one of the vias 110 is labeled, and that the vias in the pad regions 104 may also be referred to as pad vias 110. The vias 110 electrically connect the control gates 102 and the word lines 108 to strap lines (not shown), respectively. The strap lines run parallel to the control gates 102 and the word lines 108 and have lower resistances than the control gates 102 and the word lines 108. By electrically connecting, or "strapping," the strap lines to the control gates 102 and the word lines 108, voltage drops along the control gates 102 and the word lines 108 are reduced and power efficiency is improved.

[0037] In Fig. 5B is a more detailed top view 500B of some embodiments of the integrated chip of Fig. 5A, which also shows a device region 116d. Note that only some segments of the device region 116d are labeled 116d. The device region 116d is a region of a substrate that is active during operation of the integrated chip. As explained above, the device region 116d is bounded by an isolation structure (not shown) and may, for example, have a layout that is the negative of a layout of the isolation structure.

[0038] In Fig. 6 is a top view 600 of some embodiments of the integrated chip of the Fig. 5A and Fig. 5B, in which a plurality of wires (e.g., 602, 604, and 606) and a plurality of vias (e.g., 110p, 608, and 610) interconnect the pad regions 104 of the control gates 102. Note that only wires and vias interconnecting the pad regions 104 are shown, but additional wires and / or vias may be present in the integrated chip. The wires and / or vias have resistances that are lower than those of the control gates 102 and electrically connect each pad region to every other pad region in a corresponding row. This reduces resistances and thus voltage drops across the control gates 102, thereby improving power efficiency. In some embodiments, the wires and / or vias are or comprise a metal, while the control gates 102 are or comprise doped polysilicon.However, other materials can also be used.

[0039] The wires and vias are grouped by elevation above a substrate (not shown), and each elevation is represented by a different hatching (e.g., for wires) and / or a different shape (e.g., for vias). The plurality of wires includes a plurality of first-level pad wires 602, a plurality of second-level pad wires 604, and a plurality of third-level pad wires 606. Note that only some of the first-level pad wires 602 are labeled, only some of the second-level pad wires 604 are labeled, and only some of the third-level pad wires 606 are labeled. Additionally, the plurality of vias includes a plurality of pad vias 110p (also known as zero-level pad vias), a plurality of first-level pad vias 608, and a plurality of second-level pad vias 610.Note that only some of the pad vias 110p are labeled, only some of the first-level pad vias 608 are labeled, and only some of the second-level pad vias 610 are labeled. Furthermore, note that the vias 110 are located in the pad areas 104 of the . Fig. 5A and Fig. 5B correspond to the pad vias 110p.

[0040] The first-level pad wires 602 and the pad vias 110p are different for the pad regions 104, and the pad vias 110p electrically connect the first-level pad wires 602 to the pad regions 104. The second-level pad wires 604 and the first-level pad vias 608 are different for the pad regions 104, and the first-level pad vias 608 electrically connect the second-level pad wires 604 to the first-level pad wires 602. The third-level pad wires 606 are for the rows (e.g., R m to R m+3) of the memory array and run along the rows. Furthermore, the third-level pad wires 606 may also be referred to as control gate strap lines (discussed above). The second-level pad vias 610 are different for the pad regions 104 and electrically connect the third-level pad wires 606 to the second-level pad wires 604.

[0041] In Fig. Figure 7 is a sectional view 700 of some embodiments of the integrated chip of the Fig. 5A, Fig. 5B and Fig. 6 in one of the strap cells 502. The sectional view 700 can be taken, for example, along the line B in each of the Fig. 5A, Fig. 5B and Fig. 6. The control gates 102, the erase gate 106, and the word lines 108 are arranged above a substrate 116, and the control gates 102 and the word lines 108 are further arranged above an isolation structure 118. The isolation structure 118 protrudes into a top surface of the substrate 116 to define a device region 116d of the substrate 116, and source / drain regions 120 extend in the device region 116d to sides of the isolation structure 118. It should be noted that the control gates 102, the word lines 108, and the source / drain regions 120 are each referenced only once.

[0042] The control gates 102 are also disposed over respective floating gates 122 and are at least partially covered by respective control gate hard masks 124. The floating gates 122 are spaced from the substrate 116 by respective floating gate dielectric layers 126 and are spaced from the control gates 102 by respective control gate dielectric layers 128. The control gates 102 are covered by respective control gate sidewall spacers 130. Note that the floating gates 122, the control gate hard masks 124, the floating gate dielectric layers 126, the control gate dielectric layers 128, and the control gate sidewall spacers 130 are each referenced only once.

[0043] The erase gate 106 is covered by an erase gate dielectric layer 132, and the wordlines 108 are covered by respective wordline dielectric layers 134. Note that only one of the wordline dielectric layers 134 is labeled. The erase gate dielectric layer 132 separates the erase gate 106 from the floating gates 122, the control gate sidewall spacers 130, and the substrate 116. The wordline dielectric layers 134 separate the wordlines 108 from the substrate 116, the isolation structure 118, and the control gate sidewall spacers 130.

[0044] The control gates 102, the erase gate 106, and the wordlines 108 are covered by a wordline hardmask layer 112 and an interconnect structure 702. The interconnect structure 702 includes a dielectric interconnect layer 114 and a plurality of wires and a plurality of vias. The plurality of wires and the plurality of vias are stacked on top of each other in the dielectric interconnect layer 114. The plurality of wires includes a first-level pad wire 602, a second-level pad wire 604, and a third-level pad wire 606. The plurality of vias includes a pad via 110p, a first-level pad via 608, and a second-level pad via 610.

[0045] In the Fig. 8 to 20, a series of cross-sectional views 800 to 1200 of some embodiments of a method for manufacturing an integrated chip is shown, wherein the integrated chip has control gates with pad regions protruding on wordline sides of the control gates and on erase gate sides of the control gates. The method can be used to manufacture the integrated chip using any of the Fig. 1A, 1B, 2, 3A to 3C, 4A, 4B, 5A, 5B, 6 and 7 or a combination thereof. In addition, the sectional views 800 to 2000 can be used, for example, along line A in each of the Fig. 1A, Fig. 2, Fig. 5A, Fig. 5B and Fig. 6 or a combination thereof.

[0046] As shown in section view 800 of Fig. 8, an isolation structure 118 is formed in a substrate 116 so as to define a device region 116d. The device region 116d may, for example, have a plan view that is Fig. 2, 3A to 3C, and 5B, or a combination thereof. The isolation structure 118 may, for example, have a top view that is a negative of the top view of the device area 116d. In some embodiments, a method of forming the isolation structure 118 includes the following steps: 1) depositing a pad oxide layer on the substrate 116; 2) depositing a pad nitride layer on the pad oxide layer; 3) patterning the pad oxide layer and the pad nitride layer with a layout of the isolation structure 118; 4) performing an etch into the substrate 116 when the pad oxide layer and the pad nitride layer are in place to create isolation openings; 5) filling the isolation openings with a dielectric material; and 6) removing the pad oxide layer and the pad nitride layer. However, other methods are also possible.

[0047] As shown in section view 900 of Fig. 9, a first dielectric layer 902 and a first conductive layer 904 (also referred to as a floating gate layer) are formed one above the other on the substrate 116, between segments of the isolation structure 118. A method for forming the first dielectric layer 902 and the first conductive layer 904 may, for example, include the following steps: 1) depositing the first dielectric layer 902 on the substrate 116; 2) depositing the first conductive layer 904 on the first dielectric layer 902 and the isolation structure 118; and 3) performing planarization into the first conductive layer 904 until the isolation structure 118 is reached. However, other methods are also possible. The deposition of the first dielectric layer 902 may, for example, be performed by thermal oxidation and / or with one or more other suitable deposition techniques.The deposition of the first conductive layer 904 may be performed, for example, by vapor deposition and / or by one or more other suitable deposition techniques.

[0048] As shown in section view 1000 of Fig. 10, a second dielectric layer 1002, a second conductive layer 1004 (also referred to as a control gate layer), and a hard mask layer 1006 are formed over the first conductive layer 904 and the isolation structure 118. The second dielectric layer 1002 and the hard mask layer 1006 may be or include, for example, silicon oxide, silicon nitride, one or more other suitable dielectrics, or a combination thereof. In some embodiments, the second dielectric layer 1002 is or includes an ONO layer (ONO: oxide-nitride-oxide), and / or the hard mask layer 1006 is or includes an ONO layer. The second conductive layer 1004 may be or include, for example, doped polysilicon and / or one or more other suitable conductive materials.

[0049] As shown in section view 1100 of Fig. 11, a plurality of control gate stacks 1102 are formed from the second dielectric layer 1002 (see Fig. 10), the second conductive layer 1004 (see Fig. 10) and the hard mask layer 1006 (see Fig. 10). The control gate stacks 1102 include respective control gate dielectric layers 128, respective control gates 102, and respective control gate hard masks 124. The control gates 102 are each disposed over the control gate dielectric layers 128 and have respective pad regions 104 disposed along lengths of the control gates 102 (viewed from top to bottom). The control gate hard masks 124 are each disposed over the control gates 102. The plurality of control gate stacks 1102 may, for example, have the same top view as the plurality of control gates 102 in each of the Fig. 5A, Fig. 5B and Fig. 6. However, other top views are also possible.

[0050] The plurality of control gate stacks 1102 includes a first control gate stack 1102a and a second control gate stack 1102b, and the first and second control gate stacks 1102a and 1102b include a first control gate 102a and a second control gate 102b, respectively. The first control gate 102a has a first pad region 104a that extends toward and away from the second control gate 102b (viewed from top to bottom). Therefore, a width W pof the first pad region 104a between an erase gate side of the first control gate 102a and a word line side of the first control gate 102a. In addition, a distance S between the first and second control gates 102a and 102b, and thus between the first and second control gate stacks 1102a and 1102b, is large. As will be explained later, hard mask fusion during the formation of word lines between the first and second control gate stacks 1102a and 1102b can be avoided because the distance S is large. The first control gate stack 1102a may, for example, have a top view as shown for the first control gate 102a in each of the Fig. 1, 2 and 3A to 3C, and / or the second control gate stack 1102b may, for example, have a top view as shown for the second control gate 102b in each of the Fig. 1, 2, and 3A to 3C. However, other top views are also possible.

[0051] In some embodiments, a method for fabricating the control gate stacks 1102 includes the following steps: 1) patterning the hard mask layer 1006 with a control gate structure; and 2) performing an etch into the second dielectric layer 1002 and the second conductive layer 1004 when the hard mask layer 1006 is in place to transfer the control gate structure. However, other methods for fabricating the control gate stacks 1102 are also possible. Patterning may be performed, for example, using a photolithographic or etching process or another suitable patterning technique.

[0052] As shown in section view 1200 of Fig. 12, control gate sidewall spacers 130 are formed on sidewalls of the control gate stacks 1102. The control gate sidewall spacers 130 may be or include, for example, silicon oxide, silicon nitride, one or more other suitable dielectrics, or a combination thereof. In some embodiments, the control gate sidewall spacers 130 may be or include an ONO layer. In some embodiments, a method of forming the control gate sidewall spacers 130 includes the steps of: 1) depositing a sidewall spacer layer to cover the control gate stacks 1102; and 2) performing an etch into the sidewall spacer layer. However, other methods are also possible.

[0053] As also shown in section view 1200 of Fig. 12, floating gates 122 and dielectric floating gate layers 126 are formed from the first conductive layer 904 (see Fig. 11) and the first dielectric layer 902 (see Fig. 11) are formed, which are respectively disposed beneath the control gate stacks 1102. In some embodiments, a method of forming the floating gates 122 and the floating gate dielectric layers 126 includes performing an etch into the first conductive layer 904 and the first dielectric layer 902 using the control gate sidewall spacers 130 and the control gate hard masks 124 as a mask. However, other methods are also possible.

[0054] As shown in section view 1300 of Fig. 13, a third dielectric layer 1302 (also referred to as a gate dielectric layer) is formed on sidewalls of the control gate sidewall spacers 130 and sidewalls of the floating gates 122. Furthermore, the third dielectric layer 1302 is formed to cover the substrate 116 and the isolation structure 118 up to sides of the control gate stacks 1102. The third dielectric layer 1302 defines erase gate dielectric layers 132 along sidewalls of the control gate stacks 1102, which may be adjacent to erase gates (not yet formed) and may be or include, for example, silicon oxide and / or one or more other suitable dielectrics.A method for forming the third dielectric layer 1302 may, for example, include the following steps: 1) depositing a first dielectric portion of the third dielectric layer 1302 to cover the control gate stacks 1102; 2) etching back the first dielectric portion; and 3) depositing a second dielectric portion of the third dielectric layer 1302 on the substrate 116. However, other methods are also possible. The first dielectric portion may, for example, be formed by vapor deposition and / or one or more other suitable methods, and / or the second portion may, for example, be formed by thermal oxidation and / or one or more other suitable methods.

[0055] As shown in section view 1400 of Fig. 14, a third conductive layer 1402 (also referred to as a gate layer) and a first anti-reflective layer 1404 are formed on top of each other to cover the substrate 116 and the control gate stacks 1102. The third conductive layer 1402 forms recesses up to sides of the control gate stacks 1102 due to the decrease in elevation from the control gate stacks 1102 to the gaps between the control gate stacks 1102. For example, a first recess 1406 (which is filled with the first anti-reflective layer 1404) is formed between the first and second control gate stacks 1102a and 1102b due to the decrease in elevation from the first and second control gate stacks 1102a and 1102b to the gap between the first and second control gate stacks 1102a and 1102b. The third conductive layer 1402 may be or include, for example, doped polysilicon and / or another suitable conductive material.The first anti-reflective layer 1404 may be or include, for example, a BARC material (BARC: bottom anti-reflective coating) and / or another suitable anti-reflective material.

[0056] As shown in section view 1500 of Fig. 15, a top surface of the third conductive layer 1402 is recessed under top surfaces of the control gate stacks 1102, and then the first anti-reflective layer 1404 is removed. Although not shown, the recessing may result in erase gates from the third conductive layer 1402. The erase gates are located on the erase gate dielectric layers 132 and may, for example, have the same top view as the erase gates 106 in each of the Fig. 5A and Fig. 5B. In addition, an erase gate adjacent to the first control gate stack 1102a may, for example, have the same layout as the first erase gate 106a in each of the Fig. 1A, 2 and 3A to 3C, and / or an erase gate adjacent to the second control gate stack 1102b may, for example, have the same layout as the second erase gate 106b of each of the Fig. 1A, 2, and 3A to 3C. The recessing may be performed, for example, by etching back and / or using one or more other suitable methods. The etching back may, for example, comprise the following steps: 1) etching the first anti-reflective layer 1404 until the third conductive layer 1402 is exposed; and 2) simultaneously etching the third conductive layer 1402 and the first anti-reflective layer 1404 until the top surface of the third conductive layer 1402 is recessed below the top surfaces of the control gate stacks 1102. The removal may be performed, for example, by plasma stripping and / or using another suitable method.

[0057] As shown in section view 1600 of Fig. 16, a wordline hardmask layer 112 is formed on the control gate stacks 1102 and the third conductive layer 1402. The wordline hardmask layer 112 conforms to and occupies the first recess 1406 in the third conductive layer 140. Since the distance S between the first and second control gate stacks 1102a and 1102b is large, a width W i the first depression 1406 large. The width W i can, for example, be large in that it is approximately 2, 3, 5, 10 or multiple times larger than a thickness T of the word line hard mask layer 112. However, other multiples are also possible. Since the width W ithe first recess 1406 is large, the wordline hardmask layer 112 does not fuse in the first recess 1406. That is, portions of the wordline hardmask layer 112 on opposite sidewalls of the first recess 1406 do not fuse or contact each other. In some embodiments, the wordline hardmask layer 112 includes a first wordline hardmask layer 112a and a second wordline hardmask layer 112b. The first wordline hardmask layer 112a may be or include, for example, silicon oxide and / or one or more other suitable dielectrics. The second wordline hardmask layer 112b may be or include, for example, silicon nitride and / or one or more other suitable dielectrics.The wordline hardmask layer 112 may be formed, for example, by conformal deposition, evaporation, one or more other suitable deposition techniques, or a combination thereof.

[0058] As also shown in section view 1600 of Fig. 16, a second anti-reflective layer 1602 is formed to cover the wordline hardmask layer 112. The second anti-reflective layer 1602 may be or include, for example, a BARC material and / or another suitable anti-reflective material.

[0059] As shown in the sectional view 1700 of Fig. As shown in Figure 17, the second anti-reflective layer 1602 and the wordline hardmask layer 112 are patterned with a wordline structure. In some embodiments, patterning includes the following steps: 1) creating a wordline structure in the second anti-reflective layer 1602; and 2) performing an etch into the wordline hardmask layer 112 when the second anti-reflective layer 1602 is in place. However, other methods are also possible. The wordline structure may be created in the second anti-reflective layer 1602, for example, using a photolithographic or etching process or another suitable method.

[0060] Since the wordline hardmask layer 112 is not fused between the first and second control gate stacks 1102a and 1102b, the thickness T of the wordline hardmask layer 112 is constant or substantially constant from the first control gate stack 1102a to the second control gate stack 1102a and 1102b. Since the thickness T of the wordline hardmask layer 112 is constant or substantially constant, patterning is performed uniformly across the wordline hardmask layer 112, and the wordline layout is accurately created in the wordline hardmask layer 112. For example, the etching may be performed with high uniformity to accurately transfer the wordline pattern from the second anti-reflective layer 1602 to the wordline hardmask layer 112.

[0061] As shown in the sectional view 1800 of Fig. As shown in Figure 18, the second anti-reflective layer 1602 is removed. Removal may be accomplished, for example, by plasma detachment or by another suitable method.

[0062] As also shown in the sectional view 1800 of Fig. 18, an etch is made into the third conductive layer 1402 (see Fig. 17) and the third dielectric layer 1302 (see Fig. 17). Through the etching, the word line structure is transferred from the word line hard mask layer 112 to the third conductive layer 1402 and the third dielectric layer 1302, so that a plurality of word lines 108 and a plurality of dielectric word line layers 134 are formed. The word lines 108 are formed along the sidewalls of the control gate stacks 1102, and the dielectric word line layers 134 cover the word lines 108. The plurality of word lines 108 may, for example, have the same top view as the plurality of word lines 108 in each of the Fig. 5A and Fig. 5B. However, other top views are also possible. In some embodiments, the etching also involves removing the second wordline hardmask layer 112b (see Fig. 17) removed and / or otherwise eaten away.

[0063] The plurality of wordlines 108 includes a first wordline 108a and a second wordline 108b between and adjacent to the first and second control gate stacks 1102a and 1102b, respectively. The first wordline 108a may, for example, have a top view as shown for the first wordline 108a in each of the Fig. 1A, 2 and 3A to 3C, and / or the second word line 108b may, for example, have a top view as shown for the second word line 108b in each of the Fig. 1, 2, and 3A to 3C. However, other top views are also possible.

[0064] Since the wordline hardmask layer 112 accurately replicates the wordline structure, the wordline structure is accurately transferred to the third conductive layer 1402 by the etching. This minimizes the likelihood of etch residues defining creepage paths between the first and second wordlines 108a and 108b. Therefore, the process window (e.g., compliance) for the etching is large, and the mass production yield is high. Furthermore, the first and second wordlines 108a and 108b may have substantially vertical sidewall profiles SW. The substantially vertical sidewall profiles SW may increase the uniformity along and / or between the first and second wordlines 108a and 108b, as well as increase the uniformity of operating parameters for devices partially defined by the first and second wordlines 108a and 108b.The higher uniformity can reduce the likelihood of component failure and thus increase the yield of mass production.

[0065] As shown in the sectional view from 1900 by Fig. As shown in Figure 19, the control gate hard masks 124 are patterned on pad regions (e.g., 104a) of the control gates 102 to create contact openings 1902 exposing the control gates 102. The patterning may be performed, for example, using a photolithographic or etching process and / or one or more other suitable patterning techniques.

[0066] As also shown in the sectional view 1900 by Fig. As shown in Figure 19, source / drain regions 120 are formed in the substrate 116, adjacent to the word lines 108. For example, a first source / drain region 120a may be formed in the substrate 116, between and adjacent to the first and second word lines 108a and 108b. The formation may be performed by ion implantation and / or another suitable doping technique.

[0067] As shown in the sectional view 2000 of Fig. 20, an interconnect structure 702 is formed to cover the word lines 108 and the control gate stacks 1102. The interconnect structure 702 includes a dielectric interconnect layer 114, as well as a plurality of wires and a plurality of vias. The plurality of wires includes a first-level pad wire 602, a second-level pad wire 604, and a third-level pad wire 606. The plurality of vias includes a pad via 110p, a first-level pad via 608, and a second-level pad via 610. The first-level pad wire 602, the second-level pad wire 604, and the third-level pad wire 606 may, for example, have top views as shown in Fig. 6. However, other top views are also possible.

[0068] In some embodiments, a method for forming the interconnect structure 702 comprises the following steps: 1) forming the pad via 110p with a single damascene process; 2) forming the first-level pad wire 602 with a single damascene process; 3) forming the first-level pad via 608 and the second-level pad wire 604 with a dual damascene process; and 4) forming the second-level pad via 610 and the third-level pad wire 606 with a dual damascene process. However, other methods are also possible. In some embodiments, the single damascene process includes: 1) depositing a dielectric layer; 2) patterning the dielectric layer with openings for only one level of conductive features (e.g.,a level of vias or a level of wires); and 3) filling the openings with a conductive material to create the one level of conductive features. In some embodiments, the dual damascene process includes: 1) depositing a dielectric layer; 2) patterning the dielectric layer with openings for two levels of conductive features (e.g., a level of vias and a level of wires); and 3) filling the openings with a conductive material to create the two levels of conductive features. In the single damascene process and the dual damascene process, the dielectric layer corresponds to a portion of the interconnect dielectric layer 114.

[0069] The Fig. 8 to 20 are described as a series of steps. The order of these steps may be changed in other embodiments, and the disclosed methods may also be used for other structures. In other embodiments, some of the illustrated and / or described steps may be omitted in whole or in part.

[0070] In Fig. 21 is a block diagram 2100 of some embodiments of the method of Fig. 8 to 20 shown.

[0071] In a step 2102, an isolation structure is formed to extend into a substrate, the isolation structure defining a device region of the substrate. See, for example, Fig. 8.

[0072] In a step 2104, a floating gate layer is formed on the substrate. See, for example, Fig. 9.

[0073] In a step 2106, a first control gate stack and a second control gate stack are formed on the floating gate layer, wherein the first control gate stack has a pad region. The pad region protrudes toward the second control gate stack on a wordline side of the first control gate stack and also protrudes away from the second control gate stack on an erase gate side of the first control gate stack. See, for example, Fig. 10 and Fig. 11. Since the pad region protrudes on the word line side and the erase gate side of the first control gate stack, a width of the pad region extends between these two sides, and a distance between the first and second control gate stacks is large at the pad region. As explained above, this prevents hard mask fusion during word line formation.

[0074] In a step 2108, the floating gate layer is patterned to create floating gates under the first and second control gate stacks. See, for example, Fig. 12.

[0075] In a step 2110, a gate dielectric layer is formed to cover the first and second control gate stacks and the substrate between the first and second control gate stacks. See, for example, Fig. 13.

[0076] In a step 2112, a gate layer and an anti-reflective layer are formed to cover the first and second control gate stacks and the gate dielectric layer. See, for example, Fig. 14. The gate layer has a recess between the gate layer and the gap between the first and second control gate stacks due to the change in topography of the first and second control gate stacks.

[0077] In a step 2114, the gate layer and the anti-reflective layer are recessed until a top surface of the gate layer is located below top surfaces of the first and second control gate stacks. See, for example, Fig. 15. In addition, the recess remains after the recessing.

[0078] In a step 2116, a wordline hardmask layer is formed on the first and second control gate stacks and the gate layer, wherein the wordline hardmask layer has a wordline structure. See, for example, Fig. 16 and Fig. 17. The manufacturing process includes depositing the wordline hardmask layer and patterning the wordline hardmask layer with the wordline structure. Since the distance between the first and second control gate stacks at the pad region is large, the width of the recess at the pad region is large. Since the width of the recess is large, the wordline hardmask layer occupies the recess without fusing into the recess. Furthermore, a thickness of the wordline hardmask layer from the first control gate stack to the second control gate stack is constant or substantially constant. This allows patterning to be performed uniformly across the wordline hardmask layer, and the wordline structure can be precisely created in the wordline hardmask layer.

[0079] In a step 2118, an etch is performed into the gate layer when the wordline hardmask layer is in place to form a first wordline and a second wordline between and adjacent to the first and second control gate stacks, respectively. See, for example, Fig. 18. Because the wordline hardmask layer has a consistent or substantially consistent thickness, it provides uniform protection for masked portions of the gate layer during etching. Due to the consistent protection during etching and because the wordline hardmask layer accurately replicates the wordline pattern, the wordline pattern is accurately transferred to the gate layer during etching. As a result, the likelihood of etch residues defining creepage paths between the first and second wordlines is low, and the sidewall profiles of the first and second wordlines are vertical or substantially vertical. The low probability of creepage paths increases the etching process window (e.g., compliance increases), and the mass production yield increases.The vertical or substantially vertical sidewall profiles improve the uniformity of operating parameters for devices partially defined by the first and second word lines, thereby further increasing the yield of mass production.

[0080] In a step 2120, a source / drain region is formed in the substrate between the first and second word lines. See, for example, Fig. 19.

[0081] In a step 2122, an interconnect structure is formed over the first and second control gate stacks and the first and second word lines. See, for example, Fig. 20.

[0082] The block diagram 2100 of Fig.21 is illustrated and described herein as a series of steps or events, but it should be understood that the illustrated order of these steps or events should not be construed in a limiting sense. For example, some steps may occur in different orders and / or concurrently with other steps or events than those illustrated and / or described herein. Furthermore, not all illustrated steps need to implement one or more aspects or embodiments of the description, and one or more of the steps described herein may be performed in one or more separate steps and / or phases.

[0083] In some embodiments, the present application provides an integrated chip comprising: a memory array having a plurality of cells in a plurality of rows and a plurality of columns, the plurality of rows including a first row; an erase gate and a first wordline running along the first row of the memory array; and a first control gate running along the first row, the first control gate being disposed between and adjacent to the erase gate and the first wordline and having a first pad region extending toward the erase gate and the first wordline. In some embodiments, the erase gate and the first wordline align with the first pad region. In some embodiments, the first pad region extends the same amount toward the erase gate and the first wordline.In some embodiments, the integrated chip further comprises a via disposed over and contacting the first pad region. In some embodiments, the first control gate comprises a second pad region extending toward the erase gate and the first word line. In some embodiments, a width of the first control gate is substantially constant from the first pad region to the second pad region. In some embodiments, the integrated chip further comprises a metal line elevated relative to the first control gate and running parallel to the first row, the metal line partially defining a conductive path from the first pad region to the second pad region.In some embodiments, the plurality of rows includes a second row, and the integrated chip further comprises: a second wordline running along the second row of the matrix; and a second control gate running along the second row, wherein the second control gate is disposed between and adjacent to the erase gate and the second wordline, wherein the second control gate has a second pad region projecting toward the erase gate and the second wordline, and the first and second pad regions are each disposed on opposite sides of the erase gate and are diagonally opposite.

[0084] In some embodiments, the present application provides another integrated chip comprising: a first control gate and a second control gate, the first and second control gates being parallel and each having a first pad region and a second pad region, the first control gate having a first width from the first pad region to approximately level with the second pad region, and the first control gate having a second width that is greater than the first width at the first pad region; and an erase gate running parallel to and adjacent to the first control gate, the erase gate having a control gate side recessed at and aligned with the first pad region. In some embodiments, the erase gate is disposed between and adjacent to the first and second control gates, the erase gate enclosing edges of the second pad region.In some embodiments, the second control gate has the first width from the second pad region to approximately level with the first pad region, and the second control gate has the second width at the second pad region. In some embodiments, the integrated chip further comprises a first word line and a second word line, the first and second word lines disposed between the first and second control gates and respectively enclosing portions of the first and second pad regions. In some embodiments, the integrated chip further comprises a source / drain region between and adjacent to the first and second word lines. In some embodiments, a distance between the first and second control gates at the first pad region is greater than about 0.39 µm.In some embodiments, the integrated chip further comprises an isolation structure partially disposed beneath the first and second pad regions.

[0085] In some embodiments, the present application provides a method of manufacturing an integrated chip, the method comprising the steps of: forming a first control gate stack and a second control gate stack on a substrate, the first control gate stack having a first protrusion projecting toward the second control gate stack and a second protrusion projecting away from the second control gate stack at a position level with the first protrusion; depositing a gate layer over the first and second control gate stacks; and patterning the gate layer to form a first erase gate and a first word line, the first erase gate and the first word line being respectively arranged on opposite sides of the first control gate stack, and the first word line and the first erase gate being respectively adapted to the first and second protrusions.In some embodiments, patterning comprises: etching back the gate layer until a top surface of the gate layer is below a top surface of the first and second control gate stacks, respectively; depositing a hard mask layer over the first and second control gate stacks and the gate layer, wherein a thickness of the hard mask layer is substantially consistent from the first control gate stack to the second control gate stack; patterning the hard mask layer with a word line pattern; and performing an etch into the gate layer when the hard mask layer is in place. In some embodiments, the method further comprises implanting dopants into the substrate to form a source / drain region adjacent to the first word line.In some embodiments, patterning forms the first wordline with a wordline sidewall facing the second control gate stack, wherein the wordline sidewall is substantially vertical. In some embodiments, forming the first and second control gates includes depositing a control gate layer on the substrate; and performing an etch into the control gate layer to transfer a control gate pattern to the control gate layer.

Claims

[1] Integrated chip with: a memory matrix (500A) having a plurality of cells (502, 504) in a plurality of rows (R) and a plurality of columns (C), the plurality of rows comprising a first row (Rm); an erase gate (106a) and a first word line (108a) extending along the first row of the memory matrix (500A); and a first control gate (102a) extending along the first row, the first control gate being arranged between and adjacent to the erase gate (106a) and the first word line (108a), the first control gate having a first pad region (104A) projecting toward the erase gate and the first word line, wherein the first word line (108a) adapts to the first pad region (104a) such that it encloses parts of the first pad region (104a). [2] The integrated chip of claim 1, wherein the erase gate (106A) conforms to the first pad region (104a). [3] The integrated chip according to claim 1 or 2, wherein the first pad region (104a) protrudes by the same amount toward the erase gate (106a) and the first word line (108a). [4] Integrated chip according to one of the preceding claims, further comprising a via (110) arranged over and contacting the first pad region (104a). [5] Integrated chip according to one of the preceding claims, wherein the first control gate (106a) has a further pad region projecting towards the erase gate (106a) and the first word line (108a). [6] The integrated chip of claim 5, wherein a width (Wcg) of the first control gate (106a) is substantially constant from the first pad region (104a) to the further pad region. [7] The integrated chip of claim 5 or 6, further comprising a metal line (606) elevated from the first control gate (102a) and extending parallel to the first row (Rm), the metal line partially defining a conductive path from the first pad region to the further pad region (104). [8] An integrated chip according to any preceding claim, wherein the plurality of rows comprises a second row (Rm+1), and the integrated chip further comprises: a second word line (108) running along the second row of the matrix; and a second control gate (102) extending along the second row (Rm+1), the second control gate being arranged between and adjacent to the erase gate (106) and the second word line (108) and having a second pad region (104) projecting toward the erase gate (106) and the second word line (108), the first and second pad regions being each arranged on opposite sides of the erase gate (106) and being diagonally opposite. [9] Integrated chip with: a first control gate (102) and a second control gate (102), the first and second control gates being parallel and each having a first pad region and a second pad region (104), the first control gate (102) having a first width from the first pad region to approximately the same as the second pad region, and the first control gate having a second width that is greater than the first width at the first pad region; and an erase gate (106) extending parallel to and adjacent to the first control gate (102), the erase gate (106) having a control gate side recessed at and adapted to the first pad region such that the erase gate (106) partially encloses the first pad region. [10] The integrated chip of claim 9, wherein the erase gate (106) is disposed between and adjacent to the first and second control gates (102) and encloses edges of the second pad region. [11] The integrated chip of claim 9 or 10, wherein the second control gate (102) has the first width from the second pad region (104) to approximately constant with the first pad region and has the second width at the second pad region (104). [12] The integrated chip of claim 9 or 11, further comprising a first word line (108a) and a second word line (108b), the first and second word lines being disposed between the first and second control gates (102a, 102b) and each enclosing portions of the first and second pad regions (104a, 104b). [13] The integrated chip of claim 12, further comprising a source / drain region (120) between and adjacent to the first and second word lines (108a, 108b). [14] The integrated chip of any one of claims 9 to 13, wherein a distance between the first and second control gates (102a, 102b) at the first pad region (104a) is greater than about 0.39 µm. [15] The integrated chip of any one of claims 9 to 14, further comprising an isolation structure (118) partially disposed beneath the first and second pad regions (104a, 104b). [16] A method of manufacturing an integrated chip comprising the following steps: Fabricating a first control gate stack (1102a) and a second control gate stack (1102b) on a substrate (116), the first control gate stack (1102a) having a first protrusion projecting toward the second control gate stack (1102b) and a second protrusion projecting away from the second control gate stack (1102b) at a position level with the first protrusion; Depositing a gate layer (1402) over the first and second control gate stacks; and Patterning the gate layer (1402) to form a first erase gate (106) and a first word line, wherein the first erase gate and the first word line are each arranged on opposite sides of the first control gate stack, and the first word line and the first erase gate each conform to the first and second protrusions in such a way that they partially enclose them. [17] The method of claim 16, wherein structuring comprises: Etching back the gate layer (1402) until a top surface of the gate layer is below a top surface of the first and second control gate stacks (1102b); Depositing a hard mask layer (112) over the first and second control gate stacks (1102b) and the gate layer (1402), wherein a thickness of the hard mask layer (112) is substantially constant from the first control gate stack to the second control gate stack; Structuring the hard mask layer (112) with a word line structure (108); and Performing an etch into the gate layer with an existing hard mask layer. [18] A method according to claim 16 or 17, further comprising: Implanting dopants into the substrate to form a source / drain region (120) adjacent to the first word line (108a). [19] The method of any one of claims 16 to 18, wherein the structuring creates the first word line (108a) having a word line sidewall (SW) facing the second control gate stack (1102b), the word line sidewall (SW) being substantially vertical. [20] The method of any one of claims 16 to 19, wherein forming the first and second control gate stacks (102a, 102b) comprises: depositing a control gate layer on the substrate (116); and Performing an etch into the control gate layer (124) to transfer a control gate structure (1102) to the control gate layer (124).

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