Application processor and system-on-chip

Abstract

Application processor comprising: a memory management unit (200) configured to respond to an access request received from a master intellectual property (190), the access request comprising a target context and a virtual target address, wherein the access request corresponds to a search request to translate the virtual destination address into a first physical destination address, and wherein the memory management unit (200) comprises: a context cache (210) configured to store contexts and context identifiers of the stored contexts as first tag and first data, respectively, while avoiding duplication of contexts, the contexts being used in the search query; a translation cache (218) configured to store a first address and first context identifiers as a second tag, and configured to store second addresses as second data, wherein the first address corresponds to a virtual address used in the browse request, the first context identifiers correspond to a first context used in the browse request, and the second addresses correspond to the first address and the first context; an invalidation queue (230) configured to store at least one context identifier to be invalidated from the context identifiers stored in the translation cache (218); and an address translation manager (260) configured to control the context cache (210), the translation cache (218), and the invalidation queue (230), and wherein the address translation manager (260) is configured to translate the first address into the second address by searching the context cache (210) in response to the search request and selectively searching the translation cache (218) based on a result of the search of the context cache (210), and wherein the address translation manager (260), if the target context matches at least one of the first entries in the context cache (210), is configured to obtain a context identifier corresponding to the target context as the target context identifier.

Description

TECHNICAL FIELD

[0001] Example embodiments of the inventive concepts relate to processors, and more particularly to an application processor and a system-on-chip including the same. DESCRIPTION OF THE RELATED ART

[0002] A memory management unit (MMU) is a hardware component that processes memory access requests issued by a direct memory access unit, such as a central processing unit (CPU). The MMU may also be referred to as a paged MMU (PMMU).

[0003] Generally, the MMU initially attempts to use an associative cache called a translation lookaside buffer (TLB) to translate virtual page addresses into physical page addresses of memory, such as instruction memory. If there is no matching physical page address for a virtual page address in the TLB, the TLB performs a slower process of referencing a page table to determine the required physical page address. This can delay MMU channel activity.

[0004] US 2015 / 0055649 A1 discloses a method for providing direct communication between a server and a network switch in a cellular structure. A host channel adapter of a cellular structure hardware accelerator is configured to provide the server with direct access to the memory within the network switch. Multiple fixed-size data packets are received from the server at the data channel adapter. The host channel adapter is connected to a bus of the server. A direct transfer is performed from the cellular structure hardware accelerator to the memory within the network switch on an interconnect bus to write the data packets directly to the memory.

[0005] US 2018 / 0004664 A1 discloses a synchronous input / output (I / O) computer system including a processor and a memory unit storing program instructions. The system clears one or more address translation entries in response to the processor executing the program instructions to issue, via an operating system executing on the synchronous I / O computer system, a synchronous I / O command indicating a request to execute a transaction. The program instructions further command the operating system to select a device table entry from a device table, load the entry into the DTC, request required address translation entries, install the required address translation entries in the address translation cache, and transmit data packets corresponding to the transaction.The program instructions also instruct the operating system to automatically flush the address translation cache entries associated with a transaction to detect that the transaction has completed. SUMMARY

[0006] According to an exemplary embodiment of the inventive concepts, an application processor includes a memory management unit (MMU). The MMU responds to an access request received from a master intellectual property (IP), and the access request includes a target context and a virtual target address. The access request corresponds to a browse request to translate the virtual target address into a first physical target address. The MMU includes a context cache, a translation cache, an invalidation queue, and an address translation manager (ATM). The context cache stores contexts and context identifiers of the stored contexts as the first tag and first data, respectively, while avoiding context duplication, and the contexts are used in the browse request.The translation cache stores a first address and first context identifiers as a second tag and stores second addresses as second data, where the first address corresponds to a virtual address used in the browse request, the first context identifiers correspond to a first context used in the browse request, and the second addresses correspond to the first address and the first context. The invalidation queue stores at least one context identifier to be invalidated from the context identifiers stored in the translation cache. The ATM controls the context cache, the translation cache, and the invalidation queue. The ATM translates the first address to the second address by browsing the context cache in response to the browse request and selectively browsing the translation cache based on a result of the context cache search.If the target context matches at least one of the first entries in the context cache, the ATM receives a context identifier corresponding to the target context as the target context identifier.

[0007] According to an exemplary embodiment of the inventive concepts, a system-on-chip includes a master intellectual property (IP) for issuing an access request, an application processor, and a memory device. The application processor includes a memory management unit (MMU), and the MMU translates a virtual target address to a first physical target address in response to the access request, which includes a target context and the virtual target address. The memory device is coupled to the MMU and includes a page table in which mapping information between virtual addresses and first physical addresses is stored. The MMU includes a context cache, a translation cache, an invalidation queue, and an address translation manager (ATM).The context cache stores contexts and context identifiers of the stored contexts as the first tag and first data, respectively, while avoiding duplication of contexts, and the contexts are used in the access request corresponding to a browse request. The translation cache stores a first address and first context identifiers as the second tag and stores second addresses as the second data, where the first address corresponds to a virtual address used in the browse request, the first context identifiers correspond to a first context used in the browse request, and the second addresses correspond to the first address and the first context. The invalidation queue stores at least one context identifier to be invalidated from the context identifiers stored in the translation cache.The ATM controls the context cache, the translation cache, and the invalidation queue.

[0008] Accordingly, according to example embodiments, the MMU in the application processor can translate a virtual address into a physical address by primarily searching the context cache that stores contexts while avoiding duplication of contexts, and by selectively searching the translation cache based on a result of the context cache search. Therefore, a size of the translation cache can be reduced. Furthermore, performance of the application processor can be improved by processing an invalidation request in the background when the translation cache is not used if the invalidation request indicates a context-based invalidation. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other features of the inventive concepts will be more clearly understood when exemplary embodiments thereof are described with reference to the accompanying drawings. Fig. 1 is a diagram of a system-on-chip (SoC) including a memory management unit (MMU) according to example embodiments. Fig. 2 is a block diagram showing an example of the application processor in Fig. 1 according to exemplary embodiments. Fig. Figure 3 is a diagram showing a mapping between virtual addresses and physical addresses. Fig. 4A is a diagram for explaining an operation of the MMU in Fig. 1 according to exemplary embodiments. Fig. Figure 4B shows an example of the translation cache in Fig. 4A according to exemplary embodiments. Fig. Figure 4C shows an example of the translation cache in Fig. 4B according to exemplary embodiments. Fig. 4D provides another example of the translation cache in Fig. 4B according to exemplary embodiments. Fig. 5 is a block diagram illustrating an MMU in the SoC of Fig. 1 according to exemplary embodiments. Fig. 6A and Fig. 6B each represent a section of the MMU in Fig. 5 according to exemplary embodiments. Fig. 7 is a flowchart showing an example operation of the MMU in Fig. 5 according to exemplary embodiments. Fig. 8 is a diagram explaining an operation in Fig. 7. Fig. Figure 9A is a flowchart showing another example operation of the MMU in Fig. 5 according to exemplary embodiments. Fig. 9B is a flowchart showing another example operation of the MMU in Fig. 5 according to exemplary embodiments. Fig. 10 shows that a new context identifier in Fig. 7 is assigned. Fig. 11 is an example operation of the MMU, the processes in Fig. 10. Fig. 12 shows that a new context identifier in Fig. 7 according to exemplary embodiments. Fig. 13A is a flowchart illustrating an example method for invalidating entries in the context cache in the MMU according to example embodiments. Fig. 13B is a flowchart illustrating an example method for invalidating entries in the translation cache in the MMU, according to example embodiments. Fig. 14 is a flowchart illustrating another example method for invalidating entries in the translation cache in the MMU, according to example embodiments. Fig. 15 shows another example of the application processor in the SoC in Fig. 1 according to exemplary embodiments. Fig. 16 is a block diagram showing an example of the MMU module in Fig. 15 according to exemplary embodiments. Fig. 17 shows an example of the address distribution in Fig. 16 according to exemplary embodiments. Fig. 18 is a conceptual diagram for explaining the operation of the MMU module in Fig. 16. Fig. 19 is a flowchart illustrating a method for operating an MMU in an application processor according to example embodiments. Fig. 20 is a block diagram of a mobile device including an SoC according to example embodiments. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0010] Embodiments of the inventive concepts are described more fully below with reference to the accompanying drawings. Like reference numerals may refer to like elements throughout the application.

[0011] Fig. 1 is a diagram of a system-on-chip (SoC) including a memory management unit (MMU) according to example embodiments.

[0012] In Fig. 1, an SoC 10 may be implemented as any of a wide variety of electronic devices; examples include a personal computer (PC), a tablet PC, a netbook, an e-reader, a personal digital assistant (PDA), a portable multimedia player (PMP), an MP3 player, and an MP4 storage device. The SoC 10 may include an application processor 100 that executes program instructions to control overall operation of the SoC 10. The SoC 10 may further include a display 20, a storage device 30, and an input device 50.

[0013] For example, application processor 100 may receive program instructions via input device 50. In some example embodiments, application processor 100 executes program instructions by reading data from storage device 30 and displaying the data on display 20. Input device 50 may include a numeric keypad, a keyboard, and point-and-touch devices such as a touchpad and a computer mouse.

[0014] The memory device 30 may include a page table 40 in which mapping information between virtual addresses and physical addresses is stored.

[0015] Fig. 2 is a block diagram showing an example of the application processor in Fig. 1 according to exemplary embodiments.

[0016] In Fig. 2, the application processor 100 includes a central processing unit (CPU) 110, a cache 170, the MMU 200, a system bus 180, a system peripheral circuit 120, a multimedia accelerator 130, an interconnect circuit 140, a display controller 150, and / or a memory controller 160.

[0017] The CPU 110 executes received program instructions. The cache 170 is a fast memory that stores selected data, e.g., frequently accessed data, to reduce the average latency of memory access operations by the CPU 110. The MMU 200 is a hardware component that processes a request from the CPU 110 to access the storage device 30.

[0018] Functionality of the MMU 200 may include translating virtual addresses to physical addresses, memory protection, controlling the cache 170, bus arbitration, and / or bank switching.

[0019] The system peripheral circuit 120, the multimedia accelerator 130, the interconnect circuit 140, the display controller 150, and / or the memory controller 160 communicate data or instructions with each other via the system bus 180.

[0020] The system bus 180 may include a plurality of channels, such as a read data channel, a read address channel, a write address channel, and / or a write data channel.

[0021] The system peripheral circuit 120 includes a real-time clock (RTC) 121, a phase-locked loop (PLL) 123 and / or a watchdog timer 125.

[0022] The multimedia accelerator 130 includes a graphics engine 133. The multimedia accelerator 130 may further include a camera interface 131, a graphics engine integrated with a frame buffer that performs graphics calculations, or a video display circuit and / or a High-Definition Multimedia Interface (HDMI) 135, which is an audio / video interface for transmitting uncompressed digital data. Note that the MMU 200 may be used to translate a virtual address output by the graphics engine 133 into a physical address.

[0023] Accordingly, the exemplary embodiments of the inventive concepts can be applied to various memory devices and various applications that ensure operational stability while maintaining or improving operational performance.

[0024] The connection circuit 140 may include an audio interface 141, a storage interface 143, such as an Advanced Technology Attachment (ATA) interface, and / or a connection interface 145. The connection circuit 140 may communicate with the input device 50.

[0025] The display controller 150 controls data to be displayed on the display 20. The MMU 200 can be used to translate a virtual address output by the display controller 150 into a physical address.

[0026] The memory controller 160 enables the memory device 30 to be accessible according to the memory type (e.g., flash memory or dynamic random access memory (DRAM)).

[0027] Fig. Figure 3 is a diagram showing a mapping between virtual addresses and physical addresses.

[0028] In the Fig. 1 to 3, a virtual address space can be divided into a plurality of pages PN0 to PNn, where n is an integer greater than two.

[0029] Each of the pages PN0 through PNn is a block of contiguous virtual addresses. Each of the pages PN0 through PNn has a given data size of, for example, 4 KB. However, the size of the pages PN0 through PNn is not limited and can be changed.

[0030] Like the virtual address space, a physical address space can be divided into a plurality of frames FN0 through FNn. Each frame FN0 through FNn has a fixed size.

[0031] A virtual address, e.g., VA2, includes a page number, e.g., PN2, and an offset, e.g., OFF2, within a page. In other words, the virtual address can be expressed by Equation 1: VAi=PNj+OFFx where "i", "j" and "x" are 1 or a natural number greater than 1, VAi is a virtual address, PNj is a page number and OFFx is an offset.

[0032] The page number PN2 is used as an index in page table 40.

[0033] The offset OFF2 is combined with a frame number, e.g., FN2, which defines a physical address, e.g., PA2. The physical address can be expressed by Equation 2: PAr=FNs+OFFx where “r”, “s” and “x” are 1 or a natural number greater than 1, PAr is a physical address, FNs is a frame number and OFFx is an offset.

[0034] The page number PA2 can be called a virtual page number and the frame number FN2 can be called a physical page number.

[0035] The page table 40 has a mapping between a virtual address of a page and a physical address of a frame.

[0036] For ease of explanation, the description assumes that processors such as CPU 110, graphics engine 133, and display controller 150, which process data in each working set, are each referred to as a master intellectual property (IP). The master IP can operate for each working set and can process a plurality of working sets simultaneously. A working set is a data set stored in storage device 30. Working sets refer to a set of pages that are frequently referenced, for example, beyond a reference number in a reference period, in storage device 30 by the master IP, or the number of pages that can be loaded from the master IP into storage device 30. In example embodiments, the master IP of each working set is managed independently of other working sets.

[0037] Fig. 4A is a diagram for explaining an operation of the MMU in Fig. 1 according to exemplary embodiments.

[0038] In Fig. 1, Fig. 2 and Fig. 4A, the MMU 200 includes a translation cache 218, a context cache 210, and / or an invalidation queue 230 and is connected to the master IP 190 and the storage device 30 through a plurality of channels.

[0039] The master IP 190 processes a working set. The master IP 190 issues an access request corresponding to the working set to the MMU 200 or the cache 170. The access request may include a virtual address VA to the working set in the storage device 30 and a context to attributes of the working set. The access request may include a browse request or an invalidate request.

[0040] The MMU 200 calculates a physical address PA using the virtual address VA based on the access request of the master IP 190. Alternatively, the MMU 200 may invalidate at least one of the entries in the translation cache 218 based on the access request of the master IP 190.

[0041] The context cache 210 stores contexts associated with attributes of the access requests as the first tag while avoiding duplication of contexts, and / or stores context identifiers of the contexts as the first data. If the access request matches the browse request, the context cache 210 may store contexts used in the browse request as the first tag while avoiding duplication of entries, and may store context identifiers of the contexts as the first data.

[0042] The translation cache 218 may store a first address and first context identifiers as a second tag, and may store a first address and first context identifiers as a second tag, and may store second addresses as second data. The first address corresponds to a virtual address used in the browse request, and the first context identifiers correspond to a first context used in the browse request. The second addresses correspond to the first address and the first context.

[0043] The translation cache 218 may include a translation lookaside buffer (TLB) or a walk cache.

[0044] The TLB is memory management hardware used to increase the translation speed of virtual addresses. The TLB stores a mapping between a page number PN and a frame number FN. The TLB stores mapping information between context identifiers, the virtual address VA, and the physical address PA associated with pages referenced by the master IP 190. The TLB stores the context identifiers and virtual addresses as a second tag and stores the physical addresses corresponding to the virtual addresses as second data.

[0045] The walk cache stores a portion of the virtual address and stores a physical address that specifies a position in the page table corresponding to the portion of the virtual address.

[0046] When translating a virtual address to a physical address, the MMU 200 first checks the context cache 210. If the context associated with the virtual address VA corresponding to the request of the master IP 190 matches at least one of the entries in the context cache 210 (referred to as a CC hit), the context cache 210 provides the translation cache 218 with a context identifier corresponding to the matching context.

[0047] If mapping information corresponding to the virtual address VA is in the translation cache 218 (referred to as a TC hit), the MMU 200 directly processes the translation without accessing the storage device 30 and reading mapping information from the storage device 30.

[0048] If the context associated with the VA corresponding to the request of the master IP 190 does not match any or all entries in the context cache 210 (referred to as a CC miss), or if no match is found in the translation cache 218 regarding the matching context identifier and the virtual address VA (referred to as a TC miss), a page table walk is performed.

[0049] The page table walk is a process for determining whether there is a match between the page number PN and the frame number FN of the virtual address VA in the page table 40 stored in the storage device 30 when the context associated with the VA corresponding to the request from the master IP 190 does not match any or all entries of the context cache 210, or when the frame number FN of the virtual address VA does not match the page number PN in the translation cache 218 (that is, no mapping information between the virtual address VA and the physical address PA is found in the translation cache 218). The page table 40 stores mapping information between a virtual address and a physical address of all data in the storage device 30.

[0050] When the master IP 190 attempts to read an instruction or data using the physical address PA, and the instruction or data corresponding to the physical address PA is in the cache 170, the cache 170 may directly issue the instruction or data of the master IP 190 without accessing the storage device 30 (referred to as a "cache hit").

[0051] However, if the instruction or data does not exist in cache 170, cache 170 may access a data / instruction storage block 45 in storage device 30 to retrieve the instruction or data (referred to as a "cache miss"). Data / instruction storage block 45 stores information about all data / instructions in storage device 30.

[0052] The invalidation queue 230 may store at least one context identifier to be invalidated from the context identifiers stored in the translation cache 218.

[0053] Fig. Figure 4B shows an example of the translation cache in Fig. 4A according to exemplary embodiments.

[0054] In Fig. 4B, the translation cache 218 includes a tag field 219a and a data field 219b.

[0055] The tag field 219a may store a context identifier CID1 and a virtual address VA1, and the data field 219b may store a physical address PA1 corresponding to the virtual address VA1.

[0056] For example, assume that context identifiers CID1_a and CID1_b are used in the search request. In exemplary embodiments, the context identifier CID1_a and virtual addresses VA1_a, VA1_b, and VA1_c corresponding to the context identifier CID1_a are stored in the tag field 219a, and the context identifier CID1_b and a virtual address VA1_d are stored in the tag field 219a. Additionally, the physical addresses PA1_a, PA1_b, PA1_c, and PA1_d corresponding to the virtual addresses VA1_a, VA1_b, VA1_c, and VA1_d, respectively, are stored in the data field 291b. The virtual addresses VA1_a, VA1_b, VA1_c, and VA1_d stored in tag field 219a may be referred to as first addresses, and the physical addresses PA1_a, PA1_b, PA1_c, and PA1_d stored in data field 219b may be referred to as second addresses.

[0057] Fig. Figure 4C shows an example of the translation cache in Fig. 4B according to exemplary embodiments.

[0058] In Fig. 4C, a translation cache 218a may include a TLB 220. Configuration of the TLB 220 is described with reference to Fig. 6A.

[0059] Fig. 4D provides another example of the translation cache in Fig. 4B according to exemplary embodiments.

[0060] In Fig. 4D, a translation cache 218b may include a walk cache 250. Configuration of the walk cache 250 is described with reference to Fig. 6B.

[0061] Fig. 5 is a block diagram illustrating an MMU in the SoC of Fig. 1 according to exemplary embodiments.

[0062] In Fig. 5, the MMU 200 includes a first interface 261, a second interface 263, a memory interface 267, an address translation manager (ATM) 260, the context cache 210, the translation cache 218, the invalidation queue 230, a page table walker 240, and / or a control register 265.

[0063] The first interface 261 provides an interface with the master IP 190. The first interface 216 may correspond to an interface structure according to, for example, an Advanced eXtensible Interface (AXI) protocol.

[0064] The master IP 190 can transmit an access request REQ to the MMU 200 through the first interface 261.

[0065] The second interface 263 is a separate slave interface to set the control register 265. For example, the CPU 110 (see Fig. 2) Control a specific operation of the MMU 200 through the second interface 263. The second interface 263 can communicate with the CPU 110 according to, for example, the Advanced Peripheral Bus (APB) protocol. The MMU 200 can receive a control signal CTL from the CPU 110.

[0066] The ATM 260 is operated to perform the translation of a virtual address VA included in the access request REQ into a physical address.

[0067] The ATM 260 primarily searches (searches or looks up) the context cache 210 to translate a virtual address VA provided by the master IP 190 into a physical address PA through address channels.

[0068] If a context associated with the virtual address VA is present in the context cache 210 (CC hit), the context cache 210 provides the ATM 260 with a context identifier corresponding to the context associated with the virtual address VA. The ATM 260 searches the translation cache 218 based on the context identifier. If the context identifier provided by the context cache 210 is present in the translation cache 218 (TC hit, i.e., if the context identifier provided by the context cache 210 matches at least one entry in the translation cache 218), the ATM 260 may generate a physical address PA by referring to the context identifier and the virtual address.

[0069] If the context associated with the virtual address is not present in the context cache 210 (CC miss), or if the context identifier provided by the context cache 210 does not match any or all entries in the translation cache 218 (TC miss), the ATM 260 controls the page table walker 240 to perform a page table walk in the page table 40.

[0070] Information used to control the operation of the MMU 200 is stored in the control register 265. The ATM 260 may control the context cache 210, the translation cache 218, the invalidation queue 230, and / or the page table walker 240 based on the information stored in the control register 265.

[0071] The memory interface 267 provides an interface for communication with the memory device 30. The MMU 200 can read the page table 40 in the memory device 30 through the memory interface 267 or it can access the data / instruction memory block 45 in the memory device 30 via the memory interface 267.

[0072] Fig. 6A and Fig. 6B each represent a section of the MMU in Fig. 5 according to exemplary embodiments.

[0073] Fig. 6A illustrates that the translation cache 218 in Fig. 5 is implemented with the TLB 220, and Fig. Figure 6B illustrates that the translation cache 218 in Fig. 5 is implemented with the walk cache 250.

[0074] In Fig. 6A, the context cache 210, the TLB 220 and the invalidation queue 230 are shown, and in Fig. 6B shows the walk cache 250. A conventional TLB 215 is also shown to connect the TLB 220 in Fig. 6A to compare.

[0075] In Fig. 6A, the context cache 210 includes a tag field 211 and a data field 213. The tag field 211 stores contexts used in the browse request of the master IP 190 as the first tag, while avoiding duplication of contexts. Each of the contexts may include validation information (VALID), an address space identifier (ASID) to identify an address space, a virtual machine identifier (VMID) to identify a virtual machine, a non-secure field NS associated with whether to secure, and an exception level field EL associated with an exception field. The data field 213 includes a context identifier CID of each of the contexts.

[0076] For example, a context CTX11 may have a VALID of "Y," an ASID of "0xA," a VMID of "0xB," an NS of "1," an EL of "1," and a context identifier CID11 of "0x4." Furthermore, a context CTX12 may have a VALID of "Y," an ASID of "0xC," a VMID of "0xB," an NS of "1," an EL of "1," and a context identifier CID12 of "0x6."

[0077] TLB 220 includes a tag field 221 and a data field 223. Tag field 221 stores a context identifier CID and a virtual address VA corresponding to the context identifier CID, and data field 223 stores a physical address corresponding to the virtual address VA and authorization information AT associated with whether read (R) / write (W) access should be permitted. Each of the entries in tag field 221 of TLB 220 may further include valid information (VALID). Tag field 221 of TLB 220 may store, as a second tag, virtual addresses (first addresses) used in the browse request and context identifiers of the contexts, and data field 223 of TLB 220 may store, as second addresses, physical addresses corresponding to the first addresses and the context identifiers.

[0078] For example, the context identifier CID11 can have virtual addresses "0x1000," "0x6000," and "0x3000." The context identifier CID12 can have a virtual address "0x8000."

[0079] The virtual address "0x1000" can have a physical address "0x9000" and an AT "R / W". The virtual address "0x6000" can have a physical address "0x9000" and an AT "R / W". The virtual address "0x3000" can have a physical address "0x0000" and an AT "R / W". The virtual address "0x8000" can have a physical address "0x2000" and an AT "W".

[0080] The invalidation queue 230 stores context identifiers “0x7” and “0x3” as invalidation entries.

[0081] The walk cache 250 includes a tag field 251 and a data field 253. The tag field 251 stores a context identifier CID and a partial virtual address pVA corresponding to the context identifier CID, and the data field 253 stores a second physical address PA2 indicating a position in the page table 40 corresponding to the partial virtual address pVA. Each of the entries in the tag field 251 of the walk cache 250 may further include valid information (VALID).

[0082] For example, the context identifier CID11 may have partial virtual addresses "pVA11" and "pVA12." The context identifier CID12 may have a partial virtual address "pVA13." The partial virtual addresses "pVA11," "pVA12," and "pVA13" refer to positions in the page table 40, which are specified by physical addresses PA11, PA12, and PA13, respectively.

[0083] As in Fig. As shown in Figure 6A, the context identifier CID11 has different virtual addresses with respect to a context identifier. Therefore, the ATM 260 can translate a virtual address VA into a physical address PA by primarily searching the context cache 210 to determine whether a target context included in the access request of the master IP 190 matches at least one of the entries of the tag field 211 in the context cache 210, and by selectively searching the TLB 220 based on a search result of the context cache 210.

[0084] Since the context cache 210 stores the contexts while avoiding duplication of the contexts, an occupied area of ​​the context cache 210 can be reduced. Furthermore, the TLB 220 does not store ASID and VMID, which have relatively more bits, thereby simplifying a configuration of the TLB 220.

[0085] If the target context does not match any or all entries of the tag field 211 of the context cache 210, a page table walk is performed without searching the TLB 220, and therefore, performance of the MMU 200 can be improved.

[0086] On the other hand, since the conventional TLB 215 including a tag field 217 and a date field 219 stores ASID and VMID having relatively more bits, a size of the TLB 215 is increased and more time is required to search the TLB 215 to determine whether the target context matches entries of the TLB 215.

[0087] Fig. 7 is a flowchart showing an example operation of the MMU in Fig. 5 according to exemplary embodiments and Fig. 8 is a diagram explaining an operation in Fig. 7.

[0088] In the Fig. 5 to 8, when the ATM 260 receives the access request REQ from the master IP 190, the ATM 260 searches (looks up) the context cache 210 based on a target context included in the access request REQ (operation S100) and determines whether the target context matches at least one of the first entries in the context cache 210 (CC tag hit? in operation S115).

[0089] If the target context does not match any or all of the first entries in the context cache 210 (NO in S115), the ATM 260 assigns the target context to a new context identifier (ID) (operation S200) and controls the page table walker 240 to perform a page table walk in the page table 40 (operation S290).

[0090] If the destination context matches one (or at least one) of the first entries in the context cache 210 (YES in S115), the ATM 260 obtains a context identifier (Context ID) corresponding to the destination context (S120). The ATM 260 searches the translation cache (TC) 218 ​​based on the obtained context identifier and the destination virtual address (operation S125) and determines whether the obtained context identifier and the destination virtual address match one of the second entries in the translation cache 218 (TC Tag Hit? in operation S130).

[0091] If the obtained context identifier and the destination virtual address match all of the second entries in the translation cache 218 (NO in S130), the ATM 260 controls the page table walker 240 to perform a page table walk in the page table 40 (operation S290).

[0092] If the obtained context identifier and the virtual destination address match one of the second entries in the translation cache 218 (YES in S130), the ATM 260 obtains a physical address PA corresponding to the virtual destination address (operation S140) and performs address translation to deliver the physical address PA to the master IP 190 (operation S285).

[0093] Fig. Figure 9A is a flowchart showing another example operation of the MMU in Fig. 5 according to exemplary embodiments.

[0094] In Fig. 5 and Fig. 9A, the ATM 260 determines whether a context currently in use has been changed (operation S105).

[0095] If the context currently in use has not been changed (NO in S105), the ATM 260 performs operation S105.

[0096] If the context currently in use has been changed (YES in S105), the ATM 260 searches the context cache 210 based on the changed context (operation S107).

[0097] The ATM 260 determines that the changed context matches at least one of the first entries in the context cache 210 (operation S120). If the changed context matches none or all of the first entries in the context cache 210 (NO in S120), the ATM 260 assigns the changed context a new context identifier (ID) (operation S200) and stores the changed context in the context cache 210.

[0098] If the changed context matches at least one of the first entries in the context cache 210 (YES in S120), the ATM 260 updates the context cache 210 by assigning the matching entry as the first context identifier (operation S123).

[0099] Since the change of context occurs rarely, operations S107, S120 and S123 can be omitted.

[0100] Fig. 9B is a flowchart showing another example operation of the MMU in Fig. 5 according to exemplary embodiments.

[0101] In the Fig. 5 and Fig. 9B, the ATM 260 determines whether a new request is received from the master IP 190 (operation S106). If the new request is not received from the master IP 190 (NO in S106), the ATM 260 performs operation S106. If the new request is not received from the master IP 190 (YES in S106), the ATM 260 searches the translation cache 218 based on the most recently used context identifier and a virtual address VA included in the new request (operation S125).

[0102] The ATM 260 determines that the most recently used context identifier and the virtual address VA match at least one of the second entries in the translation cache 218 (operation S135). If the most recently used context identifier and the virtual address VA do not match all of the second entries in the translation cache 218 (NO in S290), the ATM 260 controls the page table walker 240 to perform a page table walk in the page table 40 (operation S290). The physical address PA can be obtained after the page table walk (operation S140). If the most recently used context identifier and the virtual address VA match one (at least one) of the second entries in the translation cache 218 (YES in S290), the ATM 260 obtains the physical address PA (operation S140).

[0103] Fig. 10 shows that a new context identifier in Fig. 7 is assigned, and Fig. 11 is an example process of the MMU, the processes in Fig. 10.

[0104] In the Fig. 5, Fig. 7, Fig. 10 and Fig. 11 To assign a new context identifier to the target context (operation S200a), the ATM 260 determines whether the context cache 210 has available space, e.g., whether the context cache 210 is full (operation S210).

[0105] If the context cache 210 has available space (NO in S210), the ATM 260 controls the page table walker 240 to perform a page table walk in the page table 40 (operation S290).

[0106] If the context cache 210 has no available space (YES in S210), the ATM 260 invalidates (selects) at least one of the entries in the context cache 210 based on a usage history of the first entries and places (records) a context identifier of the selected entry to be invalidated in the invalidation queue 230 (S250). That is, the ATM 260 changes the validation information of a context identifier CID13 with "0x8" whose use is the most recent from "Y" to "N" and records "0x8" in the invalidation queue 230.

[0107] The ATM 260 stores the destination context at a location where the context identifier CDI13 was stored in the context cache 210 and assigns a new context identifier CID14 to the destination context (operation S280).

[0108] Fig. 12 shows that a new context identifier in Fig. 7 according to exemplary embodiments.

[0109] In the Fig. 5, Fig. 7 and Fig. 12 To assign a new context identifier to the target context (operation S200b), the ATM 260 determines whether the context cache 210 has available space, e.g., whether the context cache 210 is full (operation S210).

[0110] If the context cache 210 has no available space (YES in S210), the ATM 260 determines whether the invalidation queue 230 has available space, e.g., whether the invalidation queue 230 is full (operation S220). If the invalidation queue 230 has available space (NO in S220), the ATM 260 invalidates (selects) at least one of the entries in the context cache 210 based on a usage history of the first entries and places (records) a context identifier to be invalidated from the selected entry in the invalidation queue 230 (operation S250).

[0111] If the invalidation queue 230 has no available space, e.g., if the invalidation queue 230 is full (YES in S220), the ATM 260 invalidates at least some of the entries in the translation cache 218 based on the invalidation queue 230 and removes (deletes) at least some entries in the invalidation queue 230 so that the invalidation queue 230 has available space (operation S230).

[0112] The ATM 260 invalidates (selects) at least one of the entries in the context cache 210 based on a usage history of the first entries and places (records) a context identifier to be invalidated from the selected entry in the invalidation queue 230 (operation S250). The ATM 260 stores the target context at a location where the context identifier was stored in the context cache 210 and assigns a new context identifier to the target context (operation S280).

[0113] Fig. 13A is a flowchart illustrating an example method for invalidating entries in the context cache in the MMU according to example embodiments.

[0114] In the Fig. 5, Fig. 6A and Fig. 13B, the ATM 260 determines whether the access request from the master IP 190 corresponds to a new invalidation request to invalidate at least one of the entries in the translation cache 118 (operation S305).

[0115] If the access request from the master IP 190 corresponds to a new, context-based invalidation request (YES in S305), the ATM 260 searches the context cache 210 based on a target context included in the invalidation request (operation S310) and determines whether the target context matches one or more entries in the context cache 210 (operation S320). If the target context matches none or all of the entries in the context cache 210 (NO in S320), the ATM 260 notifies the master IP 190 of the completion of the invalidation (operation S330).

[0116] If the target context matches one or more of the entries in the context cache 210 (YES in S320), the ATM 260 invalidates an entry corresponding to the target context in the context cache 210, records (places) a context identifier from the invalidated entry (operation S340), and reports the completion of the invalidation to the master IP 190 (operation S330).

[0117] Fig. 13B is a flowchart illustrating an example method for invalidating entries in the translation cache in the MMU, according to example embodiments.

[0118] In Fig. 13B, the ATM 260 determines whether the invalidation queue 230 has available space, e.g., it determines whether the invalidation queue 230 is not empty (operation S350). If the invalidation queue 230 is not empty (YES in S350), the ATM 260 determines whether the translation cache 218 is not in use, e.g., whether there is no activity in the translation cache 218 (operation S355). If the translation cache 218 is not in use (YES in S355), the ATM 260 removes (extracts) the context identifier from the invalidation queue 230 and searches the translation cache 218 based on the dequeued context identifier (operation S360).

[0119] The ATM 260 determines whether the dequeued context identifier matches at least one entry in the translation cache 218 (operation S370). If the dequeued context identifier matches none or all entries in the translation cache 218 (NO in S370), the process ends. If the dequeued context identifier matches at least one of the entries in the translation cache 218 (YES in S370), the ATM 260 changes validation information of the matching entry (e.g., the matching context identifier) ​​from "Y" to "N" (operation S380).

[0120] Fig. 13A and Fig. 13B illustrate invalidation entries of the translation cache 218 based on the context. In addition, Fig. 13B represents invalidation entries of the translation cache 218 that were performed in the background when the translation cache 218 is not in use.

[0121] Fig. 14 is a flowchart illustrating another example method for invalidating entries in the translation cache in the MMU, according to example embodiments.

[0122] In Fig. 5, Fig. 6A and Fig. 14, the ATM 260 determines whether the access request from the master IP 190 corresponds to a new invalidation request to invalidate at least one of the entries in the translation cache 118 (operation S410). In exemplary embodiments, the access request may include a virtual address VA.

[0123] If the access request from the master IP 190 corresponds to a new invalidation request based on a virtual address for invalidating an entry with a specific context (YES in S410), the ATM 260 searches the context cache 210 based on a target context included in the invalidation request (operation S415) and determines whether the target context matches one or more entries in the context cache 210 (operation S420). If the target context matches none or all entries in the context cache 210 (NO in S420), the ATM 260 notifies the master IP 190 of the completion of the invalidation (operation S470).

[0124] If the target context matches one or more of the entries in the context cache 210 (YES in S420), the ATM 260 obtains a context identifier corresponding to the target context (operation S430) and searches the translation cache 218 based on the obtained context identifier and virtual address (operation S440). The ATM determines whether the obtained context identifier and virtual address match at least one of the entries in the translation cache 118 (operation S450). If the obtained context identifier and virtual address do not match all entries of the translation cache 118 (NO in S450), the ATM 260 notifies the master IP 190 of the completion of the invalidation (operation S470).

[0125] If the obtained context identifier and the virtual address match at least one of the entries in the translation cache 118 (YES in S450), the ATM 260 changes validation information of the matching entry (e.g., the matching context identifier) ​​from "Y" to "N" (operation S460) and notifies the master IP 190 of the completion of the invalidation (operation S470).

[0126] Fig. 14 illustrates invalidation entries of the translation cache 218 based on the virtual address.

[0127] The MMU 200 in the application processor 100 according to exemplary embodiments can translate a virtual address into a physical address by primarily searching the context cache that stores contexts while avoiding duplication of contexts, and by selectively searching the translation cache based on a result of the context cache search. Therefore, a size of the translation cache can be reduced. Furthermore, performance of the application processor 100 can be improved by processing an invalidation request in the background while not using the translation cache 118 when the invalidation request indicates a context-based invalidation.

[0128] Fig. 15 shows another example of the application processor in the SoC in Fig. 1 according to exemplary embodiments.

[0129] In Fig. 15, an application processor 100a may include an MMU module 200a.

[0130] The MMU module 200a may include at least one MMU and may translate a virtual address included in a request from the master IP 190 into a physical address.

[0131] Fig. 16 is a block diagram showing an example of the MMU module 200a in Fig. 15 according to exemplary embodiments.

[0132] In Fig. 16, the master IP 190 and the storage device 30 are shown for the purpose of easier explanation.

[0133] In Fig. 16, the MMU module 200a comprises an address distributor 270, a first bus interface 275, a plurality of MMUs 281~28k and / or a second bus interface 290. Although not shown in Fig. 16, the MMU module 200a may further include a cache that stores data and / or an instruction corresponding to the physical address.

[0134] The MMU (MMU1) 281 includes a context cache CC1, a translation cache TC1, and / or an invalidation queue IQ1. The MMU (MMU2) 282 includes a context cache CC2, a translation cache TC2, and / or an invalidation queue IQ2. The MMU (MMUk) 28k includes a context cache CCk, a translation cache TCk, and / or an invalidation queue IQk. Each of the translation caches TC1~TCk may include a TLB or a walk cache.

[0135] The master IP 190 can operate for each working set and can process a plurality of working sets simultaneously. A working set is a data set stored in the storage device 30. The working set indicates a set of pages that the master IP 190 frequently accesses, for example, over a reference number in a reference period, or a number of pages can be loaded from the master IP 190 into the storage device 30. According to exemplary embodiments of the inventive concepts, in the master IP 190, each working set is managed independently of other working sets.

[0136] When the master IP 190 performs operations on a plurality of working sets, the address distributor 270 can dynamically allocate an MMU for each of the working sets. The address distributor 270 stores MMU allocation information corresponding to each of the working sets.

[0137] Upon receiving a request for a working set from the master IP 190, the address distributor 270 may issue an MMU identification MMU_ID of an MMU corresponding to the virtual address VA included in the request to the first bus interface 275 based on the MMU allocation information. The first bus interface 275 may transmit the request and data to the MMU corresponding to the MMU identification MMU_ID.

[0138] Fig. 17 shows an example of the address distribution 270 in Fig. 16 according to exemplary embodiments.

[0139] In Fig. 17, the address distributor 270 comprises a register set 271 and / or an address comparator 273.

[0140] Register set 271 stores the MMU allocation information corresponding to each of the working sets. In other words, register set 271 stores the MMU allocation information in which virtual addresses VA, each corresponding to a working set, are assigned to an MMU ID. According to exemplary embodiments, the MMU allocation information may include indicator information for distinguishing the virtual addresses VA for each working set. The indicator information may, for example, be a starting point and / or an end point for the consecutive virtual addresses VA of a working set.

[0141] The address comparator 273 may compare the virtual addresses VA of the request received from the master IP 190 with the MMU allocation information. The address comparator 273 may output an MMU identification MMU_ID corresponding to the request as the result of the comparison.

[0142] Fig. 18 is a conceptual diagram for explaining the operation of the MMU module in Fig. 16.

[0143] As in Fig. 18, first to n-th working sets may, for example, comprise a plurality of pages frequently referenced in the memory device 30 by the master IP 190, for example, beyond a reference number in a reference period, that is, a plurality of adjacent virtual addresses VA. For example, the first working set comprises virtual addresses VA0 to VA2. However, the working sets are managed independently of each other in the operation of the master IP 190. In other words, a single virtual address VA does not belong to two or more working sets. For example, the virtual addresses VA0 to VAn may be arranged consecutively for the working sets, as in Fig. 18 shown.

[0144] Each MMU translates the virtual address VA of a working set assigned to the MMU into the physical address PA. Address translation can be performed based on a TLB within the MMU. The physical address PA translated by the MMU can be different from or identical to a physical address translated by another MMU.

[0145] Assuming that a working set of data to be processed by the master IP 190 is assigned to the MMU1 281, the first bus interface 275 receives an ID1 of the MMU1 281 from the address distributor 270 and transmits a request of the master IP 190 and data to the MMU1 281.

[0146] The MMU1 281 converts the virtual address VA for the request into the physical address PA. When the MMU1 281 converts the virtual address VA into the physical address PA, the MMU1 281 primarily searches the context cache CC1 and selectively searches the translation cache TC1 based on a result of the search of the context cache CC1, and transmits the requested, translated virtual address VA into the physical address PA to the master IP 190 via the first bus interface 275. Furthermore, the MMU1 281 transmits the request and the data to the storage device 30 through the second bus interface 290. The second bus interface 290 accesses the physical address PA in the storage device 30 and performs an operation on the data according to the request.

[0147] When the master IP 190 starts an operation on another working set while performing an operation on a current working set, one of the MMUs not assigned to the current working set is assigned to the new working set in the MMU module 200a and operated independently. Consequently, a TC error is reduced compared to a case where only one MMU is shared among all the working sets used by the master IP 190. Accordingly, the hit ratio during the data processing operation of the master IP 190 is increased, and the operation speed of the SoC 10 is also increased, while minimizing or reducing mutual interference between working sets. Furthermore, since the MMU is assigned for each working set, the MMU operates flexibly.

[0148] Fig. 19 is a flowchart illustrating a method for operating an MMU in an application processor according to example embodiments.

[0149] In the Fig. 1 to 14 and 19, in a method of operating an MMU 200 in an application processor 100, the ATM 260 in the MMU 200 receives an access request including a destination context and a destination virtual address from the master IP 190 (operation S510).

[0150] The ATM 260 determines whether the target context matches at least one of the first entries in a context cache 210 by searching the context cache 210 (operation S520). The context cache 210 stores contexts and context identifiers of the stored contexts as the first tag and first data, respectively, while avoiding context duplication.

[0151] The ATM 260 selectively determines whether a target context identifier corresponding to the target context matches at least one of the second entries in a translation cache 218 by selectively searching the translation cache 218 based on the search of the context cache 210 (operation S530). The translation cache 218 stores the context identifiers and virtual addresses corresponding to the context identifiers as a second tag and stores physical addresses corresponding to the virtual addresses as second data.

[0152] The ATM 260 converts the physical destination address into a physical destination address based on the selective determination (operation S540) and outputs the physical destination address to the master IP 190.

[0153] Fig. 20 is a block diagram of a mobile device including an SoC according to example embodiments.

[0154] In Fig. 20, a mobile device 900 includes a SoC 910, an LPDDRx memory device 940, an image sensor 950, and / or a display 960. The SoC 910 includes an application processor 920 and / or a WideIO memory 930.

[0155] Data stored on the WideIO memory 930 or the LPDDRx storage device 940 may be displayed on the display 960 under the control of the SoC 910. The SoC 910, in particular the application processor 920, may control the MMU 200 in Fig. 5 or the MMU module 200a in Fig. 16 include.

[0156] Therefore, the MMU of the application processor 920 may include a context cache, a translation cache, an invalidation queue, and / or an ATM. The ATM may translate a virtual address included in an access request from a master IP into a physical address by primarily searching the context cache that stores contexts while avoiding duplication of contexts, and by selectively searching the translation cache based on the context cache search. Therefore, a size of the translation cache can be reduced.

[0157] An SoC and a semiconductor device according to the inventive concepts can be packaged as one of various types to be subsequently embedded. For example, an SoC according to the inventive concepts can be packaged by PoP (Package on Package), Ball Grid Array (BGA), Chip Scale Package (CSPs), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In-Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi-Chip Package (MCP), Wafer-level Fabricated Package (WFP), or Wafer-Level Processed Stack Package (WSP).

[0158] The elements of the Fig.1 to 20 may be implemented in processing circuitry, such as hardware including logic circuitry, a hardware / software combination, such as processor-executing software, or a combination of the same and memory. For example, the processing circuitry may specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

Claims

[1] Application processor comprising: a memory management unit (200) configured to respond to an access request received from a master intellectual property (190), the access request comprising a target context and a virtual target address, wherein the access request corresponds to a search request to translate the virtual destination address into a first physical destination address, and wherein the memory management unit (200) comprises: a context cache (210) configured to store contexts and context identifiers of the stored contexts as first tag and first data, respectively, while avoiding duplication of contexts, the contexts being used in the search query; a translation cache (218) configured to store a first address and first context identifiers as a second tag, and configured to store second addresses as second data, wherein the first address corresponds to a virtual address used in the browse request, the first context identifiers correspond to a first context used in the browse request, and the second addresses correspond to the first address and the first context; an invalidation queue (230) configured to store at least one context identifier to be invalidated from the context identifiers stored in the translation cache (218); and an address translation manager (260) configured to control the context cache (210), the translation cache (218), and the invalidation queue (230), and wherein the address translation manager (260) is configured to translate the first address to the second address by searching the context cache (210) in response to the search request and selectively searching the translation cache (218) based on a result of the search of the context cache (210), and wherein the address translation manager (260), if the target context matches at least one of the first entries in the context cache (210), is configured to obtain a context identifier corresponding to the target context as the target context identifier. [2] The application processor of claim 1, wherein the translation cache (218a) comprises an address translation buffer (220), wherein the address translation buffer (220) is arranged to store the virtual addresses as first addresses and is arranged to store physical addresses corresponding to the virtual addresses as second addresses, and wherein the address translation manager (260), if the destination context identifier and the virtual destination address match one of the second entries in the address translation buffer (220), is configured to control the address translation buffer (220) to provide a first physical address corresponding to the virtual destination address as the first physical destination address. [3] The application processor of claim 2, wherein the memory management unit (200) further comprises a page table walker (240), wherein the address translation manager (260), if the target context identifier does not match any or all of the second entries in the address translation buffer (220), is configured to control the page table walker (240) to perform a page table walk in a page table (40) that maps a virtual address (VA) to a corresponding physical address (PA), and the address translation manager (260), if the target context identifier does not match any or all of the first entries in the context cache (210), is configured to control the page table walker (240) to perform a page table walk in a page table (40). [4] The application processor of claim 1, wherein the memory management unit (200) further comprises a page table walker (240), wherein the translation cache (218b) comprises a walk cache (250), wherein the walk cache (250) is configured to store partial virtual addresses of the virtual addresses (VA) as first addresses, and is configured to store second physical addresses to indicate a position of the page table (40) corresponding to the first address, wherein the address translation manager (260) is configured to control the page table walker (240) to perform a page table walk in a page table (40) that maps a virtual destination address to the first physical destination address, and wherein the address translation manager (260), if the destination context identifier and the virtual destination address correspond to one of the second entries in the walk cache (250), is configured to control the walk cache (250) to provide the page table walker (240) with a second physical address corresponding to the first address. [5] The application processor of claim 1, wherein the address translation manager (260), if the target context does not match any or all of the first entries in the context cache (210), is configured to assign a new context identifier to the target context and store the target context in the context cache (210), where the address translation manager (260) is configured to determine whether the context cache (210) has available memory space, if the context cache (210) has no available memory space, the address translation manager (260) is configured to record in the invalidation queue (230) a context identifier of at least one of the first entries stored in the context cache (210) based on a usage history of the first entries, and is configured to store the target context and the new context identifier in the context cache (210). [6] The application processor of claim 1, wherein the address translation manager (260), if the target context does not match any or all of the first entries in the context cache (210), is configured to assign a new context identifier to the target context and store the target context in the context cache (210), where the address translation manager (260) is configured to determine whether the context cache (210) has a first available memory location, if the context cache (210) does not have a first available memory location, the address translation manager (260) is configured to determine whether the invalidation queue (230) has a second available memory location, if the invalidation queue (230) does not have the second available memory location, the address translation manager (260) is configured to remove at least one of the context identifiers to be invalidated from the invalidation queue (230), is configured to invalidate zero or more second entries in the translation cache (218) based on the context identifier removed from the queue, and is configured to store the target context and the new context identifier in the context cache (210). [7] Application processor according to claim 1, wherein the address translation manager (260) is arranged: determine whether the context has been changed and primarily search the context cache (210) to determine whether the context has been changed; if the changed context does not match any or all of the first entries of the context cache (210) according to a result of the search, assigning a new context identifier to the changed context and storing the new context identifier in the context cache (210) as the first context identifier; and, if the changed context matches at least one of the first entries in the context cache (210) according to the result of the search, storing the matching context in the context cache (210) as a first context identifier, wherein the address translation manager (260) is configured to respond to the search request: search the translation cache (218) based on the first context identifier and the virtual address (VA); and obtain the second address if at least one of the second entries in the translation cache (218) matches the first address corresponding to the first context identifier and the virtual address (VA). [8] The application processor of claim 1, wherein the access request corresponds to a context-based invalidation request to invalidate second entries in the translation cache (218), and the translation cache (218) stores a context identifier corresponding to the target context as a second tag, and wherein the address translation manager (260) is configured to: search the context cache (210) in response to the context-based invalidation request; selectively search the translation cache (218) based on a result of the search of the context cache (210); and to report the completion of an invalidation of the second entries in the translation cache (218). [9] The application processor of claim 8, wherein the address translation manager (260), if the target context corresponds to at least one of the first entries in the context cache (210), is configured to: invalidate a target context identifier according to the target context; and record the invalidated target context identifier in the invalidation queue (230), and wherein the address translation manager (260), if the target context does not match any or all of the first entries in the context cache (210), is configured to report the completion of the invalidation. [10] Application processor according to claim 8, wherein the address translation manager (260) is configured to determine whether the invalidation queue (230) has available storage space, if the invalidation queue (230) has no available storage space, the address translation manager (260) is configured to determine whether the translation cache (218) is used, the address translation manager (260), if the translation cache (218) is not used, is configured to extract a context identifier recorded in the invalidation queue (230), is configured to search the translation cache (218) based on the extracted context identifier, and, if the extracted context identifier matches at least one of the entries in the translation cache (218), is configured to invalidate the matching entry. [11] The application processor of claim 1, wherein the access request corresponds to an invalidation request based on a virtual address (VA) to invalidate second entries in the translation cache (218), and the translation cache (218) stores a context identifier corresponding to the target context as a second tag, and wherein the address translation manager (260) is configured to: perform a first search in the context cache (210) based on the target context; obtain a target context identifier corresponding to a target context if the target context matches at least one of the first entries of the context cache (210) according to a result of the first search; perform a second search in the translation cache (218) based on a virtual address (VA) and the target context identifier; and if the virtual address and the target context identifier match at least one of the second entries in the translation cache (218) according to a result of the second search, invalidate the matching entry. [12] The application processor of claim 1, wherein the address translation manager (260) is configured, when performing a page table walk, to translate the first address into the second address by searching the context cache (210) primarily in response to the search request and performing the page table walk based on a result of the search of the context cache (210), wherein the address translation manager (260), if the target context corresponds to at least one of the first entries in the context cache (210), is configured to receive a context identifier corresponding to the target context as the target context identifier, and wherein the address translation manager (260), if the destination context identifier and the virtual destination address match at least one of the second entries in the walk cache (250), is configured to control the walk cache (250) to provide a physical address (PA) corresponding to the address as the physical destination address. [13] System-on-chip comprising: a master intellectual property (190) configured to issue an access request; an application processor (100) comprising a memory management unit (200) configured to translate a virtual target address into a first physical target address in response to the access request, which includes a target context and the virtual target address; and a memory device (30) coupled to the memory management unit (200) comprising a page table (40) in which map information between virtual addresses and first physical addresses is stored, wherein the memory management unit (200) comprises: a context cache (210) configured to store contexts and context identifiers of the stored contexts as first tag and first data, respectively, while avoiding duplication of contexts, the contexts being used in a search request corresponding to the access request; a translation cache (218) configured to store a first address and first context identifiers as a second tag, and configured to store second addresses as second data, wherein the first address corresponds to a virtual address used in the browse request, the first context identifiers correspond to a first context used in the browse request, and the second addresses correspond to the first address and the first context; an invalidation queue (230) configured to store at least one context identifier to be invalidated from the context identifiers stored in the translation cache (218); and an address translation manager (260) configured to control the context cache (210), the translation cache (218), and the invalidation queue (230).

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