Printed electronic devices exhibiting improved performance and multiple electrical devices, as well as methods for manufacturing and methods for using them.

Abstract

Printed electronic device comprising the following: several contact surfaces arranged in a pattern (104), several electrode tracks (106a-j) arranged in a different pattern, wherein the several electrode tracks comprise a set of lower electrode tracks (106f-g) and a set of upper electrode tracks (106a-e), each electrode track being in electrical contact with an associated contact surface (104a-j) of the several contact surfaces, and multiple memory cells, each memory cell being located at an intersection of a pair of electrode tracks of the multiple electrode tracks and comprising: a lower electrode layer (112) formed from a region of one of the lower electrode tracks, an upper electrode layer (110) formed from a region of one of the upper electrode tracks, and a ferroelectric layer (114) between the lower and the upper electrode layer, wherein the multiple contact surfaces comprise at least one unmodified contact surface having a surface, shape and size, wherein the multiple contact surfaces further comprise at least one modified contact surface having a reduced surface area, a different size or a different shape compared to the at least one unmodified contact surface, wherein one end of each electrode track of the multiple electrode tracks extends linearly to the associated contact surface and wherein the at least one modified contact surface has an edge that is aligned linearly and parallel to a nearest adjacent electrode track, and wherein the at least one modified contact surface has a non-rectangular polygonal shape and the at least one non-modified contact surface has a rectangular shape.

Description

[0001] Memory cell-based printed electronics are used in a variety of applications, including markers, labels, and sensors. The memory cells are capacitor-like structures, each containing a layer of memory material sandwiched between a pair of electrode layers. The memory cells are accessed via conductive traces that connect the electrodes to an electronic driver and sensing circuit, which may be located at the periphery of the memory cells or in a separate module, such as a read / write unit. Depending on the application, the printed electronic device can contain anywhere from a few to several million memory cells. Regardless of the specific configuration of the printed electronic device, its performance is generally maximized to ensure it functions as intended (e.g.,(to enable accurate and efficient reading and writing of the individual memory cells). Unfortunately, despite the advantages of the various printing processes (e.g., inkjet printing, screen printing, gravure printing, etc.) used to manufacture printed electronic devices, many factors in the manufacturing process can contribute to reduced device performance.

[0002] Document WO 2006 / 135 247 A1 discloses a data storage device consisting of a passive storage unit and a physically separate read / write unit, which come into direct physical contact for data transmission.

[0003] Publication US 9 659 819 B2 describes a method in which a single vertical via is used to connect multiple stacked wiring levels of a memory chip to the underlying control circuit.

[0004] The publication EP 2 881 984 B1 discloses an encapsulated semiconductor device that uses contact pads with deliberately different polygonal shapes on its underside to maximize the distance between them and prevent short circuits.

[0005] The publication EP 0 158 363 A2 describes a storage arrangement produced on a flexible substrate, in which the storage element and the insulation element are arranged laterally next to each other, so that the resistance is determined by the length of the element.

[0006] Patent application US 2007 / 0243678A1 discloses a manufacturing process for crossbar memory arrays in which the electrodes and functional material are entirely applied by inkjet printing to enable cost-effective production. Patent application EP 2351083B1 discloses resistive random-access memory (RRAM). Patent application US 9564576B2 discloses semiconductor devices and methods, and in particular multi-bit ferroelectric devices and methods for their fabrication.

[0007] The task is to provide appropriate devices and storage cells with improved performance.

[0008] The problem is solved by the printed electronic device according to claim 1, the multiple electronic devices according to claim 15, and the method for manufacturing according to claim 16, as well as the use of the method according to claim 17. Further embodiments are set forth in the dependent claims.

[0009] In embodiments, printed electronic devices are provided comprising: several contact surfaces arranged in one pattern, several electrode tracks arranged in another pattern, wherein the several electrode tracks comprise a set of lower electrode tracks and a set of upper electrode tracks, each electrode track being electrically connected to an associated contact surface of the several contact surfaces, and several memory cells, each memory cell being located at an intersection of a pair of electrode tracks of the several electrode tracks and comprising: a lower electrode layer formed from a region of one of the lower electrode tracks, an upper electrode layer formed from a region of one of the upper electrode tracks, and a ferroelectric layer between the lower and upper electrode layers.The multiple contact surfaces comprise at least one unmodified contact surface having a surface, shape and size, wherein the multiple contact surfaces further comprise at least one modified contact surface having a reduced surface area and a different size, shape or both compared to the at least one unmodified contact surface.

[0010] In embodiments, methods for manufacturing printed electronic devices are provided, comprising: printing multiple lower electrode tracks on a substrate; printing a layer of a ferroelectric material onto the multiple lower electrode tracks; printing multiple upper electrode tracks onto the layer of ferroelectric material, wherein the multiple lower and upper electrode tracks form multiple electrode tracks arranged in a pattern and define multiple memory cells, each memory cell being located at an intersection of a pair of electrode tracks of the multiple electrode tracks; and printing multiple contact pads onto the multiple electrode tracks, wherein the multiple contact pads are arranged in another pattern and each electrode track of the multiple electrode tracks is in electrical contact with an associated contact pad of the multiple contact pads.The multiple contact surfaces comprise at least one unmodified contact surface having a surface, shape and size, wherein the multiple contact surfaces further comprise at least one modified contact surface having a reduced surface area and a different size, shape or both compared to the at least one unmodified contact surface.

[0011] In embodiments, methods for using printed electronic devices are provided, which include contacting multiple contact surfaces of a printed electronic device having multiple pins of a read / write unit, wherein the electronic device comprises: the multiple contact surfaces arranged in one pattern, multiple electrode tracks arranged in another pattern, wherein the multiple electrode tracks comprise a set of lower electrode tracks and a set of upper electrode tracks, each electrode track being in electrical contact with an associated contact surface of the multiple contact surfaces, and multiple memory cells, wherein each memory cell is located at an intersection of a pair of electrode tracks of the multiple electrode tracks and comprises: a lower electrode layer formed from a region of one of the lower electrode tracks,An upper electrode layer formed from a region of one of the upper electrode tracks, and a ferroelectric layer between the lower and upper electrode layers. The multiple contact surfaces comprise at least one unmodified contact surface having a surface area, shape, and size, and the multiple contact surfaces further comprise at least one modified contact surface having a reduced surface area and a different size, shape, or both compared to the at least one unmodified contact surface. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1A shows a top view of a printed electronic device according to an illustrative embodiment. Fig. Figure 1B shows an enlarged view of section A of the printed electronic device of Fig. 1A. Fig. Figure 1C shows an enlarged view of section B of the printed electronic device of Fig. 1A. Fig. Figure 1D shows a cross-sectional view of a memory cell of the printed electronic device from Fig. 1A. Fig. Figure 2A shows a top view of a printed electronic device according to another illustrative embodiment. Fig. Figure 2B shows an enlarged view of section C of the printed electronic device of Fig. 2A.

[0012] Printed electronic devices with improved performance and methods for manufacturing and using such devices are provided.

[0013] The printed electronic devices are based on arrays or matrices of memory cells known as passive arrays or matrices. The devices are multilayer structures comprising stacked layers, each layer being made of a different material and / or configured in a different pattern, depending on the layer's function. The devices include multiple contact pads arranged in one pattern; multiple electrode tracks arranged in another pattern, the multiple electrode tracks comprising a set of lower electrode tracks and a set of upper electrode tracks, each electrode track being electrically connected to an associated contact pad of the multiple contact pads; and multiple memory cells, each memory cell being located at an intersection of a pair of electrode tracks of the multiple electrode tracks.Each memory cell comprises a lower electrode layer, an upper electrode layer, and a ferroelectric layer between the upper and lower electrode layers. The upper and lower electrode layers of the memory cells correspond to areas of the upper and lower electrode tracks, respectively. Moving from bottom to top within the devices, the set of lower electrode tracks is one of the layers of the multilayer structure, the ferroelectric layer is a layer above the set of lower electrode tracks, the set of upper electrode tracks is a layer above the ferroelectric layer, and the multiple contact pads are a layer above the set of upper electrode tracks.

[0014] The contact surfaces of the multiple contact pads provide an electrical contact point that has pins of a read / write unit configured to generate voltage waveforms to control the reading / writing of the multiple memory cells and to detect the state of the memory cells during the read process. Conventionally, the surface area of ​​each contact pad is maximized to reduce the problem of contact pad / pin misalignment when the printed electronic device and the read / write unit are brought into contact. Additionally, to facilitate fabrication, contact pads with uniform sizes and shapes have been produced (i.e., all contact pads on the same printed electronic device have the same size and shape).

[0015] The present disclosure is based in part on the finding that the performance of printed electronic devices can be improved (i.e., increased) by modifying the size and / or shape of some contact surfaces on the same printed electronic device. The modification (whether in size and / or shape) results in a reduction of the surface area of ​​the modified contact surfaces (compared to one or more other, unmodified contact surfaces in the printed electronic device). Thus, in the present printed electronic devices, the multiple contact surfaces comprise one or more contact surfaces that have a reduced surface area compared to one or more other contact surfaces within the multiple contact surfaces. The contact surfaces that have a reduced surface area and a modified size and / or shape may be referred to herein as “modified contact surfaces.”The other contact surfaces in the printed electronic device may be referred to herein as “unmodified contact surfaces.” When a printed electronic device having both modified and unmodified contact surfaces is printed on the same printing system as a comparable printed electronic device having only unmodified contact surfaces, the performance of the printed electronic device having both modified and unmodified contact surfaces is found to be significantly higher. This is illustrated below with reference to illustrative embodiments of printed electronic devices (see [reference]). Fig. 1A and Fig. 2A).

[0016] Several shapes and sizes can be applied to the modified contact surfaces, provided that the shape or size, or both, differ from the non-modified contact surface(s), which have a larger surface area, in the printed electronic device. Illustrative shapes include non-rectangular polygonal shapes, such as triangular, pentagonal, hexagonal, etc. The non-rectangular polygonal shape can be irregular, meaning that not all sides have the same length and not all angles are equal. Rectangular shapes can be used for modified contact surfaces, provided that the non-modified contact surfaces have a larger surface area and are either non-rectangular or a larger rectangular shape.

[0017] The modified contact surface generally has an edge configured such that there is a distance between the edge and the nearest adjacent electrode track of at least 2∗2∗(row registration capability) The term "nearest adjacent electrode track" refers to an electrode track among the multiple electrode tracks that is assigned to a different contact surface than the modified contact surface (i.e., is electrically connected to it) and is closest to the modified contact surface. This could be, for example, an electrode track assigned to a contact surface adjacent to the modified contact surface, but it could also be an electrode track assigned to a non-adjacent contact surface. "Line registration capability" refers to the registration error value associated with the printing device used to print the multiple contact surfaces. The registration error value for a printing device may be provided by the printing device manufacturer or may be determined by monitoring the printed registration marks against a fixed date against which all printed layers are registered.In embodiments, the distance is at least 500 µm, at least 700 µm, at least 900 µm or is in the range of 500 µm to 900 µm.

[0018] The distance between an edge of a modified contact surface and the nearest adjacent electrode track can be determined by measuring the distances between respective points along the length of the modified contact surface's edge and the length of the nearest adjacent electrode track. If each of the measured distances satisfies one of the distance values ​​described above, the edge is considered appropriately configured. Instead of measuring distances between respective points distributed along the length of the edge / nearest adjacent electrode track, the distance between a nearest pair of respective points along the length of the modified contact surface's edge and the length of the nearest adjacent electrode track can be measured. This is described in the Fig. 1B, Fig. 1C, Fig. 2B is further illustrated and described below. During the design phase, distances can be calculated using CAD software. After manufacturing, these distances can be measured using a video measuring system.

[0019] A top view of an illustrative printed electronic device 100 is shown in Fig. 1A is shown. The process directions and the directions lying perpendicular to the process are shown in Fig. 1A is marked. An outline illustrating the edge of a substrate 102 on which the layers of the device 100 are shown. However, the substrate 102 can be much larger, allowing many printed electronic devices to be printed on it. The device 100 comprises several contact pads 104a-j arranged in one pattern, and several electrode tracks 106a-j arranged in another pattern. The pattern of the multiple contact pads 104a-j consists of two linear arrangements 105a, b that extend parallel to each other and parallel to the process direction transversely. The linear arrangements 105a, b are spaced apart in the process direction to define a gap between them. The multiple electrode tracks 106a-j are positioned in this gap. Each electrode track of the conductor tracks 106a-j is electrically connected to an associated contact pad of the contact pads 104a-j, e.g.The electrode track 106a and the contact surface 104f are an associated pair.

[0020] The multiple electrode tracks 106a-j comprise both upper electrode tracks 106a-e and lower electrode tracks 106f-j. (Both are visible because a ferroelectric layer formed between the upper and lower electrode tracks 106a-e, 106f-j is not shown.) Sections of both the upper and lower electrode tracks 106a-e, 106f-j are configured as strips in which the strip sections of the upper electrode tracks 106a-e are aligned parallel to each other, and the strip sections of the lower electrode tracks 106f-j are aligned parallel to each other and orthogonal to the upper electrode tracks 106a-e, forming a lattice pattern. The remaining portions of the upper and lower electrode tracks 106a-e, 106f-j extend linearly to their associated contact surfaces. In this embodiment, the grid pattern is aligned at 45° with respect to the process direction and the direction perpendicular to the process.Although other orientations can be used, the 45° orientation is advantageous because it minimizes any shift in the physical position of the bit and the associated electrical response due to displacement of the straight process or displacement perpendicular to the process during device registration. Compared to a device whose matrix is ​​oriented orthogonally to the printing direction, a matrix oriented at 45° minimizes the resulting offset in a registration error by a factor of 1 / square meter (2).

[0021] As mentioned above, each memory cell of the multiple memory cells is formed at an intersection of a pair of electrode tracks of the multiple electrode tracks 106a-j. Such an intersection and memory cell is labeled 108. Although not in Fig. As shown in Figure 1A, the printed electronic device 100 comprises the ferroelectric layer between the upper and lower electrode tracks 106a-e, 106f-j. A cross-sectional view of the memory cell 108 is shown in Figure 1A. Fig. Figure 1D illustrates and shows an upper electrode layer 110, a lower electrode layer 112, and a ferroelectric layer 114 between the upper and lower electrode layers 110, 112. The upper electrode layer 110 corresponds to a region of the upper electrode track 106c. The lower electrode layer 112 corresponds to a region of the lower electrode track 106h at the intersection. If one considers again Fig. As 1A is applied, the device comprises 100 25 memory cells. Due to the configuration of the multiple electrode tracks 106a-j (i.e., grid pattern), the multiple memory cells are arranged as a 5×5 matrix of memory cells.

[0022] Returning to the multiple contact surfaces 104a-j, the printed electronic device comprises 100 contact surfaces 104a, e, f, j, which have a rectangular shape. In the present disclosure, the term "rectangular" includes rectangles with sharp corners as well as rectangles with rounded corners, as described in Fig. Figure 1A shows that both corners define an angle of 90°. The device 100 also includes contact surfaces 104b-d and gi with a reduced surface area and a different, non-rectangular shape compared to contact surfaces 104a, e, f, j. In particular, contact surfaces 104b-d and gi each have a non-rectangular, but polygonal shape, specifically that of an irregular pentagon. Each contact surface 104b-d and gi has three 90° angles, two angles greater than 90°, and five sides of different lengths. (See also Fig. 1B and Fig. 1C, enlarged views of contact surface 104b ( Fig. 1B) and contact surface 104c ( Fig. 1C) show). Although other shapes can be used for the contact surfaces 104b-d and gi, each contact surface has an edge configured so that the distance between the edge and a nearest adjacent electrode track is at least 2∗2∗(row registration capability) amounts.

[0023] When you get back Fig. 1B, which shows an enlarged view of section A of Fig. In 1A, an edge of the contact surface 104b is marked 104b'. A circle 116 highlights the area between edge 104b' and the nearest adjacent electrode track of contact surface 104b', the lower electrode track 106f. Edge 104b' is linear and aligned parallel to the upper electrode track 106f. Thus, the distances between the respective points along the length of edge 104b' and the length of electrode track 106a are equal, i.e., the distance is constant along the lengths. This distance is at least 2∗2∗(row registration capability). This is illustrated by the two arrows, each representing a distance measured between a set of respective points along the length of edge 104b' and the length of electrode track 106f. The distances are measured perpendicular to the lengths of edge 104b' and electrode track 106f, as this corresponds to the shortest distance between respective points along these lengths.

[0024] When you get back Fig. 1C, which shows an enlarged view of section B of Fig. Given that 1A is the case, one edge of the contact surface 104c is labeled 104c'. The nearest adjacent electrode track of the contact surface 104c is the lower electrode track 106j. The edge 104c' is linear, although due to the 45° orientation of the grid pattern of the multiple electrodes 106a-j, the edge 104c' is not aligned parallel to the length of the lower electrode track 106j. However, the distance between a nearest pair of respective points along the length of the edge 104c' and the length of the lower electrode track 106j is determined by the Fig. The arrow contained in 1C indicates this distance. 2∗2∗(row registration capability).

[0025] When you get back Fig. 1A, the contact surface 104d also has a linear edge 104d' which is configured to have a distance of at least 2∗2∗(row registration capability) to its nearest adjacent electrode track, the upper electrode track 106e. Furthermore, the linear edge 104d' is aligned parallel to the upper electrode track 106e. The contact surface 104g has a linear edge 104g' configured to have a distance of at least 2∗2∗(row registration capability) to its nearest adjacent electrode track, the upper electrode track 106a. Furthermore, the linear edge 104g' is aligned parallel to the upper electrode track 106a. The contact surface 104h has a linear edge 104h' configured to have a distance of at least 2∗2∗(row registration capability) to its nearest adjacent electrode track, the upper electrode track 106e. The contact surface 104i has a linear edge 104i' configured to have a distance of at least 2∗2∗(row registration capability) to its nearest adjacent electrode track, the lower electrode track 106j. In addition, the linear edge 104i' is aligned parallel to the lower electrode track 106j.

[0026] In summary, the device 100 has four unmodified contact surfaces, the rectangular contact surfaces 104a, e, f, j and six modified contact surfaces, the irregular pentagonal contact surfaces 104b-d and gi.

[0027] A roller comprising printed electronic devices configured according to the embodiment of device 100 was manufactured according to the method described below. In particular, a printing system was used comprising a printing device configured for gravure printing of silver (for the multiple electrode tracks), a printing device configured for extrusion coating of a ferroelectric material (for the ferroelectric layer), and a printing device configured for rotary screen printing of carbon (for the multiple contact surfaces). A roller comprising comparable printed electronic devices was manufactured using the same printing system and the same method, but each of the contact surfaces was configured as a rectangle, i.e., as contact surfaces 104a, e, f, j, such that all contact surfaces 104a-jh had the same shape, size, and surface area. Rollers generally have between 200.000 and 1,000,000 printed electronic devices were tested. Performance was evaluated as follows. A sample set of memory cells (1400 memory cells) in the devices of each drum was tested for short-circuit faults, a common failure mode for printed electronic devices. Commercially available ohmmeters can be used to test for short-circuit faults. The higher the percentage of cells exhibiting short-circuit faults, the lower the performance. In the sample set of the drum containing comparable printed electronic devices, 84.8% of the cells showed short-circuit faults. In contrast, in the sample set of the drum containing printed electronic devices according to the embodiment of Device 100, only 27.3% of the cells showed short-circuit faults.Thus, the performance of printed electronic devices according to the embodiment of device 100 is increased by more than a factor of 3 compared to comparable printed electronic devices. This performance improvement of more than a factor of 3 is extremely significant from an economic perspective.

[0028] A top view of another illustrative printed electronic device 200 is shown in Fig. Figure 2A shows an outline illustrating the edge of a substrate 202 on which the layers of the device 200 are shown. The device 200 is similar to the device 100 of Fig. 1A configured, except that the device 200 comprises two additional contact surfaces, two additional electrode tracks, and thus additional memory cells (in this embodiment, 11). In particular, the device 200 comprises multiple contact surfaces 204a-l arranged in a pair of linear arrangements. The device 200 further comprises multiple electrode tracks 206a-l arranged in a grid pattern, the grid pattern being positioned between the two linear arrangements of contact surfaces and oriented at 45 degrees with respect to the process and transverse directions. Each electrode track of tracks 206a-l is electrically connected to an associated contact surface of contact surfaces 204a-l. The multiple electrode tracks 206a-l include both upper electrode tracks 206a-f and lower electrode tracks 206g-l.Sections of both the upper and lower electrode tracks 206a-f and gl are configured as strips to form the grid pattern, with the remaining sections extending linearly to their associated contact surfaces. In this embodiment, however, the upper and lower electrode tracks 206a-f and g-1 extend to electrode surfaces positioned on an associated contact surface. One such electrode surface 207a is marked. Electrode surfaces are useful for improving the electrical contact between the electrode surfaces and their associated contact surfaces. In this embodiment, the electrode surfaces have a rectangular shape, but other shapes and sizes can also be used.

[0029] As mentioned above, each memory cell of the multiple memory cells is formed at an intersection of a pair of electrode tracks of the multiple electrode tracks 206a-l. Such an intersection is labeled 208. Although not shown, a cross-sectional view of memory cell 208 would be similar to that of the one in Fig. The memory cell 108 shown in 1D looks like this. In the embodiment of Fig. However, device 2A comprises 36 memory cells, which are arranged as a 6×6 matrix due to the additional two electrode tracks.

[0030] Returning to the multiple contact surfaces 204a-l, the printed electronic device 200 comprises contact surfaces 204a, f, g, 1 (non-modified contact surfaces) that have a rectangular shape, each defining four 90° angles. The device 200 also includes contact surfaces 204b-e and hk (modified contact surfaces) with a reduced surface area and a different, non-rectangular shape compared to contact surfaces 204a, f, g, 1. Although all modified contact surfaces 204b-e and hk have a polygonal shape, in this embodiment they do not all have the same polygonal shape. In particular, contact surfaces 204b, e, h, k each have an irregular pentagonal shape, while contact surfaces c, d, i, j each have an irregular hexagonal shape. As with device 100 of Fig. 1A, contact surfaces 204b, e, h, k each have three angles of 90°, two angles greater than 90°, and five sides of unequal length. However, contact surfaces 204c, d, i, j each have only two angles of 90°, four angles greater than 90°, four sides of unequal length, and two sides of equal length.

[0031] Although other shapes can be used for the contact surfaces 204b-e and hk, as in Fig. As shown in Figure 2A, each contact surface has an edge configured such that there is a distance between the edge and the nearest adjacent electrode track of at least 2∗2∗(row registration capability) is. In particular, the contact surfaces 204b, e, h, k are similar to the contact surfaces 104b, d, g, i of the device 100 of Fig. 1A configured. However, the contact surfaces 204c, d, i, j each have an edge configured such that a distance between an edge and the nearest adjacent electrode track is also at least 2∗2∗(row registration capability) amounts.

[0032] When you get back Fig. Turning to Figure 2B, which is an enlarged view of section C, the contact surface 204c is shown with a nearest adjacent electrode track, a lower electrode track 2061, and a nearest adjacent electrode track, the lower electrode track 206h. One edge 204c' is linear and the distance (indicated by the arrow) is at least 2∗2∗(row registration capability). Another edge 204c'' is linear and is also parallel with respect to the lower electrode track 206h. The distance (indicated by the arrows) between edge 204c'' and the lower electrode track 206h is also at least 2∗2∗(row registration capability) It is noted that if the lower electrode tracks 206h and 2061 were arranged equally close to the contact surface 204c, both edges 204c' and 204c'' could be considered as the "nearest adjacent electrode tracks".

[0033] As described above, contact pads arranged in linear configurations and electrode tracks arranged in a grid pattern can be used to form a matrix of memory cells. However, other configurations and patterns can also be used. For example, contact pads can be arranged in circular or matrix patterns and occupy multiple lateral positions over an underlying substrate with respect to the electrode tracks and memory cells. Additionally, by a suitable configuration of electrode tracks, memory cells can be arranged to form linear configurations, e.g., using a single (1) common lower electrode and N parallel upper electrodes oriented orthogonally to the lower electrode (i.e., a linear 1×N arrangement). The matrix arrangements described in Fig. 1A and Fig.Figure 2A shows illustrative N×N matrix arrangements, featuring N upper electrode tracks and N lower electrode tracks. However, odd numbers of upper and lower electrode tracks can be used, e.g., M lower electrode tracks and N upper electrode tracks, to form an M×N matrix arrangement. Additionally, as mentioned above, the orientation of the pattern of multiple electrode tracks relative to the multiple contact surfaces can vary. Furthermore, the segments of the electrode tracks extending from the memory cells to their associated contact surfaces can take multiple paths.

[0034] The materials used for the various layers of a printed electronic device depend on the application and the specific function of each layer. Examples of substrate materials include silicon, glass, polymers, paper, etc. Examples of electrode track / electrode layer materials include metals, such as silver, or conductive polymers, such as polyethylene dioxythiophene. Examples of ferroelectric layer materials include ferroelectric polymers, such as a copolymer of polyvinylidene fluoride and trifluoroethylene. Printed electronic devices may also include other layers, such as insulating polymers (e.g., acrylic-based polymers) placed between the substrate and the lower electrode tracks. These layers improve planarity and adhesion.A protective layer can be applied as the top layer to a printed electronic device to prevent contamination, oxidation, UV degradation, physical wear, and other damage. These protective layers can consist of various sublayers made from different compositions. A top sublayer can be made from a curable polymer (e.g., polyester, polyether). Examples of materials used as an underlying sublayer of a protective layer include polypropylene glycol (PPG), silicone rubber, natural rubber, and polyvinyl acetate and acrylate-based resins.

[0035] Apart from the requirements regarding the spacing values ​​described above, other dimensions of the features of the printed electronic devices, as well as the overall dimensions of the printed electronic devices, can be selected depending on the application and the number of memory cells. The printed electronic devices can be used in a variety of applications, including product authentication applications for print cartridges, event tickets, credit cards, etc.

[0036] Methods for manufacturing the disclosed printed electronic devices are also provided. The methods are carried out on printing systems comprising one or more printing devices configured for printing on layers of material using a thin-film printing technique, such as inkjet printing, screen printing, flexographic printing, offset printing, electrographic printing, gravure printing, extrusion coating, etc. Since different layers of material can be printed using different techniques, the printing system may include several different types of printing devices. The printing devices used in the printing system may be characterized by a line registration capability. The line registration capability may be at least 50 µm, at least 75 µm, at least 100 µm, at least 150 µm, at least 200 µm, at least 250 µm, or in the range of 50 µm to 300 µm.The processes involve sequentially printing the material layers of the desired printed electronic device from bottom to top, layer by layer.

[0037] In embodiments, a method for manufacturing a printed electronic device comprises the following: printing multiple lower electrode tracks onto a substrate; printing a layer of a ferroelectric material onto the multiple lower electrode tracks; printing multiple upper electrode tracks onto the layer of ferroelectric material, wherein the multiple lower and upper electrode tracks form multiple electrode tracks arranged in a pattern and define multiple memory cells, each memory cell being located at an intersection of a pair of electrode tracks of the multiple electrode tracks; and printing the multiple contact pads onto the multiple upper electrode tracks, wherein the multiple contact pads are arranged in another pattern and each electrode track of the multiple electrode tracks is in electrical contact with an associated contact pad of the multiple contact pads.In this process, the multiple electrode tracks, multiple contact pads, and multiple memory cells that are printed can be arranged in one of the corresponding patterns described above. In this process, the multiple printed contact pads comprise one or more of the modified contact pads and one or more of the unmodified contact pads, as described above.

[0038] Methods for using a printed electronic device are also provided. In embodiments, such a method includes contacting multiple contact pads of a printed electronic device with multiple pins of a read / write unit. This contact enables the application of voltage waveforms to control the reading / writing of the multiple memory cells and to detect the state of the memory cells during the reading process. Any of the printed electronic devices disclosed herein can be used. The configuration of the read / write unit is not particularly restricted, provided that the multiple pins are arranged in a pattern that corresponds to the pattern of the multiple contact pads of the printed electronic device. Commercially available read / write units can be used.

Claims

[1] Printed electronic device comprising the following: several contact surfaces arranged in a pattern (104), several electrode tracks (106a-j) arranged in a different pattern, wherein the several electrode tracks comprise a set of lower electrode tracks (106f-g) and a set of upper electrode tracks (106a-e), each electrode track being in electrical contact with an associated contact surface (104a-j) of the several contact surfaces, and multiple memory cells, each memory cell being located at an intersection of a pair of electrode tracks of the multiple electrode tracks and comprising: a lower electrode layer (112) formed from a region of one of the lower electrode tracks, an upper electrode layer (110) formed from a region of one of the upper electrode tracks, and a ferroelectric layer (114) between the lower and the upper electrode layer, wherein the multiple contact surfaces comprise at least one unmodified contact surface having a surface, shape and size, wherein the multiple contact surfaces further comprise at least one modified contact surface having a reduced surface area, a different size or a different shape compared to the at least one unmodified contact surface, wherein one end of each electrode track of the multiple electrode tracks extends linearly to the associated contact surface and wherein the at least one modified contact surface has an edge that is aligned linearly and parallel to a nearest adjacent electrode track, and wherein the at least one modified contact surface has a non-rectangular polygonal shape and the at least one non-modified contact surface has a rectangular shape. [2] Device according to claim 1, wherein the at least one modified contact surface has a non-rectangular polygonal shape. [3] Device according to claim 2, wherein the at least one modified contact surface has an irregular, non-rectangular, polygonal shape. [4] Device according to claim 3, wherein the at least one modified contact surface has an irregular pentagonal shape. [5] Device according to claim 3, wherein the at least one modified contact surface has an irregular hexagonal shape. [6] Device according to claim 1, wherein the multiple contact surfaces comprise multiple modified contact surfaces, comprising at least one irregular pentagonal contact surface and at least one irregular hexagonal contact surface. [7] Device according to claim 1, wherein the at least one non-modified contact surface has a rectangular shape. [8] Device according to claim 1, wherein the at least one modified contact surface has an edge configured such that the distance between the edge and the nearest adjacent electrode track is at least 2*√2*(row registration capability). [9] Device according to claim 1, wherein the at least one modified contact surface has an edge configured such that the distance between the edge and the nearest adjacent electrode track is at least 500 µm. [10] Device according to claim 1, wherein an end of each electrode track of the multiple electrode tracks extends linearly to the associated contact surface and wherein the at least one modified contact surface has an edge that is aligned linearly and parallel to a nearest adjacent electrode track. [11] Device according to claim 10, wherein the at least one modified contact surface has a non-rectangular polygonal shape. [12] Device according to claim 11, wherein the at least one modified contact surface has an irregular, non-rectangular polygonal shape. [13] Device according to claim 1, wherein the multiple contact surfaces are arranged in two linear arrangements which extend parallel to each other and define a gap between them, and wherein the multiple electrode tracks are arranged in a grid pattern which is positioned in the gap. [14] Device according to claim 1, wherein the at least one modified contact surface has an irregular, pentagonal shape. [15] Several electronic devices comprising a substrate and several electronic devices on the substrate, each device being configured according to the device of claim 1. [16] Method for manufacturing a printed electronic device, the method comprising: Printing multiple lower electrode tracks onto a substrate; Printing a layer of ferroelectric material onto the multiple lower electrode tracks; Printing multiple upper electrode tracks onto the layer of ferroelectric material, wherein the multiple lower and upper electrode tracks form multiple electrode tracks arranged in a pattern and define multiple memory cells, each memory cell being located at an intersection of a pair of electrode tracks of multiple electrode tracks; and Printing multiple contact surfaces onto the multiple electrode tracks, wherein the multiple contact surfaces are arranged in a different pattern and each electrode track of the multiple electrode tracks is in electrical contact with an associated contact surface of the multiple contact surfaces, wherein the multiple contact surfaces comprise at least one unmodified contact surface having a surface, shape and size, wherein the multiple contact surfaces further comprise at least one modified contact surface having a reduced surface area, a different size or a different shape compared to the at least one unmodified contact surface, wherein one end of each electrode track of the multiple electrode tracks extends linearly to the associated contact surface and wherein the at least one modified contact surface has an edge that is aligned linearly and parallel to a nearest adjacent electrode track, and wherein the at least one modified contact surface has a non-rectangular polygonal shape and the at least one non-modified contact surface has a rectangular shape. [17] Method for using a printed electronic device, wherein the method comprises contacting multiple contact surfaces of a printed electronic device with multiple pins of a read / write unit, wherein the electronic device comprises: several contact surfaces arranged in a pattern, several electrode tracks arranged in a different pattern, wherein the several electrode tracks comprise a set of lower electrode tracks and a set of upper electrode tracks, each electrode track being in electrical contact with an associated contact surface of the several contact surfaces, and multiple memory cells, each memory cell being located at an intersection of a pair of electrode tracks of the multiple electrode tracks and comprising: a lower electrode layer formed from a region of one of the lower electrode tracks, an upper electrode layer formed from a region of one of the upper electrode tracks, and a ferroelectric layer between the lower and upper electrode layers, wherein the multiple contact surfaces comprise at least one unmodified contact surface having a surface, shape and size, wherein the multiple contact surfaces further comprise at least one modified contact surface having a reduced surface area, a different size or a different shape compared to the at least one unmodified contact surface, wherein one end of each electrode track of the multiple electrode tracks extends linearly to the associated contact surface and wherein the at least one modified contact surface has an edge that is aligned linearly and parallel to a nearest adjacent electrode track, and wherein the at least one modified contact surface has a non-rectangular polygonal shape and the at least one non-modified contact surface has a rectangular shape.

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