SEMI-CONDUCTOR PACKAGES

Abstract

Semiconductor package (10), comprising: a package substrate (200S), including a substrate body (200); and a semiconductor chip (500C) mounted on the package substrate (200S), the package substrate (200S) includes the following: first, second and third pad-bonding sections (211, 212, 213) arranged on the substrate body (200), wherein the first pad-bonding section (211) is arranged between the second and third pad-bonding sections (212, 213); first, second and third via placement sections (231, 232, 233) which are arranged on the substrate body (200) to be spaced apart from the first, second and third pad bonding sections (211, 212, 213); a first connection trace section (251) extending to connect the first pad bonding section (211) to the first via placement section (231); a second connection trace section (252) which is connected to the second pad bonding section (212), wherein the second connection trace section (252) runs parallel to the first connection trace section (251); a first guard trace section (253) with an end section (253E) spaced apart from the third pad bonding section (213) and wherein the first guard trace section (253) extends to be arranged parallel to the first bonding trace section (251); a first interconnection plane section (271) spaced apart from the first via insertion section (231) and which delimits and electrically bypasses the first via insertion section (231) to connect the second interconnection trace section (252) to the first guard trace section (253), and which connects the second interconnection trace section (252) to the second via insertion section (232); and a second connection plane section (273) that connects the third pad bonding section (213) to the third via placement section (233).

Description

BACKGROUND 1. Area of ​​application

[0001] The present disclosure relates generally to semiconductor packages. 2. Description of the state of the art

[0002] Semiconductor packages can be configured to enclose a semiconductor chip mounted on a package substrate. The package substrate can include a circuit interconnect structure connected to the semiconductor chip. The circuit interconnect structure can be configured to include a ground line, a power line, and signal lines for transmitting electrical signals. Because high-speed semiconductor chips are required in high-performance electronic systems, high-frequency signals are transmitted via the signal lines of the circuit interconnect structure. The high-frequency signals have a relatively short wavelength, resulting in unwanted crosstalk between the high-frequency signals, leading to reliability issues.

[0003] US patent application US 2017 / 0 156 208 A1 describes a microelectronic system including a printed circuit board and a semiconductor package mounted on the printed circuit board. The printed circuit board includes a laminated core with an inner conductive layer and a build-up layer. The build-up layer includes an upper conductive layer. Micro-vias are arranged in the build-up layer to connect the upper conductive layer to the inner conductive layer. A power / ground ball pad array is arranged in the upper conductive layer. The array of power and ground ball pads includes power ball pads and ground ball pads arranged in an array with a fixed ball-pad pitch P. The array of power and ground ball pads includes a 4-ball pad unit area consisting of either one ground ball pad and three power ball pads or one power ball pad and three ground ball pads.The 4-ball pad unit area has a rectangular shape and a dimension of approximately 2Px2P. SUMMARY

[0004] According to one embodiment, a semiconductor package includes a package substrate having a substrate body and a semiconductor chip mounted on the package substrate. The package substrate includes first, second, and third pad bonding portions disposed on the substrate body, the first pad bonding portion being disposed between the second and third pad bonding portions, first to third via landing portions disposed on the substrate body and spaced apart from the first to third pad bonding portions, and a first connection trace portion extending to connect the first pad bonding portion to the first via landing portion.The package substrate further includes a second interconnect trace portion connected to the second pad bonding portion, the second interconnect trace portion being substantially parallel to the first interconnect trace portion, and a first guard trace portion having an end portion spaced from the third pad bonding portion and extending to be substantially parallel to the first interconnect trace portion. The package substrate also includes a first interconnect level portion spaced from the first via landing portion, surrounding and electrically bypassing the first via landing portion to connect the second interconnect trace portion to the first guard trace portion, and connecting the second interconnect trace portion to the second via landing portion.The package substrate additionally includes a second interconnect level portion connecting the third pad bonding portion to the third via landing portion. SHORT DESCRIPTION OF THE CHARACTERS

[0005] They show: Fig. 1 is a cross-sectional view illustrating a semiconductor package according to an embodiment. Fig. 2 is a plan view illustrating a circuit connection structure of a semiconductor package according to an embodiment. Fig. 3 is a cross-sectional view of a semiconductor package along a line X2-X2' of Fig. 2. Fig. 4 is a cross-sectional view of a semiconductor package along a line X3-X3' of Fig. 2. Fig. 5 is a plan view illustrating a circuit connection structure of a semiconductor package according to an embodiment. Fig. 6 is a plan view illustrating a circuit connection structure of a semiconductor package according to an embodiment. Fig. 7 is a block diagram illustrating an electronic system using a memory card with a semiconductor package according to one embodiment. Fig. 8 is a block diagram illustrating an electronic system including a semiconductor package according to one embodiment. DETAILED DESCRIPTION

[0006] The terms used herein may correspond to words selected in consideration of their functions in the embodiments, and the meanings of the terms may be interpreted to vary depending on ordinary skill in the art to which the embodiments belong. If the terms are defined in detail, they may be interpreted according to the definitions. Unless otherwise defined, the terms used herein (including technical and scientific terms) have the same meaning as generally understood by those with ordinary skill in the art to which the embodiments belong.

[0007] It should be understood that while the terms "first," "second," "third," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another and not to suggest or define a particular number or order of the elements.

[0008] It should also be understood that when an element or layer is described as being "on," "over," "below," "behind," or "outside" another element or layer, the element or layer may be in direct contact with the other element or layer, or intervening elements or layers may be present. Other words used to describe the relationship between elements or layers should be interpreted similarly (e.g., "between" versus "directly between" or "adjacent" versus "directly adjacent").

[0009] Spatially relative terms such as "beneath," "underneath," "below," "above," "upper," "highest," "lower," and the like may be used to describe an element and / or the relationship of a feature to other element(s) and / or feature(s), for example, as illustrated in the figures. It is understood that the spatially relative terms are intended to encompass various orientations of the device in use and / or operation, in addition to the orientation illustrated in the figures. For example, if the device in the figures is turned over, the elements described as being below and / or adjacent to other elements or features would then be oriented above the other elements or features. The device may be oriented differently (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein could be interpreted accordingly.

[0010] In the embodiments illustrated below, a semiconductor package may include electronic devices, such as semiconductor chips or semiconductor dies. The semiconductor chips or semiconductor dies may be obtained by separating a semiconductor substrate, such as a wafer, into a plurality of parts using a die-sawing process. The semiconductor chips may correspond to memory chips, logic chips (including application-specific integrated circuits (ASIC chips)), or system-on-chips (SoCs).The memory chips may include dynamic DRAM (Dynamic Random Access Memory) circuits, static SRAM (Static Random Access Memory) circuits, NAND (NAND Type Flash Memory) circuits, NOR (NOR Type Flash Memory) circuits, magnetic MRAM (Magnetic Random Access Memory) circuits, resistive ReRAM (Resistive Random Access Memory) circuits, ferroelectric FeRAM (Ferroelectric Random Access Memory) circuits, or PcRAM (Phase Change Random Access Memory) circuits integrated on the semiconductor substrate. The logic chips may include logic circuits integrated on the semiconductor substrate. The semiconductor package can be used in communication systems such as mobile phones, electronic systems related to biotechnology or healthcare, or portable electronic systems.

[0011] The same reference numbers refer to the same elements throughout the specification. Even if a reference number is not mentioned or described with reference to one figure, the reference number may be mentioned or described with reference to another figure. Even if a reference number is not shown in one figure, it may be mentioned or described with reference to another figure.

[0012] Fig. 1 shows a cross-sectional view illustrating a semiconductor package 10 according to one embodiment. Fig. Fig. 2 is a plan view illustrating a circuit connection structure 100 of a package substrate 200S used in the semiconductor package 10 of Fig. 1 is included. Fig. 1 shows a cross-sectional view of the semiconductor package 10 with a cross-sectional view along a line X1-X1' of Fig. 2. Fig. 3 shows a cross-sectional view of the semiconductor package 10 with a cross-sectional view along a line X2-X2' of Fig. 2. Fig. Fig. 4 shows a cross-sectional view of the semiconductor package 10 with a cross-sectional view along a line X3-X3' of Fig. 2.

[0013] With reference to Fig. 1, the semiconductor package 10 may be configured to include the package substrate 200S and a semiconductor chip 500C. The semiconductor chip 500C may include a chip body 500 in or on which an integration circuit is formed. Chip pads 510 may be disposed on a surface 501 of the chip body 500. The chip pads 510 may include signal pads that transmit data signals to the semiconductor chip 500C or the package substrate 200S, a ground pad that sends a ground voltage to the semiconductor chip 500C, and a power pad that transmits a power voltage to the semiconductor chip 500C.

[0014] The semiconductor chip 500C may be mounted on the package substrate 200S. The semiconductor chip 500C may be bonded to the package substrate 200S in a flip-chip configuration such that the die pads 510 of the semiconductor chip 500C face the package substrate 200S. The semiconductor chip 500C may be electrically connected to the package substrate 200S via internal connectors 560 located between the semiconductor chip 500C and the package substrate 200S. The internal connectors 560 may have unevenness. A passivation layer 540 may be disposed on the surface 501 of the chip body 500 to expose the die pads 510. The passivation layer 540 may be formed to include a dielectric layer.

[0015] The package substrate 200S may be a connecting element that electrically connects the semiconductor chip 500C to an external device (not shown). The package substrate 200S may be implemented with a printed circuit board (PCB) structure.

[0016] The package substrate 200S may be configured to enclose the substrate body 200. The substrate body 200 may include a dielectric layer. The substrate body 200 may have a first surface 201 on which the semiconductor chip 500C is disposed, and a second surface 203 opposite the semiconductor chip 500C. External leads 600 may be attached to the second surface 203 of the substrate body 200. The external leads 600 may be interconnecting elements for electrically connecting the semiconductor package 10 to an external device. The external leads 600 may be interconnecting elements, e.g., solder balls.

[0017] External connector landing portions 260 may be disposed on the second surface 203 of the substrate body 200. In this case, the external connectors 600 may be bonded to the external connector landing portions 260. The external connector landing portions 260 may be conductive patterns. A second dielectric layer 430 may be disposed on the second surface 203 of the substrate body 200 to expose the external connector landing portions 260. The second dielectric layer 430 may be formed to receive a solder resist layer.

[0018] Conductive vias 240 may be arranged to penetrate vertically into the substrate body 200. The conductive vias 240 may be electrically connected to the outer connector landing portions 260 arranged on the second surface 203 of the substrate body 200. The conductive vias 240 may each be arranged to overlap with the outer connector landing portions 260 in a plan view. Although not shown in the drawings, additional conductive connection trace portions may be arranged on the second surface 203 of the substrate body 200 to electrically connect the conductive vias 240 to the outer connector landing portions 260 when the conductive vias 240 are arranged laterally offset from the outer connector landing portions 260.

[0019] The circuit interconnection structure 100 may be disposed on the first surface 201 of the substrate body 200. The circuit interconnection structure 100 may include conductive patterns. The circuit interconnection structure 100 may be disposed to electrically connect the conductive vias 240 to the internal terminals 560. The circuit interconnection structure 100 may consist of conductive patterns that electrically connect the conductive vias 240 and the semiconductor chip 500C. A first dielectric layer 410 may be disposed on the first surface 201 of the substrate body 200 to expose portions of the circuit interconnection structure 100.

[0020] With reference to the Fig. 1 and Fig. 2, the circuit connection structure 100 arranged on the first surface 201 of the substrate body 200 may be configured to receive first to fifth pad bonding sections 211, 212, 213, 214, and 215. The first to fifth pad bonding sections 211, 212, 213, 214, and 215 may be conductive patterns. The third, first, second, fourth, and fifth pad bonding sections 213, 211, 212, 214, and 215 may be arranged sequentially in a first row, which may include the line X1-X1' of Fig. 2. The circuit interconnection structure 100 may further include a plurality of sixth pad bonding portions 217, and the sixth pad bonding portions 217 may be sequentially arranged in a second row spaced apart from the first row. The sixth pad bonding portions 217 may be arranged to oppose the third, first, second, fourth, and fifth pad bonding portions 213, 211, 212, 214, and 215, respectively.

[0021] The third, first, second, fourth, and fifth pad bonding portions 213, 211, 212, 214, and 215 may each be electrically connected to the corresponding chip pads 510 of the semiconductor chip 500C. The sixth pad bonding portions 217 may also each be electrically connected to the corresponding chip pads 510 of the semiconductor chip 500C. The third, first, second, fourth, and fifth pad bonding portions 213, 211, 212, 214, and 215 and the sixth pad bonding portions 217 may each be arranged at positions that overlap with the chip pads 510 of the semiconductor chip 500C in a plan view. The third, first, second, fourth, and fifth pad bonding portions 213, 211, 212, 214, and 215 and the sixth pad bonding portions 217 may be electrically connected to the chip pads 510 of the semiconductor chip 500C via the inner connectors 560, respectively.

[0022] The first to fourth via contact portions 231, 232, 233, and 234 may be arranged on the first surface 201 of the substrate body 200 to form a portion of the circuit connection structure 100. The first to fourth via contact portions 231, 232, 233, and 234 may be arranged to be spaced apart from the first to sixth pad bonding portions 211, 212, 213, 214, 215, and 217 in a plan view. The first to fourth via contact portions 231, 232, 233, and 234 may be arranged to be aligned with the conductive vias (240 of Fig. 1) to overlap. As for example in Fig. 1, the first via application portion 231 may be arranged to overlap with a first conductive via 241 included in the conductive vias 240 and electrically connected to the first conductive via 241.

[0023] First to third connection trace sections 251, 252, and 254 and first and second guard trace sections 253 and 255 may be arranged on the first surface 201 of the substrate body 200 to form a portion of the circuit interconnection structure 100. The first to third connection trace sections 251, 252, and 254 and the first and second guard trace sections 253 and 255 may be line-shaped traces.

[0024] The first connection trace portion 251 may extend to connect the first pad bonding portion 211 to the first via landing portion 231. The second connection trace portion 252 may be connected to the second pad bonding portion 212 and arranged parallel to the first connection trace portion 251. The third connection trace portion 254 may extend to connect the fourth pad bonding portion 214 to the fourth via landing portion 234. The first to third connection trace portions 251, 252, and 254 may be arranged to be spaced apart from each other by a certain distance. The first to third connection trace portions 251, 252, and 254 may extend parallel to each other. In further embodiments, the trace sections may be arranged substantially parallel to one another.Essentially parallel means that the trace sections do not intersect or cross each other along their length.

[0025] The first guard trace portion 253 may be arranged such that an end portion 253E of the first guard trace portion 253 is spaced apart from and adjacent to the third pad bonding portion 213. The first guard trace portion 253 may extend parallel to the first connection trace portion 251. The first guard trace portion 253 may be arranged on a side of the first connection trace portion 251 opposite the second connection trace portion 252. The first guard trace portion 253 and the first connection trace portion 251 may be arranged adjacent to each other to be spaced apart from each other by a certain distance. The second guard trace portion 255 may be arranged such that an end portion 255E of the second guard trace portion 255 is spaced apart from and adjacent to the fifth pad bonding portion 215.The second guard trace section 255 may extend parallel to the third connection trace section 254. The second guard trace section 255 may be arranged on a side of the third connection trace section 254 opposite the second connection trace section 252.

[0026] First and second interconnect level sections 271 and 273 may be disposed on the first surface 201 of the substrate body 200 to form a portion of the circuit interconnect structure 100. The first and second interconnect level sections 271 and 273 may be conductive patterns, each having a relatively large planar area compared to the interconnect trace sections 251, 254 and the guard trace sections 253, 255. The first and second interconnect level sections 271 and 273 may be conductive patterns that are electrically isolated from the via landing sections 231 and 234.

[0027] In one embodiment, the first interconnect level portion 271 may be arranged to be spaced apart from the first via landing portion 231 by a certain distance. The first interconnect level portion 271 may be arranged to partially define the first via landing portion 231 in a plan view. The first interconnect level portion 271 may extend to connect the second interconnect trace portion 252 to the first guard trace portion 253 and to electrically bridge or bypass the first via landing portion 231. The first interconnect level portion 271 may further extend to connect the second interconnect trace portion 252 to the second via landing portion 232. The first interconnect level portion 271 may be a conductive pattern that includes the second via landing portion 232.That is, the second via landing portion 232 may correspond to a portion of the first interconnect level portion 271.

[0028] The first interconnect level portion 271 may additionally extend to be spaced apart from the fourth via landing portion 234. The first interconnect level portion 271 may extend to partially encompass and electrically bridge or bypass the fourth via landing portion 234 in a plan view. The first interconnect level portion 271 may extend to connect the second interconnect trace portion 252 to the second guard trace portion 255. The first interconnect level portion 271 may electrically connect the first and second guard trace portions 253 and 255 to the second via landing portion 232.

[0029] The second interconnect level portion 273 may be arranged to connect the third pad bonding portion 213 to the third via landing portion 233. The second interconnect level portion 273 may be configured to enclose the third via landing portion 233. That is, the third via landing portion 233 may correspond to a portion of the second interconnect level portion 273. The second interconnect level portion 273 may extend such that a side surface 273S of the second interconnect level portion faces the first, second, and fourth pad bonding portions 211, 212, and 214. The second interconnect level portion 273 may further extend to connect the fifth pad bonding portion 215 to the third via landing portion 233.The second interconnect level portion 273 may be arranged to be spaced apart from the first, second, and fourth pad bonding portions 211, 212, and 214 by a certain distance. For example, the second interconnect level portion 273 may partially surround and electrically bridge or bypass the first, second, and fourth pad bonding portions 211, 212, and 214, as shown in the top view of FIG. Fig. 2 shown.

[0030] With reference to Fig. 2, the first guard trace section 253 and the second connection trace section 252 may each be located on either side of the first connection trace section 251. As used herein for various embodiments, first and second sections each being located on either side of a third section means that the third section is located between the first and second sections. For example, the arrangement of the first guard trace section 253 and the second connection trace section 252 on either side of the first connection trace section 251 means that the first connection trace section 251 is located between the first guard trace section 253 and the second connection trace section 252. The second guard trace section 255 and the second connection trace section 252 may be located on either side of the third connection trace section 254.The first guard trace section 253, the first connection trace section 251, the second connection trace section 252, the third connection trace section 254, and the second guard trace section 255 may be arranged sequentially in a direction parallel to the first row. Accordingly, the third, first, second, fourth, and fifth pad bonding sections 213, 211, 212, 214, and 215 may also be arranged sequentially in the first row.

[0031] The first guard trace portion 253 and the second interconnect level portion 273 may be located on both sides of the third pad bonding portion 213, respectively. Furthermore, the first interconnect trace portion 251 and the second interconnect level portion 273 may be arranged on both sides of the first pad bonding portion 211. Since the first via contact portion 231 is connected to the first interconnect trace portion 251 and the third via contact portion 233 is connected to the second interconnect level portion 273, the first via contact portion 231 and the third via contact portion 233 may be arranged on both sides of the first pad bonding portion 211, respectively. As one embodiment, the first pad bonding portion 211 is located between the first via placement portion 231 and the third via placement portion 233.

[0032] The second connection trace portion 252 and the second connection level portion 273 may each be located on either side of the second pad bonding portion 212. Since the second connection trace portion 252 is connected to the second via landing portion 232 by the first connection level portion 271, the second via landing portion 232 and the third via landing portion 233 may be located on either side of the second pad bonding portion 212. For one embodiment, the second pad bonding portion 212 is located between the second via landing portion 232 and the third via landing portion 233.

[0033] The second connection-level portion 273 may be disposed between a first-row pad bonding portion including the first to fifth pad bonding portions 211, 212, 213, 214, and 215 arranged in the first row, and a second-row pad bonding portion including the sixth pad bonding portion 217 arranged in the second row. Thus, the first connection-level portion 271 and the second connection-level portion 273 may each be disposed on both sides of the first-row pad bonding portion including the first to fifth pad bonding portions 211, 212, 213, 214, and 215. For one embodiment, the first row in which the first to fifth pad bonding sections 211, 212, 213, 214, and 215 are arranged is located between the first interconnect level section 271 and the second interconnect level section 273.In some cases, the first sides of the first to fifth pad bonding sections 211, 212, 213, 214, and 215 are arranged opposite to or facing the first interconnect level 271 and the second via landing section 232. The second sides of the first to fifth pad bonding sections 211, 212, 213, 214, and 215 are arranged opposite to or facing the second interconnect level section 273 and the third via landing section 233.

[0034] With reference to the Fig. 1 and Fig. 2, the first pad bonding portion 211, the first connection trace portion 251, and the first via landing portion 231 may form a first data signal line. The first data signal line may be a signal line that transmits a data signal to the semiconductor chip 500C. The first data signal line may further include the first conductive via 241, a first outer connector landing portion 261 included in the outer connector landing portions 260, and a first outer connector 601 included in the outer connectors 600 connected in series to the first via landing portion 231. Likewise, a second data signal line may include the fourth pad bonding portion 214, the third connection trace portion 254, and the fourth via landing portion 234.

[0035] With reference to the Fig. 2 and Fig. 3, the second pad bonding portion 212, the second connection trace portion 252, the first connection level portion 271, and the second via application portion 232 may form a ground line. The ground line may provide an electrical path for providing a ground voltage to the semiconductor chip 500C. As shown in Fig. 4, the ground line may further include a second conductive via 242 enclosed within the conductive vias 240, a second outer connector landing portion 262 enclosed within the outer connector landing portions 260, and a second outer connector 602 enclosed within the outer connectors 600 connected in series to the second via landing portion 232. The first and second guard trace portions 253 and 255 may also be electrically connected to the ground line via the first interconnect level portion 271 to be grounded.

[0036] With reference to the Fig. 2 and Fig. 4, the third pad bonding portion 213, the second interconnect level portion 273, and the third via application portion 233 may form a first power line. The first power line may provide an electrical path for applying a power voltage to the semiconductor chip 500C. As shown in Fig. 3, the first power line may further include a third conductive via 243 enclosed within the conductive vias 240, a third external connector landing portion 263 enclosed within the external connector landing portions 260, and a third external connector 603 enclosed within the external connectors 600, which are connected in series to the third via landing portion 233. The fifth pad bonding portion 215, the second interconnect level portion 273, and the third via landing portion 233 may form a second power line.

[0037] With further reference to the Fig. 1 and Fig. 2, a data signal may be applied to the semiconductor chip 500C via the first data signal line including the first pad bonding section 211, the first connection trace section 251, and the first via application section 231. A change in an impedance value of a signal path including the first connection trace section 251 and the first via application section 231 may affect the transmission of a data signal transmitted through the first connection trace section 251 and the first via application section 231. However, according to the present embodiment, the entire first guard trace portion 253, the first interconnect level portion 271, and the second interconnect trace portion 252 surrounding an electrical path including the first interconnect trace portion 251 and the first via application portion 231 have the same ground potential.Thus, the impedance change of the signal path including the first connection trace section 251 and the first via application section 231 can be mitigated or suppressed.

[0038] The first guard trace section 253, the first interconnect level section 271, and the second interconnect trace section 252 may provide a continuous trace structure surrounding the first interconnect trace section 251 and the first via landing section 231. The first guard trace section 253 may extend parallel to the first interconnect trace section 251 and be connected to the first interconnect level section 271. The first interconnect level section 271 may extend to surround the first via landing section 231 and be connected to the second interconnect trace section 252. The second interconnect trace section 252 may extend to be arranged parallel to the first interconnect trace section 251.Thus, the first guard trace section 253, the first link level section 271 and the second link trace section 252 can be connected in series to provide a continuous trace structure.

[0039] The entire first guard trace section 253, the first interconnect level section 271, and the second interconnect trace section 252 may be grounded as described above. Consequently, the structure including the first guard trace section 253, the first interconnect level section 271, and the second interconnect trace section 252 may serve as a reference plane of the signal path including the first interconnect trace section 251 and the first via application section 231.Thus, the structure including the first guard trace section 253, the first interconnect level section 271, and the second interconnect trace section 252 can function as a continuous signal return path without a discontinuous region, or as a continuous current return path without a discontinuous region for a data signal transmitted over the signal path including the first interconnect trace section 251 and the first via application section 231.

[0040] As described above, no discontinuous region exists in the structure including the first guard trace section 253, the first interconnect-level section 271, and the second interconnect trace section 252. Thus, the occurrence of the abrupt impedance change of the signal path including the first interconnect trace section 251 and the first via application section 231 can be reduced, suppressed, or mitigated by the continuity of the structure including the first guard trace section 253, the first interconnect-level section 271, and the second interconnect trace section 252. Furthermore, the first guard trace section 253 and the first interconnect trace section 251 can extend to be adjacent and parallel to each other.Consequently, the impedance change of the signal path including the first connection trace portion 251 and the first via application portion 231 can be more significantly mitigated or suppressed.

[0041] If a discontinuous region exists in the structure including the first guard trace section 253, the first interconnect level section 271, and the second interconnect trace section 252, the discontinuous region may cause the abrupt impedance change of the signal path including the first interconnect trace section 251 and the first via application section 231. The abrupt impedance change of the signal path including the first interconnect trace section 251 and the first via application section 231 may affect the transmission of a data signal transmitted over the signal path including the first interconnect trace section 251 and the first via application section 231. This means that the abrupt impedance change of the signal path can disrupt the transmission of a data signal transmitted over the signal path.

[0042] A power signal with a logic "high" level may be supplied to the semiconductor chip 500C via the third pad bonding portion 213. A first data signal may be transmitted through the first pad bonding portion 211. A ground signal with a logic "low" level may be supplied to the semiconductor chip 500C via the second pad bonding portion 212. Thus, the first, second, and third pad bonding portions 211, 212, and 213 may function as a power pad, a signal pad, and a ground pad, respectively, and may be arranged to be adjacent to one another. That is, the first, second, and third pad bonding portions 211, 212, and 213 may be arranged to be substantially closest to one another. Accordingly, routing distances between the power signal, the data signal, and the ground signal applied to the semiconductor chip 500C can be reduced to improve an operating speed of the semiconductor chip 500C.

[0043] Buffer circuits for the data signals, the power signal and the ground signal can be integrated in or on the chip body (500 of Fig. 1) of the semiconductor chip (500C from Fig. 1). The buffer circuits can be configured to perform a switching operation. Since the power pad, signal pads, and ground pads are arranged side by side, the routing distances between the power line, data line, and ground line connected to the buffer circuits can be reduced. This can improve the operating speed of the buffer circuits.

[0044] With further reference to Fig. 2, the sixth pad bonding portions 217 arranged in the second row may be arranged to have a symmetrical configuration with the first to fifth pad bonding portions 211-215 arranged in the first row with respect to a straight line between the first and second rows. However, in some other embodiments, the sixth pad bonding portions 217 may be randomly arranged at arbitrary positions to have an asymmetrical configuration with the first to fifth pad bonding portions 211-215.

[0045] Although in Fig. 2 a third interconnect level portion 275 is arranged to have a symmetrical configuration to the first interconnect level portion 271 with respect to a straight line between the first and second rows, according to other embodiments the third interconnect level portion 275 could be arranged to have an asymmetrical configuration to the first interconnect level portion 271.

[0046] Although in Fig. 2, a third guard trace section 293 and a fourth guard trace section 295 are arranged to have a symmetrical configuration to the first and second guard trace sections 253 and 255 with respect to a straight line between the first and second rows, according to other embodiments, the third guard trace section 293 and the fourth guard trace section 295 may be arranged to have an asymmetrical configuration to the first and second guard trace sections 253 and 255.

[0047] Although in Fig. 2, a fourth connection trace section 291, a fifth connection trace section 292, and a sixth connection trace section 294 are arranged to have a symmetrical configuration to the first, second, and third connection trace sections 251, 252, and 254 with respect to a straight line between the first and second rows, according to other embodiments, the fourth connection trace section 291, the fifth connection trace section 292, and the sixth connection trace section 294 may be arranged to have an asymmetrical configuration to the first, second, and third connection trace sections 251, 252, and 254.

[0048] Although in Fig. 2, a fifth via landing section 281, a sixth via landing section 282, and a seventh via landing section 284 are arranged to have a symmetrical configuration to the first, second, and fourth via landing sections 231, 232, and 234 with respect to a straight line between the first and second rows, according to other embodiments, the fifth via landing section 281, the sixth via landing section 282, and the seventh via landing section 284 may be arranged to have a non-symmetrical configuration.

[0049] Fig. 5 shows a top view illustrating another circuit interconnection structure 1100 used in a semiconductor package, according to one embodiment.

[0050] With reference to Fig. 5, the circuit connection structure 1100 may include first to fifth pad bonding portions 1211, 1212, 1213, 1214, and 1215; first to third connection trace portions 1251, 1252, and 1254; first and second guard trace portions 1253 and 1255; first to fourth via landing portions 1231, 1232, 1233, and 1234; and first and second connection level portions 1271 and 1273.

[0051] The first pad bonding portion 1211, the first connection trace portion 1251, and the first via application portion 1231 may form a first data signal line. The fourth pad bonding portion 1214, the third connection trace portion 1254, and the fourth via application portion 1234 may form a second data signal line.

[0052] The second pad bonding section 1212, the second interconnect trace section 1252, the first interconnect level section 1271, and the second via application section 1232 may form a power line. The first and second guard trace sections 1253 and 1255 may also be electrically connected to the first interconnect level section 1271 to act as a power line section. When a first data signal is transmitted through the first via application section 1231 and the first interconnect trace section 1251, the first guard trace section 1253, the second interconnect trace section 1252, and the first interconnect level section 1271 may serve as a signal return path.The first guard trace section 1253, the second connection trace section 1252, and the first connection-level section 1271 may be provided to suppress the impedance change of the first connection trace section 1251 or to reduce the magnitude of the impedance change of the first connection trace section 1251. When a second data signal is transmitted through the fourth via application section 1234 and the third connection trace section 1254, the second guard trace section 1255, the second connection trace section 1252, and the first connection-level section 1271 may serve as a signal return path.The second guard trace section 1255, the second connection trace section 1252, and the first connection level section 1271 may be provided to suppress the impedance change of the third connection trace section 1254 or to reduce a magnitude of the impedance change of the third connection trace section 1254.

[0053] The third pad bonding portion 1213, the second interconnection level portion 1273, and the third via contact portion 1233 may form a first ground line. The fifth pad bonding portion 1215, the second interconnection level portion 1273, and the third via contact portion 1233 may form a second ground line.

[0054] Fig. 6 shows a top view illustrating another circuit interconnection structure 2100 used in a semiconductor package according to one embodiment.

[0055] With reference to Fig. 6, the circuit connection structure 2100 may include: first to fifth pad bonding sections 2211, 2212, 2213, 2214, and 2215; first to third connection trace sections 2251, 2252, and 2254; first and second guard trace sections 2253 and 2255; first to fourth via landing sections 2231, 2232, 2233, and 2234; and first and second connection level sections 2271 and 2273.

[0056] A first additional pad bonding portion 2218 may be connected to an end portion 2253E of the first guard trace portion 2253 to be arranged opposite the third pad bonding portion 2213. The first additional pad bonding portion 2218 may have substantially the same shape as the third pad bonding portion 2213, which is arranged opposite the first additional pad bonding portion 2218. An additional inner connector (not shown), for example, having the same shape as the inner connectors (560 of Fig. 1) can be connected to the first additional pad bonding section 2218. Thus, the first additional pad bonding section 2218 can be electrically connected to the semiconductor chip (500C of Fig. 1) can be connected.

[0057] A second additional pad bonding portion 2219 may be connected to an end portion 2255E of the second guard trace portion 2255 to be arranged opposite the fifth pad bonding portion 2215. The second additional pad bonding portion 2219 may have substantially the same shape as the fifth pad bonding portion 2215, which is arranged opposite the second additional pad bonding portion 2219. An additional inner connector (not shown), for example, having the same shape as the inner connectors (560 of Fig. 1) can be connected to the second additional pad bonding section 2219. Thus, the second additional pad bonding section 2219 can also be electrically connected to the semiconductor chip (500C of Fig. 1) can be connected.

[0058] Fig. 7 shows a block diagram illustrating an electronic system with a memory card 7800 using a semiconductor package according to an embodiment of the present disclosure. The memory card 7800 includes a memory 7810, such as a non-volatile memory device, and a memory controller 7820. The memory 7810 and the memory controller 7820 can store data or read the stored data. At least one of the memory 7810 and the memory controller 7820 can include a semiconductor package according to an embodiment.

[0059] Memory 7810 may include a non-volatile memory device to which the teachings of the embodiment of the present disclosure are applied. Memory controller 7820 may control memory 7810 to read stored data or store data in response to a read / write request from host 7830.

[0060] Fig. Figure 8 shows a block diagram illustrating an electronic system 8710 including a semiconductor package according to an embodiment of the present disclosure. The electronic system 8710 may include a controller 8711, an input / output device 8712, and a memory 8713. The controller 8711, the input / output device 8712, and the memory 8713 may be coupled together via a bus 8715, which provides a data path through which data moves.

[0061] In one embodiment, the controller 8711 may include one or more of a microprocessor, a digital signal processor, a microcontroller, and / or a logic device capable of performing the same functions as these components. The controller 8711 and / or the memory 8713 may include one or more of the semiconductor packages according to an embodiment of the present disclosure. The input / output device 8712 may include at least one of a keypad, a keyboard, a display device, a touchscreen, and so on. The memory 8713 is a device for storing data. The memory 8713 may store data and / or instructions to be executed by the controller 8711 and the like.

[0062] The memory 8713 may include a volatile memory device, such as DRAM, and / or a non-volatile memory device, such as flash memory. For example, flash memory may be attached to an information processing system, such as a mobile device or a desktop computer. The flash memory may be a solid-state disk (SSD). In this case, the electronic system 8710 can reliably store a large amount of data in a flash memory system.

[0063] The electronic system 8710 may further include an interface 8714 configured to send and receive data to and from a communications network. The interface 8714 may be wired or wireless. For example, the interface 8714 may include an antenna or a wired or wireless transceiver.

[0064] The electronic system 8710 can be implemented as a mobile system, a personal computer, an industrial computer, or a logic system that performs various functions. For example, the mobile system can be one of a personal digital assistant (PDA), a wearable computer, a tablet computer, a mobile phone, a smartphone, a cordless phone, a laptop computer, a memory card, a digital music system, and an information transmission / reception system.

[0065] When the electronic system 8710 represents equipment capable of performing wireless communication, the electronic system 8710 may be used in a communication system using a technology of CDMA (Code Division Multiple Access), GSM (Global System for Mobile Communications), NADC (North American Digital Cellular), E-TDMA (Enhanced Time Division Multiple Access), WCDMA (Wide Band Code Division Multiple Access), CDMA2000, LTE (Long Term Evolution) or Wibro (Wireless Broadband Internet).

[0066] A limited number of possible embodiments of the present disclosure have been disclosed for illustrative purposes. Those skilled in the art will recognize that various modifications, additions, and alternatives to the illustrated embodiments are possible without departing from the scope and spirit of the present disclosure and the appended claims.

Claims

[1] Semiconductor package (10) comprising: a package substrate (200S) including a substrate body (200); and a semiconductor chip (500C) mounted on the package substrate (200S), wherein the package substrate (200S) includes: first, second and third pad bonding sections (211, 212, 213) arranged on the substrate body (200), wherein the first pad bonding section (211) is arranged between the second and third pad bonding sections (212, 213); first, second and third via contacting portions (231, 232, 233) disposed on the substrate body (200) to be spaced apart from the first, second and third pad bonding portions (211, 212, 213); a first connection trace portion (251) extending to connect the first pad bonding portion (211) to the first via application portion (231); a second connection trace section (252) connected to the second pad bonding section (212), the second connection trace section (252) running parallel to the first connection trace section (251); a first guard trace portion (253) having an end portion (253E) spaced from the third pad bonding portion (213), the first guard trace portion (253) extending to be parallel to the first connection trace portion (251); a first connection level section (271) spaced from the first via application section (231) and surrounding and electrically bypassing the first via application section (231) to connect the second connection trace section (252) to the first guard trace section (253), and connecting the second connection trace section (252) to the second via application section (232); and a second connection level portion (273) connecting the third pad bonding portion (213) to the third via application portion (233). [2] The semiconductor package (10) of claim 1, wherein the first interconnect trace portion (251) is disposed between the first guard trace portion (253) and the second interconnect trace portion (252). [3] The semiconductor package (10) of claim 1, wherein the third pad bonding portion (213) is disposed between the first guard trace portion (253) and the second interconnect level portion (273). [4] The semiconductor package (10) of claim 1, wherein the first pad bonding portion (211) is disposed between the first interconnect trace portion (251) and the second interconnect level portion (273). [5] The semiconductor package (10) of claim 1, wherein the second pad bonding portion (212) is disposed between the second interconnect trace portion (252) and the second interconnect level portion (273). [6] The semiconductor package (10) of claim 1, wherein the first guard trace portion (253) is spaced apart from the first interconnect trace portion (251). [7] The semiconductor package (10) of claim 1, wherein the first interconnect level portion (271) is spaced apart from the first via landing portion (231). [8] The semiconductor package (10) according to claim 1, wherein the first, second and third pad bonding portions (211, 212, 213) are arranged between the first via contacting portion (231) and the third via contacting portion (233). [9] The semiconductor package (10) according to claim 1, wherein the first, second and third pad bonding portions (211, 212, 213) are arranged between the second via application portion (232) and the third via application portion (233). [10] The semiconductor package (10) according to claim 1, wherein the first, second and third pad bonding portions (211, 212, 213) are arranged between the first interconnection level portion (271) and the second interconnection level portion (273). [11] The semiconductor package (10) according to claim 1, wherein the first via application portion (231), the first connection trace portion (251) and the first pad bonding portion (211) form a data signal line for transmitting a data signal to the semiconductor chip (500C). [12] The semiconductor package (10) according to claim 11, wherein the second via application portion (232), the first interconnection level portion (271), the second interconnection trace portion (252) and the second pad bonding portion (212) form a ground line for supplying a ground voltage to the semiconductor chip (500C). [13] The semiconductor package (10) according to claim 12, wherein the third via application portion (233), the second interconnection plane portion (273) and the third pad bonding portion (213) form a power line for supplying a power voltage to the semiconductor chip (500C). [14] The semiconductor package (10) according to claim 11, wherein the second via application portion (232), the first interconnect level portion (271), the second interconnect trace portion (252) and the second pad bonding portion (212) form a power line for supplying a power voltage to the semiconductor chip (500C). [15] The semiconductor package (10) according to claim 14, wherein the third via application portion (233), the second interconnection plane portion (273) and the third pad bonding portion (213) form a ground line for supplying a ground voltage to the semiconductor chip (500C). [16] The semiconductor package (10) according to claim 1, further comprising an additional pad bonding portion (2218) connected to an end portion (253E) of the first guard trace portion (253) to be disposed opposite to the third pad bonding portion (213). [17] The semiconductor package (10) of claim 1, further comprising: fourth and fifth pad bonding sections (214, 215) arranged on the substrate body (200); a fourth via application portion (234) disposed on the substrate body (200) to be spaced apart from the fourth pad bonding portion (214); a third connection trace portion (254) extending to connect the fourth pad bonding portion (214) to the fourth via application portion (234); and a second guard trace section (255) having an end section (255E) spaced from the fifth pad bonding section (215), and wherein the second guard trace section (255) extends to be arranged parallel to the third connection trace section (254), wherein the first connection level section (271) is arranged at a distance from the fourth via contact section (234) and surrounds and electrically bypasses the fourth via contact section (234) to connect the second connection trace section (252) to the second guard trace section (255), and wherein the second connection level portion (273) connects the fifth pad bonding portion (215) to the third via application portion (233). [18] The semiconductor package (10) according to claim 17, wherein the first, second, third, fourth and fifth pad bonding portions (211, 212, 213, 214, 215) are arranged in a first row. [19] The semiconductor package (10) of claim 18, further comprising a plurality of sixth pad bonding portions (217) disposed on the substrate body (200) and arranged in a second row spaced from the first row, the second interconnect level portion (273) being disposed between the first row and the second row. [20] The semiconductor package (10) according to claim 19, wherein the third via landing portion (233) is disposed between the first row and the second row. [21] The semiconductor package (10) according to claim 17, wherein the second interconnection plane portion (273) has a side surface (273S) disposed facing the first, second and fourth pad bonding portions (211, 212, 214). [22] The semiconductor package (10) according to claim 17, wherein the fourth via application section (234), the third connection trace section (254) and the fourth pad bonding section (214) form an additional data signal line for supplying an additional data signal to the semiconductor chip (500C). [23] The semiconductor package (10) according to claim 22, wherein the second via application portion (232), the first interconnect level portion (271), the second interconnect trace portion (252) and the second pad bonding portion (212) form a ground line for supplying a ground voltage to the semiconductor chip (500C). [24] The semiconductor package (10) according to claim 23, wherein the third via application portion (233), the second interconnection plane portion (273) and the fifth pad bonding portion (215) form a power line for supplying a power voltage to the semiconductor chip (500C). [25] The semiconductor package (10) according to claim 22, wherein the second via application portion (232), the first interconnect level portion (271), the second interconnect trace portion (252) and the second pad bonding portion (212) form a power line for supplying a power voltage to the semiconductor chip (500C). [26] The semiconductor package (10) according to claim 25, wherein the third via application portion (233), the second interconnection plane portion (273) and the fifth pad bonding portion (215) form a ground line for supplying a ground voltage to the semiconductor chip (500C). [27] The semiconductor package (10) according to claim 1, wherein the semiconductor chip (500C) includes chip pads respectively connected to the first, second and third pad bonding portions (211, 212, 213) via internal connectors (560).

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