SEMI-CONDUCTOR PACKAGES

Abstract

Semiconductor package (10), comprising: a package substrate (200S), including a substrate body (200); and a semiconductor chip (500C) mounted on the package substrate (200S), the package substrate (200S) includes the following: first, second and third pad-bonding sections (211, 212, 213) arranged on the substrate body (200), wherein the first pad-bonding section (211) is arranged between the second and third pad-bonding sections (212, 213); first, second and third via placement sections (231, 232, 233) which are arranged on the substrate body (200) to be spaced apart from the first, second and third pad bonding sections (211, 212, 213); a first connection trace section (251) extending to connect the first pad bonding section (211) to the first via placement section (231); a second connection trace section (252) which is connected to the second pad bonding section (212), wherein the second connection trace section (252) runs parallel to the first connection trace section (251); a first guard trace section (253) with an end section (253E) spaced apart from the third pad bonding section (213), and wherein the first guard trace section (253) extends to be arranged parallel to the first bonding trace section (251); a first interconnection plane section (271) spaced apart from the first via insertion section (231) and which delimits and electrically bypasses the first via insertion section (231) to connect the second interconnection trace section (252) to the first guard trace section (253), and which connects the second interconnection trace section (252) to the second via insertion section (232); and a second interconnection plane section (273) connecting the third pad bonding section (213) to the third via insertion section (233), and enclosing the semiconductor chip (500C): a chip body (500); first inner chip pads (521) arranged on a surface of the chip body (500); first outer chip pads (511) arranged on the surface of the chip body (500) to be spaced apart from the first inner chip pads (521), which are arranged to overlap with the first to third pad-bonding sections (211, 212, 213) and are connected to the respective first to third pad-bonding sections (211, 212, 213); and first pad connection trace sections (531) that connect the first inner chip pads (521) to the first outer chip pads (511).

Description

BACKGROUND 1. Application area

[0001] The present disclosure relates generally to semiconductor packages. 2. Description of the state of the art

[0002] Each semiconductor package can be configured to enclose a semiconductor chip mounted on a package substrate. The package substrate can include a circuit interconnect structure connected to the semiconductor chip. The circuit interconnect structure can be configured to include a ground line, a power line, and signal lines for transmitting electrical signals. Because high-speed semiconductor chips are required in high-performance electronic systems, high-frequency signals are transmitted over the signal lines of the circuit interconnect structure. These high-frequency signals have a short wavelength, which leads to crosstalk between the high-frequency signals. Consequently, a method for suppressing interference between the signal lines may be necessary to provide reliable semiconductor chips.

[0003] US patent application US 2017 / 0156208A1 describes a microelectronic system comprising a printed circuit board and a semiconductor package mounted on the printed circuit board. The printed circuit board contains a laminated core with an inner conductive layer and a build-up layer. The build-up layer includes an upper conductive layer. Micro vias are arranged in the build-up layer to connect the upper conductive layer to the inner conductive layer. A power / ground ball pad array is arranged in the upper conductive layer. The power and ground ball pad array comprises power and ground ball pads arranged with a fixed ball pad spacing P. The power and ground ball pad array includes a 4-ball pad unit area consisting of either one ground ball pad and three power ball pads or one power ball pad and three ground ball pads.The 4-ball pad unit area has a rectangular shape and dimensions of approximately 2Px2P. SUMMARY

[0004] According to one embodiment, a semiconductor package includes a package substrate and a semiconductor chip mounted on the package substrate. The package substrate includes first, second, and third pad-bonding sections arranged on a substrate body, wherein the first pad-bonding section is located between the second and third pad-bonding sections; first to third via insertion sections arranged on the substrate body to be spaced apart from the first to third pad-bonding sections; a first interconnect trace section extending to connect the first pad-bonding section to the first via insertion section; a second interconnect trace section connected to the second pad-bonding section to be substantially parallel to the first interconnect trace section; and a first guard trace section with an end section.which is spaced from the third pad bonding section and extends to be substantially parallel to the first interconnect trace section, and a first interconnect plane section which is spaced from the first via insertion section. The first interconnect plane section electrically surrounds and bypasses the first via insertion section to connect the second interconnect trace section to the first guard trace section. Furthermore, the first interconnect plane section is arranged to connect the second interconnect trace section to the second via insertion section. A second interconnect plane section is arranged to connect the third pad bonding section to the third via insertion section. The semiconductor chip includes a chip body, first internal chip pads arranged on a surface of the chip body,and first outer chip pads, which are arranged on the surface of the chip body to be spaced apart from the first inner chip pads. The first outer chip pads are arranged to overlap with the first and third pad bonding sections. Furthermore, the first outer chip pads are connected to the respective first through third pad bonding sections. First pad connection trace sections connect the first inner chip pads to the first outer chip pads. BRIEF DESCRIPTION OF THE FIGURES Fig. 1 A cross-sectional view showing a semiconductor package according to one embodiment. Fig. 2 a top view showing the outer chip pads of a semiconductor package according to one embodiment. Fig. 3 A top view illustrating an example of a circuit interconnect structure contained in a semiconductor package according to one embodiment. Fig. 4 a cross-sectional view of a semiconductor package, a cross-sectional view along a line X2-X2' of Fig. Including 3. Fig. Figure 5 is a cross-sectional view of a semiconductor package, a cross-sectional view along a line X3-X3' of Fig. Including 3. Fig. Figure 6 is a top view illustrating an example of a circuit interconnect structure enclosed in a semiconductor package according to one embodiment. Fig. Figure 7 is a top view illustrating an example of a circuit interconnect structure contained in a semiconductor package according to one embodiment. Fig. Figure 8 is a block diagram illustrating an electronic system that uses a memory card with a semiconductor package according to one embodiment. Fig. Figure 9 is a block diagram illustrating an electronic system, including a semiconductor package according to one embodiment. DETAILED DESCRIPTION

[0005] The terms used herein may correspond to words chosen taking into account their functions in the embodiments, and the meanings of the terms may be interpreted differently according to ordinary abilities in the field to which the embodiments belong. Where the terms are defined in detail, they may be interpreted in accordance with those definitions. Unless otherwise defined, the terms used herein (including technical and scientific terms) have the same meaning as they are generally understood by someone with ordinary abilities in the field to which the embodiments belong.

[0006] It is understood that, although the terms "first", "second", "third", etc. may be used herein to describe various elements, these elements should not be restricted by these terms. These terms are used only to distinguish one element from another, not to define the element itself or to establish the meaning of a particular order.

[0007] It is also understood that when an element or layer is described as being "on," "above," "below," "behind," or "outside" another element or layer, the element or layer may be in direct contact with the other element or layer, or there may be intervening elements or layers. Other words used to describe the relationship between elements or layers should be interpreted similarly (e.g., "between" versus "directly between" or "adjacent" versus "directly adjacent").

[0008] Spatially relative terms such as "below," "under," "below," "above," "upper," "highest," "lower," and the like can be used to describe an element and / or the relationship of a feature to another element(s) and / or feature(s), as illustrated, for example, in the figures. It is understood that, in addition to the orientation shown in the figures, the spatially relative terms are intended to encompass various orientations of the device used and / or operated. For example, if the device in the figures is inverted, the elements described as below and / or beside other elements or features will then be oriented above those other elements or features. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatially relative descriptors used herein could be interpreted accordingly.

[0009] In the following embodiments, a semiconductor package can include electronic devices such as semiconductor chips or semiconductor dies. The semiconductor chips or semiconductor dies can be obtained by separating a semiconductor substrate, such as a wafer, into a multitude of parts using a die-sawing process. The semiconductor chips can correspond to memory chips, logic chips (including application-specific integrated circuits (ASIC chips)), or system-on-chips (SoCs).The memory chips can include dynamic DRAM (Dynamic Random Access Memory) circuits, static SRAM (Static Random Access Memory) circuits, NAND flash memory (NAND flash memory), NOR flash memory (NOR flash memory), magnetic MRAM (Magnetic Random Access Memory), resistive ReRAM (Resistive Random Access Memory), ferroelectric FeRAM (Ferroelectric Random Access Memory), or phase-change random access memory (PcRAM) circuits integrated on the semiconductor substrate. The logic chips can include logic circuits integrated on the semiconductor substrate. The semiconductor package can be used in communication systems such as mobile phones, electronic systems related to biotechnology or healthcare, or wearable electronic systems.

[0010] Identical reference numbers refer to the same elements throughout the entire specification. Even if a reference number is not mentioned or described with reference to a figure, it can be mentioned or described with reference to another figure. Even if a reference number is not shown in a figure, it can be mentioned or described with reference to another figure.

[0011] Fig. Figure 1 is a cross-sectional view showing a semiconductor package 10 according to one embodiment. Fig. Figure 2 is a top view showing the first outer chip pads 511 and second outer chip pads 512 of a semiconductor chip 500C enclosed in a semiconductor package 10 according to one embodiment. Fig. Figure 3 is a top view showing a circuit interconnect structure 100 of a package substrate 200S enclosed in a semiconductor package 10 according to an embodiment. Fig. 1 is a cross-sectional view along a line X1-X1' of Fig. 3. Fig. Figure 4 is a cross-sectional view of the semiconductor package 10, a cross-sectional view along a line X2-X2' of Fig. Including 3. Fig. Figure 5 is a cross-sectional view of the semiconductor package 10, a cross-sectional view along a line X3-X3' of Fig. Including 3.

[0012] With reference to the Fig. 1 and Fig. 2 The semiconductor package 10 can be configured to enclose the package substrate 200S and the semiconductor chip 500C. The semiconductor chip 500C can enclose a chip body 500 in or on which an integrated circuit is formed. First inner chip pads 521 can be arranged on a surface 501 of the chip body 500. Second inner chip pads 522 can be arranged on the surface 501 of the chip body 500, spaced apart from and opposite the first inner chip pads 521. A first dielectric layer 541 can be arranged on the surface 501 of the chip body 500 to expose the first and second inner chip pads 521 and 522. The first dielectric layer 541 can fill a space between the first and second inner chip pads 521 and 522 to electrically isolate the first and second inner chip pads 521 and 522 from each other.

[0013] The first outer chip pads 511 can be arranged on a surface of the first dielectric layer 541 opposite the chip body 500, in order to be spaced apart from the first inner chip pads 521 in a top view (see Fig. 2) The second outer chip pads 512 can be arranged on the surface of the first dielectric layer 541 opposite the chip body 500 to be spaced apart from the second inner chip pads 522 in a top view (see Fig. 2) As in Fig. As shown in Figure 2, the first and second inner chip pads 521 and 522 can be arranged between the first outer chip pads 511 and the second outer chip pads 512. A first distance d1 between the first inner chip pads 521 and the second inner chip pads 522 can be smaller than a second distance d2 between the first outer chip pads 511 and the second outer chip pads 512.

[0014] The first pad connection trace sections 531 can be arranged on the first dielectric layer 541 to connect the first inner chip pads 521 to the first outer chip pads 511. These first pad connection trace sections 531 can correspond to redistribution lines extending from the first inner chip pads 521 to the first outer chip pads 511. Second pad connection trace sections 532 can be arranged on the first dielectric layer 541 to connect the second inner chip pads 522 to the second outer chip pads 512. These second pad connection trace sections 532 can also correspond to redistribution lines extending from the second inner chip pads 522 to the second outer chip pads 512.

[0015] A second dielectric layer 542 can be arranged on the surface of the first dielectric layer 541 opposite the chip body 500 to cover the first and second pad interconnect trace sections 531 and 532. The second dielectric layer 542 can be arranged to expose the first and second outer chip pads 511 and 512.

[0016] The first and second outer chip pads 511 and 512 can serve as connections for applying electrical signals to the semiconductor chip 500C. The first and second outer chip pads 511 and 512 can include signal pads for applying electrical data signals to the semiconductor chip 500C, at least one ground pad for supplying a ground voltage to the semiconductor chip 500C, and at least one power pad for supplying a mains voltage to the semiconductor chip 500C.

[0017] The semiconductor chip 500C can be mounted on the package substrate 200S. The semiconductor chip 500C can be bonded to the package substrate 200S in a flip-chip configuration, such that the first and second outer chip pads 511 and 512 of the semiconductor chip 500C face the package substrate 200S. The semiconductor chip 500C can be electrically connected to the package substrate 200S via internal connectors 560 located between the semiconductor chip 500C and the package substrate 200S. The internal connectors 560 may have protrusions.

[0018] With reference to Fig. 1. The package substrate 200S can function as a connecting element that electrically connects the semiconductor chip 500C to an external device (not shown). The package substrate 200S can be configured to have a printed circuit board (PCB) structure.

[0019] The package substrate 200S can be configured to enclose a substrate body 200. The substrate body 200 can include a dielectric layer. The substrate body 200 can have a first surface 201 on which the semiconductor chip 500C is arranged, and a second surface 203 facing the semiconductor chip 500C. External terminals 600 can be attached to the second surface 203 of the substrate body 200. The external terminals 600 can be connecting elements for electrically connecting the semiconductor package 10 to an external device. The external terminals 600 can be connecting elements such as solder balls.

[0020] Outer connector attachment sections 260 can be arranged on the second surface 203 of the substrate body 200. In this case, the outer connectors 600 can be bonded to the outer connector attachment sections 260. The outer connector attachment sections 260 can be conductor patterns. A fourth dielectric layer 430 can be arranged on the second surface 203 of the substrate body 200 to expose the outer connector attachment sections 260. The fourth dielectric layer 430 can be formed to accommodate a solder resist layer.

[0021] Conductive vias 240 can be arranged to penetrate vertically into the substrate body 200. The conductive vias 240 can be electrically connected to the outer connector attachment sections 260, which are arranged on the second surface 203 of the substrate body 200. In one embodiment, the conductive vias 240 can be electrically connected one-to-one to the outer connector attachment sections 260, with each individual conductive via 240 being connected to a single outer connector attachment section 260. The conductive vias 240 can be arranged to overlap with the outer connector attachment sections 260 in a top view.Although not shown in the figures, conductive connection trace sections can additionally be arranged on the second surface 203 of the substrate body 200 to electrically connect the conductive vias 240 to the outer connector attachment sections 260 if the conductive vias 240 are arranged laterally offset to the outer connector attachment sections 260.

[0022] With reference to the Fig. 1 and Fig. 3. The circuit interconnection structure 100 can be arranged on the first surface 201 of the substrate body 200. The circuit interconnection structure 100 can include conductor patterns. The circuit interconnection structure 100 can be arranged to electrically connect the conductive vias 240 to the internal terminals 560. The circuit interconnection structure 100 can consist of conductor patterns that electrically connect the conductive vias 240 and the semiconductor chip 500C. A third dielectric layer 410 can be arranged on the first surface 201 of the substrate body 200 to expose sections of the circuit interconnection structure 100.

[0023] The circuit interconnection structure 100 can include first to fifth pad-bonding sections 211, 212, 213, 214, and 215 arranged on the first surface 201 of the substrate body 200. The first to fifth pad-bonding sections 211, 212, 213, 214, and 215 can be conductor patterns. The third, first, second, fourth, and fifth pad-bonding sections 213, 211, 212, 214, and 215 can be arranged sequentially in a first row forming the line X1-X1' of Fig. 3 intersects. The circuit interconnection structure 100 can further include a plurality of sixth pad-bonding sections 217, and the sixth pad-bonding sections 217 can be arranged sequentially in a second row spaced apart from the first row. The sixth pad-bonding sections 217 can be arranged such that they are each opposite the third, first, second, fourth, and fifth pad-bonding sections 213, 211, 212, 214, and 215, respectively. In one embodiment, the sixth pad-bonding sections 217 can be arranged such that they are opposite the third, first, second, fourth and fifth pad-bonding sections 213, 211, 212, 214 and 215 in a one-to-one ratio, with a single sixth pad-bonding section 217 opposite one of the pad-bonding sections of the third, first, second, fourth and fifth pad-bonding sections 213, 211, 212, 214 and 215.

[0024] The third, first, second, fourth and fifth pad-bonding sections 213, 211, 212, 214 and 215 can each be electrically bonded to the corresponding first outer chip pads (511 of Fig. 1) of the semiconductor chip 500C. In one embodiment, the third, first, second, fourth, and fifth pad-bonding sections 213, 211, 212, 214, and 215 are electrically connected to the corresponding first outer chip pads (511 of Fig. 1) One-to-one bonding, with a single pad-bonding section (i.e., 213) electrically bonded to a single first outer chip pad (i.e., a corresponding first outer chip pad 511). The sixth pad-bonding sections 217 can also each be electrically bonded to the corresponding second outer chip pads (512 of Fig. 1) of the semiconductor chip 500C. In one embodiment, the sixth pad-bonding sections 217 are electrically connected one-to-one to the corresponding second outer chip pads 512, with a single sixth pad-bonding section 217 being electrically connected to a single corresponding second outer chip pad 512. The third, first, second, fourth, and fifth pad-bonding sections 213, 211, 212, 214, and 215 can each be arranged at positions corresponding to the first outer chip pads (511 of Fig. 1) of the semiconductor chip 500C overlap in a top view. The sixth pad bonding sections 217 can each be arranged in positions corresponding to the second outer chip pads (512 of Fig. 1) of the semiconductor chip 500C overlap in a top view. The third, first, second, fourth, and fifth pad-bonding sections 213, 211, 212, 214, and 215, and the sixth pad-bonding section 217 can each be electrically connected to the first and second outer chip pads 511 and 512 of the semiconductor chip 500C via the inner connectors 560. In one embodiment, the third, first, second, fourth, and fifth pad-bonding sections 213, 211, 212, 214, and 215, and the sixth pad-bonding section 217 can be electrically connected one-to-one to the first and second outer chip pads 511 and 512 via the inner connectors 560, thereby forming a single pad-bonding section (i.e.,213) is electrically connected to a single first outer chip pad 511 via a single inner connector 560, and a single sixth pad bonding section 217 is electrically connected to a single second outer chip pad 512 via a single inner connector 560.

[0025] The first inner chip pads 521 of the semiconductor chip 500C can be arranged such that, viewed from a top view, they are spaced apart at a certain distance from the third, first, second, fourth and fifth pad bonding sections 213, 211, 212, 214 and 215. Although the first inner chip pads 521 of the semiconductor chip 500C do not overlap with the third, first, second, fourth, and fifth pad-bonding sections 213, 211, 212, 214, and 215 in a top view, the first inner chip pads 521 can be electrically connected to the respective third, first, first, fourth, and fifth pad-bonding sections 213, 211, 212, 214, and 215 via the first pad-connection trace sections 531 and the first outer chip pads 511. The second inner chip pads 522 of the semiconductor chip 500C can be arranged such that, viewed from a top view, they are spaced a certain distance from the sixth pad-bonding sections 217.The second inner chip pads 522 can be electrically connected to the respective sixth pad bonding sections 217 via the second pad connection trace sections 532 and the second outer chip pads 512.

[0026] The first and second outer chip pads 511 and 512 and the first and second pad-connection trace sections 531 and 532 enable the first to sixth pad-bonding sections 211, 212, 213, 214, 215, and 217 to be arranged at any position on the first surface 201 of the substrate body 200. Thus, the third, first, second, fourth, and fifth pad-bonding sections 213, 211, 212, 214, and 215 can be arranged laterally offset from the first inner chip pads 521 in a top view, and the sixth pad-bonding section 217 can be arranged laterally offset from the second inner chip pads 522 in a top view.Consequently, a third distance d3 between the first row, in which the first to fifth pad-bonding sections 211-215 are arranged, and the second row, in which the sixth pad-bonding sections 217 are arranged, can be designed to be larger than the first distance d1 between the first inner chip pads 521 and the second inner chip pads 522.

[0027] The first to fourth via-placement sections 231, 232, 233, and 234 can be arranged on the first surface 201 of the substrate body 200 to form a section of the circuit interconnect structure 100. The first to fourth via-placement sections 231, 232, 233, and 234 can be arranged so that, viewed from above, they are spaced apart from the first to sixth pad-bonding sections 213, 211, 212, 214, 215, and 217. The first to fourth via-placement sections 231, 232, 233, and 234 can be arranged so that they align with the conductive vias (240 of Fig. 1) overlap in a top view. As in, for example, Fig. As shown in Figure 1, the first via placement section 231 can be arranged to overlap with a first conductive via 241 enclosed in the conductive vias 240 and be electrically connected to the first conductive via 241.

[0028] The first to third connection trace sections 251, 252, and 254, and the first and second guard trace sections 253 and 255, can be arranged on the first surface 201 of the substrate body 200 to form a section of the circuit connection structure 100. The first to third connection trace sections 251, 252, and 254, and the first and second guard trace sections 253 and 255, can be linear conductor patterns.

[0029] The first trace section 251 can extend to connect the first pad bonding section 211 to the first via insertion section 231. The second trace section 252 can be connected to the second pad bonding section 212 and arranged parallel to the first trace section 251. The third trace section 254 can extend to connect the fourth pad bonding section 214 to the fourth via insertion section 234. The first to third trace sections 251, 252, and 254 can be spaced apart from each other at a specific distance. The first to third trace sections 251, 252, and 254 can extend parallel to each other. In one embodiment, the first to third connection trace sections 251, 252 and 254 can extend in such a way that they do not overlap.

[0030] The first guard trace section 253 can be arranged such that an end section 253E of the first guard trace section 253 is spaced apart from and adjacent to the third pad bonding section 213. The first guard trace section 253 can extend parallel to the first connecting trace section 251. The first guard trace section 253 can be located on one side of the first connecting trace section 251, opposite the second connecting trace section 252. The first guard trace section 253 and the first connecting trace section 251 can be arranged side by side, spaced apart from each other at a specific distance. The second guard trace section 255 can be arranged such that an end section 255E of the second guard trace section 255 is spaced apart from and adjacent to the fifth pad bonding section 215.The second guard trace section 255 can extend parallel to the third connecting trace section 254. The second guard trace section 255 can be located on one side of the third connecting trace section 254 opposite the second connecting trace section 252.

[0031] First and second interconnection plane sections 271 and 273 can be arranged on the first surface 201 of the substrate body 200 to form a section of the circuit interconnection structure 100. The first and second interconnection plane sections 271 and 273 can be conductor patterns, each of which has a large planar area compared to the planar areas of the first interconnection trace section 251 and the third interconnection trace section 254. The first and second interconnection plane sections 271 and 273 can be conductor patterns that are electrically isolated from the first and fourth via insertion sections 231 and 234.

[0032] In one embodiment, the first interconnection plane section 271 can be arranged to be spaced a certain distance from the first via placement section 231. The first interconnection plane section 271 can be arranged to partially enclose the first via placement section 231 in a top view. In another embodiment, the first interconnection plane section 271 can be arranged to be spaced at least a certain distance or more from the first via placement section 231 while partially enclosing it. The first interconnection plane section 271 can extend to connect the second interconnection trace section 252 to the first guard trace section 253, electrically bridging or bypassing the first via placement section 231.The first interconnection plane section 271 can further extend to connect the second interconnection trace section 252 to the second via insertion section 232. The first interconnection plane section 271 can be a conductor pattern that includes the second via insertion section 232. That is, the second via insertion section 232 can correspond to a section of the first interconnection plane section 271.

[0033] The first interconnection plane section 271 can additionally extend to be spaced apart from the fourth via-placement section 234. The first interconnection plane section 271 can extend to partially surround and electrically bridge or bypass the fourth via-placement section 234 in a top view. In one embodiment, the first interconnection plane section 271 can be arranged to be spaced apart from the fourth via-placement section 234 by at least a certain distance or more, while partially surrounding it. The first interconnection plane section 271 can extend to connect the second interconnection trace section 252 to the second guard trace section 255.The first interconnection level section 271 can electrically connect the first and second guard trace sections 253 and 255 to the second via insertion section 232.

[0034] The second interconnection plane section 273 can be arranged to connect the third pad-bonding section 213 to the third via-placement section 233. The second interconnection plane section 273 can be configured to include the third via-placement section 233. That is, the third via-placement section 233 can correspond to a section of the second interconnection plane section 273. The second interconnection plane section 273 can extend such that a side face 273S of the second interconnection plane section 273 faces the first, second, and fourth pad-bonding sections 211, 212, and 214, respectively. The second interconnection plane section 273 can further extend to connect the fifth pad-bonding section 215 to the third via-placement section 233.The second connection plane section 273 can be arranged such that it is spaced a certain distance apart from the first, second, and fourth pad-bonding sections 211, 212, and 214. For example, the second connection plane section 273 can partially surround and electrically bridge or bypass the first, second, and fourth pad-bonding sections 211, 212, and 214 in a top view.

[0035] With reference to Fig. 3. The first guard trace section 253 and the second connection trace section 252 can be located on either side of the first connection trace section 251. As used herein for various embodiments, first and second sections each located on either side of a third section mean that the third section is located between the first and second sections. For example, the first guard trace section 253 and the second connection trace section 252 located on either side of the first connection trace section 251 mean that the first connection trace section 251 is located between the first guard trace section 253 and the second connection trace section 252. The second guard trace section 255 and the second connection trace section 252 can each be located on either side of the third connection trace section 254.The first guard trace section 253, the first connecting trace section 251, the second connecting trace section 252, the third connecting trace section 254, and the second guard trace section 255 can be arranged sequentially in one direction parallel to the first row. Accordingly, the third, first, second, fourth, and fifth pad bonding sections 213, 211, 212, 214, and 215 can also be arranged sequentially in the first row.

[0036] The first guard trace section 253 and the second interconnection plane section 273 can each be located on either side of the third pad bonding section 213. Furthermore, the first interconnection trace section 251 and the second interconnection plane section 273 can each be located on either side of the first pad bonding section 211. Since the first via placement section 231 is connected to the first interconnection trace section 251 and the third via placement section 233 is connected to the second interconnection plane section 273, the first via placement section 231 and the third via placement section 233 can each be located on either side of the first pad bonding section 211.In one embodiment, the first via placement section 231 is located on the first sides of the first to third pad-bonding sections 211-213, and the third via placement section 233 is located on the second sides of the first to third pad-bonding sections 211-213, opposite the first via placement section 231. In another embodiment, the first to third pad-bonding sections 211-213 are located between the third via placement section 233 and the first via placement section 231.

[0037] The second connection trace section 252 and the second connection plane section 273 can each be located on either side of the second pad bonding section 212. Since the second connection trace section 252 is connected to the second via placement section 232 by the first connection plane section 271, the second via placement section 232 and the third via placement section 233 can each be located on either side of the second pad bonding section 212. In one embodiment, the second via placement section 232 is located on the first sides of the first to third pad bonding sections 211-213, and the third via placement section 233 is located on the second sides of the first to third pad bonding sections 211-213, opposite the second via placement section 232.In one embodiment, the first to third pad bonding sections 211-213 are located between the third via placement section 233 and the second via placement section 232.

[0038] The second bonding plane section 273 can be arranged between a first pad-bonding row section, consisting of the first to fifth pad-bonding sections 211, 212, 213, 214, and 215 arranged in the first row, and a second pad-bonding row section, consisting of the sixth pad-bonding sections 217 arranged in the second row. Thus, the first bonding plane section 271 and the second bonding plane section 273 can be arranged on either side of the first pad-bonding row section, which consists of the first to fifth pad-bonding sections 211, 212, 213, 214, and 215.In one embodiment, the first bonding plane section 271 is located on the first sides of the first to third pad-bonding sections 211-213, and the second bonding plane section 273 is located on the second sides of the first to third pad-bonding sections 211-213, opposite the first bonding plane section 271. In another embodiment, the first to third pad-bonding sections 211-213 are located between the first bonding plane section 271 and the second bonding plane section 273.

[0039] With reference to the Fig. 1 and Fig. 3. The first pad bonding section 211, the first trace section 251, and the first via insertion section 231 can form a first data signal line. The first data signal line can be a signal line that transmits a data signal to the semiconductor chip 500C. The first data signal line can further include the first conductive via 241, a first outer connector insertion section 261 enclosed within the outer connector insertion sections 260, and a first outer connector 601 enclosed within the outer connectors 600, which are connected in series with the first via insertion section 231. Likewise, a second data signal line can include the fourth pad bonding section 214, the third trace section 254, and the fourth via insertion section 234.

[0040] With reference to the Fig. 3 and Fig. 4. The second pad bonding section 212, the second connection trace section 252, the first interconnection plane section 271, and the second via insertion section 232 can form a ground trace. The ground trace can provide an electrical path for supplying a ground voltage to the semiconductor chip 500C. As shown in Fig. As shown in Figure 5, the ground line can further include a second conductive via 242 enclosed within the conductive vias 240, a second outer connector attachment section 262 enclosed within the outer connector attachment sections 260, and a second outer connector 602 enclosed within the outer connectors 600, which are connected in series with the second via attachment section 232. The first and second guard trace sections 253 and 255 can also be electrically connected to the ground line via the first grounding connection plane section 271.

[0041] With reference to the Fig. 3 and Fig. 5. The third pad-bonding section 213, the second interconnection layer section 273, and the third via-placement section 233 can form a first power line. The first power line can provide an electrical path for supplying a mains voltage to the semiconductor chip 500C. As shown in Fig. As shown in Figure 4, the first power line can further include a third conductive via 243, which is inserted into the conductive vias 240, a third outer connector insertion section 263, which is enclosed in the outer connector insertion sections 260, and a third outer connector 603, which is enclosed in the outer connectors 600, which are connected in series with the third via insertion section 233. The fifth pad bonding section 215, the second connection plane section 273, and the third via insertion section 233 can form a second power line.

[0042] With renewed reference to the Fig. 1 and Fig. 3. A data signal can be applied to the semiconductor chip 500C via the first data signal line, which includes the first pad bonding section 211, the first interconnect trace section 251, and the first via insertion section 231. A change in the impedance value of a signal path that includes the first interconnect trace section 251 and the first via insertion section 231 can affect the transmission of a data signal carried through the first interconnect trace section 251 and the first via insertion section 231. However, according to one embodiment, the entire first guard trace section 253, the first interconnection plane section 271 and the second interconnection trace section 252, which surrounds an electrical path including the first interconnection trace section 251 and the first via insertion section 231, have the same ground potential.Thus, the impedance change of the signal path, including the first connection trace section 251 and the first via insertion section 231, can be suppressed.

[0043] The first guard trace section 253, the first interconnection plane section 271, and the second interconnection trace section 252 can provide a continuous trace structure that surrounds the first interconnection trace section 251 and the first via insertion section 231. The first guard trace section 253 can extend parallel to the first interconnection trace section 251 and be connected to the first interconnection plane section 271. The first interconnection plane section 271 can extend to surround the first via insertion section 231 and can be connected to the second interconnection trace section 252. The second interconnection trace section 252 can extend to be arranged parallel to the first interconnection trace section 251.Thus, the first guard trace section 253, the first connection level section 271 and the second connection trace section 252 can be connected in series to provide a continuous trace structure.

[0044] The entire first guard trace section 253, the first interconnection plane section 271, and the second interconnection trace section 252 can be grounded as described above. Consequently, the structure encompassing the first guard trace section 253, the first interconnection plane section 271, and the second interconnection trace section 252 can serve as a reference plane for the signal path that includes the first interconnection trace section 251 and the first via insertion section 231.Thus, the structure, which includes the first guard trace section 253, the first interconnection level section 271 and the second interconnection trace section 252, can function as a continuous signal return path without a discontinuous area, or as a continuous current return path without a discontinuous area for a data signal that is transmitted via the signal path with the first interconnection trace section 251 and the first via insertion section 231.

[0045] As described above, the structure contains no discontinuous region encompassing the first guard trace section 253, the first interconnection plane section 271, and the second interconnection trace section 252. Therefore, the occurrence of the abrupt impedance fluctuation of the signal path, which includes the first interconnection trace section 251 and the first via insertion section 231, can be suppressed or mitigated by the continuity of the structure encompassing the first guard trace section 253, the first interconnection plane section 271, and the second interconnection trace section 252. Furthermore, the first guard trace section 253 and the first interconnection trace section 251 can extend in such a way that they lie adjacent to and parallel to each other.Consequently, the impedance change of the signal path, which includes the first connection trace section 251 and the first via insertion section 231, can be suppressed more significantly.

[0046] If a discontinuous area is present in the structure that includes the first guard trace section 253, the first interconnection plane section 271, and the second interconnect trace section 252, this discontinuous area can cause an abrupt impedance change in the signal path, including the first interconnect trace section 251 and the first via insertion section 231. This abrupt impedance change can affect the transmission of a data signal carried over the signal path. In other words, the abrupt impedance change can disrupt the transmission of a data signal carried over the signal path.

[0047] A power signal with a logical "high" level can be supplied to the semiconductor chip 500C via the third pad bonding area 213. A first data signal can be transmitted through the first pad bonding section 211. A ground signal with a logical "low" level can be supplied to the semiconductor chip 500C via the second pad bonding section 212. Thus, the first, second, and third pad bonding sections 211, 212, and 213 can each function as a power pad, signal pad, and ground pad, respectively, and can be arranged so that they are adjacent to each other. That is, the first, second, and third pad bonding sections 211, 212, and 213 can be arranged so that they are essentially closest to each other. Accordingly, routing distances between the power signal, the data signal and the ground signal applied to the 500C semiconductor chip can be reduced to improve the operating speed of the 500C semiconductor chip.

[0048] Buffer circuits (not shown) for the data signals, the power signal, and the ground signal can be integrated into or placed on the chip body (500 of Fig. 1) adjacent to the first inner chip pads (521 and 522 of Fig. 1) of the semiconductor chip (500C from Fig. 1) be provided. The buffer circuits can be configured to perform a switching operation. Because the power pad, signal pads, and ground pads are located next to each other, the routing distances between the power line, the data line, and the ground line connected to the buffer circuits can be reduced. This can improve the operating speed of the buffer circuits.

[0049] With further reference to Fig. 3. The sixth pad-bonding sections 217, which are arranged in the second row, can be arranged such that they have a symmetrical configuration with respect to a straight line between the first and second rows compared to the first to fifth pad-bonding sections 211-215, which are arranged in the first row. In some other embodiments, however, the sixth pad-bonding sections 217 can be arranged randomly at arbitrary positions to have an asymmetrical configuration compared to the first to fifth pad-bonding sections 211-215.

[0050] Although in Fig. 3 a third connection plane section 275 is arranged to have a symmetrical configuration with respect to the first connection plane section 271 with respect to a straight line between the first and the second row, the third connection plane section 275 could be arranged to have an asymmetrical configuration with respect to the first connection plane section 271 according to the embodiments.

[0051] Although in Fig. 3 a third guard-trace section 293 and a fourth guard-trace section 295 are arranged such that they have a symmetrical configuration with respect to the first and second guard-trace sections 253 and 255 with respect to a straight line between the first and second row, the third guard-trace section 293 and the fourth guard-trace section 295 can be arranged according to the embodiments such that they have an asymmetrical configuration with respect to the first and second guard-trace sections 253 and 255.

[0052] Although in Fig. 3 a fourth connection trace section 291, a fifth connection trace section 292 and a sixth connection trace section 294 are arranged such that they have a symmetrical configuration with respect to the first, second and third connection trace sections 251, 252 and 254 with respect to a straight line between the first and second row, according to the embodiments the fourth connection trace section 291, the fifth connection trace section 292 and the sixth connection trace section 294 can be arranged such that they have an asymmetrical configuration with respect to the first, second and third connection trace sections 251, 252 and 254.

[0053] Although in Fig. 3. A fifth via placement section 281, a sixth via placement section 282, and a seventh via placement section 284 are arranged such that they have a symmetrical configuration with respect to the first, second, and fourth via placement sections 231, 232, and 234 with respect to a straight line between the first and second rows. Alternatively, the fifth via placement section 281, the sixth via placement section 282, and the seventh via placement section 284 can be arranged such that they have an asymmetrical configuration according to the embodiments. With reference to the Fig. 1, Fig. 2 and Fig. 3. The line width of the second interconnection plane section 273 in a direction parallel to the line X1-X1' can be limited by the third distance d3 between the first row, in which the first to fifth pad-bonding sections 211-215 are arranged, and the second row, in which the sixth pad-bonding sections 217 are arranged. The third distance d3 between the first and second rows can be larger than the first distance d1 between the first inner chip pads 521 and the second inner chip pads 522. The second interconnection plane section 273 can be a conductor pattern with a width in a direction parallel to the line X1-X1' that is larger than the first distance d1 between the first inner chip pads 521 and the second inner chip pads 522.

[0054] Since, for example, the second interconnection plane section 273 has a relatively wide conductor pattern compared to the first, second, and third interconnection trace sections 251, 252, and 254, its resistance and impedance values ​​can be reduced to more effectively stabilize the ground voltage or the line voltage induced by a current flowing through the second interconnection plane section 273. Furthermore, a specific space or area may be required to accommodate the via attachment sections. However, since the second interconnection plane section 273 has a relatively wide conductor pattern compared to, for example, the first, second, and third interconnection trace sections 251, 252, and 254, the third via attachment section 233 can be located within a region of the second interconnection plane section 273 in a top view.This means that the third conductive via 243 can be arranged to overlap with the second interconnection plane section 273 in a top view. This significantly reduces the routing length of an electrical path between the third conductive via 243 and the second interconnection plane section 273, thereby improving the reliability and electrical properties of the semiconductor package 10.

[0055] If the third spacing between the first and second rows is equal to the first spacing d1, it can be difficult to increase the width of the second interconnection layer. In this case, the resistance of the second interconnection layer may increase. That is, if the third spacing between the first and second rows is designed to be equal to the first spacing d1, it can be difficult to implement the third conductive via between the first and second rows. Consequently, since the third conductive via is positioned laterally offset relative to the second interconnection layer, the routing length of an electrical path between the third conductive via and the second interconnection layer may increase, reducing the reliability and electrical properties of the semiconductor package 10.

[0056] As described above, according to one embodiment, the second interconnection plane section 273 can have a relatively wide conductor pattern compared to, for example, the first, second, and third interconnection trace sections 251, 252, and 254, and the third conductive via 243 can be designed to overlap with the second interconnection plane section 273 in a top view. Thus, the mains voltage or the ground voltage can be efficiently supplied to the semiconductor chip 500C via the third conductive via 243 and the second interconnection plane section 273.

[0057] Fig. Figure 6 is a top view illustrating another circuit interconnection structure 1100 used in a semiconductor package according to one embodiment.

[0058] With reference to Fig. 6 can include the circuit interconnection structure 1100 first to fifth pad bonding sections 1211, 1212, 1213, 1214 and 1215, first to third interconnection trace sections 1251, 1252 and 1254, first and second guard trace sections 1253 and 1255, first to fourth via plating sections 1231, 1232, 1233 and 1234, and first and second interconnection level sections 1271 and 1273.

[0059] The first pad bonding section 1211, the first connection trace section 1251, and the first via insertion section 1231 can form a first data signal line. The fourth pad bonding section 1214, the third connection trace section 1254, and the fourth via insertion section 1234 can form a second data signal line.

[0060] The second pad bonding section 1212, the second connection trace section 1252, the first connection plane section 1271, and the second via insertion section 1232 can form a power conductor. The first and second guard trace sections 1253 and 1255 can also be electrically connected to the first connection plane section 1271 to act as part of the power conductor.

[0061] When an initial data signal is transmitted through the first via insertion section 1231 and the first interconnect trace section 1251, the first guard trace section 1253, the second interconnect trace section 1252, and the first interconnect level section 1271 can serve as a signal return path. The first guard trace section 1253, the second interconnect trace section 1252, and the first interconnect level section 1271 can be provided to suppress or reduce the magnitude of the impedance change of the first interconnect trace section 1251. If a second data signal is transmitted through the fourth via insertion section 1234 and the third connection trace section 1254, the second guard trace section 1255, the second connection trace section 1252 and the first connection plane section 1271 can serve as a signal return path.The second guard trace section 1255, the second link trace section 1252 and the first link plane section 1271 can be provided to suppress the impedance change of the third link trace section 1254 or to reduce the magnitude of the impedance change of the third link trace section 1254.

[0062] The third pad bonding section 1213, the second connection plane section 1273, and the third via placement section 1233 can form a first ground connection. The fifth pad bonding section 1215, the second connection plane section 1273, and the third via placement section 1233 can form a second ground connection.

[0063] Fig. Figure 7 shows a top view which, according to one embodiment, represents a further circuit interconnect structure 2100 used in a semiconductor package.

[0064] With reference to Fig. 7 The circuit interconnect structure 2100 can include the following: first to fifth pad bonding sections 2211, 2212, 2213, 2214 and 2215, first to third interconnect trace sections 2251, 2252 and 2254, first and second guard trace sections 2253 and 2255, first to fourth via insertion sections 2231, 2232, 2233 and 2234, and first and second interconnect level sections 2271 and 2273.

[0065] A first additional pad-bonding section 2218 can be connected to an end section 2253E of the first guard-trace section 2253 to be positioned opposite the third pad-bonding section 2213. The first additional pad-bonding section 2218 can have substantially the same shape as the third pad-bonding section 2213, which faces the first additional pad-bonding section 2218. An additional inner connector (not shown) with the same shape as the inner connectors (560 from Fig. 1) can be connected to the first additional pad-bonding section 2218. Thus, the first additional pad-bonding section 2218 can be electrically connected to the semiconductor chip (500C from Fig. 1) be connected.

[0066] A second additional pad-bonding section 2219 can be connected to an end section 2255E of the second guard-trace section 2255 to be positioned opposite the fifth pad-bonding section 2215. The second additional pad-bonding section 2219 can have substantially the same shape as the fifth pad-bonding section 2215, which faces the second additional pad-bonding section 2219. An additional inner connector (not shown) with the same shape as the inner connectors (560 from Fig. 1) can be connected to the second additional pad-bonding section 2219. Thus, the second additional pad-bonding section 2219 can also be electrically connected to the semiconductor chip (500C from Fig. 1) be connected.

[0067] Fig. Figure 8 is a block diagram representing an electronic system with a memory card 7800 that uses the semiconductor package according to the embodiments. The memory card 7800 includes a memory 7810, such as a non-volatile memory device, and a memory controller 7820. The memory 7810 and the memory controller 7820 can store data or read the stored data. At least one of the memory 7810 and the memory controller 7820 can include the semiconductor package according to the embodiments.

[0068] The memory 7810 can include a non-volatile storage device to which the technology of the embodiments of the present disclosure is applied. The memory controller 7820 can control the memory 7810 to read stored data or to write data in response to a read / write request from a host 7830.

[0069] Fig. Figure 9 is a block diagram illustrating an electronic system 8710 with a semiconductor package according to the embodiments. The electronic system 8710 can include a controller 8711, an input / output device 8712, and a memory 8713. The controller 8711, the input / output device 8712, and the memory 8713 can be interconnected via a bus 8715, which provides a path for data movement.

[0070] In one embodiment, the controller 8711 can include one or more microprocessors, digital signal processors, microcontrollers, and / or logic devices capable of performing the same functions as these components. The controller 8711 or the memory 8713 can include one or more of the semiconductor packages according to the embodiments of this disclosure. The input / output device 8712 can include at least one keypad, keyboard, display device, touchscreen, and so on. The memory 8713 is a data storage device. The memory 8713 can store data and / or instructions to be executed by the controller 8711 and the like.

[0071] The 8713 memory can include a volatile memory device, such as DRAM, and / or a non-volatile memory device, such as flash memory. For example, flash memory can be attached to an information processing system, such as a mobile device or a desktop computer. The flash memory can be a solid-state drive (SSD). In this case, the 8710 electronic system can reliably store a large amount of data in a flash memory system.

[0072] The electronic system 8710 can further include an interface 8714 configured for sending and receiving data to and from a communications network. The interface 8714 can be wired or wireless. For example, the interface 8714 can include an antenna or a wired or wireless transceiver.

[0073] The electronic system 8710 can be implemented as a mobile system, a personal computer, an industrial computer, or a logic system, performing various functions. The mobile system could, for example, be a personal digital assistant (PDA), a portable computer, a tablet computer, a mobile phone, a smartphone, a cordless phone, a laptop computer, a memory card, a digital music system, or an information transmission / receiving system.

[0074] If the electronic system 8710 is equipment capable of performing wireless communication, the electronic system 8710 can be used in a communication system using a technique of CDMA (Code Division Multiple Access), GSM (Global System for Mobile Communications), NADC (North American Digital Cellular), E-TDMA (Enhanced Time Division Multiple Access), WCDMA (Wide Band Code Division Multiple Access), CDMA2000, LTE (Long Term Evolution) or Wibro (Wireless Broadband Internet).

[0075] Embodiments of the present disclosure have been disclosed for illustrative purposes. Those experienced in the field will recognize that various modifications, additions, and alternatives are possible with respect to the embodiments shown, without deviating from the scope and application of the present disclosure and the related claims.

Claims

[1] Semiconductor package (10) comprising: a package substrate (200S) including a substrate body (200); and a semiconductor chip (500C) mounted on the package substrate (200S), wherein the package substrate (200S) includes: first, second and third pad bonding sections (211, 212, 213) arranged on the substrate body (200), wherein the first pad bonding section (211) is arranged between the second and third pad bonding sections (212, 213); first, second and third via contacting portions (231, 232, 233) disposed on the substrate body (200) to be spaced apart from the first, second and third pad bonding portions (211, 212, 213); a first connection trace portion (251) extending to connect the first pad bonding portion (211) to the first via application portion (231); a second connection trace section (252) connected to the second pad bonding section (212), the second connection trace section (252) running parallel to the first connection trace section (251); a first guard trace portion (253) having an end portion (253E) spaced from the third pad bonding portion (213), and wherein the first guard trace portion (253) extends to be arranged parallel to the first connection trace portion (251); a first connection level section (271) spaced from the first via application section (231) and surrounding and electrically bypassing the first via application section (231) to connect the second connection trace section (252) to the first guard trace section (253), and connecting the second connection trace section (252) to the second via application section (232); and a second connection level portion (273) connecting the third pad bonding portion (213) to the third via application portion (233), and wherein the semiconductor chip (500C) includes: a chip body (500); first inner chip pads (521) arranged on a surface of the chip body (500); first outer chip pads (511) arranged on the surface of the chip body (500) to be spaced apart from the first inner chip pads (521), arranged to overlap with the first to third pad bonding portions (211, 212, 213) respectively, and connected to the respective ones of the first to third pad bonding portions (211, 212, 213); and first pad connection trace sections (531) connecting the first inner chip pads (521) to the first outer chip pads (511). [2] The semiconductor package (10) of claim 1, wherein the first interconnect trace portion (251) is disposed between the first guard trace portion (253) and the second interconnect trace portion (252). [3] The semiconductor package (10) of claim 1, wherein the third pad bonding portion (213) is disposed between the first guard trace portion (253) and the second interconnect level portion (273). [4] The semiconductor package (10) of claim 1, wherein the first pad bonding portion (211) is disposed between the first interconnect trace portion (251) and the second interconnect level portion (273). [5] The semiconductor package (10) of claim 1, wherein the second pad bonding portion (212) is disposed between the second interconnect trace portion (252) and the second interconnect level portion (273). [6] The semiconductor package (10) of claim 1, wherein the first guard trace portion (253) is elongated in one direction, the first connection trace portion (251) is elongated in one direction, and the first guard trace portion (253) and the first connection trace portion (251) are spaced apart from each other. [7] The semiconductor package (10) of claim 1, wherein the first interconnect level portion (271) is spaced apart from the first via landing portion (231). [8] The semiconductor package (10) according to claim 1, wherein the first to third pad bonding portions (211, 212, 213) are arranged between the first via contacting portion (231) and the third via contacting portion (233). [9] The semiconductor package (10) according to claim 1, wherein the first to third pad bonding portions (211, 212, 213) are arranged between the second via contacting portion (232) and the third via contacting portion (233). [10] The semiconductor package (10) according to claim 1, wherein the first to third pad bonding portions (211, 212, 213) are arranged between the first interconnection level portion (271) and the second interconnection level portion (273). [11] The semiconductor package (10) according to claim 1, wherein the first via application portion (231), the first connection trace portion (251) and the first pad bonding portion (211) form a data signal line for transmitting a data signal to the semiconductor chip (500C). [12] The semiconductor package (10) according to claim 11, wherein the second via application portion (232), the first interconnection level portion (271), the second interconnection trace portion (252) and the second pad bonding portion (212) form a ground line for supplying a ground voltage to the semiconductor chip (500C). [13] The semiconductor package (10) according to claim 12, wherein the third via application portion (233), the second interconnection plane portion (273) and the third pad bonding portion (213) form a power line for supplying a power voltage to the semiconductor chip (500C). [14] The semiconductor package (10) according to claim 11, wherein the second via application portion (232), the first interconnect level portion (271), the second interconnect trace portion (252) and the second pad bonding portion (212) form a power line for supplying a power voltage to the semiconductor chip (500C). [15] The semiconductor package (10) according to claim 14, wherein the third via application portion (233), the second interconnection plane portion (273) and the third pad bonding portion (213) form a ground line for supplying a ground voltage to the semiconductor chip (500C). [16] The semiconductor package (10) of claim 1, further comprising: fourth and fifth pad bonding sections (214, 215) arranged on the substrate body (200); a fourth via application portion (234) disposed on the substrate body (200) to be spaced from the fourth pad bonding portion (214); a third connection trace portion (254) extending to connect the fourth pad bonding portion (214) to the fourth via application portion (234); and a second guard trace section (255) having an end section (255E) spaced from the fifth pad bonding section (215), and wherein the second guard trace section (255) extends to be arranged substantially parallel to the third connection trace section (254), wherein the first connection level section (271) is arranged at a distance from the fourth via contact section (234) and surrounds and electrically bypasses the fourth via contact section (234) to connect the second connection trace section (252) to the second guard trace section (255), and wherein the second connection level portion (273) is extended to connect the fifth pad bonding portion (215) to the third via landing portion (233). [17] The semiconductor package (10) according to claim 16, wherein the first, second, third, fourth and fifth pad bonding portions (211, 212, 213, 214, 215) are arranged in a first row. [18] The semiconductor package (10) of claim 17, further comprising a plurality of sixth pad bonding portions (217) disposed on the substrate body (200) and arranged in a second row spaced from the first row, the second interconnect level portion (273) being disposed between the first row and the second row. [19] The semiconductor package (10) of claim 18, wherein the semiconductor chip (500C) further includes: second outer chip pads (512) arranged on the chip body (500) to overlap with the sixth pad bonding portions (217) and connected to the respective ones of the sixth pad bonding portions (217); second inner chip pads (522) arranged on the chip body (500) to be spaced from the second outer chip pads (512) and to face the first inner chip pads (521); and second pad connection trace sections (532) connecting the second inner chip pads (522) to the second outer chip pads (512). [20] The semiconductor package (10) of claim 19, wherein a first distance between the first inner chip pads (521) and the second inner chip pads (522) is less than a second distance between the first outer chip pads (511) and the second outer chip pads (512).

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