Multiplexer for a memory

Abstract

Multiplexer for controlling access to memory cells of a memory, including: - a first chain that controls access to the source lines of the memory, wherein the first chain comprises two high-voltage transistors and several low-voltage transistors; - a second chain that controls access to the memory's bit lines, the second chain comprising two high-voltage transistors and several low-voltage transistors, - wherein the two high-voltage transistors of the first chain and / or the second chain are arranged such that a first high-voltage transistor is arranged in each chain to apply the high voltage to the memory, and a second high-voltage transistor is arranged in series with the several low-voltage transistors to protect the low-voltage transistors from the high voltage.

Description

[0001] The solutions described herein relate in particular to an area-optimized bit-line / source-line multiplexer for memory, e.g., RRAMs. An RRAM is a resistive random-access memory, e.g., an NV (non-volatile) RAM, which functions by changing the resistance value via a dielectric solid-state material, often referred to as a memristor.

[0002] US 2019 / 0164606 A1 concerns a multiplexer for controlling access to memory cells.

[0003] A bit-line (BL) and source-line (SL) multiplexer (MUX) is used to connect addressed memory elements to signal paths required for memory operations, such as setting / shaping or resetting. A signal path to a sense amplifier (SA) is also used to perform read operations. The memory elements may be part of the RRAM.

[0004] Such a multiplexer comprises repeating structures, the number of which can depend on the number of BLs (Blended Block Arrays), e.g., several thousand repeating structures for embedded memory. Due to this vast number of repeating parts, area optimization is one of the main tasks in the development of area-efficient memory modules.

[0005] For setting / forming and reading operations, higher voltages than a core voltage are required. This leads to dedicated high-voltage (HV) devices for the repeating structures. However, the HV devices are significantly larger than the core voltage device, resulting in a significant amount of additional space (area).

[0006] It is noted that high voltage in this respect refers to a positive high voltage range of 1.5 V to 3.5 V, and core voltage (also called "low voltage", LV) can refer to a positive supply voltage range of 0.8 V to 1.3 V.

[0007] Based on the general objective of efficient land use, one task is therefore to reduce the number of high-voltage building components.

[0008] This is solved according to the features of the independent claims. Further embodiments are described in the dependent claims.

[0009] The examples proposed herein can be based on at least one of the following solutions. Combinations of the following features can be used to achieve a desired result. The features of the method could be combined with one or more arbitrary features of the component, device, or system, or vice versa.

[0010] A multiplexer is proposed for controlling access to memory cells of a memory, comprising: - a first chain that controls access to the source lines of the memory, wherein the first chain comprises two high-voltage transistors and several low-voltage transistors; - a second chain that controls access to the memory's bit lines, the second chain comprising two high-voltage transistors and several low-voltage transistors - wherein the two high-voltage transistors of the first chain and / or the second chain are arranged such that a first high-voltage transistor is arranged in each chain to apply the high voltage to the memory, and a second high-voltage transistor is arranged in series with the several low-voltage transistors to protect the low-voltage transistors from the high voltage.

[0011] It is noted that the memory can also be accessed by using word lines.

[0012] Advantageously, this approach allows the use of only two high-voltage (HS) transistors for each chain. This leads to a significant reduction in the area required on a chip. Therefore, the memory multiplexer requires less area on the chip than previous solutions.

[0013] It is noted that the HV transistors are able to withstand a voltage of up to 2.5 V, whereas the LV transistors are limited to voltages below, for example, 1.3 V.

[0014] It is noted that the transistors can be PMOS or NMOS transistors.

[0015] According to one embodiment, a high-voltage control unit is provided for controlling the high-voltage transistors and a low-voltage control unit is provided for controlling the low-voltage transistors.

[0016] This applies to either the first chain or the second chain (or both). Thus, the first high-voltage transistor can be used in such a way that the high voltage is supplied in the direction towards (or from) the memory, and the second high-voltage transistor, arranged in series with the several low-voltage transistors, ensures that part of the voltage drops across this second high-voltage transistor, so that only a reduced voltage is applied to the low-voltage transistors.

[0017] According to one embodiment, the multiple low-voltage transistors of the first chain and / or the second chain are arranged such that the bit lines or source lines can be selected for each chain and that different voltages can be applied.

[0018] According to one embodiment, the first chain and the second chain are used to access memory cells of the memory and to perform either a set / form operation, a reset operation, or a read operation.

[0019] According to one embodiment, the memory is an RRAM.

[0020] According to one embodiment, the memory cells are arranged in a matrix structure and a first chain and a second chain are provided for each row of memory cells.

[0021] According to one embodiment, the memory cells are arranged in a matrix structure and a first chain is provided for two or a multiple of two second chains, so that two bit lines share one source line.

[0022] This allows for a further reduction in the area required for multiplexer functionality. This concept can also be described here as a shared source line for multiple bit lines.

[0023] According to one embodiment, the multiplexer is arranged on the same chip or in the same component as the memory.

[0024] Furthermore, a method is provided for operating a multiplexer that controls access to memory cells of a memory, wherein the multiplexer comprises - a first chain that controls access to the source lines of the memory, wherein the first chain comprises two high-voltage transistors and several low-voltage transistors; - a second chain that controls access to the memory's bit lines, the second chain comprising two high-voltage transistors and several low-voltage transistors - wherein the two high-voltage transistors of the first chain and / or the second chain are arranged such that a first high-voltage transistor is arranged in each chain to apply the high voltage to the memory, and a second high-voltage transistor is arranged in series with the several low-voltage transistors to protect the low-voltage transistors from the high voltage; wherein the method comprises: - Applying voltages to the first chain and the second chain so that one of the following operations is performed on memory cells of the memory: - a reading operation; - a typesetting / forming operation; - a reversal operation.

[0025] Embodiments are shown and illustrated with reference to the drawings. The drawings serve to illustrate the basic principle, so only aspects necessary for understanding the basic principle are shown. The drawings are not to scale. In the drawings, the same reference numbers denote the same features. Fig. Figure 1 shows a basic structure of an RRAM array comprising several memory cells arranged in a matrix-like structure comprising rows and columns; Fig. Figure 2 shows an example of the diagram, comprising four HV components for controlling a bit line; Fig. Figure 3 shows a schematic diagram of a circuit that allows the control of a bit line using only two HV components; Fig. Figure 4 shows a schematic diagram comprising sections of a multiplexer that operate with an RRAM array; Fig.Figure 5 shows a schematic diagram of a multiplexer structure that accesses multiple memory cells, wherein the multiplexer structure comprises an HV circuit arrangement and an LV circuit arrangement; Fig. Figure 6 shows a basic structure of another RRAM array, comprising eight memory cells, with two bit lines sharing a single source line; Fig. Figure 7 shows a schematic diagram comprising sections of a multiplexer that operate in combination with an RRAM array using one source line for every two bit lines; Fig. 8 shows the concept in more detail. Fig. 7 for 64 memory cells; Fig. Table 9 shows a comprehensive list of exemplary stresses at the in Fig. 8 shown nodes / lines for the different operation modes, e.g. read operation, set / form operation and reset operation; Fig.Figure 10 shows an exemplary circuit, including components for generating the voltage level VCLAMP.

[0026] The solutions described herein allow for efficient use of space in a multiplexer circuit arrangement, which is used in combination with memory, especially with RRAMs.

[0027] It is proposed to reduce the number of HV components, thereby reducing the amount of space (area) required for the repeating structures within the multiplexer to access memory cells.

[0028] Advantageously, the exemplary multiplexer concept described herein requires only one HV-PMOS and one HV-NMOS per bit line. This can also apply per source line.

[0029] Fig.Figure 1 shows an example of a basic structure of an RRAM array comprising nine memory cells. A memory cell 101 comprises an NMOS 102 and an RRAM element 103 (which is represented by a resistor). The same structure applies to all the elements in the RRAM array of Fig. 1 memory cells shown.

[0030] The nine memory cells are addressed via word lines WL1, WL2, WL3, and they are selected via bit lines BL1, BL2, BL3 and source lines SL1, SL2, SL3.

[0031] There are three operations that can be performed on each memory cell: a set operation (also called a forming operation), a reset operation, and a read operation.

[0032] To select memory cell 101, word line WL2 is set to 2.5 V (which also selects all memory cells on the same line as memory cell 101, indicated by box 104). The remaining word lines WL1 and WL3 are not selected and are therefore set to 0 V.

[0033] Furthermore, the bit line BL1 and the source line SL1 are selected to access memory cell 101, while the other bit lines BL2, BL3 and the other source lines SL2, SL3 are not selected (“deselected”).

[0034] Additionally, depending on the operation to be performed at memory cell 101, the following signals can be applied to the bit lines BL1 to BL3 and the source lines SL1 to SL3: BL1 SL1 BL2, BL3 SL2, SL3 Set / Form operation 2,5 V 0 V 1 V 1 V Reset operation 0 V 2,5 V 1 V 1 V Reading operation 0,2 V 0 V 0 V 0 V

[0035] In the case of setting / shaping memory cell 101, a current flows through the selected NMOS 102 by setting the bit line voltage BL1 to 2.5 V and the source line voltage SL1 to 0 V. The other bit lines BL2 and BL3 and source lines SL2 and SL3 can be connected to a voltage on the order of 1 V to determine the gate-source voltage (VG). GS ) and the gate-drain voltage (V GD ) to maintain the other transistors, which are also selected at a low potential by the word line WL2.

[0036] To perform the read operation, an exemplary voltage of 0.2 V is applied to the bit line BL1, and the current flowing through the RRAM element to the source line is measured.

[0037] In the case of a reset applied to memory cell 101, the current flows in the reverse direction. This can be achieved by setting the bit line voltage BL1 to 0 V and the source line voltage SL1 to 2.5 V. The deselected bit lines / source lines are connected to the same voltages using the set / form operation described above.

[0038] If memory cell 101 is to be read, the direction of the current through the NMOS is the same as in the set / form scenario, but the amplitude is significantly smaller (i.e., the voltage applied to bit line BL1 is 0.2 V).

[0039] Fig. Figure 2 shows an exemplary diagram comprising four high-voltage components that allow a bit line 201 to meet the following requirements: - Bit line 201 can be connected to ground GND (VSS), which is used for deselected bit lines during read operations; - Bit line 201 can be connected to a voltage VINH (e.g. 1.0 V) which is used for deselected bit lines during the set / form operation or the reset operation; - The bit line 201 can be connected to a voltage GBL, which applies to a chosen bit line, where the voltage GBL can be either 0 V, a high voltage (e.g. 2.5 V) or the voltage VINH (e.g. 0.2 V or 1.0 V).

[0040] The above applies accordingly to the source line.

[0041] The voltage VINH represents a voltage between 0 V and the voltage across a selected word line (e.g., 2.5 V). All disselected bit lines and source lines are connected to the VINH voltage to reduce the voltage difference between the gate voltage of the selected transistor and its corresponding source and drain terminals, thereby lowering the stress conditions. The selected transistors, together with the selected word line, can be connected to Vgs and Vgd, which V(WL)−VINH=1.5 V is, This can be claimed if VINH = 1 V (where V(WL) is the voltage of the selected word line). For pragmatic reasons, VDD = 1 V can be used for VINH, as it is within a useful range and is already available. The voltage of 0.2 V in this example is the read voltage applied by the read amplifier. This voltage may differ in other use cases and, in particular, depend on the acquisition approach used.

[0042] In Fig. 2 A PMOS 202 is connected in series with an NMOS 203, with the source of the PMOS 202 connected to the voltage VINH and the source of the NMOS 203 connected to GND (also referred to as VSS). A node 204 is connected to the source of the PMOS 202 and to the source of the NMOS 203. The node 204 is also connected to the bit line 201 and to the drain of a PMOS 205 and to the drain of an NMOS 206. The source of the PMOS 205 and the source of the NMOS 206 are connected to each other and are connected to an HV and LV control unit 207.

[0043] It is noted that all in Fig. The two transistors shown are designed to handle HV and therefore require a significant amount of area on a chip.

[0044] Fig.Figure 3 shows a schematic diagram illustrating the same features for setting the voltages of a bit line 303, comprising only two HV components: a PMOS 301 and an NMOS 302. The drain of the PMOS 301 is connected to the bit line 303 and to the drain of the NMOS 302. The source of the PMOS 301 is connected to an HV and LV control unit 304. Furthermore, the HV and LV control unit 304 is connected to an LV block 305. The source of the NMOS 302 is also connected to the LV block 305.

[0045] It is possible that only a single HV and LV control unit 304 is provided per multiplexer, e.g., one block per 64 bit lines. Therefore, the HV and LV control unit 304 may be less relevant for space optimization purposes.

[0046] On the other hand, the LV block 305 and the two HV transistors 301 and 302 are required for each individual bit line. Advantageously, the LV block 305 is only exposed to LV and therefore does not require any HV components. This design results in a significant saving of area on the chip.

[0047] It is noted that the gates of the HV transistors are controlled in combination with the LV and HV control unit 304 and the LV block 305, so that set / form operations, reset operations, and read operations can be performed on individual memory cells of a matrix-shaped memory. This is explained in more detail below.

[0048] Furthermore, the NMOS 302 is used to "protect" the LV block 305 from voltages exceeding the LV range. Thus, the NMOS 302 may provide a voltage drop (e.g., 0.6 V) across its drain-source, thereby reducing the voltage supplied to the LV block 305.

[0049] This approach can be applied to source lines accordingly.

[0050] Fig. Figure 4 shows a schematic diagram that includes sections of a multiplexer operating in combination with a 401 RRAM array.

[0051] The diagram includes, as an example, source lines SL1, SL2 and SL3 with HV transistors 402 to 407. An LV circuit 408 is also provided for driving these source lines SL1 to SL3.

[0052] The diagram of Fig.4 also includes bit lines BL1, BL2 and BL3 with HV transistors 409 to 414. In addition, an LV circuit 415 is provided for driving the bit lines up to BL1 to BL3.

[0053] It is noted below that the expression "the transistor is connected between node A and node B" means that the drain of the transistor is connected to node A and the source is connected to node B, or vice versa, depending on whether the transistor is a PMOS or an NMOS. It is further noted that transistors 402, 404, 406, 410, 412, and 414 are NMOS transistors (also referred to as "NMOS"), and that transistors 403, 405, 407, 409, 411, and 413 are PMOS transistors (also referred to as "PMOS").

[0054] It is noted that MOS transistors can be symmetrical with respect to their source and drain, thus the respective source and drain can be interchanged.

[0055] The NMOS 402 is connected between node 431 and the source line SL1 of the RRAM array 401. The NMOS 404 is connected between node 433 and the source line SL2 of the RRAM array 401. The NMOS 406 is connected between node 434 and the source line SL3 of the RRAM array 401.

[0056] The gates of NMOS 402, 404 and 406 are connected to a node 432.

[0057] PMOS 403 is connected between node 435 and source line SL1, PMOS 405 is connected between node 435 and source line SL2, and PMOS 407 is connected between node 435 and source line SL3. Node 435 provides the positive supply for performing the reset operation.

[0058] The gate of PMOS 403 is connected to node 436, the gate of PMOS 405 is connected to node 437, and the gate of PMOS 407 is connected to node 438.

[0059] The NMOS 410 is connected between node 451 and bit line BL1 of the RRAM array 401. The NMOS 412 is connected between node 453 and bit line BL2 of the RRAM array 401. The NMOS 414 is connected between node 454 and bit line BL3 of the RRAM array 401.

[0060] The gates of NMOS 410, 412 and 414 are connected to a node 452.

[0061] PMOS 409 is connected between node 455 and bit line BL1, PMOS 411 is connected between node 455 and bit line BL2, and PMOS 413 is connected between node 455 and bit line BL3. Node 455 provides the positive supply for performing the set operation.

[0062] The gate of PMOS 409 is connected to node 456, the gate of PMOS 411 is connected to node 457, and the gate of PMOS 413 is connected to node 458.

[0063] The nodes introduced above can be connected with different voltages (or they may not be connected at all) depending on the mode of operation to be performed. This will be discussed in Fig. 4 is indicated by the triple of values ​​that could potentially be applied to the corresponding node / line. The top value represents the set / form operation, the middle value represents the reset operation, and the bottom value of the triple represents the read operation.

[0064] The following is a summary of the values ​​for the respective lines / nodes: node Set / Form operation Reset operation Reading operation 431 0 V / 1 V 1 V 0 V 433 1 V 1 V 0 V or 1 V or Z 434 1 V 1 V 0 V or 1 V or Z 432 2,5 V 1,5 V 2,5 V 436 2,5 V 0 V 2,5 V 437 2,5 V 2,5 V 2,5 V 438 2,5 V 2,5 V 2,5 V 435 X 2.5 V / 1 V X 451 1 V or Z 0 V / 1 V 0.2 V (reading amplifier connection) 453 1 V 1 V 0 V or 1 V or Z 454 1 V 1 V 0 V or 1 V or Z 452 1,5 V 2,5 V 2,5 V 456 0 V 2,5 V 2,5 V 457 2,5 V 2,5 V 2,5 V 458 2,5 V 2,5 V 2,5 V 455 2.5 V / 1 V X X

[0065] The notation "a / b", where a and b are voltages, means the following: Voltage a is applied in the chosen scenario, for example, if the memory cell is to be modified by an operation. Voltage b is used if the chosen cell is not to be modified. The latter can be applied if the chosen cell is already in the desired state and no change is needed. It is also applicable if the chosen cell is to be modified, but in a delayed manner: For example, 20 parallel multiplexers have selected a BL / SL combination, but only three can write to it at any given moment; the other multiplexers must wait for their time window to write to the memory cell, i.e., apply voltage b until it is time to write to the cell.

[0066] "X" means that the voltage at this node is irrelevant. "Z" means that the bit line or the source line is not connected. It should be noted that the voltages shown above are only examples and may be changed based on a chosen technology or use case scenario.

[0067] In the Fig. In the example shown, bit line BL1 and source line SL1 are selected, whereas the remaining bit lines BL2, BL3 and the remaining source lines SL2, SL3 are deselected.

[0068] As in Fig. As shown in Figure 4, the HV-NMOS transistors share a common gate voltage.

[0069] Fig. Figure 5 shows an exemplary scenario involving a selected memory cell 501 and a deselected memory cell 502. As mentioned above, many deselected memory cells may be present in addition to this memory cell 502.

[0070] In a real-world scenario, only a single memory cell might be selected from a multitude, e.g., 64 memory cells, while the remaining 63 memory cells remain deselected. This deselected state is exemplified by the single memory cell 502, which is one of these 63 deselected memory cells.

[0071] Fig. Figure 5 also shows the HV and LV circuit arrangements in more detail. Both the HV and LV circuit arrangements can be part of a multiplexer that enables different operations for different memory cells or an RRAM array. Fig. 5 also includes a simplification of Fig. 4 regarding the connection of transistors 402, 403 and 404, 405. Such a simplification can optionally also be applied to transistors 409, 410 and 411, 412.

[0072] Each of the memory cells 501 and 502 comprises an NMOS and a resistive element (see also Fig. 1 for a further detail). Memory cells 501 and 502 are selected via a word line 503.

[0073] In Fig. Figure 5 shows two bit lines BL1 and BL2 and two source lines SL1 and SL2. Bit line BL1 and source line SL1 are used to select memory cell 501, and bit line BL2 and source line SL2 are used to deselect memory cell 502.

[0074] The NMOS 410 is connected between bit line BL1 and node 451. An NMOS 522 is connected between node 451 and node 558.

[0075] A PMOS 521 is connected between a node 555 and the node 451, and the gate of the PMOS 521 and the gate of the NMOS 522 are connected to a node 551.

[0076] A PMOS 525 is connected between node 563 and node 558, and an NMOS 526 is connected between node 558 and ground.

[0077] The gate of the PMOS 525 is connected to a node 556, and the gate of the NMOS 526 is connected to a node 557.

[0078] As stated above, the gate of NMOS 410 and the gate of NMOS 412 are connected to node 452.

[0079] The PMOS 409 is connected between node 455 and bit line BL1. The gate of the PMOS 409 is connected to node 456.

[0080] A PMOS 527 is connected between node 561 and node 455, and a PMOS 528 is connected between node 455 and node 562.

[0081] The gate of PMOS 527 is connected to a node 559, and the gate of PMOS 528 is connected to a node 560.

[0082] The PMOS 403 is connected between the source line SL1 and node 435. The NMOS 402 is connected between node 564 and the source line SL1. The gate of the NMOS 402 and the gate of the PMOS 403 are connected to node 436.

[0083] A PMOS 511 is connected between node 552 and node 564, and an NMOS 512 is connected between node 564 and ground. The gate of the PMOS 511 and the gate of the NMOS 512 are connected to node 561.

[0084] The NMOS 412 is connected between the BL2 bit line and a node 453.

[0085] A PMOS 523 is connected between nodes 555 and 453. An NMOS 524 is connected between nodes 453 and 558. The gate of the PMOS 523 and the gate of the NMOS 524 are connected to node 554.

[0086] Node 558 is connected to a read amplifier (not shown).

[0087] The PMOS 411 is connected between node 455 and bit line BL2. The gate of the PMOS 411 is connected to node 457.

[0088] The NMOS 404 is connected between node 564 and the source line SL2. The PMOS 405 is connected between the source line SL2 and node 435. The gate of the NMOS 404 and the gate of the PMOS 405 are connected to node 437.

[0089] The LV circuit 408 thus includes transistors 511 and 512, and the LV circuit 415 includes transistors 521 to 526.

[0090] As above regarding Fig. As indicated in section 4, transistors 409 to 412 and transistors 402 to 405 are high-voltage (HV) transistors. Transistors 527 and 528 are HV transistors that are part of an HV control circuit, which can be used for multiple bit lines, e.g., for all bit lines of a memory module comprising, for example, 64 memory cells.

[0091] The following are exemplary values ​​for the respective lines / nodes: node Set / Form operation, adding selected bit line / source line, Scenario 1a Set / Form operation, selected bit line / source line not to be set, Scenario 1b Reset operation, selected bit line / source line to be reset, Scenario 2a Reset operation, non-resettable selected bit line / source line, Scenario 2b Reading Operation Scenario 3 561 1 V 0 V 0 V 0 V 1 V 552 1 V 1 V 1 V 1 V 1 V 564 0 V 1 V 1 V 1 V 0 V 436 2,5 V 2,5 V 0 V 0 V 2,5 V 437 0 V 0 V 2,5 V 2,5 V 2,5 V SL1 0 V 1 V 2,5 V 1 V 0 V SL2 1 V 1 V 1 V 1 V 0 V 435 1 V 1 V 2,5 V 1 V X 503 2 V 2 V 2 V 2 V 2 V 559 0 V 2,5 V 2,5 V 2,5 V 2,5 V 560 2,5 V 0 V 2,5 V 2,5 V 2,5 V 561 2,5 V 2,5 V 2,5 V 2,5 V 2,5 V 562 1 V 1 V 1 V 1 V 1 V 455 2,5 V 1 V Z Z Z 456 0 V 0 V 2,5 V 2,5 V 2,5 V BL1 2,5 V 1 V 0 V 1 V 0,2 V 457 2,5 V 2,5 V 2,5 V 2,5 V 2,5 V BL2 1 V 1 V 1 V 1 V Z (0 V) 452 1,5 V 1,5 V 1,5 V 1,5 V 1,5 V 555 1 V 1 V 1 V 1 V Z 451 1 V 1 V 0 V 1 V 0,2V 551 0 V 0 V 1 V 1 V 1 V 453 1 V 1 V 1 V 1 V Z 554 0 V 0 V 0 V 0 V 0 V 563 1 V 1 V 1 V 1 V 1 V 556 1 V 1 V 1 V 0 V 1 V 557 1 V 1 V 1 V 0 V 0 V 558 0 0 0 1 V 0,2 V (*) (*) This voltage is defined by the connected read amplifier (SA). Voltage levels other than 0.2 V may be used in other applications. Here, the SA drives the input to a defined level (i.e., 0.2 V) and then measures the current. The connected SA has a high impedance at its input when the SA is switched off. Furthermore, when switched off, the SA is preferably able to tolerate other voltages at its input without drawing any current.

[0092] In scenario 1a, the bit line / source line is used for setting / shaping, whereas in scenario 1b the (already) selected bit line / source line is kept unchanged.

[0093] In scenario 2a, the bit line / source line is chosen for the reset, whereas in scenario 2b, the (already) chosen bit line / source line is kept unchanged.

[0094] Scenario 3 shows the read operation, which generates a voltage of 0.2 V at node 558 to the read amplifier.

[0095] It is noted that for scenario 2a, the voltage of 2.5 V at node 435 can be generated by a similar arrangement to that shown by transistors 527 and 528: Two PMOS transistors can be arranged in series, with the upper node (compared to node 561) connected to 2.5 V and the lower node (compared to node 562) connected to 1 V; the gate of the upper PMOS (compared to node 559) is connected to 0 V, and the gate of the lower PMOS (compared to node 560) is connected to 2.5 V.

[0096] Regarding scenario 2b, the voltage of 1 V can be generated at node 435 accordingly, whereas the gate of the upper PMOS (compared to node 559) is connected to 2.5 V and the gate of the lower PMOS (compared to node 560) is connected to 0 V.

[0097] It is noted that, with regard to scenarios 1a and 1b, the voltages applied to nodes 559, 560, and 561 are used to distinguish between a selected bitline / source line memory cell and one that is not to be modified. Conversely, the voltages applied to nodes 436, 437, 456, and 457 are used to distinguish between a selected and a deselected bitline / source line combination.

[0098] It is further noted that, with regard to scenarios 2a and 2b, the voltages applied to nodes 556, 557, and 435 are used to distinguish between the selected bit line / source line memory cell and whether it is to be modified or not. Conversely, the voltages applied to nodes 436, 437, 551, and 554 are used to distinguish between a selected and a deselected bit line / source line combination.

[0099] Furthermore, with regard to the read operation (scenario 3), the voltages applied to nodes 551 and 554 are used to distinguish between a selected and a deselected bit line / source line combination. Examples: Shared source control

[0100] It is possible for multiple bit lines to share a single source line. This has the advantage of significantly reducing the complexity and the area required for the multiplexer on a single chip. Furthermore, a reduced number of source lines allows for an increased width of the metal traces, thereby reducing their resistance.

[0101] An example shown below associates a single source line with two bit lines.

[0102] Fig.Figure 6 shows an example of a basic structure of another RRAM array comprising eight memory cells 601 to 608. As regarding Fig. As explained in section 1, each memory cell comprises an NMOS and an RRAM element (which is represented by example as a resistor).

[0103] One of the memory cells can be addressed (selected or deselected) via the word lines WL1, WL2, the bit lines BL0, BL1, BL2 and the source lines SL01, SL23.

[0104] As mentioned above, three operations can be performed for each memory cell 601 to 608: a set / form operation, a reset operation, or a read operation.

[0105] In the Fig.In the example shown, only memory cell 601 is to be selected. Therefore, word line WL1 is selected, and the other word lines (here, word line WL2) are deselected. Additionally, source line SL01 is selected, and the other source lines (here, source line SL23) are deselected. However, by selecting source line SL01, both memory cells 601 and 602 can be active. To select only memory cell 601, bit line BL0 is selected, and bit line BL1 is deselected. Naturally, the other bit lines BL2 and BL3 are also deselected.

[0106] Furthermore, depending on the operation to be performed at memory cell 601, the following signals can be applied to the word lines, the source lines and the bit lines: Typesetting / Forming Operations Reset operations Reading operation WL1 2,5 V WL2 0 V BL0 2,5 V 0 V 0,2 V BL1 0 V 2,5 V 0 V BL2 1 V 1 V 0 V BL3 1 V 1 V 0 V SL01 0 V 2,5 V 0 V SL23 1 V 1 V 0 V

[0107] The concept of shared source line(s) includes additional conditions for a deselected bit line and a selected source line (where in the Fig. (In the example shown in Figure 6, the bit line BL0 is the selected bit line, the bit line BL1 is the deselected bit line, and the source line SL01 is the selected source line): Preferably, the bit line voltages are (essentially) such that the flow of any cell current through the memory cell 602 is avoided.

[0108] Fig. Figure 7 shows a schematic diagram that includes sections of a multiplexer operating in combination with an RRAM array 701 using one source line per two bit lines.

[0109] The diagram includes, as an example, source lines SL12 and SL34 with HV transistors 702 to 705. An LV circuit 721 is also provided for driving these source lines SL12 and SL34.

[0110] The diagram of Fig. 7 also includes bit lines BL1, BL2, BL3 and BL4 with HV transistors 706 to 713. In addition, an LV circuit 722 is provided for driving the bit lines BL1 to BL4.

[0111] Transistors 702, 704, 707, 709, 711 and 713 are NMOS transistors (also referred to as "NMOS"), and transistors 703, 705, 706, 708, 710 and 712 are PMOS transistors (also referred to as "PMOS").

[0112] The NMOS 702 is connected between a node 731 and the source line SL12 of the RRAM array 701. The NMOS 704 is connected between a node 732 and the source line SL34 of the RRAM array 701.

[0113] The gates of NMOS 702 and 704 are connected to a node 733.

[0114] The PMOS 703 is connected between a node 736 and the source line SL12, and the PMOS 705 is connected between the node 736 and the source line SL34.

[0115] The gate of PMOS 703 is connected to a node 734, and the gate of PMOS 705 is connected to a node 735.

[0116] The NMOS 707 is connected between node 751 and bit line BL1 of the RRAM array 701. The NMOS 709 is connected between node 752 and bit line BL2 of the RRAM array 701. The NMOS 711 is connected between node 753 and bit line BL3 of the RRAM array 701. The NMOS 713 is connected between node 754 and bit line BL4 of the RRAM array 701.

[0117] The gates of NMOS 707, 709, 711 and 713 are connected to a node 756.

[0118] The PMOS 706 is connected between a node 755 and the bit line BL1, the PMOS 708 is connected between the node 755 and the bit line BL2, the PMOS 710 is connected between the node 755 and the bit line BL3, and the PMOS 712 is connected between the node 755 and the bit line BL4.

[0119] The gate of PMOS 706 is connected to a node 757, the gate of PMOS 708 is connected to a node 758, the gate of PMOS 710 is connected to a node 759, and the gate of PMOS 712 is connected to a node 760.

[0120] The nodes introduced above can be connected to different voltages (or they may not be connected at all) depending on the mode of operation to be performed. This is in Fig. 7 is indicated by the triple of values ​​that could be applied to the respective node / line. The top value represents the set / form operation, the middle value represents the reset operation, and the bottom value of the triple represents the read operation.

[0121] The following is a summary of the values ​​for each line / node: node Set / Form operation Reset operation Reading operation 731 0 V / 1 V 1 V 0 V 732 1 V 1 V 0 V or 1 V or Z 733 2,5 V 1,5 V 2,5 V 734 2,5 V 0 V 2,5 V 735 2,5 V 2,5 V 2,5 V 736 X 2.5 V / 1 V X SL12 0 V / 1 V 2.5 V / 1 V 0 V 751 1 V or Z 0 V / 1 V 0.2 V (reading amplifier connection) 752 (0 V or Z) / 1 V 1 V or Z 0 V or 1 V or Z 753 1 V 1 V 0 V or 1 V or Z 754 1 V 1 V 0 V or 1 V or Z 755 2.5 V / 1 V (2.5 V → Z) / 1 V X 756 1,5 V 1,5 V 2,5 V 757 0 V 2,5 V 2,5 V 758 2,5 V 0 V 2,5 V 759 2,5 V 2,5 V 2,5 V 760 2,5 V 2,5 V 2,5 V

[0122] 0 V / 1 V means that 0 V is selected for setting, resetting, or changing the state of the memory cell, and 1 V is selected in the case where the memory should not be set (the memory cell may remain as it is). The specific BL / SL combination is selected by the multiplexer in addition to a selected WL; thus, a single memory cell is selected. Whether the selected memory cell is set, unset, or reset can depend, in particular, on the current state of that memory cell (it may already be in the set state) and on the stored data (it might be that the specific element should remain in the reset state).

[0123] “(2.5 V → Z) / 1 V” means that “2.5 V / 1 V” is an ideal case. Since the 2.5 V on bit line BL2 may differ slightly from the competing 2.5 V on source line SL12, a static current can occur through the deselected memory cell. Therefore, one option is to switch node 755 to 2.5 V for a short duration (e.g., a few nanoseconds) and transition to the high-impedance state. Bit line BL2 then drifts through the memory cell to the voltage of source line SL12 with a small charging current (but without any static current). This is advantageous because static currents could cause undesirable changes in the state of the memory cell.

[0124] "X" means that any voltage is in the range of 0 V to 2.5 V (the circuit could handle these voltages), specifically either 1 V or 2.5 V. "Z" means that the bit line or the source line is not connected. It should be noted that the voltages shown above are only examples and may be changed based on a chosen technology or use case.

[0125] In the Fig. In the example shown, bit line BL1 and source line SL12 are selected, whereas the remaining bit lines BL2 to BL4 are deselected.

[0126] Fig. 8 shows the concept of Fig. 7 for 64 memory cells in more detail, including - an LV circuit 802 and an HV circuit 804 for controlling 32 source lines SL1_2 to SL62_63, - an LV circuit 803 and an HV circuit 805 for controlling the 64 bit lines BL0 to BL63.

[0127] The LV circuit 802 includes a PMOS P6 and an NMOS N5, both of which are LV transistors.

[0128] The HV circuit 804 comprises 32 PMOS P5, as P5 <0> up to P5 <31> designated, and 32 NMOS N4, as N4 <0> to N4 <31> designated.

[0129] The PMOS P6 is connected between VDD (which can be 0.9 V) and a node gsl, the NMOS N5 is connected between node gsl and ground. The gates of the PMOS P6 and the NMOS N5 are connected to a node gsl_n.

[0130] The NMOS N4 <0> is connected between the node gsl and the source line SL1_2. The PMOS p5 <0> is connected between the source line SL1_2 and a node sl_pos_hv. The gate of the NMOS N4 <0> and the gate of the PMOS P5 <0> are connected to a node sel_sl_hv_n <0> connected.

[0131] It is noted that the reference symbol mentioned herein may contain a number in parentheses, e.g. “ <0> This refers to the fact that the referenced node or transistor can be provided multiple times. Regarding the 32 source lines SL1_2 to SL62_63, there are also 32 pairs of HV transistors N4. <0> , P5 <0> to N4 <31> up to P5 <31> provided, with their gates connected to the nodes sel_sl_hv_n <0> until sel_sl_hv_n <31> are connected. Thus, this section addresses with i=0, ..., 32 or i=0, ... 61 one of many nodes or transistors.

[0132] Regarding the 32nd HV transistor of the HV circuit 804, the following applies: The NMOS N4 <31> is connected between node gsl and the source line SL62_63. The PMOS P5 <31> is connected between the source line SL62_63 and the node sl_pos_hv. The gate of the NMOS N4 <31> and the gate of the PMOS P5 <31> are connected to a node sel_sl_hv_n <31> connected.

[0133] Source lines SL1_2 to SL62_63 are connected to a memory array 801. A word line 808 is connected to the memory array 801 to select a line from memory cells (as explained in more detail above).

[0134] Applying the naming scheme introduced above, the LV circuit 803 comprises 64 PMOS P1, 64 NMOS N1, 32 PMOS P3, 32 PMOS P4, 32 NMOS N3 and 32 NMOS N2.

[0135] The HV circuit 805 comprises 64 PMOS P0 and 64 NMOS N0.

[0136] The HV circuit 805 and the LV circuit 803 can each be grouped for two consecutive bit lines.

[0137] The following applies to the bit lines BL0 and BL1, which are connected to the memory array 801: The PMOS PO <0> is connected between a node bl_pos_hv and the bit line BL0. The gate of the PMOS PO <0> is at a node sel_bl_hv_n <0> connected.

[0138] The NMOS N0 <0> is between the bit line BL0 and a node lv <0> switched. The gate of the NMOS N0 <0> is connected to a node vclamp_bl.

[0139] The PMOS P3 <0> is between VDD and a node at <0> switched. The gate of the PMOS P3 <0> is at a node en_lv_pos_n <0> connected.

[0140] The PMOS P1 <0> is between the nodes at <0> and the node lv <0> switched. The NMOS N1 <0> is between the nodes lv <0> and a node bn <0> switched. The gate of the PMOS P1 <0> and the gate of the NMOS N1 <0> are connected to a node sel_bl_lv <0> connected.

[0141] The PMOS P4 <0> is between VDD and the nodes bn <0> switched, and the NMOS N3 <0> is between nodes bn <0> and a node 809 is connected. An NMOS N6 is connected between node 809 and ground. The gate of the PMOS P4 <0> is connected to a node bl_tievdd_n. This node bl_tievdd_n is also connected to the gate of NMOS N6. The gate of NMOS N3 <0> is attached to a node bl_tiedwn <0> connected.

[0142] The NMOS N2 <0> is between nodes bn <0> and connected a node rd_path. The gate of the NMOS N2 <0> is attached to a node sel_rd <0> connected.

[0143] The node rd_path is further connected to a read amplifier (not shown).

[0144] The PMOS P0 <1> is connected between the nodes bl_pos_hv and the bit line BL1. The gate of the PMOS P0 <1> is at a node sel_bl_hv_n <1> connected.

[0145] The NMOS N0 <1> is between the bit line BL1 and a node lv <1> switched. The gate of the NMOS N0 <1> is connected to the node vclamp_bl.

[0146] The PMOS P1 <1> is between the nodes at <0> and the node lv <1> switched. The NMOS N1 <1> is between the nodes lv <1> and the node bn <0> switched. The gate of the PMOS P1 <1> and the gate of the NMOS N1 <1> are connected to a node sel_bl_lv <1> connected.

[0147] This approach is applied accordingly to any subsequent group of two bit lines. Therefore, the following applies to the last two bit lines BL62 and BL63: The PMOS P0 <62> is connected between the nodes bl_pos_hv and the bit line BL62. The gate of the PMOS P0 <62> is at a node sel_bl_hv_n <62> connected.

[0148] The NMOS N0 <62> is between the BL62 bit line and a node lv <62> switched. The gate of the NMOS N0 <62> is connected to the node vclamp_bl.

[0149] The PMOS P3 <31> is between VDD and a node at <31> switched. The gate of the PMOS P3 <31> is at a node en_lv_pos_n <31> connected.

[0150] The PMOS P1 <62> is between the nodes at <31> and the node lv <62> switched. The NMOS N1 <62> is between the nodes lv <62> and a node bn <31> switched. The gate of the PMOS P1 <62> and the gate of the NMOS N1 <62> are connected to a node sel_bl_lv <62> connected.

[0151] The PMOS P4 <31> is between VDD and the nodes bn <31> switched, and the NMOS N3 <31> is between nodes bn <31> and node 809 is switched. The gate of PMOS P4 <31> is connected to the node bl_tievdd_n. The gate of the NMOS N3 <31> is attached to a node bl_tiedwn <31> connected.

[0152] The NMOS N2 <31> is between nodes bn <31> and switched the node rd_path. The gate of the NMOS N2 <31> is attached to a node sel_rd <31> connected.

[0153] The PMOS P0 <63> is connected between the nodes bl_pos_hv and the bit line BL63. The gate of the PMOS P0 <63> is at a node sel_bl_hv_n <63> connected.

[0154] The NMOS N0 <63> is between the BL63 bit line and a node lv <63> switched. The gate of the NMOS N0 <63> is connected to the node vclamp_bl.

[0155] The PMOS P1 <63> is between the nodes at <31> and the node lv <63> switched. The NMOS N1 <63> is between the nodes lv <63> and the node bn <31> switched. The gate of the PMOS P1 <63> and the gate of the NMOS N1 <63> are connected to a node sel_bl_lv <63> connected.

[0156] Fig. Table 9 shows exemplary stresses at the in Fig. The 8 shown nodes / lines include the different operation modes, i.e., read operation, set / form operation, and reset operation.

[0157] The table shows several rows 921 to 937 and columns 901 to 912.

[0158] Columns 901 to 903 refer to an inactive read operation, where no bit line has been selected yet.

[0159] Columns 904 to 906 refer to a read operation using a bit line selected for performing the read operation. When a device is powered on and the RRAM memory module is in an idle state, it is read-inactive. This read-inactive state is similar to the read state; a read operation can be initiated immediately.

[0160] Columns 907 to 909 refer to a set / form operation for the selected bit line.

[0161] Columns 910 to 912 refer to a reset operation for the selected bit line.

[0162] As explained above, a single source line is used for two bit lines. Thus, selecting the source line results in selecting a pair of bit lines. This "selected pair" is shown by columns 901 / 902, 904 / 905, 907 / 908, and 910 / 911. Within the "selected pair," there is one selected bit line (shown by columns 901, 904, 907, and 910) and one deselected bit line (shown by columns 902, 905, 908, and 911). The remaining bit lines are also deselected, as shown in columns 903, 906, 909, and 912.

[0163] Line 924 of the table specifies the desired (target) voltages for the respective bit lines (BL), and line 925 of the table shows the desired (target) voltages for the respective source lines (SL).

[0164] Furthermore, rows 926 to 928 of the table show how this is achieved by applying certain voltages to the respective nodes / lines for the source lines (upper part of Fig. 8).

[0165] Furthermore, the table in rows 929 to 937 shows how this is achieved by applying certain voltages to the respective nodes / lines for the bit lines (lower part of Fig. 8).

[0166] The notation “<31:0>” refers to any one of <0> until <31> Accordingly, the notation “<63:0>” refers to any one of <0> until <63> .

[0167] It is noted that VDD refers to a voltage of 0.9 V or 1 V, and "0" refers to 0 V (also known as ground or VSS).

[0168] VCLAMP corresponds to a voltage level that represents an exemplary threshold voltage of the HV-NMOS across VDD. The voltage level of VCLAMP can be an on-chip voltage that may vary with temperature, process corners, or other effects. If VCLAMP is applied to the gate of an HV-NMOS, its source can be connected to VDD and its drain to a higher voltage, e.g., 2.5 V, with no channel current above the leakage current level (e.g., less than 1 µA). If the source of this HV-NMOS is held floating and the conditions remain constant (gate voltage at VCLAMP, drain voltage at 2.5 V), the source will charge to the VDD level.

[0169] In the Fig. 4 (see e.g. node 452), Fig. 7 (see e.g. node 756) and Fig. In the examples shown in 8 (see e.g. HV circuit 804), the HV NMOS components separate the LV and HV areas.

[0170] One embodiment of the VCLAMP voltage generator is in Fig. 10 shown.

[0171] “Z” means that the bit line or the source line is not connected (high impedance).

[0172] Furthermore, there can be a common N-well area for the HV transistors, which can be located at suitable voltage levels (e.g. 1.5 V or 2.5 V).

[0173] The voltage levels shown in parentheses are applied if the selected memory cell is not to be changed (either it already has the intended state or it is waiting to be written to).

[0174] The node bl_pos_hv (line 936 of the table) shows a value “2.5 V / Z” for the reset operation, indicating that there is an initial pulse set to 2.5 V, which is kept potential-free at high impedance Z.

[0175] Fig. Figure 10 shows an example circuit that includes components for generating the voltage level VCLAMP.

[0176] The voltage VCLAMP can depend on specific parameters, such as temperature. Advantageously, VCLAMP can be generated on the chip. The NMOS N0 can be a transistor that is connected to the NMOS N0 <0> to N0 <64> as well as the NMOS N4 <0> to N4 <31> is adapted, as in Fig. 8 shown.

[0177] The voltage VDD, which in this example is 0.9 V, is applied to the positive input of an operational amplifier 1001. The output of the operational amplifier 1001 is connected to the gate of the NMOS N0, which also provides the voltage VCLAMP. The NMOS N0 is connected between a high voltage, e.g., 2.5 V, and a node 1003. The negative input of the operational amplifier 1001 is connected to the node 1003. A current source 1002 is connected between the node 1003 and ground. The current source 1002 supplies a small current in the region of the device channel leakage or slightly higher (e.g., 1 µA). The voltage at the negative input of the operational amplifier 1001 settles to a value close to VDD (ideally at VDD). The gate-source voltage of the NMOS N0 settles to a value close to the threshold voltage of N0 (Vth). Since the source voltage of the NMOS N0 is approximately VDD, the voltage of VCLAMP is approximately VDD+Vth.

Claims

[1] Multiplexer for controlling access to memory cells of a memory, comprising: - a first chain that controls access to the source lines of the memory, wherein the first chain comprises two high-voltage transistors and several low-voltage transistors; - a second chain that controls access to the memory's bit lines, the second chain comprising two high-voltage transistors and several low-voltage transistors, - wherein the two high-voltage transistors of the first chain and / or the second chain are arranged such that a first high-voltage transistor is arranged in each chain to apply the high voltage to the memory, and a second high-voltage transistor is arranged in series with the several low-voltage transistors to protect the low-voltage transistors from the high voltage. [2] Multiplexer according to claim 1, wherein a high-voltage control unit is provided for controlling the high-voltage transistors and a low-voltage control unit is provided for controlling the low-voltage transistors. [3] Multiplexer according to one of the preceding claims, wherein the multiple low-voltage transistors of the first chain and / or the second chain are arranged such that the bit lines or source lines can be selected for each chain and that different voltages can be applied. [4] Multiplexer according to any of the preceding claims, wherein the first chain and the second chain are used to access memory cells of the memory and to perform either a set / form operation, a reset operation or a read operation. [5] Multiplexer according to any of the preceding claims, wherein the memory is an RRAM. [6] Multiplexer according to one of the preceding claims, wherein the memory cells are arranged in a matrix structure and a first chain and a second chain are provided for each row of memory cells. [7] Multiplexer according to any one of claims 1 to 5, wherein the memory cells are arranged in a matrix structure and a first chain is provided for two or a multiple of two second chains, such that two bit lines share one source line. [8] Multiplexer according to any of the preceding claims, wherein the multiplexer is arranged on the same chip or in the same component as the memory. [9] Method for operating a multiplexer that controls access to memory cells of a memory, wherein the multiplexer comprises - a first chain that controls access to the source lines of the memory, wherein the first chain comprises two high-voltage transistors and several low-voltage transistors; - a second chain that controls access to the memory's bit lines, the second chain comprising two high-voltage transistors and several low-voltage transistors, - wherein the two high-voltage transistors of the first chain and / or the second chain are arranged such that a first high-voltage transistor is arranged in each chain to apply the high voltage to the memory, and a second high-voltage transistor is arranged in series with the several low-voltage transistors to protect the low-voltage transistors from the high voltage; wherein the method comprises: - Applying voltages to the first chain and the second chain so that one of the following operations is performed on memory cells of the memory: - a reading operation; - a typesetting / forming operation; - a reversal operation.

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