METAL REFLECTOR GROUNDING FOR NOISE REDUCTION IN A PHOTO DETECTOR

Abstract

Having an IC device: a semiconductor substrate (137); a photodiode (143) formed in the semiconductor substrate (137); a metal compound structure (155) formed on the semiconductor substrate (137); and a reflector (153) formed in the metal compound structure (155) above the photodiode (143), where the reflector (153) is grounded, wherein the reflector (153) is grounded to the semiconductor substrate (137), where the reflector (153) is attached to a P + -doped area (149) of the semiconductor substrate (137) is grounded, where the P + -doped area (149) of the semiconductor substrate (137) is part of the photodiode (143).

Description

BACKGROUND

[0001] Integrated circuits (ICs) with image sensors are used in a wide range of electronic devices, such as cameras and mobile phones. In recent years, complementary metal-oxide semiconductor (CMOS) image sensors have largely replaced charge-coupled device (CCD) image sensors. CMOS image sensors are preferred over CCD image sensors due to their low power consumption, small size, fast data processing, direct data output, and low manufacturing costs. Some types of CMOS image sensors include front-illuminated (FSI) and back-illuminated (BSI) image sensors. Many of these image sensors are optimized for detecting visible light.However, there is a growing need for image sensors that detect non-visible radiation, especially near-infrared (NIR) for security, personal authentication and distance measurement applications.

[0002] US 2014 / 0 077 323 A1 reveals in Fig. 2 a photodetector semiconductor device for detecting light in the infrared range with photodiodes 38 in a substrate 50, wherein light enters the semiconductor device through lenses 39 and is reflected at a reflector 55.

[0003] Further prior art relating to the subject matter of the invention can be found, for example, in publications US 2012 / 0 050 554 A1 and US 2013 / 0 200 251 A1.

[0004] The invention provides for an IC device according to claim 1, a semiconductor image sensor device according to claim 7, and a method according to claim 11. Embodiments are specified in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Aspects of this disclosure are best understood with reference to the detailed description below in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been enlarged or reduced arbitrarily for the sake of clarity. Fig. Figure 1 shows a cross-sectional view of an IC device according to some aspects of the present disclosure. Fig. Figure 2 shows a cross-sectional view of an IC device according to some further aspects of the present disclosure. Fig. Figure 3 shows a cross-sectional view of an IC device according to some further aspects of the present disclosure. Fig. Figures 4-20 show a sequence of cross-sectional views of an IC device undergoing a manufacturing process according to some aspects of the present disclosure. Fig. Figures 21-22 show a sequence of cross-sectional views of an IC undergoing a manufacturing process according to some further aspects of the present disclosure. Fig. Figure 23 shows a flowchart of a manufacturing process according to some aspects of the present disclosure. DETAILED DESCRIPTION

[0006] The present disclosure provides many different embodiments and examples for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not to be understood as limiting. For example, the following description of the formation of a first feature over or on a second feature may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact.

[0007] Back-illuminated CMOS image sensors suitable for visible light detection require increased sensitivity for use in NIR detection applications. One approach to achieving this increased sensitivity is to increase the thickness of the substrate's photoadsorption layer. However, this approach has limitations, such as reduced visible image quality due to increased lateral crosstalk. Another approach involves using reflectors on the front of the substrate. However, static buildup on these reflectors has been found to introduce noise.

[0008] The present disclosure solves, in various embodiments, the problem of noise reduction in image sensor devices, particularly NIR detectors, by providing grounding for the reflectors. In some embodiments, the reflectors are grounded by means of vias that couple the reflectors to grounded regions of the substrate. In some of these teachings, the grounded regions of the substrate may be P + These are -doped regions that can form near the surface of the substrate. In some of these teachings, the P + -doped regions around parts of photodiodes. In some other of these teachings, the reflectors are grounded by a metal compound structure formed over the front of the substrate.

[0009] A semiconductor IC device for image acquisition, as described in these teachings, can comprise an array of photodiodes or other CMOS image sensors formed on a semiconductor substrate. After forming the photodiode array, a first dielectric intermediate layer (ILDo) can be formed over the substrate surface. Vias are formed through the first dielectric intermediate layer to make contacts with the substrate. In some of these teachings, one or more of these vias are subsequently used to couple a subsequently formed metal reflector to a region of the substrate held at ground potential. A hard mask can be formed over the first dielectric intermediate layer. The hard mask can be used to selectively structure an opening a portion of the way through the dielectric intermediate layer. The opening can be filled with metal.A planarization process ending at the hard mask can be used to remove excess metal. The remaining metal can form one or more reflectors spaced from the substrate by the dielectric intermediate layer.

[0010] A first metallization layer (M1) can be formed over the hard mask. Forming this first metallization layer can involve depositing dielectric material, etching to create openings through the dielectric, and filling these openings to form various metal structural elements. In some of these designs, one of these openings is formed over a reflector, and one of the metal structural elements is formed in direct contact with the reflector. The reflector can then be grounded through the metal structural element.

[0011] During the operation of a semiconductor IC device for image acquisition according to the present disclosure, electrical charge carriers can migrate to the reflector. These charges can be dissipated by grounding before they accumulate to a sufficient extent to generate an electric field that could constitute a noise source in the IC device.

[0012] Fig. Figure 1 illustrates an IC device 100 according to some aspects of the present disclosure. The IC device 100 comprises a metal compound structure 155 formed over a front face 150 of a semiconductor substrate 137. A lens 141 on a rear face 142 of the substrate 137 focuses light onto a photodiode 143 formed in the substrate 137. The photodiode 143 is a pinned photodiode comprising a deep N-doped region 135 and a shallow P +The doped pinning layer 149 is located near the surface of the front face 150. The photodiode 143 could alternatively be a PIN photodiode or another type of radiation detection device. A reflector 153 is positioned above the front face 150 to reflect light passing through the substrate 137 back onto the photodiode 143 to increase its radiation sensitivity. According to some aspects of the present teachings, the reflector 153 is grounded to the pinning layer 149 of the photodiode 143 by means of a via 151.

[0013] The reflector 153 can be located near the substrate 137. In some of the present teachings, the reflector 153 is formed in a dielectric intermediate layer 113, which is the first dielectric intermediate layer 113 above the substrate 137. In some of the present teachings, the dielectric intermediate layer 113 is a low-k dielectric layer. The reflector 153 is separated from the substrate 137 by various thin films and a section of the dielectric intermediate layer 113. The various thin films can, for example, include an oxide layer 119, a resist protective oxide (RPO) layer 117, and / or a contact etch stop layer 115, or the like. The reflector 153 has a distance 152 from the substrate 137. In some of these gauges, the distance 152 is in the range of 0.01 to 0.5 µm. In some of these gauges, the distance 152 is in the range of 0.05 to 0.3 µm.

[0014] The photodiode 143 can be an arrangement of identical photodiodes formed in the substrate 137. The substrate 137 can be any suitable type of semiconductor substrate. In some of the present teachings, the substrate 137 can be a single-crystal semiconductor. In some of these teachings, the substrate 137 is silicon. The substrate 137 can also be silicon-germanium, indium phosphide, another semiconductor material, or the like. A passivation layer 139 can be formed over the back surface 142 of the substrate 137. A well in the passivation layer 139 can contain a color filter 140 beneath the microlens 141.

[0015] The substrate 137 can be lightly P-doped. Adjacent to photodiodes 143, deep P-wells 145 can be formed in the substrate 137. Electrical insulation can be provided by shallow trench insulation (STI) structures 121. Alternatively, insulation can be provided by deep trench insulation structures, other suitable insulation structures, or the like.

[0016] The metal compound structure 155 can comprise multiple metal compound layers, such as a first metallization layer 107, a second metallization layer 105, a third metallization layer 103, and additional metallization layers (not shown). The vias 104 can connect metal structural elements 102, such as wires and the like, between adjacent metallization layers 103, 105, and 107. The vias 104 and metal structural elements 102 can be made of metals such as copper, aluminum, gold, tungsten, and the like. The vias 104 and metal structural elements 102 are formed in a matrix of interlayer dielectric 106. The interlayer dielectric 106 can be a low-k dielectric or an ultra-low-k dielectric.

[0017] A low-k dielectric is a material with a dielectric constant lower than that of SiO₂. SiO₂ has a dielectric constant of approximately 3.9. Examples of low-k dielectrics include organosilicate glasses (OSGs), such as carbon-doped silicon dioxide, fluorine-doped silicon dioxide (also known as fluorinated silica glass, FSG), low-k dielectrics made of organic polymers, and porous silicate glass. An ultra-low-k dielectric is a material with a dielectric constant of approximately 2.1 or less. An ultra-low-k dielectric material is generally a low-k dielectric material formed into a porous structure. Porosity reduces the effective dielectric constant.

[0018] The photodiode 143 can be selectively coupled to a floating diffusion node 123 by means of a transfer transistor 147. The floating diffusion node 123 can be an N + The doped region of substrate 137 is designed to collect charges produced by the interaction of light with photodiode 143. Additional transistors can be provided to operate photodiode 143. For example, a single pixel in a photodiode array of IC device 100 can use two, three, four, five, or six transistors. Coupling photodiode 143 with transfer transistor 147 can form an N +The doped region of the substrate 137 couples the deep N-well 135 of the photodiode 143 to a channel region of the transfer transistor 147. The transfer transistor 147 may include a gate electrode 129, which is separated from the substrate 137 providing the channel region by a gate dielectric layer 128. A hard mask layer 127 may be present over the gate electrode 129. Spacers 125 may be formed at the sides of the gate electrode 129.

[0019] Fig. Figure 2 illustrates an IC device 200 according to some further aspects of the present disclosure. The IC device 200 is similar to the IC device 100, except that in the IC device 200, the via 151, through which the reflector 153 is grounded, is coupled to a deep p-well 145 in the substrate 137, which is not part of the photodiode 143. The deep p-well 145 can effectively be held at ground potential. Charges migrating onto the reflector 153 due to one process or another can flow away through the deep p-well 145.

[0020] Fig. Figure 3 illustrates a device 300 according to some further aspects of the present disclosure. The IC device 300 is similar to the IC device 100, except that the IC device 300 does not include the via 151 which grounds the reflector 153 to the substrate 137 in the IC device 100. Instead, the reflector 153 is grounded by a metal structural element 154 in the first metallization layer 107. The metal structural element 154 can, in turn, be grounded by means of connections made through the metal connection structure 155.

[0021] In some embodiments, a support structure 101 is attached to the metal interconnect structure 155 above the substrate 137. The support structure 101 can be, for example, a solid substrate or a second IC chip. In some embodiments, the second IC chip is electrically coupled to the reflector 153 via the metal interconnect structure 155. A second IC chip can comprise a second metal interconnect structure (not shown) arranged above a second semiconductor substrate (not shown).

[0022] Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19 to Fig. Figure 20 provides a sequence of cross-sectional views 400 to 2000 illustrating an IC device according to the present disclosure at various stages of manufacture according to a process of the present disclosure. Even if Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19 to Fig. 20. It is understood that the sequence of measures described in section 20 may be changed in some cases and that this sequence of measures may also be applicable to structures other than those illustrated. In some embodiments, some of these measures may be omitted entirely or partially. Furthermore, it is understood that Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19 to Fig. 20 are not limited to a manufacturing process, but can also stand alone as structures separate from the process.

[0023] Fig. Figure 4 shows a cross-sectional view 400 of an IC device 100 or the like in an early stage of fabrication. The cross-sectional view 400 illustrates a substrate 137 in which p-wells 145 and a deep n-well 135 have been formed. The deep n-well 135 can be formed through or almost through the entire thickness of the substrate 137. The substrate 137 can be lightly p-doped. The substrate 137 can be a single-crystal semiconductor. In particular, the substrate 137 can be silicon or the like.

[0024] As the cross-sectional view 400 of the Fig. As further shown in Figure 4, shallow trench insulation regions 121 can be formed in the substrate 137. The shallow trench insulation regions 121 can be formed by etching trenches in the substrate 137 and filling the trenches with a dielectric or a dielectric precursor. The dielectric can be silicon dioxide (SiO2) or the like. A planarization process can be used to remove dielectric from the front face 150 of the substrate 137. The planarization process can be chemical-mechanical polishing (CMP).

[0025] Like the cross-sectional view 500 of the Fig. As shown in Figure 5, a transistor gate stack 502 can be formed on the front face 150 of the substrate 137. The transistor gate stack 502 can comprise a gate dielectric layer 507, a gate electrode layer 505, and a hard mask layer 503. The gate dielectric layer 507 can be silicon dioxide (SiO2) or any other dielectric suitable for the gate of a CMOS transistor. The gate dielectric layer 507 can be deposited onto the substrate 137 or grown by oxidizing a layer on the surface of the substrate 137. The gate electrode layer 505 can be doped polysilicon or the like, or any other conductor suitable for the gate of a CMOS transistor. The gate electrode layer 505 can be formed by chemical vapor deposition (CVD) or any other suitable process.The hard mask layer 503 can be silicon nitride or the like, or any other material suitable for a hard mask. The hard mask layer 503 can be formed by chemical vapor deposition (CVD) or any other suitable process.

[0026] Like the cross-sectional view 500 of the Fig. As shown in Figure 5, a photoresist mask 501 can be formed and structured over the transistor gate stack 502. The photoresist mask 501 can be structured by a photolithography process. The photoresist mask 501 can be a positive or negative resist, which is structured by selective exposure through an intermediate stencil and selective ablation of either the exposed or the unexposed areas to transfer the intermediate stencil structure onto the photoresist mask 501.

[0027] Like the cross-sectional view 600 of the Fig. As shown in Figure 6, the transistor gate stack 502 can be structured using the photoresist mask 501. The structuring process can involve etching through the various layers of the transistor gate stack 502. Any suitable etching process can be used. The etching process can include dry etching processes such as plasma etching or the like, and can comprise multiple phases. The structuring forms the transfer transistor 147 and includes forming the hard mask 127 from the hard mask layer 503, the gate electrode 129 from the gate electrode layer 505, and the gate dielectric layer 131 from the gate dielectric layer 507.

[0028] Like the cross-sectional view 700 of the Fig. As shown in Figure 7, after forming the transfer transistor 147 over the substrate 137, a photoresist mask 701 can be formed and the substrate 137 can be intensively N+-doped to form the floating diffusion node 123. This doping can also form a source / drain region 133 of the deep N-well 135, which provides a source / drain region for the transfer transistor 147 and couples the deep N-well 135 to the transfer transistor 147.

[0029] Like the cross-sectional view 800 of the Fig. As shown in section 8, the photoresist mask 701 can then be removed and another photoresist mask 801 formed, followed by intensive P +Doping follows to form the pinning layer 149 of the photodiode 143. As illustrated, the pinning layer 149 can extend beyond the area of ​​the deep N-well 135. The pinning layer 149 can extend to the STI region 121 or terminate before the STI region 121, as shown in this example. In some of these teachings, the pinning layer 149 and other intensive P + -doped regions exhibit a dopant concentration that is at least 1×10 18 atoms per cm 3 is. In some of these teachings, the intensive P + -doped regions exhibit a dopant concentration of at least 1×10 19 atoms per cm 3 is. In some of these teachings, the intensive P + -doped regions exhibit a dopant concentration of at least 3×10 19 atoms per cm 3 amounts.

[0030] Like the cross-sectional view 900 of the Fig. As shown in Figure 9, the photoresist mask 801 can then be removed and applied over the surface as shown in the cross-sectional view 800. Fig. In the structure shown in Figure 8, an oxide layer 119 is formed. This oxide layer 119 can be formed by CVD, plasma-enhanced CVD (PECVD), or any other suitable process. In some of these teachings, the oxide layer 119 is formed from tetraethyl orthosilicate (TEOS).

[0031] Like the cross-sectional view 1000 of the Fig. As shown in Figure 10, spacers 125 can be formed on the sides of the transfer transistor 147. The formation of the spacers 125 can involve the deposition of silicon nitride or another spacer material by CVD or the like, or any other suitable process, followed by etching to leave only the material forming the spacers 125.

[0032] As the cross-sectional view 1100 of the Fig. As shown in section 11, 1000 of the cross-sectional views can be viewed above. Fig. In the structure shown in Figure 10, various boundary layers can be conformally deposited. These can include the RPO layer 117, the contact etch stop layer 115, or the like. As shown in the cross-sectional view 1100 of the Fig. As further shown in Figure 11, a first dielectric intermediate layer 113 (an ILD0 layer) can then be formed. These layers can be formed by any suitable process or any suitable combination of processes. The ILD0 can be formed with a flat top surface 112 or subjected to a planarization process after deposition. A planarization process could be CMP or the like.

[0033] Like the cross-sectional view 1200 of the Fig. As shown in Figure 12, a photoresist mask 1203 can be formed over the dielectric intermediate layer 113 and used to structure openings through the dielectric intermediate layer 113 and further intermediate layers, extending the openings down to the substrate 137. These openings can include an opening 1205 leading to the floating diffusion region 123. In some of these drawings, these openings include an opening 1201 that intersects the pinning layer 149 of the substrate 137.

[0034] As the cross-sectional view 1300 of the Fig. Figure 13 shows that the cross-sectional view 1200 of the Fig. The openings 1201, 1205 shown in Figure 12 are filled with conductive material to form vias through the dielectric intermediate layer 113. In particular, opening 1201 can be filled to form the via 151, and opening 1205 can be filled to form the via 111. The conductive material can be deposited or grown from a seed layer. Filling the openings 1201, 1205 with conductive material can be followed by a planarization step to remove conductive material outside the openings 1201, 1205. The vias 111, 151 can be a metal such as copper, aluminum, gold, tungsten, and the like. In some embodiments, the vias 111, 151 are made of cobalt or the like.

[0035] As the cross-sectional view 1400 of the Fig. Figure 14 shows that the cross-sectional view 1300 can be viewed above. Fig. In the structure shown in Figure 13, an etch stop layer 109 is formed. The etch stop layer 109 can be silicon carbide (SiC) or the like, or another dielectric material suitable for an etch stop layer. In some embodiments, the etch stop layer 109 is deposited to a thickness in the range of 100 Å to 600 Å. In some embodiments, the etch stop layer 109 is deposited to a thickness in the range of 300 Å to 500 Å.

[0036] Like the cross-sectional view 1500 of the Fig. 15 shows, can be seen above the cross-sectional view 1400 of the Fig. Figure 14 illustrates a photoresist mask 1501 formed and used to etch an opening 1503 through the etch stop layer 109 and a portion of the way through the dielectric intermediate layer 113. The material of the via 151 may have a lower etch rate than the dielectric of the dielectric intermediate layer 113. As a result, the via 151 may protrude into the opening 1503.

[0037] As the cross-sectional view 1600 of the Fig. As shown in Figure 16, the photoresist mask 1501 can be removed and the metal 1601 grown or deposited to fill the opening 1503. The metal 1601 can be deposited around the exposed portion of the via 151. The metal 1601 can be formed by electroplating, electroless deposition, physical vapor deposition (PVD), or any other suitable process. The metal 1601 can be any material suitable as a reflector. In some of these teachings, the metal 1601 is an aluminum-copper alloy (AlCu) or the like.

[0038] As the cross-sectional view 1700 of the Fig. Figure 17 shows that the excess metal 1601 can be removed by a planarization process such as CMP to form the reflector 153. The planarization process can reduce the thickness of the etch stop layer 109. As shown in the cross-sectional view 1800 of the Fig. As shown in Figure 18, an additional deposition can be carried out to increase the thickness of the etch stop layer 109 and to provide a thickness of the etch stop layer 109 above the reflector 153.

[0039] As the cross-sectional view from 1900 shows Fig. Figure 19 shows that a layer of intermediate dielectric 106 can be formed above the etch stop layer 109. As shown in the cross-sectional view 1900 of the Fig. Figure 19 further shows that a photoresist 1903 can be formed above the intermediate dielectric 106 and used to structure openings 1901 through the intermediate dielectric 106. As shown in the cross-sectional view 2000 of the Fig. As shown in Figure 20, the openings 1901 can be filled with metal to form a metal structural element 102 as well as further metal structural elements of the first metallization layer 107 (M1). The metal can be deposited or grown by any suitable process. A suitable process could be electroplating, electroless deposition, physical vapor deposition (PVD), or the like. Subsequently, additional processing can be carried out to complete the BEOL processing, forming the metal compound layer 155 and adding further structural elements to create a device such as the one shown in Figure 20. Fig. 1 IC device shown, 100 to be produced.

[0040] Variations of the cross-sectional views 400 to 2000 are possible. Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19 to Fig. The process illustrated in Figure 20 can be used to form further devices according to the present teachings. For example, an alternative placement of the via 151, the formation of which is shown in the cross-sectional views 1200 and 1300 of the Fig. 12 and Fig. Figure 13 illustrates how to use the IC device 200. Fig. 2. In some embodiments, the through-hole connection 151 grounding the reflector 153 is not formed at all, and the reflector 153 is grounded in an alternative way.

[0041] The cross-sectional views 2100 and 2200 of the Fig. 21 and Fig. Figure 22 illustrates an alternative process in which the via 151 may not be formed. In addition to the omission of the via 151, the process in this figure differs from that shown in cross-sectional views 400 to 2000. Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19 to Fig. Figure 20 illustrated that, in addition to the formation of the opening in 1901 in the photoresist in 1903, as shown by the cross-sectional view in 1900, the Fig. Figure 19 shows that a further opening 2101 is formed, as shown by the cross-sectional view 2100 of the Fig. 21 is shown. The opening 2101 is formed above the reflector 153. Subsequently, the formation of the first metallization layer 107 (M1) by filling the openings 1901, 2101 in the dielectric intermediate layer 106 produces a metal structural element 154, which, as shown by the cross-sectional view 2100 of the Fig. 21 shows the reflector 153 being contacted. Further processing of this structure can be found in Fig. Provide the IC device shown in section 300.

[0042] Fig. Figure 23 provides a flowchart of a process 2300 according to some aspects of the present disclosure, which can be used to produce IC devices according to the present disclosure. Although process 2300 is illustrated and described here as a sequence of actions or events, it is understood that the illustrated sequence of such actions or events is not to be interpreted restrictively. For example, some actions may be carried out in different sequences and / or simultaneously with other actions or events than those illustrated and / or described here. Furthermore, not all illustrated actions need to be required to implement one or more aspects or embodiments of the present description. Additionally, one or more of the actions illustrated here may be carried out in one or more separate actions and / or phases.

[0043] Process 2300 begins with measure 2301, the formation of deep N-troughs 135 and deep P-troughs 145 in a substrate 137, as shown in the cross-sectional view 400 of the Fig. 4 shown. The substrate 137 can initially be easily P - -doped. The deep N-wells 135 later correspond to pixels of photodiodes 143, and the deep P-wells 145 can provide insulation between adjacent photodiodes 143.

[0044] Measure 2303 includes the formation of insulating structures 121, which are also shown in the cross-sectional view 400 of the Fig. Figure 4 shows that the insulating structures 121 can provide electrical insulation between components formed in the substrate 137 near the front face 150.

[0045] Measure 2305 comprises forming a transistor gate stack 502 over the front face 150, as shown in Fig. Figure 5 shows that the transistor gate stack 502 can be used to form one type of transistor. The transistor gate stack 502 can be removed from some areas of substrate 137, and other transistor gate stacks (not shown) can be formed and structured to provide other types of transistors.

[0046] Measure 2307 includes structuring the transistor gate stack 502 to accommodate the transfer transistor 147 as shown in cross-sectional view 600. Fig. 6 shown. The structuring carried out by measure 2307 can also produce further transistors that serve other purposes.

[0047] Measure 2309 includes doping the substrate 137 as shown in cross-sectional view 700 of the Fig. 7 shown to the floating diffusion node 123 and further intensive N +-to form doped regions such as the source / drain region 133. The transfer transistor 147 can provide an alignment for this doping process. A photoresist mask can be used to further limit the regions to be doped with the measure 2309.

[0048] Measure 2311 includes doping as shown in cross-sectional view 800 of the Fig. Figure 8 shows how to pin the layer 149 of the photodiode 143. Fig. 8 shown as well as further intensive P + -doped areas on the front face 150 of substrate 137 to define. The intensive P + The doping-receiving areas can be delimited by a photoresist 801. In some embodiments, the pinning layer 149 is permitted to extend to the STI region 121.

[0049] Measure 2313 comprises forming the side wall spacers 125 and the various boundary layers on the front face 150 of the substrate 137, which are shown in cross-sectional views 900 to 1100 of the Fig. 9, Fig. 10 to Fig. Figure 11 shows the interface layers. The interface layers can comprise the oxide layer 119, the photoresist protective oxide layer 117, and the etch stop layer 115. The oxide layer 119 can be formed upstream of the sidewall spacers 125. The photoresist protective oxide layer 117 can be formed downstream of the sidewall spacers 125.

[0050] Measure 2315 includes the formation of the first dielectric intermediate layer (ILD0) 113 as shown in cross-sectional view 1100 of the Fig. Figure 11 shows that the first dielectric intermediate layer 113 can be formed with a planar top surface or its top surface can be planarized after its formation.

[0051] Measure 2317 comprises forming vias 111, 151 through the first dielectric intermediate layer 113, as shown in cross-sectional views 1200 and 1300 of the Fig. 12 and Fig. Figure 13 shows that in some embodiments, the via 151 is formed such that it contacts the pinning layer 149. In some embodiments, the via 151 is formed such that it contacts the deep P-well 145. In some embodiments, the via 151 is not formed at all.

[0052] Measure 2319 comprises forming the etch stop layer 109 over the first dielectric intermediate layer 113, as shown in cross-sectional view 1400 of the Fig. 14 shown. Measure 2321 includes forming the reflector 153 as shown in cross-sectional views 1500 to 1700 of the Fig. 15, Fig. 16 to Fig. Figure 17 shows the formation of the reflector 153. This can be achieved by etching an opening 1503 in the first dielectric intermediate layer 113 as shown in Figure 17. Fig. 15 shown, filling the opening 1503 with metal 1601 as in Fig. 16 shown and chemical-mechanical polishing as in Fig. 17 shown include.

[0053] Measure 2323 includes a re-deposition of the etch stop layer 109 as shown in cross-sectional view 1800 of the Fig. Figure 18 shows that the re-deposition can restore the thickness of the etch stop layer 109 lost during the formation of the reflector 153 and can also extend the etch stop layer 109 over the reflector 153.

[0054] Measure 2325 comprises forming the first metallization layer 107 over the etch stop layer 109, as shown in cross-sectional views 1900 and 2000 of the Fig. 19 and Fig. 20 or alternatively in the cross-sectional views 2100 and 2200 of the Fig. 21 and Fig. 22 shown. The first metallization layer 107 can comprise metal structural elements 102. In some embodiments, the first metallization layer 107 comprises metal structural elements 154 that provide connections with the reflector 153, as shown in Fig. 22 shown. Measure 2327 includes further processing to complete the formation of an IC device such as IC device 100 of the Fig. 1, the IC device 200 of the Fig. 2, the IC device 300 of the Fig. 3 or the like.

[0055] Some aspects of the present teachings relate to an integrated circuit (IC) device comprising a semiconductor substrate, a photodiode formed in the semiconductor substrate, a metal compound structure formed on the semiconductor substrate, and a reflector formed in the metal compound structure above the photodiode. According to the present teachings, the reflector is grounded.

[0056] Several aspects of the present teachings relate to a semiconductor image sensor device. The device comprises a radiation detection region located in the semiconductor substrate. The radiation detection region is configured to detect radiation projected from a rear side of the semiconductor substrate. The device further comprises a reflector positioned on a front side of the semiconductor substrate. The reflector is configured to reflect light passing through the semiconductor substrate back onto the radiation detection region. A connection to the reflector is provided through which the reflector can be grounded. In some of these teachings, the connection is made to a metal compound structure. In some of these teachings, the connection is made to the substrate.

[0057] Some aspects of the present teachings relate to a method for fabricating an integrated circuit (IC) device. The method includes forming a photodiode array in a semiconductor substrate, forming a dielectric layer over the semiconductor substrate, forming vias through the dielectric layer, forming a hard mask over the dielectric layer, using the hard mask to selectively etch an opening a portion of the way through the dielectric layer, filling the opening with metal, planarizing the metal to form a reflector, and forming a metal compound layer over the dielectric layer and the reflector. The reflector is connected either to one of the vias or to a metal structural element in the metal compound layer.

[0058] The foregoing outlines features of various embodiments so that a person skilled in the art may better understand the aspects of the present disclosure. It is obvious to a person skilled in the art that the present disclosure can readily be used as a basis for designing or modifying further processes and structures to pursue the same purposes and / or achieve the same advantages as the embodiments presented herein. The person skilled in the art should further recognize that such equivalent designs do not deviate from the fundamental concept and scope of the present disclosure and that various changes, substitutions, and modifications can be made to what is described herein without deviating from the fundamental concept and scope of the present disclosure.

Claims

[1] Having an IC device: a semiconductor substrate (137); a photodiode (143) formed in the semiconductor substrate (137); a metal compound structure (155) formed on the semiconductor substrate (137); and a reflector (153) formed in the metal compound structure (155) above the photodiode (143), where the reflector (153) is grounded, wherein the reflector (153) is grounded to the semiconductor substrate (137), where the reflector (153) is attached to a P + -doped area (149) of the semiconductor substrate (137) is grounded, where the P + -doped area (149) of the semiconductor substrate (137) is part of the photodiode (143). [2] IC device according to claim 1, wherein the reflector (153) is grounded by a metallization layer in the metal compound structure (155). [3] IC device according to any of the preceding claims, wherein a transistor is formed on the semiconductor substrate (137), wherein a dielectric intermediate layer (113) is formed around and above the transistor, wherein the metal compound structure (155) has a first metallization layer which is separated from the semiconductor substrate (137) by the dielectric intermediate layer (113); and wherein the reflector (153) is formed on the dielectric intermediate layer (113). [4] IC device according to claim 3, wherein a metal structural element (154) is formed in the first metallization layer above the reflector (153) and contacts the reflector (153). [5] IC device according to claim 3 or 4, wherein several vias (151, 111) are formed in the dielectric intermediate layer (113); and one (151) of the several vias (151, 113) contacts the reflector (153). [6] IC device according to claim 1, wherein the photodiode (143) is configured to detect near-infrared light. [7] comprising a semiconductor image sensor device: a radiation detection region (143) arranged in a semiconductor substrate (137), wherein the radiation detection region (143) is configured to detect radiation projected from a rear side of the semiconductor substrate (137); a reflector (153) arranged on a front face of the semiconductor substrate (137), wherein the reflector (153) is configured to reflect light passing through the semiconductor substrate (137) back onto the radiation detection region (143); and a connection (151, 154) to the reflector (153) through which the reflector (153) can be placed on earth, wherein the connection (151, 154) has a via (151) that couples the reflector (153) to a grounded area of ​​the semiconductor substrate (137), wherein the connection (151, 154) has a via (151) which connects the reflector (153) to a P + -doped region (149) of the semiconductor substrate (137) couples, wherein the P + -doped area (149) of the semiconductor substrate (137) is part of a photodiode of the radiation detection region (143). [8] Semiconductor image sensor device according to claim 7, wherein the connection (151, 154) comprises a metal structural element (154) in a metal compound structure (155) on the front side of the semiconductor substrate (137). [9] Semiconductor image sensor device according to one of claims 7 or 8, wherein the semiconductor image sensor device is configured to detect near infrared light. [10] Semiconductor image sensor device according to one of claims 7 to 9, wherein the reflector (153) is spaced apart from the semiconductor substrate (137) by a low-k dielectric layer. [11] Method for manufacturing an IC device, comprising: Forming a photodiode array in a semiconductor substrate (137); Forming a dielectric layer (113) over the semiconductor substrate (137); Formation of vias (151, 111) through the dielectric layer (113); Forming a hard mask (1501) over the dielectric layer (113); Using the hard mask (1501) to selectively etch an opening (1503) a portion of the way through the dielectric layer (113); Filling the opening (1503) with metal (1601); Planarizing the metal (1601) to form a reflector (153); and Forming a metal compound layer (107) over the dielectric layer (113) and the reflector (153), wherein the reflector (153) is connected either to one of the vias (151, 111) or to a metal structural element (154) in the metal compound layer (107), wherein at least one (151) of the vias (151, 111) connects the reflector (153) to the semiconductor substrate (137), wherein at least one (151) of the vias (151, 111) connects the reflector (137) with a P + -doped region (149) of the semiconductor substrate (137) connects, where the P + -doped region (149) of the semiconductor substrate (137) is part of a photodiode (143) of the photodiode arrangement. [12] Method according to claim 11, wherein the reflector (153) is in contact with the metal structural element (154). [13] Method according to one of claims 11 or 12, wherein the dielectric layer (113) is a low-k dielectric layer.

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