ACTIVE FILTER WITH ADAPTIVE AMPLIFICATION FOR HIGH-FREQUENCY DC-DC CONVERTERS WITHOUT DIVIDER

Abstract

Power converter for performing a power conversion and generating an output voltage (Vout) according to a reference voltage (Vref) for the output voltage (Vout), wherein the power converter comprises the following: a filter circuit for filtering (S1010) the output voltage (Vout) of the power converter; an error amplifier circuit (50, 250) which receives the reference voltage (Vref) as the first input voltage (Vin1) and receives the filtered output voltage (Vout) as the second input voltage (Vin2), for comparing (S1020) the first input voltage (Vin1) and the second input voltage (Vin2) and for generating (S1020) an error voltage according to a result of the comparison; and a control circuit for controlling (S1030) one or more switching devices depending on the fault voltage; wherein the error amplifier circuit (50, 250) has the following: a first differential circuit (610) that receives the first input voltage (Vin1) and the second input voltage (Vin2) as inputs, and a first bias current generation circuit (630) for generating a first bias current for the first differential circuit (610); a second differential circuit (620) that receives the first input voltage (Vin1) and the second input voltage (Vin2) as inputs, and a second bias current generation circuit (640) for generating a second bias current for the second differential circuit (620); and a bias current redistribution circuit for redistributing (S1130) at least part of the first bias current to the second differential circuit (620) or for redistributing (S1130) at least part of the second bias current to the first differential circuit (610).

Description

Technical area

[0001] This disclosure relates to power converters (e.g., DC-DC converters) and methods for performing power conversion using power converters (e.g., DC-DC converters). More particularly, this disclosure relates to the application of adaptive gain techniques to create adaptive active filters of loop compensators that enable wide-range, divider-free, high-frequency power converters (such as DC-DC converters, e.g., buck converters). The disclosure is particularly applicable to power converters where a wide output regulation range is desired while maintaining stable bandwidth operation and low frequency gain. background

[0002] A large number of conventional power conversion techniques (e.g., DC-DC power conversion) rely on a converter control loop with a feedback factor of less than one to reduce the input voltage range of the active filter amplifier.However, these techniques achieve the control objective at the expense of system cost and a number of drawbacks, including static power loss due to static divider power consumption, reduced efficiency especially at low load / power conditions, higher sensitivity to thermal noise due to higher thermal (4KTR) noise, reduced signal fidelity due to reduced signal-to-noise ratio (SNR) resulting from reduced signal level with increased noise, reduced output voltage accuracy due to divider component loss, higher number of large passive components resulting in larger silicon area, and possible bandwidth stability issues depending on the chosen divider component values.

[0003] On the other hand, loop compensators without feedback splitting can suffer from correlated gain variation of an error amplifier (EA) input signal level and severe bandwidth degradation when using a feedback factor equal to one. Such loop compensators are subject to large gain variations, which complicates loop design and stability, and are therefore only applicable in scenarios where a limited or narrow input operating range is relevant.

[0004] There is also currently an emerging trend in the area of ​​portable computer power management toward the use of fully integrated or system-in-package (SiP) high-speed voltage regulators / converters to reduce system printed circuit board (PCB) area and bill of material (BOM) costs, as well as to provide fast dynamic voltage scaling (DVS) performance in response to CPU / GPU power-saving needs, among others. For such practical embedded high-speed multiphase power converters (e.g., DC-DC converters) that must operate at switching frequencies in the high tens to hundreds of megahertz (MHz), the previously neglected system costs of using control loop dividers, discussed above, begin to play a role.

[0005] Thus, there is a need for improved power converters (e.g., DC-DC converters) and improved methods for power conversion using power converters (e.g., DC-DC converters). There is also a need for power converters (e.g., DC-DC converters) and corresponding methods that utilize a feedback factor equal to one and can achieve fast, efficient, and wide-range, dividerless high-frequency operation without gain programming.

[0006] US 2018 / 0 034 376 A1 describes a control device for a switching power converter comprising an inductor element, a switch coupled to the inductor element, a storage element coupled to an output at which an output voltage is provided, and a diode element coupled to the storage element. US 2016 / 0261260 A1 describes an input buffer circuit comprising a first current source, a first differential control circuit, a second current source, a second differential control circuit, a third current source, a first differential output circuit, a fourth current source, and a second differential output circuit. Summary

[0007] In view of some or all of these needs, the present disclosure proposes a power converter and a method for performing power conversion having the features of the respective independent claims.

[0008] One aspect of the disclosure relates to a power converter according to the appended main claim (claim 1). The power converter may, for example, be a DC-DC converter. The first differential circuit may be a p-type differential circuit (e.g., a p-type differential pair). The second differential circuit may be an n-type differential circuit (e.g., an n-type differential pair).

[0009] When configured as proposed, the error amplifier circuit has a wide input voltage range, a wide bandwidth, and stable gain across the entire input voltage range to provide sufficient gain for a low overall loop accuracy error, while avoiding the degradation of system phase margin by avoiding the introduction of pole(s) into the converter loop bandwidth. This is a key element to achieve a constant-gain loop compensator (adaptive active filter) with greater flexibility in passive component selection, enabling efficient, wide-range, high-frequency, divider-free power converters (such as DC-DC converters, e.g., buck converters) with fast dynamic voltage scaling response, particularly in large-node CMOS technologies such as 0.13 µm CMOS or older.Accordingly, the proposed power converter can be dividerless (i.e., have a divider ratio of one for the feedback voltage).

[0010] In some embodiments, the bias current redistribution circuit may be configured to redistribute at least a portion of the first bias current or at least a portion of the second bias current such that an input transconductance of the error amplifier circuit is brought closer to a constant input transconductance across an input voltage range of the error amplifier circuit. This may achieve a substantially flat input transconductance of the error amplifier circuit from rail to rail.

[0011] In some embodiments, the filtered output voltage received by the error amplifier circuit as the second input voltage may have the same voltage range as the output voltage. The voltage range may be rail-to-rail, for example, extending from the negative rail (e.g., ground rail) to the positive rail (e.g., power rail). This means that the output voltage does not need to be divided by a voltage divider before being fed to the error amplifier circuit.That is, the power converter can be a divider-less power converter, thereby avoiding static power consumption of the divider, increasing system efficiency especially under light load / power conditions, reducing sensitivity to thermal noise, increasing signal fidelity due to improved SNR, increasing output voltage accuracy due to the absence of divider component loss, reducing the number of large passive components, resulting in reduced silicon area, and avoiding potential bandwidth stability issues.

[0012] In some embodiments, the bias current redistribution circuit may include a first bypass circuit configured to bypass the first differential circuit and apply at least a portion of the first bias current to the second differential circuit. The bias current redistribution circuit may further include a second bypass circuit configured to bypass the second differential circuit and apply at least a portion of the second bias current to the first differential circuit. This enables a simple and efficient implementation of the bias current redistribution circuit.

[0013] In some embodiments, the first bypass circuit may operate under the control of a first control signal. The second bypass circuit may operate under the control of a second control signal. The error amplifier circuit may further comprise a controller circuit for generating the first control signal for the first bypass circuit and the second control signal for the second bypass circuit. The controller circuit may be referred to as a matching controller. The control signals may be threshold voltage-dependent references or may depend on the first and / or second input voltage. This may allow appropriate control of the bias current to the more suitable differential circuit to maximize the input transconductance.

[0014] In some embodiments, the first differential circuit may include a first p-type field-effect transistor (FET). The first differential circuit may further include a second p-type FET. The first input voltage may be applied to a gate terminal of the first p-type FET. The second input voltage may be applied to a gate terminal of the second p-type FET. Further, source terminals of the first and second p-type FETs may be coupled to the first bias current generation circuit. A first differential output signal may be tapped at respective drain terminals of the first and second p-type FETs.

[0015] In some embodiments, the first and second p-type FETs can be operated in their subthreshold region. This can improve matching (maximizing input transconductance) and reduce overall power consumption.

[0016] In some embodiments, the first bypass circuit may comprise a third p-type FET. The first bypass circuit may further comprise a first current mirror for mirroring a current flowing through the third p-type FET. The first control voltage may be applied to a gate terminal of the third p-type FET. A source terminal of the third p-type FET may be coupled to the first bias current generation circuit. The first current mirror may be arranged to apply the mirrored current of the current flowing through the third p-type FET to the second differential circuit (e.g., the first current mirror may be arranged to sink the mirrored current from the second differential circuit). For example, the first current mirror may be arranged to apply the mirrored current of the current flowing through the third p-type FET to source terminals of first and second n-type FETs of the second differential circuit (e.g.,the first current mirror may be arranged to drain the mirrored current from the source terminals of the first and second n-type FETs of the second differential circuit).

[0017] In some embodiments, the second differential circuit may include a first n-type FET. The second differential circuit may further include a second n-type FET. The first input voltage may be applied to a gate terminal of the first n-type FET. The second input voltage may be applied to a gate terminal of the second n-type FET. Source terminals of the first and second n-type FETs may be coupled to the second bias current generation circuit. A second differential output signal may be tapped at respective drain terminals of the first and second n-type FETs.

[0018] In some embodiments, the first and second n-type FETs may be operated in their subthreshold range. This may improve matching (maximizing input transconductance) and reduce overall power consumption.

[0019] In some embodiments, the second bypass circuit may comprise a third n-type FET. The second bypass circuit may further comprise a second current mirror for mirroring a current flowing through the third n-type FET. The second control voltage may be applied to a gate terminal of the third n-type FET. A source terminal of the third n-type FET may be coupled to the second bias current generation circuit. The second current mirror may be arranged to apply the mirrored current of the current flowing through the third n-type FET to the first differential circuit (e.g., the second current mirror may be arranged to supply the mirrored current to the first differential circuit). For example, the second current mirror may be arranged to apply the mirrored current of the current flowing through the third n-type FET to source terminals of the first and second p-type FETs of the first differential circuit (e.g.,the second current mirror may be arranged to supply the mirrored current to the source terminals of the first and second p-type FETs of the first differential circuit).

[0020] In some embodiments, the controller circuit may include a current source. The controller circuit may further include a current sink. The controller circuit may further include a fourth p-type FET coupled in series with the current sink between a supply voltage and ground. A gate terminal of the fourth p-type FET may be coupled to a drain terminal of the fourth p-type FET. The controller circuit may further include a fourth n-type FET coupled in series with the current source between the supply voltage and ground. A gate terminal of the fourth n-type FET may be coupled to a drain terminal of the fourth n-type FET. The first control voltage may be tapped at the gate terminal of the fourth p-type FET. The second control voltage may be tapped at the gate terminal of the fourth n-type FET.

[0021] In some embodiments, the controller circuit may be configured to generate the first and second control voltages based on a third input voltage that depends on the first input voltage and / or the second input voltage. Then, the controller circuit may comprise a current source. The controller circuit may further comprise a current sink. The controller circuit may further comprise a fourth p-type FET and a fifth p-type FET coupled in series with the current sink between a supply voltage and ground. A gate terminal of the fourth p-type FET may be coupled to a drain terminal of the fifth p-type FET. The controller circuit may further comprise a fourth n-type FET and a fifth n-type FET coupled in series with the current source between the supply voltage and ground.A gate terminal of the fourth n-type FET may be coupled to a drain terminal of the fifth n-type FET. The third input voltage may be applied to a gate terminal of the fifth p-type FET and to a gate terminal of the fifth n-type FET. The first control voltage may be tapped at the gate terminal of the fourth p-type FET. The second control voltage may be tapped at the gate terminal of the fourth n-type FET.

[0022] In some embodiments, the error amplifier circuit may further comprise a signal combiner stage for combining a first differential signal generated by the first differential circuit and a second differential signal generated by the second differential circuit.

[0023] In some embodiments, the filter circuit may comprise a first parallel circuit having two parallel branches with a first resistance in one of the parallel branches and a series connection of a second resistance and a first capacitance in the other of the parallel branches. The first parallel circuit may be coupled to an input terminal of the error amplifier circuit. The filter circuit may further comprise a second parallel circuit having two parallel branches with a second capacitance in one of the parallel branches and a series connection of a third resistance and a third capacitance in the other of the parallel branches. The second parallel circuit may be connected between the input terminal of the error amplifier circuit and an output terminal of the error amplifier circuit.

[0024] A further aspect of the disclosure relates to a method according to appended independent claim 18 (patent claim 18). The method can be carried out using a power converter. The power converter can be, for example, a DC-DC converter.

[0025] In some embodiments, redistributing at least a portion of the first bias current to the second differential circuit or redistributing at least a portion of the second bias current to the first differential circuit may comprise redistributing at least a portion of the first bias current or at least a portion of the second bias current such that an input transconductance of the error amplifier circuit is brought closer to a constant input transconductance over an input voltage range of the error amplifier circuit.

[0026] In some embodiments, the filtered output voltage input to the error amplifier circuit as the second input voltage may have the same voltage range as the output voltage. That is, the output voltage does not need to be divided by a voltage divider before being applied to the error amplifier circuit.

[0027] In some embodiments, redistributing at least a portion of the first bias current to the second differential circuit or redistributing at least a portion of the second bias current to the first differential circuit may comprise providing a bypass for the first differential circuit and applying at least a portion of the first bias current to the second differential circuit using a first bypass circuit. Alternatively, the redistributing may comprise providing a bypass for the second differential circuit and applying at least a portion of the second bias current to the first differential circuit using a second bypass circuit. These two modes of providing a bypass may be used alternately depending on the circumstances (e.g., depending on the first and second input voltages Vin1, Vin2, or more generally, on the input signal level).

[0028] In some embodiments, providing the bypass for the first differential circuit may operate under the control of a first control signal. Providing the bypass for the second differential circuit may operate under the control of a second control signal. Then, the method may further comprise generating the first control signal and the second control signal using a controller circuit.

[0029] In some embodiments, the first differential circuit may include a first p-type FET. The first differential circuit may further include a second p-type FET. Then, the method may further include applying the first bias current to source terminals of the first and second p-type FETs. The method may further include applying the first input voltage to a gate terminal of the first p-type FET. The method may further include applying the second input voltage to a gate terminal of the second p-type FET.

[0030] In some embodiments, the method may further comprise operating the first and second p-type FETs in their subthreshold region.

[0031] In some embodiments, the first bypass circuit may include a third p-type FET. Then, the method may further include applying the first bias current to a source terminal of the third p-type FET. The method may further include applying the first control voltage to a gate terminal of the third p-type FET. The method may further include mirroring a current flowing through the third p-type FET using a first current mirror. The method may further include applying the mirrored current of the current flowing through the third p-type FET to the second differential circuit.

[0032] In some embodiments, the second differential circuit may include a first n-type FET. The second differential circuit may further include a second n-type FET. Then, the method may further include applying the second bias current to source terminals of the first and second n-type FETs. The method may further include applying the first input voltage to a gate terminal of the first n-type FET. The method may further include applying the second input voltage to a gate terminal of the second n-type FET.

[0033] In some embodiments, the method may further comprise operating the first and second n-type FETs in their subthreshold region.

[0034] In some embodiments, the second bypass circuit may include a third n-type FET. Then, the method may further include applying the second bias current to a source terminal of the third n-type FET. The method may further include applying the second control voltage to a gate terminal of the third n-type FET. The method may further include mirroring a current flowing through the third n-type FET using a second current mirror. The method may further include applying the mirrored current of the current flowing through the third n-type FET to the first differential circuit.

[0035] In some embodiments, the controller circuit may include a current source. The controller circuit may further include a current sink. The controller circuit may further include a fourth p-type FET coupled in series with the current sink between a supply voltage and ground. A gate terminal of the fourth p-type FET may be coupled to a drain terminal of the fourth p-type FET. The controller circuit may further include a fourth n-type FET coupled in series with the current source between the supply voltage and ground. A gate terminal of the fourth n-type FET may be coupled to a drain terminal of the fourth n-type FET. Then, the method may further include tapping the first control voltage at the gate terminal of the fourth p-type FET. The method may further include tapping the second control voltage at the gate terminal of the fourth n-type FET.

[0036] In some embodiments, the controller circuit may be configured to generate the first and second control voltages based on a third input voltage that depends on the first input voltage and / or the second input voltage. That is, the method may include generating the first and second control voltages based on a third input voltage that depends on the first input voltage and / or the second input voltage. Then, the controller circuit may include a current source. The controller circuit may further include a current sink. The controller circuit may further include a fourth p-type FET and a fifth p-type FET coupled in series with the current sink between a supply voltage and ground. A gate terminal of the fourth p-type FET may be coupled to a drain terminal of the fifth p-type FET.The controller circuit may further comprise a fourth n-type FET and a fifth n-type FET coupled in series with the current source between the supply voltage and ground. A gate terminal of the fourth n-type FET may be coupled to a drain terminal of the fifth n-type FET. The method may further comprise applying the third input voltage to a gate terminal of the fifth p-type FET and to a gate terminal of the fifth n-type FET. The method may further comprise tapping the first control voltage at the gate terminal of the fourth p-type FET. The method may further comprise tapping the second control voltage at the gate terminal of the fourth n-type FET.

[0037] In some embodiments, the method may further comprise combining a first difference signal generated by the first difference circuit and a second difference signal generated by the second difference circuit.

[0038] In some embodiments, the filter circuit may comprise a first parallel circuit having two parallel branches with a first resistance in one of the parallel branches and a series connection of a second resistance and a first capacitance in the other of the parallel branches. The first parallel circuit may be coupled to an input terminal of the error amplifier circuit. The filter circuit may further comprise a second parallel circuit having two parallel branches with a second capacitance in one of the parallel branches and a series connection of a third resistance and a third capacitance in the other of the parallel branches. The second parallel circuit may be coupled between the input terminal of the error amplifier circuit and an output terminal of the error amplifier circuit.

[0039] In particular, the method can be applied to the circuits described above (power converters, e.g., DC-DC converters), for example, as a method for operating these circuits. In addition to the steps for operating these circuits, the method may further comprise steps for providing or arranging one, some, or all elements of these circuits and / or steps for coupling or connecting respective elements of these circuits.

[0040] It is also clear that in this document, the term "couple" or "coupled" refers to elements that are in electrical communication with each other, either directly connected, for example, via wires, or by other means (e.g., indirectly). An example of coupling is connecting. Short description of the drawings

[0041] Exemplary embodiments of the disclosure are explained below with reference to the accompanying drawings, wherein like reference numerals denote like or similar elements, and wherein Fig. 1 schematically shows an example of a DC-DC converter, Fig. 2 schematically illustrates an example of a DC-DC converter according to embodiments of the disclosure, Fig. 3 schematically illustrates an example of an error amplifier circuit according to embodiments of the disclosure, Fig. 4 schematically shows an example of a control device circuit for use in the error amplifier circuit of Fig. 3 according to embodiments of the disclosure, Fig. 5 schematically shows another example of a control device circuit for use in the error amplifier circuit of Fig. 3 according to embodiments of the disclosure, Fig. 6 schematic examples of elements of the error amplifier circuit of Fig. 3 according to embodiments of the disclosure, Fig. 7A and Fig. 7B schematically shows further examples of elements of the error amplifier circuit of Fig. 3 according to embodiments of the disclosure, Fig. 8 and Fig. 9 schematically shows examples of a signal combiner stage for use in the error amplifier circuit of Fig. 3 according to embodiments of the disclosure, Fig. 10 is a flow diagram schematically illustrating a method for performing power conversion using a DC-DC converter according to embodiments of the disclosure, and Fig. 11 is a flow diagram schematically showing a detail of the method of Fig. 10 according to embodiments of the disclosure. Detailed description

[0042] As indicated above, identical or like reference numerals throughout the disclosure denote identical or like elements, and repeated description thereof may be omitted for the sake of brevity.

[0043] In the following description of exemplary embodiments of the disclosure, reference is made to DC-DC converters as examples of power converters. However, the disclosure is not limited thereto and is intended to be applicable to various types of power converters, including switching-mode power converters such as DC-DC converters (e.g., buck converters). The present disclosure may be further applied, for example, to switching AC-DC converters.

[0044] Fig. 1 shows an example of a divider-based DC-DC converter 100 as an example of a power converter to which embodiments of the disclosure are applicable. In the present example, the DC-DC converter is shown as a DC-DC step-down converter, without any intended limitation. The DC-DC converter 100 performs power conversion and outputs an output voltage Vout according to a reference voltage Vref. For this purpose, it comprises an error amplifier circuit 50 for comparing an indication of the output voltage Vout with the reference voltage Vref. The aforementioned indication of the output voltage Vout is obtained by dividing the output voltage Vout by a voltage divider and filtering the voltage-divided output voltage using a filter circuit (e.g., an active loop filter). In the example of Fig. 1, a Type III filter is shown. The filter circuit includes a first parallel circuit having two parallel branches with a first resistor 34 in one of the parallel branches and a series connection of a second resistor 32 and a first capacitor 42 in the other of the parallel branches. The first parallel circuit is coupled to an input terminal (e.g., the inverting input) of the error amplifier circuit 50. The filter circuit further includes a second parallel circuit having two parallel branches with a second capacitor 44 in one of the parallel branches and a series connection of a third resistor 48 and a third capacitor 46 in the other of the parallel branches. The second parallel circuit is coupled between the aforementioned input terminal of the error amplifier circuit 50 and an output terminal of the error amplifier circuit 50.

[0045] As mentioned above, the output voltage Vout of the DC-DC converter 100 is divided before being filtered and fed to the error amplifier circuit 50. For this purpose, the DC-DC converter 100 includes a fourth resistor 36 that forms a voltage divider with the first resistor 34. The fourth resistor 36 is coupled to the aforementioned input terminal of the error amplifier circuit 50. Accordingly, the output voltage Vout is divided by a feedback factor β < 1, which is predetermined by the resistance values ​​of the first resistor 34 and the fourth resistor 36.

[0046] The error amplifier circuit 50 receives the reference voltage Vref and the filtered output voltage at its inputs and compares these voltages. It further generates an error voltage according to a result of the comparison.

[0047] The error voltage generated by the error amplifier circuit 50 is provided to a drive circuit for driving one or more switching devices of the DC-DC converter 100 depending on the error voltage. The switching devices may be, for example, FETs. The switching devices may include a high-side switch (e.g., a high-side FET) 10 and a low-side switch (e.g., a low-side FET) 15. The high-side switch 10 and the low-side switch may be coupled in series between an input voltage to the DC-DC converter 100 and ground.

[0048] The drive circuit includes a comparator 60 that receives the error voltage and a ramp voltage (e.g., a sawtooth voltage) and generates a drive signal D (e.g., a PWM signal) based on the result of the comparison. The ramp voltage can be generated by a ramp generator 65. The drive signal D is then provided to a non-overlapping control block 70, which generates the actual gate drive signals for the switching devices in response to the drive signal D.

[0049] The DC-DC converter 100 further includes an output filter coupled to an intermediate node between the switching devices. The output filter includes an inductor (e.g., output coil) 20 and a capacitance (e.g., output capacitor) 22 coupled in series between the intermediate node and ground. An output node 25 for outputting the output voltage Vout is arranged at an intermediate node between the inductor 20 and the capacitance 22 of the output filter.

[0050] The reference voltage Vref for the output voltage Vout can be provided by a reference voltage generation unit (block, circuit) 55.

[0051] As noted above, relying on a voltage divider to divide the output voltage Vout before providing it to the error amplifier circuit has several disadvantages. The present disclosure attempts to avoid some or all of these disadvantages.

[0052] In general, the present disclosure presents a unity feedback DC-DC converter system control loop scheme used in conjunction with an adaptive input transconductance (gm) to achieve fast and efficient, dividerless, wide output regulation and bandwidth stability for high-frequency multi-phase DC-DC converters (e.g., buck converters).

[0053] Thus, DC-DC converters according to embodiments of the disclosure—possibly in addition to a DC-DC converter active loop filter, closed-loop feedback, and a Class AB output for controlled quiescent output current—include a wide input range (dividerless) loop compensator with input transconductance matching. DC-DC converters according to embodiments of the disclosure may further include a technique for compensating a closed loop of a dividerless converter for high-frequency operation based on the concept of minimal amplifier compensation for extended bandwidth and low, self-contained open loop stability. Finally, DC-DC converters according to embodiments of the disclosure may include a fast-rising, dividerless loop compensation active filter for fast dynamic voltage scaling (DVS) response.

[0054] When using DC-DC converters according to embodiments of the disclosure, significant advantages can be achieved, for example, in the field of the Internet of Things (IoT) and in applications of DC-DC converter systems with power management for portable computers. The present disclosure helps achieve novel, fast, and efficient dividerless wide output regulation and bandwidth stability for embedded high-speed multiphase DC-DC converters using smart adaptive error amplification (SM-EA). Likewise, the design of improved loop compensators is supported, using the idea of ​​constant-gain adaptive amplification in switch-mode power supplies (SMPS). This is particularly applicable to divider-free buck designs for a variety of applications.

[0055] In contrast to conventional techniques, the present disclosure relies on the concept of WTA (winner-takes-all) contention with minimized current mirroring (minimized mirror load ratio) to achieve input transconductance matching. Furthermore, the present disclosure does not require individually associated compensation networks to match the p- and n-type differential pairs of the error amplifier circuit. Furthermore, the present disclosure does not rely on input device gate-source sensors, but rather uses a simple analog contention concept.

[0056] Fig. Figure 2 shows an example of a DC-DC converter 200 without a divider according to embodiments of the disclosure. The DC-DC converter 200 is an example of a power converter according to embodiments of the disclosure, and the disclosure should not be construed as being limited to DC-DC converters.

[0057] The DC-DC converter 200 differs from the DC-DC converter 100 in Fig. 1 in that the fourth resistor 36 is omitted. Accordingly, the output voltage Vout is not divided before being fed to the error amplifier circuit (i.e., the feedback factor β is equal to one). Thus, the DC-DC converter 200 is a DC-DC converter without a divider. Accordingly, the filtered output voltage received by the error amplifier circuit as one of its input voltages has the same voltage range as the output voltage Vout. This voltage range can be rail-to-rail, e.g., extending from the negative rail to the positive rail.

[0058] Further, DC-DC converter 200 differs from DC-DC converter 100 in that an alternative error amplifier circuit (error amplifier circuit 250) is used instead of error amplifier circuit 50. The internal configuration of error amplifier circuit 250 is described below.

[0059] The error amplifier circuit 250 in the dividerless DC-DC converter 200 can be referred to as a "smart adaptive error amplifier." It can be used in the absence of a feedback divider to achieve a nearly constant rail-to-rail input transconductance for a unity control loop feedback factor without gain programming. It adaptively adjusts the input transconductance to maximize gain and bandwidth stability based on the signal input level sensed to provide stable regulation. Therefore, the DC-DC converter 200, despite being dividerless, can provide stable gain over a wide input range. This is especially beneficial for converters operating at high frequencies.

[0060] An example of the internal configuration of the error amplifier circuit 250 is shown schematically in Fig. 3. The error amplifier circuit 250 receives the reference voltage Vref as a first input voltage Vin1 and receives the filtered output voltage as a second input voltage Vin2. It then compares the first input voltage Vin1 and the second input voltage Vin2 and generates an error voltage V EA_out according to a result of the settlement.

[0061] For this purpose, the error amplifier circuit 250 comprises a differential block 340, a controller circuit 320, and a signal combiner stage (signal combiner and output stage) 360. The controller circuit 320 and the differential block 340 can be said to implement a complementary winner-takes-all (WTA) scheme. The differential block 340 comprises complementary differential pairs (p-type and n-type), each with three inputs. It receives the first and second input signals Vin1, Vin2 as inputs along with the first and second control signals Vctrl_p, Vctrl_n. The controller circuit 320 can also be referred to as a matching circuit. It generates the first and second control signals Vctrl_p, Vctrl_n for the differential block 340. In particular, it generates a first control signal Vctrl_p for the p-type differential pair and a second control signal Vctrl_n for the n-type differential pair of the differential block 340.The control device circuit 320 may be threshold voltage (Vth) dependent. That is, the first and second control voltages Vctrl_p, Vctrl_n may be threshold voltage dependent. The signal combiner stage 360 ​​receives first and second differential outputs from the differential block 340 and generates an output signal (i.e., the error voltage) V. EA_out based on the first and second difference signals.

[0062] Fig. Figure 6 schematically shows an example of the internal configuration of the error amplifier circuit 250. In particular, Fig. 6 can be considered to represent an example of the differential block 340. As can be seen from this figure, the error amplifier circuit 250 comprises a first differential circuit 610 and a second differential circuit 620. The first differential circuit 610 is a p-type differential circuit. The second differential circuit 620 is an n-type differential circuit. As will become apparent from the following description, the first and second differential circuits 610, 620 can be referred to as p-type and n-type analog winner-takes-all (WTA) circuits. The first differential circuit 610 receives the first input voltage Vin1 and the second input voltage Vin2 as inputs. Likewise, the second differential circuit 620 also receives the first input voltage Vin1 and the second input voltage Vin2 as inputs. The error amplifier circuit 250 further comprises a first bias current generation circuit (e.g.Current source) 630 for generating a first bias current for the first differential circuit 610 and a second bias current generation circuit (e.g., current sink) 640 for generating a second bias current for the second differential circuit 620. Here, generating a bias current can refer to supplying or sinking the bias current. The error amplifier circuit 250 further includes a bias current redistribution circuit for redistributing at least a portion of the first bias current to the second differential circuit 620 or redistributing at least a portion of the second bias current to the first differential circuit 610 depending on circumstances (e.g., depending on the input signal level).This bias current redistribution circuit is configured to redistribute at least a portion of the first bias current or at least a portion of the second bias current (depending on the circumstances) such that an input transconductance of the error amplifier circuit 250 is brought closer to a constant input transconductance across an input voltage range of the error amplifier circuit 250. This input voltage range may be the rail-to-rail range.

[0063] For this purpose, the bias current redistribution circuit comprises a first bypass circuit and a second bypass circuit. The first bypass circuit is configured to bypass the first differential circuit 610 and to apply at least a portion of the first bias current to the second differential circuit 620 (e.g., to divert at least a portion of the first bias current from the second differential circuit 620). That is, the first bypass circuit may redirect some or all of the first bypass current to the second differential circuit 620. The second bypass circuit is configured to bypass the second differential circuit 620 and to apply at least a portion of the second bias current to the first differential circuit 610 (e.g., to supply at least a portion of the second bias current to the first differential circuit 610).That is, the second bypass circuit may bypass some or all of the second bypass current to the first differential circuit 610. The first bypass circuit operates under the control of the first control signal Vctrl_p. The second bypass circuit operates under the control of the second control signal Vctrl_n. Accordingly, the first control signal Vctrl_p may be referred to as a control signal for the first bypass circuit, and the second control signal Vctrl_n may be referred to as a control signal for the second bypass circuit. As stated above, the control signals may be threshold-voltage-dependent references. Furthermore, they may depend on the first and / or second input voltages Vin1, Vin2.

[0064] In general, the p-type and n-type analog WTA circuits (i.e., the first and second differential circuits 610, 620) of the SM-EA (i.e., error amplifier circuit 250) each comprise three FETs (input FETs) biased with adjustable tail current sources (i.e., bias current generation circuits 630, 640). Each WTA circuit operates with a common tail current source for all three input transistors, with two of the transistors being directly driven by the first and second input voltages Vin1, Vin2 (i.e., the reference voltage Vref and the undivided (filtered) converter output voltage Vout via the first resistor 34). The third FET is driven by the threshold voltage dependent controller circuit 320, which generates the first and second control voltages (i.e., Vctrl_p for the p-type WTA circuit and Vctrl_n for the n-type WTA circuit) for a local analog contention at the end node of the WTA circuit, which forms the SM-EA input.In this way, the SM-EA adapts to its sensed inputs and makes the adjusted input transconductance and thus the gain nearly constant for the rail-to-rail input range.

[0065] Back to Fig. 6, the first differential circuit 610 includes a first p-type FET 612 and a second p-type FET 614. The first input voltage Vin1 is applied to the gate terminal of the first p-type FET 612. The second input voltage Vin2 is applied to the gate terminal of the second p-type FET 614. The source terminals of the first and second p-type FETs 612, 614 are coupled to the first bias current generation circuit 630. The drain terminals of the first p-type FET 612 and the second p-type FET 614 are coupled to a first low-impedance load 650. In some implementations, the first low-impedance load 650 may form part of the signal combiner stage 360. A first differential output signal (of the first differential circuit 610) can be tapped at respective drain terminals of the first and second p-type FETs 612, 614.

[0066] Analogously, the second differential circuit 620 includes a first n-type FET 622 and a second n-type FET 624. The first input voltage Vin1 is applied to the gate terminal of the first n-type FET 622. The second input voltage Vin2 is applied to the gate terminal of the second n-type FET 624. The source terminals of the first and second n-type FETs 622, 624 are coupled to the second bias current generation circuit 640. The drain terminals of the first n-type FET 622 and the second n-type FET 624 are coupled to a second low-impedance load 660. In some implementations, the second low-impedance load 660 may form part of the signal combiner stage 360. A second differential output signal (of the second differential circuit 620) can be tapped at respective drain terminals of the first and second n-type FETs.

[0067] The outputs derived from the drain terminals of the first and second differential circuits 610, 620 (WTA circuits) are provided to the signal combiner stage 360 ​​to generate a single-ended output (e.g., error voltage). For example, the first stage of the signal combiner stage 360 ​​may have a folded cascode amplifier structure or a folded operational transconductance amplifier (OTA) structure. The output of this first stage may then drive a class AB output stage structure to generate the converter loop control voltage (e.g., the error voltage) for pulse-width modulation (PMW). Example implementations of the signal combiner stage 360 ​​are described below with reference to Fig. 8 and Fig. 9 described.

[0068] As also in Fig. As shown in Figure 6, the first differential circuit 610 includes a third p-type FET 616. The second differential circuit 620 includes a third n-type FET 626. The source terminal of the third p-type FET 616 is coupled to the first bias current generation circuit 630, and the source terminal of the third n-type FET 626 is coupled to the second bias current generation circuit 630. The third p-type FET 616 may also be referred to as part of the first bypass circuit. The third n-type FET 626 may also be referred to as part of the second bypass circuit.

[0069] Accordingly, the first bypass circuit includes the third p-type FET 616. Furthermore, the first bypass circuit includes a first mirror load 635 for mirroring a current flowing through the third p-type FET 616. In this configuration, the first control voltage Vctrl_p is applied to the gate terminal of the third p-type FET 616. The first mirror load 635 is arranged to apply the mirrored current of the current flowing through the third p-type FET 616 to the second differential circuit 620 (e.g., to the source terminals of the first, second, and third n-type FETs 622, 624, 626). The first mirror load 635 may be referred to as being arranged to drain the mirrored current of the current flowing through the third p-type FET 616 from the second differential circuit 620.

[0070] Likewise, the second bypass circuit includes the third n-type FET 626. Furthermore, the second bypass circuit includes a second mirror load 645 for mirroring a current flowing through the third n-type FET 626. In this configuration, the second control voltage Vctrl_n is applied to the gate terminal of the third n-type FET 626. The second mirror load 645 is arranged to apply the mirrored current of the current flowing through the third n-type FET 626 to the first differential circuit 610 (e.g., to the source terminals of the first, second, and third p-type FETs 612, 614, 616). The second mirror load 645 may be referred to as being arranged to supply the mirrored current of the current flowing through the third n-type FET 626 to the first differential circuit 610.

[0071] An example of the first mirror load 635 is shown schematically in Fig. 7A. An example of the second mirror load 645 is shown schematically in Fig. 7B. Therein, the third p-type FET 616 is schematically illustrated as a current source 615 that supplies the tail current (first bias current) Itail_WTA_p of the first differential circuit 610 (i.e., p-type WTA circuit). The third n-type FET 626 is schematically illustrated as a current sink 625 that sinks the tail current (second bias current) Itail_WTA_n of the second differential circuit 620 (i.e., n-type WTA circuit). The first and second bias currents are indicated by Itail_WTA_p and Itail_WTA_n. As can be seen from these figures, the first and second mirror loads 635, 645 may include (or correspond to) first and second current mirrors, respectively. The first current mirror (n-type current mirror) includes two gate-connected n-type FETs 636, 638. The gate terminal of the input-side n-type FET 636 of the first current mirror is coupled to its drain terminal. The second current mirror (p-type current mirror) has two gate-connected p-type FETs 646, 648.The gate terminal of the input-side p-type FET 646 of the second current mirror is coupled to its drain terminal.

[0072] In some embodiments, the first and second p-type FETs 612, 614 and the first and second n-type FETs 622, 624 are operated in their subthreshold region. The third p-type FET 616 and the third n-type FET 626 may also be operated in their subthreshold region. As can be seen, the matching (maximizing the transconductance) works best for subthreshold operation of the adaptive error amplifier input differential pairs. While the matching would also work for operation in the saturation region, the behavior of the resulting circuit would not be nearly as linear as for subthreshold operation.

[0073] In other words, in some embodiments, the WTA FETs are operated in the subthreshold region to maximize the achievable transconductance and also minimize the overall power consumption. For operation in the subthreshold region, the mirror ratios of the current mirror of the first and second mirror loads 635, 645 can be selected as unity (1:1). Operation in the saturation region is possible, but requires a mirror load ratio higher than 1:1 for matching and thus higher power consumption for the achievable bandwidth.

[0074] The first and second control signals Vctrl_p, Vctrl_n generated by the controller circuit (adaptation controller) 320 are dependent on the threshold voltage (Vth) and are used for analog contention at the end node of the differential pairs that form the input of the differential block 340. The Vth-dependent control voltages Vctrl_p and Vctrl_n can be generated by various methods. Fig. 4 schematically shows a first example of an implementation of the controller circuit 320.

[0075] In this first example of an implementation of the controller circuit 320, diode-connected p-type and n-type FETs are biased with a constant bias current (Type 1). Accordingly, the controller circuit 320 includes a current source 410, a current sink 415, a fourth p-type FET 425, and a fourth n-type FET 420.

[0076] As stated above, the fourth p-type FET 425 is diode-connected, meaning its gate terminal is coupled to its drain terminal. Furthermore, the gate terminal of the fourth n-type FET 420 is coupled to its drain terminal. The fourth p-type FET 425 is coupled in series with the current sink 415 between a supply voltage and ground. The drain terminal of the fourth p-type FET 425 is coupled to the current sink 415. Furthermore, the fourth n-type FET 420 is coupled in series with the current source 410 between the supply voltage and ground. The drain terminal of the fourth n-type FET 420 is coupled to the current source 410.

[0077] In this configuration, the first control voltage Vctrl_p is tapped at the gate terminal of the fourth p-type FET 425 and the second control voltage Vctrl_n is tapped at the gate terminal of the fourth n-type FET 420.

[0078] Another scheme is to enable indirect WTA contention by driving the third FET (non-input driven) of the WTA circuit with one of the outputs of the control device (Type 2). An input voltage Vin drives a device stacked on the drain of another FET matched to the tail current source transistor in a flipped-voltage-follower (FVF) structure. This structure then forms a Vth-dependent driver to adaptively drive the 1:1 mirror load for the tail current of the opposite-type WTA bias.

[0079] A second example of an implementation of a controller circuit 320 operating according to the above scheme is shown in Fig. 5. This controller circuit 320 is configured to generate the first and second control voltages Vctrl_p, Vctrl_n based on a (third) input voltage Vin that depends on the first input voltage Vin1 and / or the second input voltage Vin2. For example, the third input voltage Vin can be the reference voltage Vref (i.e., the first input voltage Vin1) or an average of the first and second input voltages Vin1, Vin2.

[0080] The controller circuit 320 includes a current source 510, a current sink 515, a fourth p-type FET 525, a fifth p-type FET 526, a fourth n-type FET 520, and a fifth n-type FET 522. The gate terminal of the fourth p-type FET 525 is coupled to the drain terminal of the fifth p-type FET 526. Similarly, the gate terminal of the fourth n-type FET 520 is coupled to the drain terminal of the fifth n-type FET 522. The fourth p-type FET 525 and the fifth p-type FET 526 are coupled in series with the current sink 515 between the supply voltage and ground. The source terminal of the fifth p-type FET 526 is coupled to the drain terminal of the fourth p-type FET 525. Furthermore, the drain terminal of the fifth p-type FET 526 is coupled to the current sink 515. Similarly, the fourth n-type FET 520 and the fifth n-type FET 522 are coupled in series with the current source 510 between the supply voltage and ground.The source terminal of the fifth n-type FET 522 is coupled to the drain terminal of the fourth n-type FET 520. Furthermore, the drain terminal of the fifth n-type FET 522 is coupled to the current source 510.

[0081] In this configuration, the third input voltage Vin is applied to the gate terminal of the fifth p-type FET 526 and to the gate terminal of the fifth n-type FET 522. Furthermore, the first control voltage Vctrl_p is tapped at the gate terminal of the fourth p-type FET 525, and the second control voltage Vctrl_n is tapped at the gate terminal of the fourth n-type FET 520.

[0082] The error amplifier circuit 250 described above has three different operating modes, depending on the magnitude of the first and second input voltages Vin1, Vin2 with respect to the first and second control voltages Vctrl_p, Vctrl_n (i.e., depending on the input voltage level). For control voltages generated according to embodiments of the disclosure, the first control voltage Vctrl_p is below the positive rail (e.g., power rail, VDD). The second control voltage Vctrl_n is below the first control voltage Vctrl_p and above the negative rail (e.g., ground rail, GND). A first control mode is active when the first and second input voltages Vin1, Vin2 are between the negative rail and the second control voltage Vctrl_n. In the first control mode, which is a control mode via the second control voltage Vctrl_n, only the first differential circuit 610 (p-type differential circuit or p-type differential pair) is active.In this mode, the input transconductance gm of the error amplifier circuit 250 is given by twice the input transconductance gm_p of the first differential circuit 610 (p-type differential pair), i.e., gm = 2 · gm_p. A second control mode is active when the first and second input voltages Vin1, Vin2 are between the first control voltage Vctrl_p and the positive rail. In the second control mode, which is a control mode via the first control voltage Vctrl_p, only the second differential circuit 620 (n-type differential circuit or n-type differential pair) is active. In this mode, the input transconductance gm of the error amplifier circuit 250 is given by twice the input transconductance gm_n of the second differential circuit 620 (n-type differential pair), i.e., gm = 2 · gm_n. Finally, a so-called stealth mode is active when the first and second input voltages Vin1, Vin2 are between the first control voltage Vctrl_p and the second control voltage Vctrl_n.In the stealth mode, the first and second bypass circuits provide complementary control of both the first and second differential circuits 610, 620 under the control of the first and second control voltages Vctrl_p, Vctrl_n, respectively. That is, both the first and second differential circuits 610, 620 are active. In this mode, the input transconductance gm of the error amplifier circuit 250 is given by the sum of the input transconductance gm_p of the first differential circuit 610 (p-type differential pair) and the input transconductance gm_n of the second differential circuit 620 (n-type differential pair), i.e., gm = gm_p + gm_n.

[0083] As mentioned above, the error amplifier circuit 250 further comprises the signal combiner stage 360 ​​for combining the first difference signal generated by the first difference circuit 610 and the second difference circuit generated by the second difference circuit 620. Several implementations of such a signal combiner stage 360 ​​are feasible in the context of the present disclosure. Without intended limitation, two examples of implementations of the signal combiner stage are shown in Fig. 8 or Fig. 9 is shown schematically.

[0084] The signal combiner stage in the example of Fig. 8 is a folded cascode type. It includes p-type FETs 840, 845, 850, and 855, which are gate-connected in pairs to form p-type current mirrors. Furthermore, the signal combiner stage includes n-type FETs 810, 815, 820, and 825, which are gate-connected in pairs to form n-type current mirrors. Specifically, the drain terminal of p-type FET 850 is coupled to the source terminal of p-type FET 840. The drain terminal of p-type FET 855 is coupled to the source terminal of p-type FET 845. The gate terminals of p-type FETs 850 and 855 are coupled together, and the gate terminals of p-type FETs 840 and 845 are coupled together. The voltage at the gate terminals of p-type FETs 840 and 845 is a p-type bias Vbiasp. The gate terminals of p-type FETs 850 and 855 are further coupled to the drain terminal of p-type FET 840.The n-type differential signal (from the second differential circuit 620) is applied to intermediate nodes between p-type FETs 840 and 850 and between p-type FETs 845 and 855, respectively.

[0085] The drain terminal of n-type FET 810 is coupled to the source terminal of n-type FET 820. The drain terminal of n-type FET 815 is coupled to the source terminal of n-type FET 825. The gate terminals of n-type FETs 820 and 825 are coupled together, and the gate terminals of n-type FETs 810 and 815 are coupled together. The voltage at the gate terminals of n-type FETs 810 and 815 is an n-type bias Vbiasn. The gate terminals of n-type FETs 810 and 815 are further coupled to the drain terminal of n-type FET 820. The p-type differential signal (from the first differential circuit 610) is applied to intermediate nodes between n-type FETs 810 and 820 and between n-type FETs 815 and 825, respectively.

[0086] The drain terminal of the p-type FET 840 is coupled to the drain terminal of the n-type FET 820 via a floating current source 830. Furthermore, the drain terminal of the p-type FET 845 is coupled to the drain terminal of the n-type FET 825. Two voltages are tapped at the drain terminal of the p-type FET 845 and the drain terminal of the n-type FET 825, respectively, and fed to the second class AB stage 860. The second class AB stage 860 provides the error amplifier output V EA_out (e.g. the fault voltage).

[0087] The signal combiner stage in the example of Fig. 9 is of the wrap-around OTA type. It has p-type FETs 930, 935, 940, 945, which are gate-connected in pairs to form p-type current mirrors. Furthermore, the signal combiner stage has n-type FETs 910, 915, 920, 925, which are gate-connected in pairs to form n-type current mirrors. Specifically, the gate terminals of p-type FETs 930 and 935 are coupled to each other and to the drain terminal of p-type FET 930. The gate terminals of p-type FETs 940 and 945 are coupled to each other and to the drain terminal of p-type FET 940. These gate terminals are further coupled to the drain terminal of n-type FET 915. The gate terminals of n-type FETs 910 and 915 are coupled to each other and to the drain terminal of n-type FET 910. The gate terminals of n-type FETs 920 and 925 are coupled to each other and to the drain terminal of n-type FET 920. These gate terminals are further coupled to the drain terminal of p-type FET 935.The drain terminal of the p-type FET 945 is coupled to the drain terminal of the n-type FET 925.

[0088] The n-type differential signal (from the second differential circuit 620) is applied to the drain terminals of the p-type FETs 930 and 940, respectively. The p-type differential signal (from the first differential circuit 610) is applied to the drain terminals of the n-type FETs 910 and 920, respectively. A voltage is tapped at an intermediate node between the drain terminal of the p-type FET 945 and the drain terminal of the n-type FET 925 and applied to the second stage 960. The second stage 960 outputs the error amplifier output V EA_out (e.g. the fault voltage).

[0089] Simulation results for the DC-DC converter according to embodiments of the disclosure show a substantially constant rail-to-rail input transconductance. Without adjustment, the input transconductance would drop significantly for input voltages near the positive and negative rails.

[0090] In summary, DC-DC converters according to embodiments of the disclosure enable a wide input range (rail-to-rail) without the need for an input divider resistor. In particular, the present disclosure can achieve a stable wide bandwidth using minimal internal compensation to extend the bandwidth for high-frequency DC-DC converter operation.

[0091] DC-DC converters according to embodiments of the disclosure further enable voltage mode operation with Type III compensation and fast DVS, even when using an older CMOS technology node, such as 0.13 µm CMOS or older.

[0092] The present disclosure further provides DC-DC converters (e.g., buck converters) with inherently good recovery and good loop gain near both power and ground rails. Due to the adaptive nature of the loop compensator, a wide output range capability and lower offset can be achieved, as adaptation ensures stable, higher loop gain over a wide signal range. The present disclosure further simplifies achieving an adaptive active filter for loop compensation by exploiting inherent contention existing at the end node of common differential pairs.

[0093] Passive element values ​​(small values) of the adjustable loop compensator are linearly adjusted using combinations of series and shunt trimmed resistor and capacitor blocks.

[0094] Additional advantages of the present disclosure include a rail-to-rail input voltage capability for the converter without the need for a divider or divider programming to avoid stability problems, stable adaptation of gain over a wide input voltage range, maximized input transconductance (gm) with almost complete (e.g.90%) Improvement in rail-to-rail peak-to-peak flatness compared to conventional techniques with conventional inputs, an inherently good gain near both power and ground rails compared to conventional techniques with conventional inputs, higher converter loop gain with lower offset independent of input signal levels, extended "closed loop" converter bandwidth suitable for high frequency operation, and fast dynamic voltage scaling response coupled with the ability to use smaller loop compensator component values ​​without the limitations of a feedback loop divider.

[0095] Fig. 10 is a flow diagram schematically showing a method 1000 for performing a DC-DC conversion and generating an output voltage in accordance with a reference voltage, e.g., using the DC-DC converter of Fig. 3.

[0096] In step S1010, the output voltage is filtered. This step can be performed, for example, using the filter circuit described above. In step S1020, the reference voltage as the first input voltage and the filtered output voltage as the second input voltage are compared with each other, and an error voltage is generated according to a result of the comparison. This step can be performed, for example, using the error amplifier circuit described above. In step S1030, one or more switching devices are driven (controlled) depending on the error voltage generated in step S1020.

[0097] Fig. 11 is a flowchart schematically illustrating a method 1100 for performing step S1020 in the method 1000 of Fig. 10. Accordingly, the flowchart shows substeps of the above step of comparing the first input voltage and the second input voltage and generating the error voltage according to the result of the comparison.

[0098] In step S1110, the first input voltage and the second input voltage are input to a first differential circuit, and a first bias current is generated for the first differential circuit. In step S1120, the first input voltage and the second input voltage are input to a second differential circuit, and a second bias current is generated for the second differential circuit. In step S1130, at least a portion of the first bias current is redistributed to the second differential circuit, or at least a portion of the second bias current is redistributed to the first differential circuit.

Claims

[1] Power converter for performing power conversion and generating an output voltage (Vout) according to a reference voltage (Vref) for the output voltage (Vout), the power converter comprising: a filter circuit for filtering (S1010) the output voltage (Vout) of the power converter; an error amplifier circuit (50, 250) receiving the reference voltage (Vref) as a first input voltage (Vin1) and receiving the filtered output voltage (Vout) as a second input voltage (Vin2), for comparing (S1020) the first input voltage (Vin1) and the second input voltage (Vin2) and for generating (S1020) an error voltage according to a result of the comparison; and a control circuit for controlling (S1030) one or more switching devices in dependence on the error voltage; wherein the error amplifier circuit (50, 250) comprises: a first differential circuit (610) receiving the first input voltage (Vin1) and the second input voltage (Vin2) as inputs, and a first bias current generating circuit (630) for generating a first bias current for the first differential circuit (610); a second differential circuit (620) receiving the first input voltage (Vin1) and the second input voltage (Vin2) as inputs, and a second bias current generating circuit (640) for generating a second bias current for the second differential circuit (620); and a bias current redistribution circuit for redistributing (S1130) at least a portion of the first bias current to the second differential circuit (620) or for redistributing (S1130) at least a portion of the second bias current to the first differential circuit (610). [2] The power converter of claim 1, wherein the bias current redistribution circuit is configured to redistribute at least a portion of the first bias current or at least a portion of the second bias current such that an input transconductance of the error amplifier circuit (50, 250) is brought closer to a constant input transconductance over an input voltage range of the error amplifier circuit (50, 250). [3] The power converter according to claim 1 or 2, wherein the filtered output voltage (Vout) received from the error amplifier circuit (50, 250) as the second input voltage (Vin2) has the same voltage range as the output voltage (Vout). [4] The power converter according to any one of claims 1 to 3, wherein the output voltage (Vout) is not divided by a voltage divider before being supplied to the error amplifier circuit (50, 250). [5] The power converter according to any one of claims 1 to 4, wherein the bias current redistribution circuit comprises: a first bypass circuit configured to provide a bypass for the first differential circuit (610) and to apply at least a portion of the first bias current to the second differential circuit (620); and a second bypass circuit configured to provide a bypass for the second differential circuit (620) and to apply at least a portion of the second bias current to the first differential circuit (610). [6] The power converter according to claim 5, wherein the first bypass circuit operates under the control of a first control signal; wherein the second bypass circuit operates under the control of a second control signal; and wherein the error amplifier circuit (50, 250) further comprises a controller circuit (320) for generating the first control signal for the first bypass circuit and the second control signal for the second bypass circuit. [7] The power converter according to any one of claims 1 to 6, wherein the first differential circuit (610) comprises: a first p-type field effect transistor (FET) (612); and a second p-type FET (614); wherein the first input voltage (Vin1) is applied to a gate terminal of the first p-type FET (612); wherein the second input voltage (Vin2) is applied to a gate terminal of the second p-type FET (614); and wherein source terminals of the first (612) and second (614) p-type FETs are coupled to the first bias current generation circuit (630). [8] The power converter of claim 7, wherein the first (612) and second (614) p-type FETs are operated in their subthreshold region. [9] The power converter according to claim 6, wherein the first bypass circuit comprises: a third p-type field-effect transistor (FET) (616); and a first current mirror for mirroring a current flowing through the third p-type FET; wherein the first control voltage (Vctrl_p) is applied to a gate terminal of the third p-type FET (616); wherein a source terminal of the third p-type FET (616) is coupled to the first bias current generation circuit (630); and wherein the first current mirror is arranged to apply the mirrored current of the current flowing through the third p-type FET (616) to the second differential circuit (620). [10] The power converter according to any one of claims 1 to 9, wherein the second differential circuit (620) comprises: a first n-type field-effect transistor (FET) (622); and a second n-type FET (624); wherein the first input voltage (Vin1) is applied to a gate terminal of the first n-type FET (622); wherein the second input voltage (Vin2) is applied to a gate terminal of the second n-type FET (624); and wherein source terminals of the first (622) and second (624) n-type FETs are coupled to the second bias current generating circuit (640). [11] The power converter of claim 10, wherein the first (622) and second (624) n-type FETs are operated in their subthreshold region. [12] The power converter according to claim 6 or 9, wherein the second bypass circuit comprises: a third n-type field-effect transistor (FET) (626); and a second current mirror for mirroring a current flowing through the third n-type FET (626); wherein the second control voltage (Vctrl_n) is applied to a gate terminal of the third n-type FET (626); wherein a source terminal of the third n-type FET (626) is coupled to the second bias current generation circuit (640); and wherein the second current mirror is arranged to apply the mirrored current of the current flowing through the third n-type FET (626) to the first differential circuit (610). [13] The power converter according to any one of claims 6, 9 or 12, wherein the control device circuit (320) comprises: a power source; a current sink; a fourth p-type field-effect transistor (FET) coupled in series with the current sink between a supply voltage and ground, wherein a gate terminal of the fourth p-type FET is coupled to a drain terminal of the fourth p-type FET; and a fourth n-type FET coupled in series with the current source between the supply voltage and ground, wherein a gate terminal of the fourth n-type FET is coupled to a drain terminal of the fourth n-type FET; and wherein the first control voltage (Vctrl_p) is tapped at the gate terminal of the fourth p-type FET and the second control voltage (Vctrl_n) is tapped at the gate terminal of the fourth n-type FET. [14] The power converter according to any one of claims 6, 9, 12 or 13, wherein the controller circuit (320) is configured to generate the first (Vctrl_p) and the second (Vctrl_n) control voltages based on a third input voltage that depends on the first input voltage (Vin1) and / or the second input voltage (Vin2). [15] The power converter according to claim 14, wherein the control device circuit (320) comprises: a power source; a current sink; a fourth p-type field-effect transistor (FET) and a fifth p-type field-effect transistor coupled in series with the current sink between a supply voltage and ground, wherein a gate terminal of the fourth p-type FET is coupled to a drain terminal of the fifth p-type FET; and a fourth n-type FET and a fifth n-type FET coupled in series with the current source between the supply voltage and ground, wherein a gate terminal of the fourth n-type FET is coupled to a drain terminal of the fifth n-type FET; wherein the third input voltage is applied to a gate terminal of the fifth p-type FET and to a gate terminal of the fifth n-type FET; and wherein the first control voltage (Vctrl_p) is tapped at the gate terminal of the fourth p-type FET and the second control voltage (Vctrl_n) is tapped at the gate terminal of the fourth n-type FET. [16] The power converter according to any one of claims 1 to 15, wherein the error amplifier circuit (50, 250) further comprises a signal combiner stage for combining a first difference signal generated by the first difference circuit (610) and a second difference signal generated by the second difference circuit (620). [17] The power converter according to any one of claims 1 to 16, wherein the filter circuit comprises: a first parallel circuit comprising two parallel branches with a first resistance in one of the parallel branches and a series connection of a second resistance and a first capacitance in the other of the parallel branches, the first parallel circuit being coupled to an input terminal of the error amplifier circuit (50, 250); and a second parallel circuit comprising two parallel branches with a second capacitance in one of the parallel branches and a series connection of a third resistor and a third capacitance in the other of the parallel branches, the second parallel circuit being coupled between the input terminal of the error amplifier circuit (50, 250) and an output terminal of the error amplifier circuit (50, 250). [18] A method for performing power conversion and generating an output voltage (Vout) according to a reference voltage (Vref) for the output voltage (Vout) using a power converter, the method comprising: Filtering (S1010) the output voltage (Vout) using a filter circuit; Comparing (S1020) the reference voltage (Vref) as the first input voltage (Vin1) and the filtered output voltage (Vout) as the second input voltage (Vin2) and generating (S1020) an error voltage according to a result of the comparison using an error amplifier circuit (50, 250); and Controlling (S1030) one or more switching devices depending on the fault voltage; wherein comparing (S1020) the first input voltage (Vin1) and the second input voltage (Vin2) and generating (S1020) the error voltage according to the result of the comparison comprises: Inputting (S1110) the first input voltage (Vin1) and the second input voltage (Vin2) into a first differential circuit (610) and generating (S1110) a first bias current for the first differential circuit (610); Inputting (S1120) the first input voltage (Vin1) and the second input voltage (Vin2) into a second differential circuit (620) and generating (S1120) a second bias current for the second differential circuit (620); and Redistributing (S1130) at least a portion of the first bias current to the second differential circuit (620) or redistributing (S1130) at least a portion of the second bias current to the first differential circuit (610). [19] The method of claim 18, wherein redistributing (S1130) at least a portion of the first bias current to the second differential circuit (620) or redistributing (S1130) at least a portion of the second bias current to the first differential circuit (610) comprises redistributing at least a portion of the first bias current or at least a portion of the second bias current such that an input transconductance of the error amplifier circuit (50, 250) is brought closer to a constant input transconductance over an input voltage range of the error amplifier circuit (50, 250). [20] The method according to claim 18 or 19, wherein the filtered output voltage (Vout) input to the error amplifier circuit (50, 250) as the second input voltage (Vin2) has the same voltage range as the output voltage (Vout). [21] The method according to any one of claims 18 to 20, wherein the output voltage (Vout) is not divided by a voltage divider before being supplied to the error amplifier circuit (50, 250). [22] The method according to any one of claims 18 to 21, wherein redistributing (S1130) at least a portion of the first bias current to the second differential circuit (620) or redistributing (S1130) at least a portion of the second bias current to the first differential circuit (610) comprises: Providing a bypass for the first differential circuit (610) and applying at least a portion of the first bias current to the second differential circuit (620) using a first bypass circuit; or Providing a bypass for the second differential circuit (620) and applying at least a portion of the second bias current to the first differential circuit (610) using a second bypass circuit. [23] The method according to claim 22, wherein providing the bypass for the first differential circuit (610) operates under the control of a first control signal; wherein providing the bypass for the second differential circuit (620) operates under the control of a second control signal; and wherein the method further comprises generating the first control signal and the second control signal using a controller circuit (320). [24] The method according to any one of claims 18 to 23, wherein the first differential circuit (610) comprises: a first p-type field-effect transistor (FET) (612); and a second p-type FET (614); and the method further comprising: Applying the first bias current to source terminals of the first and second p-type FETs; Applying the first input voltage (Vin1) to a gate terminal of the first p-type FET (612); and Applying the second input voltage (Vin2) to a gate terminal of the second p-type FET (614). [25] The method of claim 24, further comprising operating the first (612) and second (614) p-type FETs in their subthreshold region. [26] The method according to claim 23, wherein the first bypass circuit comprises a third p-type field effect transistor (FET); and the method further comprising: Applying the first bias current to a source terminal of the third p-type FET (616); Applying the first control voltage (Vctrl_p) to a gate terminal of the third p-type FET (616); Mirroring a current flowing through the third p-type FET (616) using a first current mirror; and Applying the mirrored current of the current flowing through the third p-type FET to the second differential circuit (620). [27] The method according to any one of claims 18 to 26, wherein the second differential circuit (620) comprises: a first n-type field-effect transistor (FET) (622); and a second n-type FET (624); and the method further comprising: Applying the second bias current to source terminals of the first (622) and second (624) n-type FETs; Applying the first input voltage (Vin1) to a gate terminal of the first n-type FET (622); and Applying the second input voltage (Vin2) to a gate terminal of the second n-type FET (624). [28] The method of claim 27, further comprising operating the first (622) and second (624) n-type FETs in their subthreshold region. [29] The method according to claim 23 or 26, wherein the second bypass circuit comprises a third n-type field effect transistor (FET) (626); and the method further comprising: Applying the second bias current to a source terminal of the third n-type FET (626); Applying the second control voltage (Vctrl_n) to a gate terminal of the third n-type FET (626); Mirroring a current flowing through the third n-type FET (626) using a second current mirror; and Applying the mirrored current of the current flowing through the third n-type FET (626) to the first differential circuit (610). [30] The method according to any one of claims 23, 26 or 29. wherein the control device circuit (320) comprises: a power source; a current sink; a fourth p-type field-effect transistor (FET) coupled in series with the current sink between a supply voltage and ground, wherein a gate terminal of the fourth p-type FET is coupled to a drain terminal of the fourth p-type FET; and a fourth n-type FET coupled in series with the current source between the supply voltage and ground, wherein a gate terminal of the fourth n-type FET is coupled to a drain terminal of the fourth n-type FET; and wherein the method further comprises tapping the first control voltage (Vctrl_p) at the gate terminal of the fourth p-type FET and tapping the second control voltage (Vctrl_n) at the gate terminal of the fourth n-type FET. [31] The method according to any one of claims 23, 26, 29 or 30, wherein the controller circuit (320) is configured to generate the first (Vctrl_p) and the second (Vctrl_n) control voltages based on a third input voltage that depends on the first input voltage (Vin1) and / or the second input voltage (Vin2). [32] The method according to claim 31, wherein the control device circuit (320) comprises: a power source; a current sink; a fourth p-type field-effect transistor (FET) and a fifth p-type FET coupled in series with the current sink between a supply voltage and ground, wherein a gate terminal of the fourth p-type FET is coupled to a drain terminal of the fifth p-type FET; and a fourth n-type FET and a fifth n-type FET coupled in series with the current source between the supply voltage and ground, wherein a gate terminal of the fourth n-type FET is coupled to a drain terminal of the fifth n-type FET; and the method further comprising: Applying the third input voltage to a gate terminal of the fifth p-type FET and to a gate terminal of the fifth n-type FET; Tapping the first control voltage at the gate terminal of the fourth p-type FET and tapping the second control voltage at the gate terminal of the fourth n-type FET. [33] The method of any one of claims 18 to 32, further comprising combining a first difference signal generated by the first difference circuit (610) and a second difference signal generated by the second difference circuit (620). [34] The method according to any one of claims 18 to 33, wherein the filter circuit comprises: a first parallel circuit comprising two parallel branches with a first resistance in one of the parallel branches and a series connection of a second resistance and a first capacitance in the other of the parallel branches, the first parallel circuit being coupled to an input terminal of the error amplifier circuit (50, 250); and a second parallel circuit comprising two parallel branches with a second capacitance in one of the parallel branches and a series connection of a third resistor and a third capacitance in the other of the parallel branches, the second parallel circuit being coupled between the input terminal of the error amplifier circuit (50, 250) and an output terminal of the error amplifier circuit (50, 250).

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