Bonding passive devices to active device dies to form 3D packages

Abstract

Package including: a package substrate; an interposer over the package substrate and bonded to the package substrate; a first wafer over the interposer and bonded to the interposer, the first wafer including independent passive device dies therein; and a second wafer over the first wafer and bonded to the wafer, the second wafer having active device dies therein.

Description

BACKGROUND

[0001] Integrated circuit packages are becoming increasingly complex as more device dies are packaged into the same package to create a system with more features. Independent Passive Devices (IPDs), which are discrete components, are often used in these packages.

[0002] In conventional package formation processes, IPDs were bonded to a package substrate. However, this resulted in long paths between the IPDs and the respective computing chips that accessed the IPDs. Furthermore, memory dies were bonded to the package substrate. This also resulted in long paths between the memory dies and the computing chips, thus degrading computing performance.

[0003] US 2018 / 0 138 101 A1 discloses a method comprising applying a first stamp to a first side of a first component using first electrical connectors, applying a first side of a second chip of the first component using second electrical connectors, and applying a dummy chip to the first side of the first component in a scribe line region of the first component. The method further comprises bonding a cover structure to a second side of the second stamp, and separating the first component and the dummy stamp to form a packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of the present disclosure can best be understood from the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of various features may be exaggerated or reduced as desired for clarity. Fig. 1-3, 4A, 4B, 5-10, 11A and 11B illustrate cross-sectional views, top views and perspective views of intermediate stages in the formation of a package according to some embodiments. Fig. 12A and Fig. 12B illustrate a perspective view and a top view of a package, respectively, according to some embodiments. Fig. 13A, 13B, 14A, 14B, 15-19, 20A and 20B illustrate cross-sectional views, top views and perspective views of intermediate stages in the formation of a package according to some embodiments. Fig. 21A, Fig. 21B, Fig. 21C, Fig. 21D, Fig. 21E and Fig. 21F illustrate interposers according to some embodiments. Fig. 22-24 illustrate cross-sectional views of the intermediate stages when using an anisotropic conductive film as an interposer according to some embodiments. Fig. 25 illustrates a process flow for forming a package according to some embodiments. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments or examples of implementing different features of the invention. Specific examples of the components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. The formation of a first feature over or on top of a second feature in the description that follows may, for example, include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, spatially relative terms such as "underlying," "beneath," "deeper," "overlying," "upper," and the like may be used herein for convenience of description to describe the relationship of one element or feature to one or more other elements or features, as illustrated in the FIGS. It is intended that the spatially relative terms include different orientations of the devices in use or operation in addition to the orientation shown in the FIGS. The device may also be oriented differently (rotated 90 degrees or other orientations), and the spatially relative descriptors used herein may also be interpreted accordingly.

[0007] A package containing independent passive devices (IPDs) and the method of forming the same are provided according to some embodiments. The intermediate steps in forming the package are illustrated according to some embodiments. Some variations of some embodiments are discussed. Embodiments discussed herein are intended to provide examples for enabling the subject matter of this disclosure to be made or used, and one of ordinary skill in the art will readily understand modifications that may be made while remaining within the contemplated scope of the various embodiments. Throughout the various views and illustrative embodiments, like reference numerals are used to refer to like elements.Although method embodiments are discussed as being performed in a particular order, other method embodiments may be performed in any logical order. According to some embodiments of the present disclosure, IPD chips are bonded to a device wafer to form a reconstructed package. The bonding may be performed by chip-on-wafer bonding or wafer-on-wafer bonding. Accordingly, a three-dimensional (3D) structure is formed, and the electrical paths between the IPD chips and the corresponding device dies in the device wafer are short. The resulting reconstructed package is then further bonded and / or additional package components are attached, such as an interposer, a package substrate, power modules, a cold plate, etc., to form a system package.

[0008] With reference to Fig. 1, a device wafer 20 is provided. Device wafer 20 may have a round shape, as shown in Fig. 2, which shows a perspective view of device wafer 20. Device wafer 20 includes a plurality of device dies 22 (including 22A and 22B). Device wafer 20 further includes semiconductor substrate 23 that extends continuously into all of the device dies 22. Although Fig. 1 illustrates two device dies 22, there may be several device dies 22, as in Fig. 2. Device dies 22 may include integrated circuit devices (such as active devices including, for example, transistors) on the front surface (the upward-facing surface) of the respective device die. According to some embodiments of the present disclosure, device dies 22 may include logic chips, including central processing unit (CPU) chips, graphics processing unit (GPU) chips, mobile application chips, micro control unit (MCU) chips, BaseBand (BB) chips, application processor (AP) chips, field-programmable gate array (FPGA) chips, application-specific integrated circuit (ASIC) chips, or the like. Device dies 22 may also include memory dies, input-output (IO) chips, or the like. Device dies 22A and 22B may be identical, or they may have different structures and / or different functions.

[0009] Device dies 22 include interconnect structure 24 formed over semiconductor substrate 23. Interconnect structure 24 includes dielectric layers 25 and metal lines and vias 26 formed in dielectric layers 25. Dielectric layers 25 may include an interlayer dielectric layer having contact plugs (not shown) formed therein and inter-metal dielectric (IMD) layers over the interlayer dielectric. According to some embodiments of the present disclosure, some of dielectric layers 25 are formed from low-k dielectric materials with dielectric constants (k values) of less than about 3.0.Dielectric layers 25 may be formed from Black Diamond (a registered trademark of Applied Materials), a carbonaceous low-k dielectric material, Hydrogen SilsesQuioxane (HSQ), MethylSilsesQuioxane (MSQ), or the like. According to alternative embodiments of the present disclosure, some or all of the dielectric layers 25 may be formed from non-low-k dielectric materials, such as silicon oxide, silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), or the like.

[0010] Metal lines and vias 26 are formed in dielectric layers 25. The metal lines on the same level are collectively referred to below as a metal layer. According to some embodiments of the present disclosure, interconnect structure 24 includes multiple metal layers connected via vias. The metal lines and vias 26 may be formed from copper or copper alloys or other metals. The formation process may include single damascene and dual damascene processes. The metal lines and vias 26 may include diffusion barrier layers and copper regions.

[0011] According to some embodiments of the present disclosure, metal pads 28 are formed on the surface of device wafer 20. Metal pads 28 may be formed from a metal, such as copper, or a metal alloy.

[0012] Further with reference to Fig. 1, a plurality of device dies 30 (including 30A and 30B) are brought into contact with device dies 22 and then bonded together. The respective process is described as process 202 in the Fig. 25 illustrates the process flow 200 shown. Fig. 3 illustrates the perspective view of device dies 30 according to some embodiments. Device dies 30 may include semiconductor substrates 31, vias 32 extending into semiconductor substrates 31, and interconnect structures 33. For example, the conductive lines in interconnect structures 33 and the devices (including active devices such as transistors and diodes, and / or passive devices such as resistors, capacitors, inductors, or the like) are not shown. Furthermore, vias 32 have at least some portions in semiconductor substrates 31 and may or may not extend into interconnect structures 33.

[0013] Device dies 30 include device dies 30A and device dies 30B, and may each be selected from an IPD chip, a memory die, a logic chip, or the like in any combination. Device dies 30A and 30B may be identical to or different from each other. For example, device dies 30A may be IPD chips, and device dies 30B may be memory dies. According to some other exemplary embodiments, device dies 30A and 30B are both IPD chips. Fig. 3 illustrates a perspective view of the device die 30.

[0014] According to some embodiments, an IPD chip 30 (such as 30A) includes a passive component (not shown). The passive component may be a capacitor (such as a multilayer ceramic capacitor (MLCC)), a resistor, an inductor, or the like. The passive component may be formed on the substrate of the corresponding IPD chip 30, which, according to some embodiments, may be a semiconductor substrate, such as a silicon substrate. An IPD chip 30A may include a single type (such as a capacitor, resistor, inductor, or the like) of passive device therein and be free of active devices therein. An IPD chip 30A may also include a single passive component. The passive component may be formed in the substrate and / or in the interconnect structure of the IPD chip 30A, wherein the interconnect structure includes multiple dielectric layers.The passive component is connected to terminals 34, which may be metal pillars, metal pads, or the like. According to some embodiments, an IPD chip 30A includes two terminals 34, each connected to one end of the passive component. According to some embodiments, an IPD chip 30A has more than two terminals.

[0015] According to some embodiments, memory dies 30 (such as 30B) include memories such as static random access memories (SRAMs), dynamic random access memories (DRAMs), resistive random access memories (RRAMs), or the like.

[0016] According to some embodiments of the present disclosure, device dies 30 are bonded to device dies 22 via hybrid bonding, wherein the surface dielectric layers of device dies 30 are fusion bonded to the surface layers of device dies 22. During bonding, for example, Si-O-Si bonds may be formed, wherein Si atoms in a first die and Si-O groups in a second die bond to the first die. The bond pads 34 in device die 30 are bonded to the bond pads 28 by direct metal-to-metal bonding. Fig. Figure 4A shows a cross-sectional view of the resulting bonded structure. In Fig. 4B shows a perspective view of the resulting bonded structure. According to alternative embodiments, bonding device dies 30 to the underlying device dies 22 may involve solder bonding, with solder regions (not shown) connecting device dies 30 to device dies 22.

[0017] Next, if there are gaps between fixture die 30 and fixture die 22, the gaps are filled with an underfill. Now referring to Fig. 5, encapsulation material 36 is encapsulated on device die 30. The encapsulation process includes dispensing encapsulation material 36, followed by a curing process. The respective process is designated as process 204 in the Fig. 25. According to some embodiments of the present disclosure, encapsulation material 36 includes a molding compound containing a base material and fillers mixed into the base material. The base material may comprise a polymer, a resin, an epoxy, and / or the like. The fillers may be formed from spherical particles of silica, alumina, silicon oxide, or the like. The curing process is performed to cure and solidify encapsulation material 36. According to some embodiments, device dies 30 are buried in encapsulation material 36. Following the curing process, a planarization process, such as a chemical mechanical polishing (CMP) process or a mechanical grinding process, is performed to remove excess portions of encapsulation material 36, with excess portions overlying device dies 30.The resulting structure is also stored in . Fig. 5. According to some embodiments of the present disclosure, the substrates 31 (such as silicon substrates) of the device dies 30 are exposed as a result of the planarization process. The planarization process also results in a portion of the substrate covering vias 32 being removed, and vias 32 being exposed. The respective process is described as process 206 in the Fig. 25 illustrates the process flow 200 shown.

[0018] Fig. Figure 6 illustrates the formation of dielectric layers 40 and redistribution lines (RDLs) 42, collectively referred to as an interconnect structure 38. The respective process is designated as process 208 in the Fig. 25. According to some embodiments, dielectric layers 40 are formed from or comprise a photosensitive polymer, which may include polybenzoxazole (PBO), polyimide, or the like. The photosensitive polymer may be patterned by exposure and development. According to alternative embodiments, dielectric layers 40 are formed from an inorganic material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like. RDLs 42 may be formed from a metal or metal alloy, such as copper, aluminum, or alloys thereof.According to some embodiments, the formation of the interconnect structure 38 may include depositing a first dielectric layer, patterning the first dielectric layer to form openings for exposing the underlying conductive features, forming a metal growth layer, forming a patterned plating mask, such as a patterned photoresist, performing a plating process, removing the patterned plating mask, and then etching the portions of the growth layer previously covered by the etch mask.

[0019] With reference to Fig. 7, bond pads 44 are formed over the interconnect structure and electrically connected to vias 32 and device dies 22 by RDLs 42. The respective process is described as process 210 in the Fig. 25. Bond pads 44 may also include under-bump metallurgy (UBM) pads, which may be formed, for example, using a plating process. Bond pads 44 are electrically connected to the devices in device dies 30, such as the passive devices in IPD chips 30A and the memory circuits in memory dies 30B. Throughout the description, the structure in Fig. 7 as reconstructed wafer 46.

[0020] According to some embodiments of the present disclosure, vias 32 are used to connect bond pads 44 to device dies 22. Accordingly, vias 32 may replace the vias that may otherwise be formed to penetrate encapsulation material 36. Because vias 32 are formed in IPD chips 30A and memory dies 30B using the processes for forming semiconductor wafers, vias 32 may be made small, and more vias 32 may be provided for electrical connection. Some or all of vias 32 are used exclusively for interconnection and are not electrically connected to components in IPD chips 30A and / or memory dies 30B.Some (or none) of the vias 32, when used for interconnection purposes, may also be electrically connected to the devices in IPD chips 30A and memory dies 30B through the metal lines and vias in IPD chips 30A and memory chips 30B. Since no vias need to be formed, the cost of forming the vias is saved.

[0021] According to some embodiments of the present disclosure, reconstructed wafer 46 may be used in the subsequent assembly process without being sawed. Fig. Figure 9 illustrates an exemplary perspective view of the reconstructed wafer 46, shown using dashed lines. According to alternative embodiments, the reconstructed wafer 46 is sawn into smaller pieces, for example, the packages 46' in Fig. 8. Each reconstructed wafer 46 may be sawn into multiple packages 46'. A package 46' may include multiple device dies 30, according to some embodiments of the present disclosure, and may include multiple IPD chips 30A and multiple memory dies 30B. According to alternative embodiments of the present disclosure, the edge portions of the reconstructed wafer 46, wherein the edge portions do not include functional components, are cut off. Fig. 11B illustrates an example in which sawing is carried out along lines 47. Accordingly, a single package 46' containing all of the device dies 22 and device dies 30 in the reconstructed wafer 46 is obtained from a reconstructed wafer 46. The resulting package 46' is Fig. 9. The package 46', as shown in Fig. 9, may be due to sawing (see lines 47 in Fig. 11B) have straight edges and can, depending on the positions of the saw lines 47 ( Fig. 11B), may or may not have curved edges.

[0022] Fig. 10 illustrates an assembly process in which reconstructed wafer 46 or package 46' is assembled into a system package. The respective process is designated as process 212 in the Fig. 25. Reconstructed wafer 46 or package 46' is hereinafter referred to as package component 46 / 46'. According to some embodiments, the assembled components include package substrate 48, power modules 52, interposer 56, package component 46 / 46', connectors 50, and cold plate (heat sink) 60. The assembly process is briefly discussed in the following paragraphs.

[0023] According to some embodiments of the present disclosure, package substrate 48 is provided. Package substrate 48 may be a substrate with a core. RDLs (not shown) are formed within package substrate 48 and on opposite sides of the core to connect the conductive features on opposite surfaces of package substrate 48. Package substrate 48 may also be a coreless substrate, with multiple dielectric layers and RDLs in the dielectric layers. Package substrate 48 and the subsequently bonded interposer 56 both perform the functions of electrically connecting conductive features on opposite sides of the respective package substrate 48 and interposer 56.

[0024] Interposer 56 is bonded to the package substrate 48. Interposer 56 may have a structure selected from several candidate structures. Fig. 21A, Fig. 21B, Fig. 21C, Fig. 21D, Fig. 21E and Fig. 21F illustrate, for example, exemplary structures of the interposer 56 according to some embodiments. In each of the Fig. 21A, Fig. 21B, Fig. 21C, Fig. 21D, Fig. 21E and Fig. 21F, the conductive features on the illustrated top surface are electrically connected to the conductive features on the illustrated bottom surface through the internal connections (not shown). Fig. 21A illustrates interposer 56 according to some embodiments, and socket pin contacts 58A are formed on both sides of interposer 56. The socket pin contacts 58A on the illustrated top side are electrically connected to the socket pin contacts 58A on the bottom side. Fig. 21B illustrates interposer 56 according to some embodiments, and socket pin contacts 58A are located on one side of the interposer 56. On the other side, metal pads 58B are formed on the surface of the interposer 56. Fig. 21C illustrates interposer 56 according to some embodiments, and socket pin contacts 58A are formed on one side of interposer 56. On the other side, solder regions 58C are formed on the surface of interposer 56. Fig. Figure 21D illustrates a perspective view wherein socket pin contacts 58A (shown in Fig. 21A, Fig. 21B and Fig. 21C) are shown as inserted into the sockets of the interposer 56.

[0025] Fig. 21E illustrates interposer 56 according to some embodiments, and contact pads 58D are exposed on one side of interposer 56. Solder regions 58C are formed on the other side. Fig. 21E illustrates interposer 56, including semiconductor substrate 160, and substrate vias 162 penetrating semiconductor substrate 160, with substrate vias 162 electrically connecting metal pads 58E on opposite sides of interposer 56.

[0026] Again with reference to Fig. 10, according to some embodiments of the present disclosure, interposer 56 is placed over package substrate 48 and bonded thereto. Bonding may be performed by solder bonding, direct metal-to-metal bonding, pin insertion, or the like. Package component 46 / 46' is to be bonded to interposer 56, for example, by solder bonding, direct metal-to-metal bonding, pin insertion, or the like.

[0027] According to alternative embodiments of the present disclosure, instead of using the interposer 56 as in Fig. 21A to 21F, an anisotropic conductive film 164 may be used as an interposer. Fig. For example, Figure 22 illustrates anisotropic conductive film 164 containing dielectric material 166 and electrically conductive particles 168 therein. Electrically conductive particles 168 are distributed throughout the dielectric material 166 and spaced apart from each other without forming electrical paths. Dielectric material 166 may be formed from a polymer, an epoxy, an acrylic, or the like. Electrically conductive particles 168 may be copper spheres, aluminum spheres, nickel spheres, or the like, or they may be metal-coated polymer spheres.

[0028] With reference to Fig. 23, package component 46 / 46' and package substrate 48 are pressed from opposite sides of the anisotropic conductive film 164. During pressing, package component 46 / 46' and package substrate 48 may or may not be heated. The protruding conductive pads 44 of package component 46 / 46' and the protruding conductive pads 49 of package substrate 48 are vertically aligned with a one-to-one correspondence. As a result of the pressing, the electrically conductive particles 168 are compressed between opposing conductive pads 44 and 49 and form conductive paths that electrically connect conductive pads 44 to the corresponding conductive pads 49. The resulting structure is shown in Fig. 24. The pressed anisotropic conductive film 164 acts as the interposer 56, as shown in Fig. 10 shown.

[0029] Now again with reference to Fig. 10, cooling plate 60 is to be attached to package component 46 / 46' by thermal interface material (TIM) 58, which is an adhesive film with good thermal conductivity. Cooling plate 60 may be formed from or comprise a metallic material, such as copper, aluminum, stainless steel, nickel, or the like.

[0030] Connectors 50, which are responsible for the signal connection between the resulting system package 66 ( Fig. 11A and Fig. 11B) and other systems are also attached to package substrate 48. Connectors 50 may include adapters, sockets, or the like. Connectors 50 may include multiple signal paths, such as multiple pins, pinholes, or the like, and may be used as one or more bus ports for parallel or serial signal transmission between system package 66 and other systems. Wires (not shown), for example, may be connected to connectors 50 and are used to connect system package 66 to other systems. Connectors 50 are electrically connected to active device die 22 and possibly IPD chips 30A and / or memory die 30B through package substrate 48.

[0031] As also in Fig. 10, power modules 52 may be bonded to package substrate 48 according to some embodiments. Power modules 52 may include pulse width modulation (PWM) circuitry for regulating power and / or other types of power management circuitry. Power modules 52 provide the regulated power to the respective overlying device dies 22 and memory dies 30B. Power modules 52 are also connected to the IPD chips 30A for power management and power storage. Power modules 52 receive power sources (such as an AC power source), for example, through interconnect lines (these interconnect lines may underlie and be connected to the power modules 52). These power sources and the interconnect lines are not illustrated.

[0032] According to some embodiments of the present disclosure, power modules 52 and device dies 22 may have a one-to-one correspondence, where each of the power modules 52 corresponds to (and may be overlapped by) one (and only one) device die 22, and each device die 22 corresponds to one of the power modules 52 (and only one). According to alternative embodiments of the present disclosure, power modules 52 and device dies 22 have an N-to-one correspondence; where multiple power modules 52 correspond to the same device die 22 and provide power thereto. According to still alternative embodiments of the present disclosure, power modules 52 and device dies 22 have a one-to-N correspondence; where one power module 52 corresponds to multiple device dies 22 and provide power thereto. Power modules 52 may be bonded to package substrate 48 by solder regions 54.Similarly, device dies 22 and IPD chips 30A may have one-to-one, N-to-one, or one-to-N correspondence.

[0033] According to some embodiments, holes 65 are formed in package substrate 48, interposer 56, package component 46 / 46', TIM 58, and cooling plate 60. Screws 69, which are attached to bolts 70, are inserted through holes 65 so that package substrate 48, interposer 56, package component 46 / 46', and cooling plate 60 are fastened together to form system package 66, as shown in Fig. 11A. Metal rings, clamps, or similar devices not shown may be used to further secure system package 66.

[0034] As in Fig. As shown in Figure 11A, electrical path 72, which are the paths connecting device die 22 to power module 52, is shortened by placing IPD chips 30A directly underlying device die 20. When connecting an IPD (shown as IPD chip 30A' using dashed lines), for example, to package substrate 48, the corresponding electrical path 172 must extend laterally from IPD chip 30A' and then to device chip 22 because IPD chip 30A' is used to store power for delivery to device die 22 when needed. Electrical paths 172 are thus long. Electrical path 72 is significantly shorter than electrical paths 172 because IPD chips 30A directly underlie device die 22. As a result of the short electrical paths 72, the response time of IPD chip 30A to provide power is much shorter. The performance of the respective Power Deliver Network (PDN) is thus improved.

[0035] According to some embodiments, IPD chips 30A, as shown in Fig. 11A, not all areas of the underlying device die 22 are occupied, and these areas can be used by memory die 30B. The access time of memory die 30B by device die 22 is thus significantly reduced compared to mounting memory chips 30B on package substrate 48, for example, at the position shown as 30B'.

[0036] Fig. 11B illustrates a top view of the system package 66 according to some embodiments. Multiple device dies 22, memory dies 30B, and IPD dies 30A are used in the system package 66 for parallel computing according to some embodiments of the present disclosure. It is appreciated that the device dies 22 in the system package 66 may have the same structures or different structures and layouts. Device dies 22 may be arranged as one array or multiple arrays offset from each other. Similarly, IPD dies 30A may be arranged as one array or multiple arrays offset from each other, and memory dies 30B may be arranged as one array or multiple arrays offset from each other.

[0037] According to some embodiments of the present disclosure, package component 46 / 46' is located as shown in Fig. 11B, at wafer level. Package component 46 / 46' may be a reconstructed wafer 46 having a round shape in plan view, or a cut, for example, along lines 47 for removing non-functional portions to reduce the size of the system package 66 and match the shape of the package substrate 48. Connectors 50 are shown in Fig. 11B is also illustrated according to some embodiments.

[0038] Fig. 12A and Fig. 12B illustrate a cross-sectional view and a top view, respectively, of the system package 66 according to some embodiments. For example, if IPD chips 30A are required to have high capacitance values to store more power, the IPD chips 30A may be larger than those shown in Fig. 11A and Fig. 11B and may occupy the spaces beneath device die 22. According to these embodiments, no memory dies are placed on the same plane as IPD chips 30A and overlapped by device die 22. Fig. 12B illustrates the top view of the Fig. 12A. According to some embodiments, each of the IPD chips 30A may comprise a plurality of smaller IPD chips connected in parallel and sawn into one piece, as shown in Fig. 12A, which shows that four IPD chips are connected in parallel as one. The molding processes for forming the system package 66 in Fig. 12A and Fig. 12B are essentially the same as those shown in the previous FIG., except that memory is used in the process in Fig. 1 are not bonded.

[0039] Fig. 13A, 13B, 14A, 14B, 15-19, 20A, and 20B illustrate cross-sectional views of intermediate stages in the formation of a system package according to some embodiments of the present disclosure. These embodiments are similar to the embodiments discussed in the preceding paragraphs, except that instead of performing chip-to-wafer bonding as in Fig. 1 and Fig. 2, the IPD chips and the device dies are bonded by wafer-to-wafer bonding. Unless otherwise indicated, the materials and formation processes of the components in these embodiments are substantially the same as the same components indicated by like reference numerals in the previous embodiments shown in the preceding FIGS. The details regarding the formation process and materials of the components shown in Fig. 13A, 13B, 14A, 14B, 15-19, 20A and 20B are therefore found in the explanation of the above embodiments.

[0040] Fig. 13A illustrates device wafer 20 and IPD wafer 130 to be bonded together. Device wafer 20 includes device dies 22, which have already been described with reference to Fig. 1. IPD wafer 130 contains IPD chips 30A. IPD chips 30A can be selected from the same group of candidate chips as described with reference to Fig. 1. They are therefore not repeated here. The IPD chips 30A in Fig. 13A are located in the unsawn wafer 130. The semiconductor substrate 31 (if present) and the dielectric layers in interconnect structure 33 may, for example, be continuous layers / regions that extend continuously through IPD wafer 130. Fig. 13B illustrates the perspective view of the device wafer 20 and the IPD wafer 130.

[0041] Fig. 14A and Fig. 14B illustrate a cross-sectional view and a perspective view, respectively, of the structure wherein device wafer 20 is bonded to IPD wafer 130. According to some embodiments of the present disclosure, the bonding is performed by hybrid bonding. According to alternative embodiments, other connection techniques may be used, such as solder bonding, direct metal-to-metal bonding, or the like. Next, as shown in Fig. 15, a backside grinding process is performed on IPD wafer 130 to expose vias 32. Then, redistribution structure 38 is formed, which includes dielectric layers 40 and RDLs 42. RDLs 42 are electrically connected to the IPDs in IPD chips 30A and the active components and passive components in device die 22. Next, as shown in Fig. 16, bond pads 44 are formed. Thus, reconstructed wafer 46 is formed, which includes device wafer 20 connected to IPD wafer 130 by wafer-to-wafer bonding.

[0042] Reconstructed wafer 46 can also be used in the subsequent assembly process without sawing. Fig. Figure 18 illustrates an exemplary perspective view of the reconstructed wafer 46 having the round shape shown using dashed lines. According to alternative embodiments, the reconstructed wafer 46 is sawn into smaller pieces, for example, the packages 46' in Fig. 17. Reconstructed wafer 46 may also be sawn into a single package by removing non-functional edge portions, similar to Fig. 18. The saw lines (scoring lines) 47 are similar to what is shown in Fig. 12B is shown by way of example by the dashed lines 47.

[0043] Fig. Figure 19 illustrates the intermediate stage in the assembly process of the package component 46 / 46' with package substrate 48, interposer 56, cooling plate 60, power modules 52 and connectors 50. The details of these components are essentially the same as described with reference to Fig. 10 and are not repeated here. Fig. 20A and Fig. 20B illustrate a cross-sectional view and a top view, respectively, of the resulting system package 66. It is appreciated that device die 22 in Fig. 20B are not physically separated from each other, and IPD chips 30 are not physically separated from each other. In other words, device dies 22 are physically connected as one integrated piece, and IPD chips 30A are physically connected as one integrated piece.

[0044] In the embodiments illustrated above, some processes and features according to some embodiments of the present disclosure for forming a three-dimensional (3D) package were discussed. Other features and processes may also be included. For example, test structures may be included to assist in verification testing of the 3D packages or 3DIC devices. The test structures may include, for example, test pads formed in the redistribution layer or on a substrate that enables testing of the 3D package or 3DIC, the use of probes and / or probe cards, and the like. Verification testing may be performed on intermediate structures as well as the final structure. Furthermore, the structures and methods disclosed herein may be used in conjunction with test methods that include intermediate verification of known good dies to increase yield and reduce costs.

[0045] The embodiments of the present disclosure have several advantageous features. By packaging IPD chips in the direct electrical paths between device dies (whose power is supplied by power modules and IPD chips) and the respective power modules, the electrical paths of the resulting power supply network are shortened. The efficiency of the power supply network is improved. Memory dies can also be connected directly to the device dies to reduce the time required for the device dies to access the memory dies.

[0046] According to some embodiments of the present disclosure, a package comprises a package substrate; an interposer over and bonded to the package substrate; a first wafer over and bonded to the interposer, the first wafer comprising independent passive device dies therein; and a second wafer over and bonded to the first wafer, the second wafer comprising active device dies therein. In one embodiment, the first wafer is a reconstructed wafer comprising the independent passive device dies; and an encapsulation material encapsulating the independent passive device dies therein, the encapsulation material separating the passive device dies from each other. In one embodiment, the package further comprises a plurality of memory dies encapsulated in the encapsulation material, each of the plurality of memory dies being overlapped by one of the active device dies.In one embodiment, the independent passive device dies are continuously and physically connected to each other to form an integrated piece. In one embodiment, the first wafer and the second wafer include curved edges. In one embodiment, the package further includes a power module underlying and bonded to the package substrate. In one embodiment, the first wafer includes a semiconductor substrate; and semiconductor vias penetrating the semiconductor substrate, wherein the active device dies are electrically connected to the power module through the semiconductor vias. In one embodiment, the package further includes a connector attached to the package substrate. In one embodiment, the package further includes a screw penetrating the package substrate, the first wafer, and the second wafer; and a bolt attached to the screw.In one embodiment, the package further comprises a thermal interface material; and a cold plate attached to the second wafer through the thermal interface material.

[0047] According to some embodiments of the present disclosure, a package comprises independent passive device dies forming a first arrangement, wherein the plurality of independent passive device dies include substrate vias therein; a plurality of active device dies forming a second arrangement, wherein the plurality of active device dies overlie and are bonded to the plurality of independent passive device dies; a package substrate underlying the plurality of independent passive device dies; and a plurality of power modules overlapped by the plurality of independent passive device dies and the plurality of active device dies, wherein the plurality of power modules are electrically connected to the plurality of independent passive device dies and the plurality of active device dies. In one embodiment, the plurality of active device dies are continuously and physically connected to each other to form a wafer.In one embodiment, the package further comprises a molding compound that forms the plurality of independent passive device dies therein. In one embodiment, the package further comprises a plurality of memory dies overlapped by and bonded to the plurality of active device dies.

[0048] According to some embodiments of the present disclosure, a method comprises bonding an interposer to a first package, the first package comprising a wafer having a plurality of device dies therein, wherein semiconductor substrates in the plurality of device dies are continuously connected as an integrated substrate; and a plurality of passive device dies bonded to the wafer, the plurality of passive device dies being bonded between the interposer and the wafer; bonding the interposer to the package substrate; and bonding power modules to the package substrate, the power modules being on an opposite side of the package substrate than the interposer. In one embodiment, the method further comprises encapsulating the plurality of passive device dies in an encapsulation material; and polishing the encapsulation material and the plurality of passive device dies.In one embodiment, substrate vias in the plurality of passive device dies are exposed by polishing, and after bonding the power modules, the substrate vias connect the power modules and the plurality of device dies. In one embodiment, the method further comprises bonding a plurality of memory dies to the plurality of device dies, wherein the plurality of memory dies are encapsulated in the encapsulation material. In one embodiment, the method further comprises bonding the plurality of passive device dies to the wafer by a chip-to-wafer bonding process. In one embodiment, the plurality of passive device dies are in an unsawn wafer, and the method further comprises bonding the plurality of passive device dies to the wafer by a wafer-to-wafer bonding process.

Claims

[1] Package comprising: a package substrate; an interposer over the package substrate and bonded to the package substrate; a first wafer over the interposer and bonded to the interposer, the first wafer including independent passive device dies therein; and a second wafer over the first wafer and bonded to the wafer, the second wafer having active device dies therein. [2] The package of claim 1, wherein the first wafer is a reconstructed wafer, the package further comprising: the independent passive device dies; and an encapsulation material encapsulating the independent passive device dies therein, the encapsulation material separating the independent passive device dies from each other. [3] The package of claim 2, further comprising a plurality of memory dies encapsulated in the encapsulation material, each of the plurality of memory dies being overlapped by one of the active device dies. [4] A package according to any preceding claim, wherein the independent passive device dies are continuously and physically connected to each other to form an integrated part. [5] Package according to one of the preceding claims, wherein the first wafer and the second wafer have curved edges. [6] Package according to one of the preceding claims, further comprising: a power module that lies beneath and is bonded to the package substrate. [7] The package of claim 6, wherein the first wafer comprises: a semiconductor substrate; and Semiconductor vias penetrating the semiconductor substrate, wherein the active device dies are electrically coupled to the power module through the semiconductor vias. [8] Package according to one of the preceding claims, further comprising a connector attached to the package substrate. [9] Package according to one of the preceding claims, further comprising: a screw penetrating the package substrate, the first wafer, and the second wafer; and a bolt attached to the screw. [10] Package according to one of the preceding claims, further comprising: a thermal interface material; and a cold plate attached to the second wafer through the thermal interface material. [11] Package comprising: a plurality of independent passive device dies forming a first array, the plurality of independent passive device dies including substrate vias therein; a plurality of active device dies forming a second array, the plurality of active device dies overlying the plurality of independent passive device dies and bonded to the plurality of independent passive device dies; a package substrate underlying the plurality of independent passive device dies; and a plurality of power modules overlapped by the plurality of independent passive device dies and the plurality of active device dies, wherein the plurality of power modules are electrically connected to the plurality of independent passive device dies and the plurality of active device dies. [12] The package of claim 11, wherein the plurality of active device dies are continuously and physically connected to form a wafer. [13] The package of claim 11 or 12, further comprising a molding compound that forms the plurality of independent passive device dies therein. [14] The package of any one of claims 11 to 13, further comprising a plurality of memory dies overlaid by and bonded to the plurality of active device dies. [15] Procedure comprising: Bonding an interposer to a first package, the first package comprising: - a wafer comprising a plurality of device dies therein, wherein semiconductor substrates in the plurality of device dies are continuously connected as an integrated substrate; and - a plurality of passive device dies bonded to the wafer, wherein the plurality of passive device dies are bonded between the interposer and the wafer; Bonding the interposer to a package substrate; and Bonding power modules to the package substrate, with the power modules located on an opposite side of the package substrate than the interposer. [16] The method of claim 15, further comprising: Encapsulating the plurality of passive device dies in an encapsulation material; and Polishing the encapsulation material and the multiple passive device dies. [17] The method of claim 16, wherein Substrate vias in the multiple passive devices are exposed by polishing, and the substrate vias connect the power modules and the multiple device dies after bonding the power modules. [18] The method of claim 16 or 17, further comprising: Bonding a plurality of memory dies to the plurality of device dies, wherein the plurality of memory dies are encapsulated in the encapsulation material. [19] A method according to any one of claims 15 to 18, further comprising: Bonding the plurality of passive device dies to the wafer by a chip-to-wafer bonding process. [20] Method according to one of the preceding claims 15 to 19, wherein the plurality of passive device dies are located in an unsawn wafer, and the method further comprises bonding the passive device to the wafer by a wafer-to-wafer bonding process.

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