Integrated circuit device packages and fabrication of a stripped redistribution layer for a package top-embedded multi-die connecting bridge

Abstract

An integrated circuit device package (108), comprising: a first integrated circuit die (150) on an integrated circuit package substrate (180), wherein the integrated circuit package substrate comprises a die side (189) and a terminal area side (111); a connecting bridge (120) on a penultimate layer of the integrated circuit package substrate; a single dielectric layer (132) over the connecting bridge, wherein the single dielectric layer forms the die side as a final layer of the integrated circuit package substrate and is penetrated by a bridge via (138) that contacts the connecting bridge, and wherein the single dielectric layer is penetrated by a package via (134) that is electrically coupled to the terminal area side, wherein the first integrated circuit die is coupled to the bridge via, the bridge via contacting a copper bridge terminal (140) which contacts an electrical protrusion which contacts the first integrated circuit die; and wherein the first integrated circuit die is coupled to the terminal area side by the package via which contacts a copper column (136) which contacts an electrical bump.

Description

AREA

[0001] This disclosure relates to embedded multi-chip interconnect bridges placed near the die side of integrated circuit packages. BACKGROUND

[0002] Integrated circuit miniaturization during interconnection experiences problems regarding the package footprint budget.

[0003] The publications US 2015 / 0 364 422 A1 and US 2013 / 0 307 162 A1 describe known semiconductor components. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Disclosed embodiments are shown by way of example and not by way of limitation in the figures of the accompanying drawings, wherein like reference numerals may refer to similar elements, and in which: is Fig. 1A is a cross-section of an integrated circuit package substrate during assembly, according to one embodiment. is Fig. 1B a cross-sectional view of the Fig. 1A depicted integrated circuit package substrate according to another arrangement, according to an embodiment; is Fig. 1C is a cross-sectional view of a stripped embedded multi-die interconnect bridge during assembly on a glass substrate, according to one embodiment; is Fig. 1D a cross-sectional view of the Fig. 1B and the integrated circuit package substrate shown in Fig. 1C depicts a glass-attached stripped embedded multi-die interconnect bridge after further processing, according to one embodiment; is Fig. 1E a cross-sectional view of the Fig. 1D depicted integrated circuit package substrate after further processing, according to one embodiment; is Fig. 1F a cross-sectional view of the Fig. 1E depicted integrated circuit package substrate after further processing, according to one embodiment; is Fig. 1G a cross-sectional view of the Fig. 1F depicted integrated circuit package substrate after further processing, according to one embodiment; is Fig. 1H is a cross-sectional view of an integrated circuit device package constructed from the integrated circuit package shown in the Fig. 1G depicted processed build film, according to several embodiments; is Fig. 2 a process flow diagram according to several embodiments; is Fig. 3 to show an example of a higher level device application for the disclosed embodiments; and is Fig. 4 a plan view with partially cut-away sections of the Fig. 1H, according to several embodiments. DETAILED DESCRIPTION

[0005] A silicon bridge interconnect is placed just below the top solder resist layer after the bridge interconnect is fabricated on a glass substrate and the glass substrate is removed. Fabricating the interconnect layers is performed in an inverted configuration compared to that of fabricating an existing silicon bridge interconnect. Depositing the glass substrate from the interconnect layers allows for a usefully low Z-height of the interconnect, where only the interconnect materials remain, and embedding the stripped interconnect just below the top solder resist layer saves valuable interconnect layers in the package substrate, beneath the interconnect; at least two copper layers. Stripping the glass substrate from the stripped bridge's interconnect layers also allows for thinner top layers in the package substrate's dielectric, improving signal referencing.Consequently, the stripped embedded multi-die interconnect bridge (sEMIB) allows an integrated circuit package substrate to maintain, for example, a 3-by-3 package layer count instead of a larger 4-by-4 package layer count. The sEMIB can also be referred to as a stripped redistribution layer (sRDL).

[0006] An integrated circuit is manufactured in a substrate that can be semiconducting, such as silicon, doped silicon, and III-V material combinations. Other semiconducting materials can be used, such as carbon in nanotube configurations. After manufacturing, the integrated circuit can be singulated from an array of integrated circuits into an integrated circuit chip, or IC (integrated circuit) chip.

[0007] Fig. 1A is a cross-sectional view 101 of an integrated circuit package substrate during assembly, according to one embodiment. A build-up film 110 is used as a base for forming a metal plate 112 and bond pads 114, among other structures, for connecting at least two integrated circuits (see Fig. 1H) by a stripped embedded multi-die interconnect bridge (sEMIB). In one embodiment, patterning of the metal plate 112 and the bond pads 114 is performed by patterning the structures 112 and 114 from a single copper-containing layer.

[0008] In one embodiment, the build film 110 is a partially completed integrated circuit package substrate 110 having a temporary die side 109 that houses at least two integrated circuits through a sEMIB and a land side 111 that is bonded to a board, such as a printed wiring board.

[0009] Fig. 1B is a cross-sectional view of the Fig. 1A depicts an integrated circuit package substrate 101 according to another arrangement, according to one embodiment. Integrated circuit package substrate 102 has been processed by placing a die attach film 116 on metal plate 112, pending receipt of an sEMIB redistribution layer.

[0010] Fig. 1C is a cross-sectional view 103 of a stripped embedded multi-die interconnect bridge (sEMIB) 120 during assembly on a glass substrate 118 according to one embodiment. The Z-direction coordinate is compared to the orientation of the integrated circuit package substrate 102 shown in Fig. 1B is inverted.

[0011] A glass substrate 118 is used to pattern and form an EMIB structure 120 using lithographic techniques and build the EMIB 120 on a separation layer 122. The glass substrate 118 is a semiconductor package substrate-grade structure with useful flatness and thermal and physical stability for fabricating silicon interconnect bridges. Techniques for forming silicon EMIBs on semiconductor material include fabricating a "silicon bridge" by fabricating the EMIB 120 on the glass substrate 118, followed by stripping the glass substrate 118.

[0012] In one embodiment, the EMIB 120 includes conductive traces, e.g., 124, bond pads, e.g., 126, and vias, e.g., 128, with an organic matrix 130, i.e., multiple build-up dielectric layers. As shown and in one embodiment, a three-conductive-trace layer redistribution layer 120 was fabricated.

[0013] Fig. 1D is a cross-sectional view of the Fig. 1B and the integrated circuit package substrate 102 shown in Fig. 1C depicted glass-attached EMIB 103 after further processing, according to an embodiment. The glass substrate 118 and the EMIB 120 are compared to the illustration in Fig. 1C reversed.

[0014] In one embodiment, the EMIB 120 is attached to the die attach film 116, and the separation layer 122 is irradiated with ultraviolet light 121 to allow the glass substrate 118 and the separation layer 122 to be removed. Patterning involves transmitting light energy through the inorganic substrate 118.

[0015] Fig. 1E is a cross-sectional view of the Fig. 1D and after further processing according to an embodiment. The integrated circuit package substrate 105 was prepared by removing the release layer 122 and stripping the glass substrate 118 (see Fig. 1D) in preparation for further building up and connecting the substrate 110 to at least two integrated circuits through the stripped redistribution layer 120.

[0016] Fig. 1F is a cross-sectional view of the Fig. 1E after further processing according to one embodiment. The integrated circuit package substrate 106 has been processed by forming a build-up film 132 in preparation for forming contact vias for both the integrated circuit package substrate and the stripped embedded multi-die interconnect bridge (sEMIB) 120. In one embodiment, the build-up film 132 is a single solder resist material curable by useful wavelengths of light, whether a positive photoresist or a negative photoresist. Accordingly, the Z-height of the plate 112 and the bond pads 114 is about 12 micrometers (µm), the die attach film is about 5 µm, the sEMIB 120 is about 10 µm, and the portion of the build film 132 above the sEMIB 120 is about 5-10 µm.

[0017] Fig. 1G is a cross-sectional view of the Fig. 1F after further processing according to an embodiment. The integrated circuit package substrate 107 was formed by opening contact corridors in the build-up film 132 and filling package vias 134 to the bond pads 114 (see Fig. 1F) and by forming package copper pins 136 that contact the package vias 134.

[0018] Further processing includes opening bridge via corridors in the build-up film 132 and filling bridge vias 138 (see inset 107i) and bridge copper pins 140.

[0019] The inset 107i represents a formation of the bridge via corridors, which includes a penetration of the build-up film 132 as well as a penetration of a bridge polyimide film 142, for example, to reach a bridge bond pad 144. The bridge polyimide film 142 is part of the sEMIB 120 that remains after the EMIB 120 (see Fig. 1D) is separated from the glass substrate 118 and the separation layer 122.

[0020] The removal of the release layer 122 and the glass substrate 118 (see Fig. 1D) is carried out in preparation for the further construction and connection of the integrated circuit package substrate 110 to at least two integrated circuits by the sEMIB 120.

[0021] Fig. 1H is a cross-sectional view of an integrated circuit device package 108 disposed from the integrated circuit package substrate 110 and the Fig. 1G and inset 107i, according to several embodiments.

[0022] The integrated circuit package substrate 110, together with the build film 132, forms a perimeter of an integrated circuit package substrate 180, which supports the stripped embedded multi-die interconnect (sEMIB) 120. Typically, in an sEMIB embodiment, the sEMIB 120 is attached to the integrated circuit package substrate 110 with the die attach film 116, and essentially only the build film 132 covers the sEMIB 120, as it is located in the last build layer of the integrated circuit package substrate 180. The sEMIB 120 leaves a useful printed wiring board footprint within the integrated circuit package substrate 110, where it is available beneath the sEMIB 120. Furthermore, a die side 189 of the integrated circuit package substrate 180 covers only the sEMIB 120, which is placed on the temporary die side 109 and attached with the die attach film 116.Accordingly, no remaining glass or anything else extends into the useful footprint of the integrated circuit package substrate 110.

[0023] In one embodiment, the sEMIB 120 is configured to connect to a first integrated circuit chip 150 and a subsequent integrated circuit chip 160. The bridge bond pads 156 and 166 couple to the sEMIB 120 through the bridge vias 138 (two reference lines) and bridge copper pins 140 (two reference lines).

[0024] Each of the first and subsequent integrated circuit chips 150 and 160 is also coupled to the integrated circuit package substrate 180 in substrate vias 134 that communicate with the connection area side 111.

[0025] Accordingly, the sEMIB 120 appears as a redistribution layer (RDL) with photolithographically formed traces and vias, leaving no glass and no semiconductor substrate, and a die attach film 116 attaches the sEMIB 120 to a metal plate 112, and only the buildup film 132 covers the sEMIB 120 at the die side 189 of the integrated circuit package substrate 180.

[0026] The copper pillar 136 contacts an electrical bump that contacts a bond pad 154 that is part of the first integrated circuit die 150. Similarly, the copper pillar contacts an electrical bump that contacts a bond pad 164 that is part of the subsequent integrated circuit die 160.

[0027] As illustrated, more details of traces and vias are generally given in the cross-sectional view of the integrated circuit package substrate 110, encompassing immediately below the footprint 119 of the sEMIB 120, where traces and vias in the integrated circuit package substrate 110 within the footprint 119 appear neither less dense nor differently arranged than in any other region of the integrated circuit package substrate 110. A specific trace and via density is selected depending on useful design rules and connections between integrated circuit devices, passive devices, and connections to a board 182.

[0028] In one embodiment, after forming electrical bumps 186 on the terminal area side 111, the integrated circuit package substrate 110 is placed on a circuit board 182, such as a printed wiring board main board 182. In one embodiment, the circuit board 182 includes an external enclosure 184 that provides both physical and electrical insulation for components within the external enclosure 184. In one embodiment, the circuit board 182 includes a chipset (see Fig. 3).

[0029] In one embodiment, the integrated circuit device package 108 is a basic structure for a disaggregated-die computing system 108 that includes chiplets, e.g., 170, 170', and 170", coupled to the first integrated circuit die 150, one of which is shown coupled to the first integrated circuit die 150 at active devices and metallization 152 through a through silicon via (TSV). The copper pillar 136 contacts an electrical bump that contacts a bond pad 145 that is part of the first integrated circuit die 150.

[0030] Similarly, in one embodiment, the integrated circuit device package 108 is a basic structure for a disaggregated die computing system 108 that includes chiplets 174, 174', and 174" coupled to the subsequent integrated circuit die 160, of which a chiplet 174" is shown coupled to the subsequent integrated circuit die 174" at active devices and metallization 162 by a TSV 168.

[0031] In one embodiment, the sEMIB 120 is designed in a three-level trace and bond pad configuration, as depicted in an inset 108i according to one embodiment. The integrated circuit package substrate 110 is partially depicted, and the metal plate 112 is an Nth metal layer in the integrated circuit package substrate 110. The Nth metal layer in one embodiment is the top conductive layer in a 3-2-3 package layer count for the integrated circuit substrate 110.

[0032] The bridge vias 138 and the bridge copper pins 140 are coupled to a signal layer 144 located at the bridge bond pad layer 144 shown in Inset 7i. The Nth metal layer 112 is a voltage source (VSS) layer, as well as a middle layer 193, which is also coupled to VSS. As shown, a signal layer 195 is adjacent to the die attach film 116, and signal integrity is enhanced by the position of the signal layer 195 opposite the die attach film 116 and opposite the Nth metal layer 112 as a VSS layer 112.

[0033] In one embodiment, processing leaves behind by using the Fig. 1D, the separation layer 122 has a separation layer inclusion 197 that can be detected between the polyimide film 142 and the last layer 132. Such separation layer inclusions 197 can occur randomly during stripping of the glass substrate 118, which is also shown in Fig. 1D can be seen.

[0034] In one embodiment, the build-up film 132 is a single solder resist material curable by useful light wavelengths, whether a positive photoresist or a negative photoresist. Accordingly, with the single photoresist build-up film 132 covering the stripped embedded multi-die interconnect bridge 120, the Z-height of the plate 112 is approximately 12 micrometers (µm), the die attach film is approximately 5 µm, the sEMIB 120 is approximately 10 µm, and the portion of the build-up film 132 above the sEMIB 120 is approximately 5-10 µm.

[0035] In one embodiment, the first integrated circuit die 150 and at least one chiplet, e.g., 170', form a disaggregated-die logic processor. In one embodiment, the subsequent integrated circuit die 160 and at least one chiplet, e.g., 174', form a disaggregated-die graphics processor.

[0036] In one embodiment, the first integrated circuit die 150 and all chiplets, e.g., 170, 170', and 170", as well as the subsequent integrated circuit die 160 and all chiplets, e.g., 174, 174', and 174", form a disaggregated-die logic processor. In one embodiment, the first integrated circuit die 150 and all chiplets, e.g., 170, 170', and 170", as well as the subsequent integrated circuit die 160 and all chiplets, e.g., 174, 174', and 174", form a disaggregated-die graphics processor.

[0037] In one embodiment, the sEMIB 120 is fabricated to translate between two or more design rule geometries, wherein the first integrated circuit die 150 has a larger design rule geometry than that of the subsequent integrated circuit die 160. Thus, the sEMIB 120 translates as a stripped RDL 120 between at least two different design rule geometries.

[0038] Fig. 2 is a process flow diagram according to several embodiments.

[0039] At 210, the process includes placing a glass-based interconnect bridge onto a die attach film on a penultimate layer of an integrated circuit package substrate. In one embodiment, the inorganic base is semiconducting or undoped silicon, which is a sacrificial substrate.

[0040] At 220, the process involves releasing the glass from the connecting bridge.

[0041] At 230, the process includes forming a final dielectric layer on the integrated circuit package substrate and the interconnect bridge.

[0042] At 240, the process includes connecting a first integrated circuit chip and a subsequent integrated circuit chip to the sEMIB through only the last dielectric layer.

[0043] At 250, the process includes arranging the sEMIB to a computing system.

[0044] Fig. 3 is included to show an example of a higher-level device application for the disclosed embodiments. Embodiments of stripped embedded multi-die interconnects can be found in various parts of a computing system. In one embodiment, the stripped embedded multi-die interconnect is part of a communications device, such as one attached to a cellular communications tower. In one embodiment, a computing system 300 includes, but is not limited to, a desktop computer. In one embodiment, a system 300 includes, but is not limited to, a laptop computer. In one embodiment, a system 300 includes, but is not limited to, a netbook. In one embodiment, a system 300 includes, but is not limited to, a tablet.In one embodiment, a system 300 includes, but is not limited to, a notebook computer. In one embodiment, a system 300 includes, but is not limited to, a personal digital assistant (PDA). In one embodiment, a system 300 includes, but is not limited to, a server. In one embodiment, a system 300 includes, but is not limited to, a workstation. In one embodiment, a system 300 includes, but is not limited to, a cellular phone. In one embodiment, a system 300 includes, but is not limited to, a mobile computing device. In one embodiment, a system 300 includes, but is not limited to, a smartphone. In one embodiment, a system 300 includes, but is not limited to, an Internet application.Other types of computing devices may be formed with the microelectronic device including stripped embedded multi-die interconnect embodiments.

[0045] In one embodiment, processor 310 includes one or more processing cores 312 and 312N, where 312N represents the Nth processor core within processor 310, where N is a positive integer. In one embodiment, electronic device system 300 employing an embodiment of a stripped embedded multi-die interconnect bridge includes multiple processors, including 310 and 305, where processor 305 includes logic similar or identical to the logic of processor 310. In one embodiment, processing core 312 includes, but is not limited to, pre-fetch logic to access instructions, decode logic to decode the instructions, execution logic to execute instructions, and the like.In one embodiment, processor 310 includes a cache 316 to cache at least one of instructions and data for the stripped embedded multi-die interconnect bridge in system 300. Cache 316 may be organized in a hierarchical structure including one or more levels of cache memory.

[0046] In one embodiment, the processor 310 includes a memory controller (MC) 314 operable to perform functions that enable the processor 310 to access and communicate with a memory 330, which includes at least one of a volatile memory 332 and a non-volatile memory 334. In one embodiment, the processor 310 is coupled to the memory 330 and a chipset 320. In one embodiment, the chipset 320 is part of a system-in-package with a stripped embedded multi-die interconnect bridge implemented in Fig. 1H and inset 108i. The processor 310 may also be coupled to a wireless antenna 378 to communicate with any device configured to at least one of transmit and receive wireless signals. In one embodiment, the wireless antenna interface 378 operates in accordance with, but is not limited to, the IEEE 802.11 standard and its relatives, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any type of wireless communication protocol.

[0047] In one embodiment, volatile memory 332 includes, but is not limited to, synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), RAMBUS dynamic random access memory (RDRAM), and / or any other type of random access memory device. Non-volatile memory 334 includes, but is not limited to, flash memory, phase change memory (PCM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or any other type of non-volatile memory device.

[0048] Memory 330 stores information and instructions to be executed by processor 310. In one embodiment, memory 330 may also store temporary variables or other intermediate information while processor 310 executes instructions. In the illustrated embodiment, chipset 320 connects to processor 310 via point-to-point (PtP or PP) interfaces 317 and 322. Each of these PtP embodiments may be achieved using an embodiment of a stripped embedded multi-die interconnect, as set forth in this disclosure. Chipset 320 enables processor 310 to connect to other elements in an embodiment of a stripped embedded multi-die interconnect in system 300.In one embodiment, interfaces 317 and 322 operate according to a point-to-point communication protocol such as the Intel® QuickPath Interconnect (QPI) or the like. In other embodiments, a different connection may be used.

[0049] In one embodiment, chipset 320 is operable to communicate with processor 310, 305N, display device 340, and other devices 372, 376, 374, 360, 362, 364, 366, 377, etc. Chipset 320 may also be coupled to a wireless antenna 378 to communicate with any device configured to perform at least one of transmitting and receiving wireless signals.

[0050] Chipset 320 connects to display device 340 via interface 326. Display 340 may be, for example, a liquid crystal display (LCD), a plasma display, a cathode ray tube (CRT) display, or any other type of visual display device. In one embodiment, processor 310 and chipset 320 are combined in a computing system in a stripped, embedded multi-die interconnect package. Additionally, chipset 320 connects to one or more buses 350 and 355 that connect various elements 374, 360, 362, 364, and 366. Buses 350 and 355 may be interconnected via a bus bridge 372, such as at least one embodiment of a stripped, embedded multi-die interconnect package device.In one embodiment, the chipset 320 couples via the interface 324 to a non-volatile memory 360, one or more mass storage devices 362, a keyboard / mouse 364, a network interface 366, the smart TV 376, and consumer electronics 377, etc.

[0051] In one embodiment, mass storage device 362 includes, but is not limited to, a solid-state drive (SSD), a hard disk drive, a universal serial bus flash memory drive, or any other type of computer data storage medium. In one embodiment, network interface 366 is implemented by any type of well-known network interface standard, including, but not limited to, an Ethernet interface, a Universal Serial Bus (USB) interface, a Peripheral Component Interconnect (PCI) Express interface, a wireless interface, and / or any other suitable type of interface. In one embodiment, the wireless interface operates in accordance with IEEE 802.11 standard and its relatives, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any type of wireless communication protocol, but is not limited to these.

[0052] While the Fig. While the modules shown in Figure 3 are depicted as separate blocks within the embedded magnetic inductor and a stripped-embedded multi-die interconnect package in a computing system 300, the functions performed by some of these blocks may be integrated within a single semiconductor circuit or may be implemented using two or more separate integrated circuits. For example, cache memory 316 (or selected aspects of 316) may be incorporated into processor core 312, although cache memory 316 is depicted as a separate block within processor 310.

[0053] In one embodiment, a single processor 310 includes embodiments of a stripped embedded multi-die interconnect bridge with chiplets, such as one, all, or more than chiplets 170 through 170", and optionally one, all, or more than chiplets 174 through 174", forming the single processor 310.

[0054] Where useful, the computing system 300 may include a broadcast fabric interface, such as for attaching the device to a cell tower.

[0055] Fig. 4 is a plan view 400 with partially cut-away sections of the Fig. 1H, according to several embodiments. The computing system 108 shown in Fig.The disaggregated-die computing system 108 depicted in Figure 1H can be seen at cross-section line 1H-1H. The first integrated circuit die 150 can be seen below a chiplet array, as can the subsequent integrated circuit die 160. The first-die chiplets 170, 170', and 170" can be seen above the first die, according to one embodiment. Similarly, the subsequent-die chiplets 174, 174', and 174" can be seen above the subsequent die 160, according to one embodiment.

[0056] In one embodiment, a 3 x 4 array of chiplet spaces is formed on the backside surface of the first integrated circuit die 150, but four of the spaces are occupied by heat pads 463 to facilitate heat dissipation from the first die 150 and into a heat sink, such as an integrated heat spreader, that contacts the heat pads. In one embodiment, all of the first chiplet spaces are occupied by integrated circuit chiplets. Similarly, in one embodiment, a 3 x 4 array of chiplet spaces is formed on the backside surface of the subsequent die 160, but four of the spaces are occupied by heat pads 481 to facilitate heat dissipation from the subsequent die 160 and into the same heat sink that contacts the heat pads 463, according to one embodiment.In one embodiment, all subsequent chiplet spaces are occupied by integrated circuit chiplets.

[0057] As shown, different useful structures for heat pads 463 and 481 are applied over the respective first and subsequent integrated circuit chips 150 and 160, depending on the usefulness of the heat extraction.

[0058] To illustrate the stripped embedded multi-die interconnect embodiments and methods disclosed herein, a non-limiting list of examples is provided herein:

[0059] Example 1 is an integrated circuit device package comprising: a first integrated circuit die on an integrated circuit package substrate, wherein the integrated circuit package substrate comprises a die side and a terminal side; an interconnect bridge on a second-to-last layer of the integrated circuit package substrate; a single dielectric layer over the interconnect bridge, wherein the single dielectric layer comprises the die side as a last layer, is penetrated by a bridge via contacting the interconnect bridge, and wherein the single dielectric layer is penetrated by a package via electrically coupled to the terminal side.

[0060] In Example 2, the subject matter of Example 1 optionally includes the interconnect bridge being on a die attach film located on the second to last layer of the integrated circuit package substrate.

[0061] In Example 3, the subject matter of one or more of Examples 1-2 optionally includes that the interconnect bridge is located on a die attach film located on the second to last layer of the integrated circuit package substrate, and that the interconnect bridge has three conductive layers, wherein a lower conductive layer contacts the die attach film, and an upper conductive layer is contacted by the bridge via.

[0062] In Example 4, the subject matter of any one or more of Examples 1-3 optionally comprises micrometers.

[0063] In Example 5, the subject matter of any one or more of Examples 1-4 optionally comprises a first integrated circuit die coupled to the bridge via contacting the interconnect bridge and coupled to the package via.

[0064] In Example 6, the subject matter of any one or more of Examples 1-5 optionally comprises a first integrated circuit die coupled to the bridge via, wherein the bridge via contacts a copper bridge pad that contacts an electrical bump that contacts the first integrated circuit die; and wherein the first integrated circuit die is coupled to the terminal area side by the package via that contacts a copper pillar that contacts an electrical bump.

[0065] In Example 7, the subject matter of any one or more of Examples 1-6 optionally comprises a first integrated circuit die coupled to the bridge via, wherein the bridge via contacts a copper bridge pad that contacts an electrical bump that contacts the first integrated circuit die; wherein the first integrated circuit die is coupled to the pad side by the package via that contacts a copper pillar that contacts an electrical bump; a subsequent integrated circuit die coupled to a subsequent bridge via, wherein the subsequent bridge via contacts a copper bridge pad that contacts an electrical bump that contacts the subsequent integrated circuit die;and wherein the subsequent integrated circuit die is coupled to the terminal area side by a subsequent package via that contacts a copper pillar that contacts an electrical bump;

[0066] In Example 8, the subject matter of any one or more of Examples 1-7 optionally includes wherein the single dielectric layer cover is also located over and contacting the second to last layer.

[0067] In Example 9, the subject matter of Example 8 optionally includes the interconnect bridge being on a die attach film located on the second to last layer of the integrated circuit package substrate.

[0068] In Example 10, the subject matter of one or more of Examples 8-9 optionally includes wherein the interconnect bridge is located on a die attach film located on the second to last layer of the integrated circuit package substrate, and wherein the interconnect bridge has three conductive layers, with a lower conductive layer contacting the die attach film.

[0069] In Example 11, the subject matter of any one or more of Examples 1-10 optionally comprises a first integrated circuit die coupled to the bridge via contacting the interconnect bridge and coupled to the package via.

[0070] In Example 12, the subject matter of any one or more of Examples 1-11 optionally comprises a first integrated circuit die coupled to the bridge via, wherein the bridge via contacts a copper bridge pad that contacts an electrical bump that contacts the first integrated circuit die; and wherein the first integrated circuit die is coupled to the terminal area side by the package via that contacts a copper pillar that contacts an electrical bump.

[0071] In Example 13, the subject matter of any one or more of Examples 1-12 optionally comprises the last layer contacting a separation layer enclosure, wherein the interconnect bridge further comprises a polyimide film penetrated by the bridge via, and wherein the separation layer enclosure is located between the polyimide film and the last layer.

[0072] Example 14 is a computing system comprising: an integrated circuit device package comprising a die side and a land side; a first integrated circuit on the integrated circuit package substrate die side; an interconnect bridge on a second-to-last layer of the integrated circuit package substrate; a single dielectric layer overlying the interconnect bridge, wherein the single dielectric layer includes the die side as a last layer, is penetrated by a bridge via contacting the interconnect bridge, and wherein the single dielectric layer is penetrated by a package via electrically coupled to the land side; a first integrated circuit die coupled to the bridge via, wherein the bridge via contacts a copper bridge pad contacting an electrical bump contacting the first integrated circuit die;wherein the first integrated circuit die is coupled to the pad side by the package via contacting a copper pillar contacting an electrical bump; a subsequent integrated circuit die coupled to a subsequent bridge via, the subsequent bridge via contacting a copper bridge pad contacting an electrical bump contacting the subsequent integrated circuit die; the subsequent integrated circuit die is coupled to the pad side by a subsequent package via contacting a copper pillar contacting an electrical bump; and wherein the first and subsequent integrated circuit dies are part of a chipset.

[0073] In Example 15, the subject matter of Example 14 optionally includes more than one chiplet on the first integrated circuit die at a backside, wherein one of the more than one chiplet communicates with the first integrated circuit die through a silicon via.

[0074] In Example 16, the subject matter of one or more of Examples 14-15 optionally includes more than one chiplet on the first integrated circuit die at a backside, wherein one of the more than one chiplet communicates with the first integrated circuit die through a silicon via; and more than one chiplet on the subsequent integrated circuit die at a backside, wherein one of the more than one chiplet communicates with the subsequent integrated circuit die through a silicon via.

[0075] In Example 17, the subject matter of one or more of Examples 14-16 optionally includes more than one chiplet on the first integrated circuit die at a backside, wherein one of the more than one chiplet communicates with the first integrated circuit die through a silicon via; more than one chiplet on the subsequent integrated circuit die at a backside, wherein one of the more than one chiplet communicates with the subsequent integrated circuit die through a silicon via; and wherein at least one of the more than one chiplet on the first integrated circuit, at least one of the more than one chiplet on the subsequent integrated circuit die, and at least one of the first and subsequent integrated circuit dies comprise a disaggregated logic processor.

[0076] In Example 18, the subject matter of any one or more of Examples 14-17 optionally includes more than one chiplet on the first integrated circuit die at a backside, wherein one of the more than one chiplet communicates with the first integrated circuit die through a silicon via; more than one chiplet on the subsequent integrated circuit die at a backside, wherein one of the more than one chiplet communicates with the subsequent integrated circuit die through a silicon via; and wherein at least one of the more than one chiplet on the first integrated circuit, wherein at least one of the more than one chiplet is on the subsequent integrated circuit die, and at least one of the first and subsequent integrated circuit dies comprises a disaggregated graphics processor.

[0077] In Example 19, the subject matter of any one or more of Examples 14-18 optionally includes more than one chiplet on the first integrated circuit die at a backside, wherein one of the more than one chiplet communicates with the first integrated circuit die through a silicon via; more than one chiplet on the subsequent integrated circuit die at a backside, wherein one of the more than one chiplet communicates with the subsequent integrated circuit die through a silicon via;wherein at least one of the more than one chiplet on the first integrated circuit, wherein at least one of the more than one chiplet on the subsequent integrated circuit die and at least one of the first and subsequent integrated circuit dies comprises a disaggregated logic processor, and wherein at least one of the more than one chiplet on the first integrated circuit, wherein at least one of the more than one chiplet on the subsequent integrated circuit die and at least one of the first and subsequent integrated circuit dies comprises a disaggregated graphics processor;

[0078] Example 20 is a process for forming an interconnect bridge, comprising: patterning metallization on an inorganic substrate, comprising patterning three metallization layers including vias and conductive traces; stripping the inorganic substrate after depositing the metallization onto a die attach film of an integrated circuit package substrate; and forming a single dielectric layer over the metallization and the integrated circuit package substrate.

[0079] In Example 21, the subject matter of Example 20 optionally includes that patterning comprises patterning with first a top layer and last a bottom layer, followed by inverting the metallization upon placement on the die attach film.

[0080] In Example 22, the subject matter of one or more of Examples 20-21 optionally comprises connecting a first and a subsequent integrated circuit die to the metallization through the single dielectric layer.

[0081] In Example 23, the article of any one or more of Examples 20-22 optionally comprises wherein patterning the metallization on the inorganic substrate comprises transmitting light energy through the inorganic substrate.

[0082] The above detailed description includes references to the accompanying drawings, which form a part of the detailed description. By way of illustration, the drawings show specific embodiments in which the invention may be practiced. These embodiments are also referred to herein as "examples." Such examples may include elements in addition to those shown or described. However, the present inventors also contemplate examples in which only those elements shown or described are provided. Further, the present inventors also contemplate examples that utilize any combination or permutation of those elements shown or described (or one or more aspects thereof), either with respect to a particular example (or one or more aspects thereof) or with respect to other examples (or one or more aspects thereof).

Claims

[1] An integrated circuit device package (108) comprising: a first integrated circuit die (150) on an integrated circuit package substrate (180), the integrated circuit package substrate comprising a die side (189) and a terminal area side (111); a connecting bridge (120) on a penultimate layer of the integrated circuit package substrate; a single dielectric layer (132) over the connecting bridge, wherein the single dielectric layer forms the die side as a last layer of the integrated circuit package substrate and is penetrated by a bridge via (138) that contacts the connecting bridge, and wherein the single dielectric layer is penetrated by a package via (134) that is electrically coupled to the connection area side, wherein the first integrated circuit die is coupled to the bridge via, the bridge via contacting a copper bridge pad (140) that contacts an electrical bump that contacts the first integrated circuit die; and wherein the first integrated circuit die is coupled to the terminal area side by the package via contacting a copper pillar (136) contacting an electrical bump. [2] The integrated circuit device package of claim 1, wherein the interconnect bridge (120) is located on a die attach film (116) located on the second to last layer of the integrated circuit package substrate (180). [3] The integrated circuit device package according to claim 1 or 2, wherein the connecting bridge (120) is located on a die attach film (116) located on the second to last layer of the integrated circuit package substrate (180), and wherein the connecting bridge has three conductive layers, wherein a lower conductive layer of the three conductive layers contacts the die attach film, and an upper conductive layer is contacted by the bridge via. [4] The integrated circuit device package of claim 1, 2 or 3, wherein the interconnect bridge (120) is located on a die attach film (116) located on the second to last layer of the integrated circuit package substrate (180), and wherein the interconnect bridge comprises three conductive layers, wherein a lower conductive layer of the three conductive layers contacts the die attach film, an upper conductive layer is contacted by the bridge via, and wherein the interconnect bridge has a Z-height of about 10 micrometers. [5] The integrated circuit device package of claim 1, 2, 3 or 4, further comprising: a subsequent integrated circuit die (160) coupled to a subsequent bridge via, the subsequent bridge via contacting a copper bridge pad that contacts an electrical bump that contacts the subsequent integrated circuit die; and wherein the subsequent integrated circuit die is coupled to the terminal area side by a subsequent package via contacting a copper pillar contacting an electrical bump. [6] The integrated circuit device package of any preceding claim, wherein the single dielectric layer (132) also overlies and contacts the second-to-last layer. [7] The integrated circuit device package of claim 6, wherein the interconnect bridge (120) is located on a die attach film (116) located on the second to last layer of the integrated circuit package substrate (180). [8] The integrated circuit device package according to claim 6 or 7, wherein the connecting bridge (120) is located on a die attach film (116) located on the second to last layer of the integrated circuit package substrate (180), and wherein the connecting bridge has three conductive layers, wherein a lower conductive layer of the three conductive layers contacts the die attach film. [9] The integrated circuit device package of claim 6, 7 or 8, further comprising: the first integrated circuit die (150), coupled to the bridge via contacting the connecting bridge (120), and coupled to the package via. [10] The integrated circuit device package of claim 6, 7, 8 or 9, further comprising: the first integrated circuit die (150) coupled to the bridge via, the bridge via contacting a copper bridge pad that contacts an electrical bump that contacts the first integrated circuit die; and wherein the first integrated circuit die is coupled to the terminal area side by the package via contacting a copper pillar contacting an electrical bump. [11] The integrated circuit device package of any preceding claim, wherein the last layer (132) contacts an isolation layer enclosure (197), wherein the interconnect bridge (120) further comprises a polyimide film (142) penetrated by the bridge via, and wherein the isolation layer enclosure is located between the polyimide film and the last layer. [12] An integrated circuit device package (108) comprising: a first integrated circuit die (150) on an integrated circuit package substrate (180), the integrated circuit package substrate comprising a die side (189) and a terminal area side (111); a connecting bridge (120) on a penultimate layer of the integrated circuit package substrate; a single dielectric layer (132) over the connecting bridge, wherein the single dielectric layer forms the die side as a last layer of the integrated circuit package substrate and is penetrated by a bridge via (138) that contacts the connecting bridge, and wherein the single dielectric layer is penetrated by a package via (134) that is electrically coupled to the connection area side, wherein the connecting bridge is located on a die attach film (116) located on the second to last layer of the integrated circuit package substrate, and wherein the connecting bridge has three conductive layers, wherein a lower conductive layer of the three conductive layers contacts the die attach film, and an upper conductive layer is contacted by the bridge via. [13] A computing system (300) comprising: an integrated circuit package substrate comprising a die side (189) and a terminal area side (111); a first integrated circuit on the integrated circuit package substrate die side; a connecting bridge (120) on a penultimate layer of the integrated circuit package substrate; a single dielectric layer (132) covering the interconnect bridge, the single dielectric layer comprising the die side as a last layer, being penetrated by a bridge via (138) contacting the interconnect bridge, and the single dielectric layer being penetrated by a package via (134) electrically coupled to the terminal area side; a first integrated circuit die (150) coupled to the bridge via, the bridge via contacting a copper bridge pad that contacts an electrical bump that contacts the first integrated circuit die; wherein the first integrated circuit die is coupled to the terminal area side by the package via contacting a copper pillar contacting an electrical bump; a subsequent integrated circuit die (160) coupled to a subsequent bridge via, the subsequent bridge via contacting a copper bridge pad that contacts an electrical bump that contacts the subsequent integrated circuit die; wherein the subsequent integrated circuit die is coupled to the terminal area side by a subsequent package via contacting a copper pillar contacting an electrical bump; and where the first and subsequent integrated circuit dies are part of a chipset. [14] The computing system of claim 13, further comprising more than one chiplet (170) on the first integrated circuit die (150) at a backside, wherein one of the more than one chiplet communicates with the first integrated circuit die through a silicon via (158). [15] The computing system according to claim 13 or 14, further comprising: more than one chiplet (170) on the first integrated circuit die (160) at a backside, wherein one of the more than one chiplet communicates with the first integrated circuit die through a silicon via (158); and more than one chiplet (174) on the subsequent integrated circuit die (160) at a backside, wherein one of the more than one chiplet communicates with the subsequent integrated circuit die through a silicon via (168). [16] The computing system of claim 13, 14 or 15, further comprising: more than one chiplet (170) on the first integrated circuit die (150) at a backside, wherein one of the more than one chiplet communicates with the first integrated circuit die through a silicon via (158); more than one chiplet (174) on the subsequent integrated circuit die (160) at a backside, wherein one of the more than one chiplet communicates with the subsequent integrated circuit die through a silicon via (168); and wherein at least one of the more than one chiplet on the first integrated circuit, at least one of the more than one chiplet on the subsequent integrated circuit die and at least one of the first and subsequent integrated circuit dies comprises a disaggregated logic processor. [17] The computing system according to any one of claims 13-16, further comprising: more than one chiplet (170) on the first integrated circuit die (150) at a backside, wherein one of the more than one chiplet communicates with the first integrated circuit die through a silicon via (158); and more than one chiplet (174) on the subsequent integrated circuit die (160) at a rear side, wherein one of the more than one chiplet communicates with the subsequent integrated circuit die through a silicon via (168), wherein at least one of the more than one chiplet is on the first integrated circuit, wherein at least one of the more than one chiplet on the subsequent integrated circuit die and at least one of the first and subsequent integrated circuit dies comprises a disaggregated graphics processor. [18] The computing system according to any one of claims 13-17, further comprising: more than one chiplet (170) on the first integrated circuit die (150) at a backside, wherein one of the more than one chiplet communicates with the first integrated circuit die through a silicon via (158); and more than one chiplet (174) on the subsequent integrated circuit die (160) at a rear side, wherein one of the more than one chiplet communicates with the subsequent integrated circuit die through a silicon via (168), wherein at least one of the more than one chiplet is on the first integrated circuit, wherein at least one of the more than one chiplet is on the subsequent integrated circuit die and at least one of the first and subsequent integrated circuit dies comprises a disaggregated logic processor, and wherein at least one of the more than one chiplet is on the first integrated circuit, wherein at least one of the more than one chiplet is on the subsequent integrated circuit die and at least one of the first and subsequent integrated circuit dies comprises a disaggregated graphics processor. [19] A process for forming a connecting bridge, comprising: Structuring a metallization on an inorganic substrate (118), comprising structuring three metallization layers comprising vias and conductive traces; Stripping the inorganic substrate after depositing the metallization onto a die attachment film (116) of an integrated circuit package substrate (118); and Forming a single dielectric layer (132) over the metallization and the integrated circuit package substrate. [20] The process of claim 19, wherein patterning comprises patterning with first an upper layer and last a lower layer, followed by inverting the metallization upon placement on the die attach film (116). [21] The process of claim 19 or 20, further comprising connecting a first and a subsequent integrated circuit die (150, 160) to the metallization through the single dielectric layer. [22] The process of claim 19, 20 or 21, wherein patterning the metallization on the inorganic substrate (118) comprises transmitting light energy through the inorganic substrate.

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