Core-cladding nanostructures for semiconductor devices

Abstract

comprising a semiconductor device: a substrate (106); a stack of nanostructured layers (120, 122) with first nanostructured regions (120A, 122A) and second nanostructured regions (121A, 123A) on the substrate (106); nanostructured mantle regions (121B, 123B) that are wrapped around the second nanostructured regions (121A, 123A), wherein - the nanostructured mantle regions (121B, 123B) and the second nanostructured regions (121A, 123A) exhibit semiconductor materials that are different from each other, and - the nanostructured mantle regions (121B, 123B) have surface planes with a first crystal orientation and the second nanostructured regions (121A, 123A) have surface planes with a second crystal orientation that is different from the first crystal orientation; a first S / D region (126A, 126B) and a second S / D region (126A, 126B) on the substrate (106), wherein the first S / D region (126A, 126B) and the second S / D region (126A, 126B) each have an epitaxial region (110A, 110B) that is wrapped around each of the first nanostructured regions (120A, 122A); and a GAA structure (112A, 112B) that is positioned between the first S / D region (126A, 126B) and the second S / D region (126A, 126B) and is wrapped around each of the nanostructured mantle regions (121B, 123B).

Description

TECHNICAL BACKGROUND

[0001] As semiconductor technology has advanced, the demand for higher storage capacity, faster processing systems, and increased performance has grown. To meet this demand, the semiconductor industry is constantly working to reduce the size of semiconductor devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs), including planar MOSFETs and fin field-effect transistors (FinFETs) (downscaling). This downscaling has increased the complexity of semiconductor manufacturing processes.

[0002] The prior art relevant to the present invention is given by US 2018 / 0 175 214 A1, US 9 525 064 B1, US 2014 / 0 001 441 A1 and DE 10 2018 108 821 A1.

[0003] The present invention is defined according to the subject matter of the attached independent claims. Particular embodiments are given by the additional features of the attached dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of this disclosure are best understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been enlarged or reduced for the sake of clarity. Fig. Figures 1A and 1B-1D illustrate an isometric view and cross-sectional views, respectively, of a semiconductor device with core-cladding nanostructures according to some embodiments. Fig. Figures 1E and 1F-1G illustrate an isometric view and cross-sectional views, respectively, of a semiconductor device with passivation layers according to some embodiments. Fig. Figures 2A-2D illustrate cross-sectional views of various configurations of a semiconductor device according to some embodiments. Fig. Figure 3 is a flowchart of a process for manufacturing a semiconductor device with core-cladding nanostructures according to some embodiments. Fig. Figures 4A-23A illustrate isometric views of a semiconductor device with internal and external spacer structures at various stages of its manufacturing process according to some embodiments. Fig. Figures 4B-23B, 9C-23C and 9D-23D illustrate cross-sectional views of a semiconductor device with internal and external spacer structures at various stages of its manufacturing process according to some embodiments.

[0005] Illustrative embodiments are now described with reference to the accompanying drawings. In the drawings, identical reference numbers generally denote identical, functionally similar, and / or structurally similar elements. DETAILED DESCRIPTION

[0006] The following disclosure provides many different embodiments or examples for implementing various features of the subject matter discussed herein. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not intended to be limiting. For instance, the process of forming a first feature over a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, so that the first and second features are not necessarily in direct contact.For the purposes of this text, the formation of a first structural element on a second structural element means that the first structural element is formed in direct contact with the second structural element. Furthermore, this disclosure may repeat reference numbers and / or letters in the various examples. This repetition does not automatically establish a relationship between the various embodiments and / or configurations discussed.

[0007] Spatially relative terms, such as "below," "under," "lower," "above," "upper," and the like, may be used in this text to simplify descriptions and to describe the relationship of one element or feature to one or more other elements or features, as illustrated in the figures. These spatially relative terms are intended to encompass other orientations of the device in use or operation besides the orientation shown in the figures. The device may also be oriented differently (rotated by 90 degrees, or in other orientations), and the spatially relative descriptors used in this text may be interpreted accordingly.

[0008] It should be noted that references in the specification to "a single embodiment," "an embodiment," "an exemplary embodiment," "exemplary," etc., indicate that the described embodiment may include a specific feature, structure, or property, but that not every embodiment necessarily has to include that specific feature, structure, or property. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, if a specific feature, structure, or property is described in connection with one embodiment, it is within the capabilities of a person skilled in the art to realize such a feature, structure, or property in connection with other embodiments, whether explicitly described or not.

[0009] It is understood that the phraseology or terminology used in the present text serves the purpose of description and not limitation, insofar as the terminology or phraseology used in the present specification is to be interpreted by the appropriately knowledgeable person in accordance with the teachings contained in the present text.

[0010] For the purposes of this text, the term "etch selectivity" refers to the ratio of the etch rates of two different materials under the same etching conditions.

[0011] For the purposes of this text, the term “deposition selectivity” refers to the ratio of the deposition rates on two different materials or surfaces under the same deposition conditions.

[0012] In the context of this text, the term "high k-value" refers to a high dielectric constant. Specifically, in the context of semiconductor device structures and manufacturing processes, "high k-value" refers to a dielectric constant greater than that of SiO2 (e.g., greater than 3.9).

[0013] For the purposes of this text, the term “p-type” defines a structure, layer and / or region as doped with p-type dopants, such as boron.

[0014] For the purposes of this text, the term "n-type" defines a structure, layer and / or region as doped with n-type dopants, such as phosphorus.

[0015] For the purposes of this text, the term “nanostructured” defines a structure, layer and / or region as having a horizontal dimension (for example, along an X and / or Y axis) and / or a vertical dimension (for example, along a Z axis) of less than 100 nm.

[0016] In some embodiments, the terms "approximately" and "essentially" may indicate a value of a certain quantity that varies within 5% of the value (for example, ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values ​​are, of course, only examples and are not intended as limitations. It is understood that the terms "approximately" and "essentially" may refer to a percentage of the values ​​as interpreted by a person skilled in the art in light of the teachings described in this text.

[0017] The fin structures disclosed herein can be structured by any suitable method. For example, the fin structures can be structured by one or more photolithography processes, including dual-structuring or multiple-structuring processes. In general, dual-structuring or multiple-structuring processes combine photolithography and self-aligning processes, thereby producing structures that, for example, have center-to-center distances smaller than those that can otherwise be obtained by a single, direct photolithography process. For example, in some embodiments, a sacrificial layer is formed over a substrate and structured by a photolithography process. Spacers are formed along the structured sacrificial layer by a self-aligning process.The sacrificial layer is then removed, and the remaining spacers can then be used to structure the fin structures.

[0018] This disclosure provides exemplary structures and methods for improving charge carrier mobility (e.g., hole and / or electron mobility) in FET devices (e.g., FinFETs, gate all-around FETs, etc.). Increasing charge carrier mobility allows for higher switching speeds and drive currents of FET devices, resulting in faster and improved FET performance.

[0019] The exemplary structures and methods provide channel regions with core-mantle nanostructures between source / drain (S / D) regions of FET devices. In some embodiments, the core-mantle nanostructures can include nanostructured core regions around which epitaxially grown nanostructured mantle regions are formed. The core-mantle nanostructures can be configured to induce tensile or compressive stresses in the channel regions for n- or p-type FET devices. Tensile or compressive stress can be induced in the channel regions by, for example, doping the nanostructured core or mantle regions or by using lattice-mismatched semiconductor materials for the nanostructured core or mantle regions. Such induced stress in the channel regions can improve charge carrier mobility within the channel regions.The core-cladding nanostructures can further be configured to tune the energy bandgap of the channel regions and / or modify the crystal orientation of the surface planes of the channel regions based on the conductivity type of the FET devices, in order to improve the charge carrier mobility in the channel regions. The channel regions with core-cladding nanostructures described here can increase the switching speeds and drive currents of FET devices by, for example, approximately 20% to 40% and approximately 30% to 50%, respectively, compared to FET devices without such core-cladding nanostructures.

[0020] A semiconductor device 100, comprising FETs 102A-102B, is described with reference to Fig. 1A-1D according to some embodiments. Fig. Figure 1A illustrates an isometric view of the semiconductor device 100 according to some embodiments. Fig. Figure 1B-1D illustrates cross-sectional views along lines BB, CC and DD of semiconductor device 100. Fig. 1A according to some embodiments. In some embodiments, the FETs 102A-102B can be either p-type FETs or n-type FETs, or a FET of each conductivity type. Even if two FETs are referred to with respect to the Fig. As discussed in sections 1A-1D, the semiconductor device 100 can have any number of FETs. The discussion of the elements of FETs 102A-102B with the same remarks applies to each other unless otherwise noted. The isometric and cross-sectional views of the semiconductor device 100 are for illustrative purposes only and need not be drawn to scale.

[0021] As in the Fig. As shown in Figures 1A-1D, the FETs 102A-102B can be formed on a substrate 106. The substrate 106 can be a semiconductor material such as silicon. In some embodiments, the substrate 106 can be a crystalline silicon substrate (for example, a wafer).In some embodiments, the substrate 106 may contain: (i) an elemental semiconductor such as germanium (Ge); (ii) a composite semiconductor comprising silicon carbide (SiC), silicon arsenide (SiAs), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb) and / or a III-V semiconductor material; (iii) an alloy semiconductor containing silicon germanium (SiGe), silicon germanium carbide (SiGeC), germanium stannum (GeSn), silicon germanium stannum (SiGeSn), gallium arsenic phosphide (GaAsP), gallium indium phosphide (GaInP), gallium indium arsenide (GaInAs), gallium indium arsenic phosphide (GaInAsP), aluminum indium arsenide (AlAs) and / or aluminum gallium arsenide (AlGaAs); (iv) a silicon-on-insulator (SOI) structure; (v) a silicon germanium (SiGe)-on-insulator (SiGeOI) structure; (vi) a germanium-on-insulator (GeOI) structure; or (vii) a combination thereof.Furthermore, substrate 106 can be doped according to the design requirements (for example, with a p-type or an n-type substrate). In some versions, substrate 106 can be doped with p-type dopants (for example, boron, indium, aluminum, or gallium) or n-type dopants (for example, phosphorus or arsenic).

[0022] The FETs 102A-102B can have fin structures 108A-108B, passivation layers 109A-109B, epitaxial fin regions 110A-110B, gate structures 112A-112B (also referred to as gate all-around structures (GAA structures) 112A-112B), internal spacers 113A-113B or external spacers 114A-114B.

[0023] As in Fig. As shown in Figures 1B-1D, the fin structure 108A can have a fin base section 119A and a stack of first semiconductor layers 120 arranged on the fin base section 119A, and the fin structure 108B can have a fin base section 119B and a stack of second semiconductor layers 122. In some embodiments, the fin base sections 119A-119B can contain a material similar to the substrate 106. The fin base sections 119A-119B can be formed by photolithographic patterning and etching of the substrate 106. The first and second semiconductor layers 120 and 122 can contain semiconductor materials that are different from each other. In some embodiments, the first and second semiconductor layers 120 and 122 can contain semiconductor materials with different oxidation rates and / or etch selectivities.In some embodiments, the first and second semiconductor layers 120 and 122 may contain semiconductor materials similar to or different from the substrate 106. The first and second semiconductor layers 120 and 122 may contain: (i) an elemental semiconductor such as silicon or germanium; (ii) a composite semiconductor containing a III-V semiconductor material; (iii) an alloy semiconductor containing SiGe, germanium stannum, or silicon germanium stannum; or (iv) a combination thereof.

[0024] In some embodiments, the first and second semiconductor layers 120 and 122 may contain SiGe with Ge in a range of about 25 atomic percent to about 50 atomic percent, each remaining atomic percent being Si, or they may contain Si without a substantial amount of Ge (for example, no Ge). The semiconductor materials of the first and / or the second semiconductor layer 120 and 122 may be undoped or may be in-situ doped during their epitaxial growth process using (i) p-type dopants, such as boron, indium, or gallium; and / or (ii) n-type dopants, such as phosphorus or arsenic.In some embodiments, the first semiconductor layers 120 may contain Si, SiAs, silicon phosphide (SiP), SiC or silicon carbon phosphide (SiCP) for the n-type FET 102A, or may contain SiGe, silicon germanium boron (SiGeB), germanium boron (GeB), silicon germanium stannumbore (SiGeSnB), or may contain a III-V semiconductor compound for the p-type FET 102A, and the second semiconductor layers 122 may contain SiGe, SiGeB, GeB, SiGeSnB or a III-V semiconductor compound for the p-type FET 102A or Si, SiAs, SiP, SiC or SiCP for the n-type FET 102B, if the semiconductor device 100 is a complementary metal-oxide semiconductor (CMOS) device. In some embodiments, both the first semiconductor layers 120 and the second semiconductor layers 122 may contain Si, SiAs, SiP, SiC or SiCP for n-type FETs 102A-102B or SiGe, SiGeB, GeB, SiGeSnB or a III-V semiconductor compound for p-type FETs 102A-102B.

[0025] Each of the first semiconductor layers 120 can (i) nanostructured regions 120A around which epitaxial fin regions 110A and underlying inner and outer spacers 113A-114A are arranged ( Fig. 1A and Fig. 1D), and (ii) nanostructured core regions 121A around which nanostructured mantle regions 121B are arranged ( Fig. 1B and Fig. 1D). Nanostructured core regions 121A and nanostructured mantle regions 121B can form nanostructured core-mantle channel regions 121 between S / D regions 126A of the FET 102A. A gate structure 112A can surround each of the nanostructured core-mantle channel regions 121 ( Fig. 1B and Fig. 1D).

[0026] Similarly, each of the second semiconductor layers 122 (i) can have nanostructured regions 122A around which epitaxial fin regions 110B and underlying inner and outer spacers 113B-114B are arranged ( Fig. 1A and Fig. 1C), and (ii) nanostructured core regions 123A around which nanostructured mantle regions 123B are arranged ( Fig. 1B and Fig. 1C). Nanostructured core regions 123A and nanostructured mantle regions 123B can form nanostructured core-mantle channel regions 123 between S / D regions 126B of the FET 102A. A gate structure 112B can surround each of the nanostructured core-mantle channel regions 123 ( Fig. 1B and Fig. 1C).

[0027] Nanostructured core regions 121A and 123A can be located beneath respective gate structures 112A-112B and can be modified by nanostructured regions 120B and 122B (in Fig. 1A-1D not shown; in Fig. 18B and Fig. (21B shown) of the first and second semiconductor layers 120 and 122, respectively. The material composition of the nanostructured core regions 121A and 123A can be similar to the material composition of the first and second semiconductor layers 120 and 122, respectively.

[0028] Nanostructured mantle regions 121B and 123B can be located beneath respective gate structures 112A-112B and can be formed epitaxially on respective nanostructured core regions 121A and 123B. In some embodiments, nanostructured cladding regions 121B may contain Si, SiAs, silicon phosphide (SiP), SiC or silicon carbon phosphide (SiCP) for the n-type FET 102A, or may contain Ge, SiGe, silicon germanium boron (SiGeB), germanium boron (GeB), silicon germanium stannumbore (SiGeSnB), or may contain a III-V semiconductor compound for the p-type FET 102A, and nanostructured cladding regions 123B may contain Ge, SiGe, SiGeB, GeB, SiGeSnB or a III-V semiconductor compound for the p-type FET 102A or Si, SiAs, SiP, SiC or SiCP for the n-type FET 102B, if the semiconductor device 100 is a complementary metal-oxide semiconductor (CMOS) device.In some embodiments, both nanostructured cladding regions 121B and 123B may contain Si, SiAs, SiP, SiC, or SiCP for n-type FETs 102A-102B, or Ge, SiGe, SiGeB, GeB, SiGeSnB, or a III-V semiconductor compound for p-type FETs 102A-102B. In some embodiments, the semiconductor materials of the nanostructured cladding regions 121B and / or 123B may be undoped or may be in-situ doped during their epitaxial growth process using (i) p-type dopants, such as boron, indium, or gallium; and / or (ii) n-type dopants, such as phosphorus or arsenic.

[0029] The material and structural composition of the nanostructured shell regions 121B and 123B can differ from the material composition of the nanostructured core regions 121A and 123A, respectively. In some embodiments, the nanostructured shell regions 121B and 123B can contain semiconductor materials with lattice constants that differ from those of the semiconductor materials in the nanostructured core regions 121A and 123A, respectively. The lattice mismatch between the semiconductor materials of the nanostructured core regions 121A and 123A, or between the nanostructured shell regions 121B and 123B, can be configured to increase the charge carrier mobility in the nanostructured core-shell channel regions 121 and 123, respectively.

[0030] In some embodiments, nanostructured cladding regions 121B and 123B of n-type FETs 102A and / or 102B may contain semiconductor materials with lattice constants larger than the lattice constants of the semiconductor materials of the nanostructured core regions 121A and 123A, respectively, in order to induce tensile strains in the resulting nanostructured core-cladding channel regions 121 and 123, respectively, which may increase the electron mobility in the nanostructured core-cladding channel regions 121 and 123. In some embodiments, nanostructured cladding regions 121B and 123B of p-type FETs 102A and / or 102B can contain semiconductor materials with lattice constants that are smaller than the lattice constants of the semiconductor materials of the nanostructured core regions 121A and 123A, respectively, in order to create nanostructured core-cladding channel regions 121A and 123A, respectively.123 to induce compressive stresses that can increase hole mobility in the nanostructured core-mantle channel regions 121 and 123.

[0031] The nanostructured mantle regions 121B and 123B can be configured to align the crystal orientation of their surface planes, thereby increasing the surface mobility of charge carriers in the resulting nanostructured core-mantle channel regions 121 and 123, respectively, leading to improved FET device performance. In this way, higher surface mobility of charge carriers can be achieved in channel regions with nanostructured mantle regions 121B and 123B than in channel regions of FET devices formed without such nanostructured mantle regions 121B and 123B.For example, in some embodiments the hole mobility in surface planes of semiconductor materials with (111)-crystal orientation can be higher, and the nanostructured mantle regions 121B and 123B can be epitaxially grown to have surface planes with (111)-crystal orientation, thereby forming the surface planes of nanostructured core-mantle channel regions 121 and 123, respectively.

[0032] In Fig. Although rectangular cross-sections of the nanostructured core regions 121A and 123A are shown in Figure 1B, these regions can also have cross-sections with other geometric shapes (for example, circular, elliptical, or polygonal). Furthermore, diamond-shaped (also referred to as diamond-shaped) cross-sections of the nanostructured mantle regions 121B and 123B are also shown in Figure 1B. Fig. Figure 1B shows that the nanostructured shell regions 121B and 123B can also have cross-sections with other geometric shapes (for example, rectangular, circular, elliptical, or polygonal). In some embodiments, nanostructured core regions 121A and 123A can have cross-sections that are similar to or differ from the cross-sections of the nanostructured shell regions 121B and 123B, respectively.

[0033] As in the Fig. As can be seen in 1B-1D, the nanostructured core-mantle channel regions 121 and 123 can have respective vertical dimensions H1 and H2 (e.g., thickness or diameter) along a Z-axis in the range of approximately 5 nm to approximately 30 nm and respective horizontal dimensions W1 and W2 (e.g., width or diameter) along a Y-axis in the range of approximately 5 nm to approximately 50 nm. The ratios of H1 / W1 and H2 / W2 can each be in the range of approximately 0.2 to approximately 5. The thickness of the nanostructured mantle regions 121B and 123B surrounding the respective nanostructured core regions 121A and 123A can be in the range of approximately 0.5 nm to approximately 5 nm. In some embodiments, the distance between adjacent nanostructured core-mantle channel regions 121 and 123 can depend on the thickness of the gate dielectric layers 128A-128B and can be in the range of about 5 nm to about 20 nm.Furthermore, the nanostructured core-mantle channel regions 121 and 123 can each have horizontal dimensions L1 (. Fig. 1D) and L2 ( Fig. 1C) along an X-axis in the range of approximately 10 nm to approximately 100 nm. The ratios of L1 / H1 and L2 / H2 can be in the range of approximately 2 to approximately 20. In some embodiments, the dimensions H1 and H2, W1 and W2, and L1 and L2 can be equal or different from each other. In some embodiments, the ratios of H1 / W1 and H2 / W2, as well as L1 / H1 and L2 / H2, can be equal or different from each other. In some embodiments, the vertical dimensions H1 and H2 of the nanostructured core-sheath channel regions 121 and 123 can be at least as large as the vertical dimensions H3 and H4 (for example, thickness or diameter) along a Z-axis of the nanostructured regions 120A and 122A, respectively. In some embodiments, the horizontal dimensions L1 and L2 of the nanostructured core-mantle channel regions 121 and 123 can be at most as large as the gate lengths GL1 and GL2 of the gate structures 112A-112B, respectively.

[0034] As in the Fig. As can be seen in 1A-1B, passivation layers 109A-109B can be deposited on the sidewalls of the nanostructured regions 120A and 122A, or on the sidewalls of the fin base sections 119A-119B. Passivation layers 109A can be deposited on nanostructured regions 120A, as shown in Fig. Figure 1D shows that passivation layers 109B are not deposited on nanostructured regions 122A, as shown in Figure 1. Fig. Figure 1C shows that sections of the passivation layers 109B are removed during the formation of the FET 102B, as described below. Passivation layers 109A-109B can improve the surface quality of these passivation-covered surfaces of the fin structures 108A-108B by reducing or eliminating vacancies on these surfaces induced by incomplete bonds. These vacancies can trap charge carriers and reduce the drive currents of the FETs 102A-102B during their operation. Reducing or eliminating these vacancies can increase the drive currents of the FETs 102A-102B by approximately 20% to approximately 50% compared to FETs without passivation layers, such as passivation layers 109A-109B.

[0035] In some embodiments, the passivation layers 109A-109B can be a nitride, oxide, fluoride, chloride, and / or sulfide film. In some embodiments, the passivation layers 109A-109B can contain fluorine, chlorine, nitrogen, oxygen, hydrogen, deuterium, and / or sulfur atoms that can bond with the incomplete bonds to reduce or eliminate the vacancies on the aforementioned surfaces of the fin structures 108A-108B. Passivation layers 109A-109B can be substantially conformally deposited on these surfaces of the fin structures 108A-108B and can have a thickness in the range of approximately 0.5 nm to approximately 5 nm.

[0036] As in the Fig. As can be seen in 1A and 1C-1D, the epitaxial fin regions 110A can be grown around nanostructured regions 120A that are not located under inner or outer spacers 113A-114A. Similarly, the epitaxial fin regions 110B can be grown around nanostructured regions 122A that are not located under inner or outer spacers 113B-114B. In some embodiments, as in the Fig. As shown in Figures 1E-1G, the epitaxial fin regions 110B-110A can be grown on fin-based sections 119B-119A instead of around nanostructured regions 122A and 120A, respectively. The epitaxial fin regions 110A-110B can contain epitaxially grown semiconductor materials that are similar to or different from each other. In some embodiments, the epitaxially grown semiconductor material can be the same material as, or different from, the material of the substrate 106. The epitaxial fin regions 110A-110B can each have a thickness along the sidewalls of the respective nanostructured regions 120A and 122A in the range of about 3 nm to about 6 nm. Although triangular cross-sections of the epitaxial fin regions 110A-110B are shown in the figures, Fig. As shown in Figures 1C-1D, the epitaxial fin regions 110A-110B can also have cross-sections with other geometric shapes (for example, rectangular shape, semicircular shape or polygonal shape).

[0037] The epitaxial fin regions 110A-110B can be p-type for p-FETs 102A-102B or n-type for n-FETs 102A-102B. In some embodiments, the epitaxial fin regions 110A-110B can have opposite doping types relative to each other if the semiconductor device 100 is a CMOS device. The p-type epitaxial fin regions 110A-110B can contain SiGe, SiGeB, GeB, SiGeSnB, a III-V semiconductor compound, or a combination thereof, and can have a dopant concentration in the range of approximately 1 x 10⁻⁶. 20 atoms / cm² 3 up to about 1x10 21 atoms / cm² 3In some embodiments, each of the p-type epitaxial fin regions 110A-110B can have several subregions (not shown) that may contain SiGe and that may differ, for example, in doping concentration, epitaxial growth process conditions, and / or the relative concentration of Ge with respect to Si. Each of the subregions may have similar or different thicknesses, ranging from about 0.5 nm to about 5 nm. In some embodiments, the atomic percentage of Ge in a first subregion may be smaller than the atomic percentage of Ge in a second subregion.In some embodiments, the first subregion may contain Ge in a range of about 15 atomic percent to about 35 atomic percent, while the second subregion may contain Ge in a range of about 25 atomic percent to about 50 atomic percent, with the remaining atomic percent in the subregions being Si.

[0038] The multiple subregions of the p-type epitaxial fin regions 110A-110B can, according to some embodiments, have varying p-dotande concentrations relative to one another. For example, the first subregion can be undoped or can have a lower dotande concentration (for example, a dotande concentration of less than approximately 8 x 10⁻⁶). 20 atoms / cm² 3 ) exhibit a higher dopant concentration (for example, a dopant concentration in the range of approximately 1x10 20 up to about 3x10 22 atoms / cm² 3 ) of the second subregion.

[0039] In some embodiments, the epitaxial fin regions 110A-110B of the n type can have several subregions of the n type (not shown). The first subregions of the n type can consist of materials with SiAs, SiC, or SiCP, and a dopant concentration in the range of approximately 1 x 10 20 atoms / cm² 3 up to about 1x10 21 atoms / cm² 3 and have a thickness in the range of approximately 1 nm to approximately 3 nm. Second n-type subregions deposited on the first n-type subregions can contain materials with SiP and a dopant concentration in the range of approximately 1 x 10 20 atoms / cm² 3 up to about 1x10 22 atoms / cm² 3 Third subregions of n-type deposited on the second subregions of n-type may exhibit materials with similar material compositions and thicknesses to the first subregions of n-type.

[0040] The epitaxial fin regions 110A-110B, together with their underlying nanostructured regions 120A and 122A, can form the source / drain (S / D) regions 126A-126B. The nanostructured core-mantle channel regions 121 and 123 can each be inserted between a pair of S / D regions 126A-126B, as shown in the Fig. 1C-1D shown.

[0041] The gate structures 112A-112B can be multilayer structures and can be placed around nanostructured core-clad channel regions 121 and 123, respectively, for which the gate structures 112A-112B can be referred to as gate all-around structures (GAA structures) or horizontal gate all-around structures (HGAA structures), and the FETs 102A-102B can be referred to as GAA-FETs 102A-102B. The distance 111 between the gate structures 112A-112B is not drawn to scale, and the gate structures 112A-112B can be separated by any distance. In some embodiments, the FETs 102A-102B can have a common gate structure that wraps around the nanostructured core-jacket channel regions 121 and 123, similar to the gate structures 112A-112B.

[0042] The gate structures 112A-112B can have gate dielectric layers 128A-128B, gate exit metal layers 130A-130B, or gate metal filler layers 132A-132B. As shown in Fig. As shown in Figure 1B, the gate dielectric layer 128A can be placed around each of the nanostructured core-sheath channel regions 121, thus electrically isolating the nanostructured core-sheath channel regions 121 from each other and from the conductive gate exit work metal layer 130A and the gate metal filler layer 132A to prevent short circuits between the gate structure 112A and the S / D regions 126A during operation of the FET 102A. Similarly, the gate dielectric layer 128B can be placed around each of the nanostructured core-mantle channel regions 123 and electrically isolate the nanostructured core-mantle channel regions 123 from each other and from the conductive gate exit metal layer 130B and the gate metal filler layer 132B to prevent short circuits between the gate structure 112B and the S / D regions 126 during operation of the FET 102B. Although Fig. Figure 1B shows that the distances between adjacent nanostructured core-mantle channel regions 121 and 123 are wide enough to allow the gate dielectric layers 128A-128B and the gate exit working layers 130A-130B to be placed around each of the nanostructured core-mantle channel regions 121 and 123, respectively. These distances can also be wider to allow the gate metal filler layers 132A-132B to be placed around each of the nanostructured core-mantle channel regions 121 and 123, respectively.

[0043] Each of the gate dielectric layers 128A-128B can have a thickness in the range of approximately 1 nm to approximately 5 nm and can contain: (i) a layer of silicon oxide, silicon nitride and / or silicon oxynitride, (ii) a high k-value dielectric material, such as hafnium oxide (HfO2), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O3), hafnium silicate (HfSiO4), zirconium oxide (ZrO2), zirconium silicate (ZrSiO2), (iii) a high k-value dielectric material comprising oxides of lithium (Li), beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), scandium (Sc), yttrium (Y), zirconium (Zr), aluminum (Al), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd). contains samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb) or lutetium (Lu), or (iv) a combination thereof.

[0044] The gate exit work metal layers 130A-130B can contain a single metal layer or a stack of metal layers. The stack of metal layers can contain metals with the same or different exit work values. In some configurations, each of the gate exit work metal layers 130A-130B can contain aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), silver (Ag), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), tantalum carbon nitride (TaCN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tungsten nitride (WN), metal alloys, and / or combinations thereof. In some embodiments, each gate exit working layer can contain 130 Al-doped metal, such as Al-doped Ti, Al-doped TiN, Al-doped Ta or Al-doped TaN.In some embodiments, each gate exit working layer 130 can have a thickness in the range of about 2 nm to about 15 nm.

[0045] In some embodiments, gate barrier layers (not shown) can be deposited between gate dielectric layers 128A-128B and gate exit metal layers 130A-130B. Gate barrier layers can serve as nucleation layers for the subsequent formation of gate exit metal layers 130A-130B and / or can help to prevent significant diffusion of metals (e.g., Al) from the gate exit metal layers 130A-130B into underlying layers (e.g., gate dielectric layers 128A-128B). Gate barrier layers can contain titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or other suitable diffusion barrier materials. In some embodiments, gate barrier layers can consist of substantially fluorine-free metal or metal-containing films.The essentially fluorine-free metal or fluorine-free metal-containing film may contain fluorine impurities of less than 5 atomic percent in the form of ions, atoms, and / or molecules. In some embodiments, gate barrier layers can have a thickness ranging from approximately 1 nm to approximately 10 nm.

[0046] Each of the gate metal filler layers 132A-132B can contain a single metal layer or a stack of metal layers. The stack of metal layers can contain different metals. In some configurations, each of the gate metal filler layers 132A-132B can contain a suitable conductive material, such as titanium (Ti), silver (Ag), aluminum (Al), titanium aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), zirconium (Zr), ruthenium (Ru), molybdenum (Mo), tungsten nitride (WN), copper (Cu), tungsten (W), cobalt (Co), nickel (Ni), titanium carbide (TiC), titanium aluminum carbide (TiAlC), tantalum aluminum carbide (TaAlC), metal alloys, and / or combinations thereof.Although the gate structures 112A-112B are shown to be similar, the FETs 102A-102B may have gate structures with different materials and / or electrical properties (for example, threshold voltage, output power). Furthermore, although the gate structures 112A-112B are shown to have GAA structures, other gate structures (for example, vertical GAA structures or gate structures without GAA structures) also fall within the scope and nature of this disclosure.

[0047] As in the Fig. As shown in Figures 1C-1D, each of the inner spacers 113A can be positioned between a subregion 110As of the epitaxial regions 110A and a subregion 112As of the gate structure 112A, and each of the inner spacers 113B can be positioned between a subregion 110Bs of the epitaxial regions 110B and a subregion 112Bs of the gate structure 112B. Each of the inner spacers 113A-113B can prevent capacitive coupling between the subregions 110As and 112As, respectively, and between the subregions 110Bs and 112Bs. Preventing capacitive coupling between these subregions can reduce parasitic capacitance between the S / D regions 126A-126B and the gate structures 112A-112B and improve the performance of the FET devices 102A-102B.

[0048] In some versions, the inner spacers 113A-113B may contain a low-k dielectric material with a dielectric constant of less than approximately 3.9 and / or between approximately 1 and approximately 3.5. In some versions, the low-k dielectric material may contain silicon, oxygen, carbon, and / or nitrogen. The concentrations of silicon, oxygen, carbon, and nitrogen in the low-k dielectric material for inner spacers 113A-113B may depend on the desired dielectric constant of the inner spacers 113A-113B. Varying the concentrations of silicon, oxygen, carbon, and nitrogen in the low-k dielectric material may change the desired dielectric constant.The dielectric material with low k-value can contain silicon oxycarbonitride (SiOCN), silicon carbonitride (SiCN), silicon oxide carbide (SiOC), polymides, carbon-doped oxides, fluorine-doped oxides, hydrogen-doped oxides or a combination thereof.

[0049] In some embodiments, the inner spacers 113A-113B may contain a low-k dielectric gas with a dielectric constant of less than about 3.9 and / or between about 0.5 and about 3.5. The low-k dielectric gas may be air, nitrogen, helium, argon, hydrogen, or other suitable dielectric gases. In some embodiments, the inner spacers 113A-113B may be in the form of air gaps between subregions 110As and 112As or between subregions 110Bs and 112Bs. In some embodiments, the inner spacers 113A-113B may be made of similar or different materials. In some embodiments, both FETs 102A-102B may have internal spacers, such as the internal spacers 113A-113B, or one of the FETs 102A-102B may have internal spacers, such as the internal spacers 113A or 113B.Although rectangular cross-sections of the inner spacers 113A-113B in the . Fig. As shown in Figures 1C-1D, the inner spacers 113A-113B can also have cross-sections with other geometric shapes (for example, semicircular, triangular, or polygonal). In some embodiments, each of the inner spacers 113A-113B can have a horizontal dimension (for example, thickness) along an X-axis in the range of approximately 3 nm to approximately 15 nm.

[0050] The outer spacers 114A-114B can, according to some embodiments, be deposited on the sidewalls of the respective gate structures 112A-112B and be in physical contact with the respective gate dielectric layers 128A-128B. The outer spacers 114A-114B can contain an insulating material, such as silicon oxide, silicon nitride, silicon carbon nitride (SiCN), silicon oxycarbonitride (SiOCN), a low-k material, or a combination thereof. The outer spacers 114A-114B can contain a low-k material with a dielectric constant of less than about 3.9 and / or between about 1 and about 3.5. In some embodiments, each of the outer spacers 114A-114B can have a thickness in the range of about 2 nm to about 10 nm.In some versions, the horizontal distance between the outer spacers 114A along an X-axis is greater than the horizontal distance between the inner spacers 113A along an X-axis. Similarly, the horizontal distance between the outer spacers 114B along an X-axis is greater than the horizontal distance between the inner spacers 113B along an X-axis.

[0051] The FETs 102A-102B can be incorporated into an integrated circuit by using other structural components, such as gate contact structures, S / D contact structures, conductive vias, lines, interconnect metal layers, etc., which are not shown here for the sake of clarity.

[0052] As in the Fig. As shown in Figures 1A-1D, the semiconductor device 100 can further comprise an etch stop layer (ESL) 116, an interlayer dielectric layer (ILD) 118, and shallow trench isolation (STI) regions 138. The ESL 116 can be deposited on the sidewalls of the outer spacers 114A-114B and on epitaxial regions 110A-110B. The ESL 116 can be configured to protect gate structures 112A-112B and / or S / D regions 126A-126B. This protection can be generated, for example, during the formation of the ILD layer 118 and / or S / D contact structures (not shown). In some versions, the ESL 116 may contain, for example, silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), silicon carbide (SiC), silicon carbonitride (SiCN), boron nitride (BN), silicon boron nitride (SiBN), silicon carbon boron nitride (SiCBN) or a combination thereof.In some embodiments, the ESL 116 can have a thickness of approximately 3 nm to approximately 30 nm.

[0053] The ILD layer 118 can be deposited on the ESL 116 and can contain a dielectric material deposited by a deposition process suitable for flowable dielectric materials (for example, flowable silicon oxide, flowable silicon nitride, flowable silicon oxynitride, flowable silicon carbide, or flowable silicon oxycarbide). In some embodiments, the dielectric material is silicon oxide. In some embodiments, the ILD layer 118 can have a thickness in the range of about 50 nm to about 200 nm.

[0054] The STI regions 138 can be configured to provide electrical insulation between the FETs 102A-102B and adjacent FETs (not shown) on the substrate 106 and / or adjacent active and passive elements (not shown) that are integrated into or deposited on the substrate 106. In some embodiments, the STI regions 138 can contain multiple layers, such as a nitride and / or oxide layer 138A and an insulating layer 138B deposited on the nitride and / or oxide layers 138A. In some embodiments, the nitride and / or oxide layers 138A can prevent oxidation of the sidewalls of the upper fin sections 108A2-108B2 during the formation of the STI regions 138. In some versions, the insulating layer 138B may contain silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a dielectric material with a low k-value and / or other suitable insulating materials.In some embodiments, STI regions 138 can have a vertical dimension along a Z-axis in the range of about 40 nm to about 200 nm.

[0055] The cross-sectional shapes of the semiconductor device 100 and its elements (for example, fin structures 108A-108B, gate structures 112A-112B, epitaxial fin regions 110A-110B, inner spacers 113-113B, outer spacers 114A-114B and / or STI regions 138) serve for illustration purposes and are not intended as a limitation.

[0056] Fig. Figures 2A-2D illustrate cross-sectional views of FETs 102A-102B along line BB. Fig. 1A for other configurations of the nanostructured core-mantle channel regions 121 and 123 than in the Fig. 1B are shown. In some embodiments, the semiconductor device 100 can be used instead of the one shown. Fig. 1B shown FETs 102A-102B which are in the Fig. The FETs 102A-102B shown in Figures 2A-2B each have nanostructured core-clad channel regions 121-123 in both FETs 102A-102B. In some embodiments, the semiconductor device 100 can be used instead of the one shown in Figures 2A-2B. Fig. 1B shown FETs 102A-102B which are in Fig. 2C shows FETs 102A-102B, wherein FET 102A has nanostructured core-mantle channel regions 121 and FET 102B has channel regions in which a stack of nanostructured regions 120B and 122B are deposited in an alternating configuration. Instead of the Fig. The FETs 102A-102B shown in 1B can alternatively be used in the semiconductor device 100 shown in the Fig. The 2D FETs 102A-102B are shown, wherein FET 102B has nanostructured core-clad channel regions 123 and FET 102A has channel regions in which a stack of nanostructured regions 120B and 122B are deposited in an alternating configuration. The material composition of the nanostructured regions 120B and 122B can be similar to the material composition of the first and second semiconductor layers 120 and 122, respectively.

[0057] Fig. Figure 3 is a flowchart of an exemplary process 300 for manufacturing the semiconductor device 100 according to some embodiments. For illustrative purposes, the figures in Figure 3 are not shown. Fig. 300 illustrated operations with reference to the exemplary manufacturing process for producing the semiconductor device 300, as described in the Fig. 4A-23A, 4B-23B, 9C-23C and 9D-23D illustrated and described. Fig. Figures 4A-23A are isometric views of the semiconductor device 100 at various stages of its manufacture. Fig. 4B-23B, 9C-23C and 9D-23D are each cross-sectional views along lines BB, CC and DD of the structures of the Fig. 4A-23A according to some embodiments. Depending on the specific applications, the operations may be performed in a different order or need not be performed at all. It should be noted that the method 300 does not need to provide a complete semiconductor device 100. Accordingly, it is understood that additional processes may be performed before, during, and after the method 300, and that some other processes may only be briefly described in this text. Elements in the Fig. 4A-23A, 4B-23B, 9C-23C and 9D-23D with the same annotations as the elements in the Fig. 1A-1D are described above.

[0058] In Operation 305, fin structures are formed on a substrate. For example, fin structures 108A*-108B* (in the Fig. 5A-5B) with fin base sections 119A-119B and stacks of first and second semiconductor layers 120 and 122 deposited in alternating configurations on the substrate 106, as shown in relation to Fig. 4A-5B described. In the subsequent processing, the fin structures 108A*-108B* can be separated from the respective fin structures 108A*-108B* after the removal of the second and first semiconductor layers 122 and 120, respectively. Fig. 1A-1D). The process for forming fin structures 108A*-108B* can involve the formation of a stacked layer 108* on the substrate 106, as shown in the Fig. Figures 4A-4B show the stacked layer 108*. The stacked layer can contain first and second semiconductor layers 120* and 122*, which are stacked in an alternating configuration. The first and second semiconductor layers 120* and 122* can have respective vertical dimensions H1 and H2 along a Z-axis in the range of approximately 5 nm to approximately 30 nm.

[0059] Each of the first and second semiconductor layers 120* and 122* can be epitaxially grown on its underlying layer and can contain different semiconductor materials. In some embodiments, the first and second semiconductor layers 120* and 122* can contain semiconductor materials with different oxidation rates and / or etch selectivities. In some embodiments, the first and second semiconductor layers 120* and 122* can contain semiconductor materials that are similar to or different from the substrate 106. The first and second semiconductor layers 120* and 122* can contain: (i) an elemental semiconductor such as silicon or germanium; (ii) a composite semiconductor containing a III-V semiconductor material; (iii) an alloy semiconductor containing SiGe, germanium stannum, or silicon germanium stannum; or (iv) a combination thereof.In some embodiments, first semiconductor layers can contain 120* Si, and second semiconductor layers can contain 122* SiGe. In some embodiments, the first and second semiconductor layers can contain 120* and 122* SiGe with Ge in a range of about 25 atomic percent to about 50 atomic percent, each remaining atomic percent being Si, or they can contain Si without a substantial amount of Ge (for example, no Ge).

[0060] The first and / or second semiconductor layers 120* and 122* can be undoped or can be in situ doped during their epitaxial growth process using (i) p-type dopants, such as boron, indium, or gallium; and / or (ii) n-type dopants, such as phosphorus or arsenic. For p-type in-situ doping, p-type doping precursors such as diborane (B₂H₆), boron trifluoride (BF₃), and / or other p-type doping precursors can be used. For n-type in-situ doping, n-type doping precursors such as phosphine (PH₃), arsine (AsH₃), and / or other n-type doping precursors can be used.

[0061] The process for forming fin structures 108A*-108B* can further involve etching the structure of Fig. 4A comprise structured hard mask layers (not shown) stacked on layer 108* of Fig. 4A are formed. In some versions, hard mask layers may contain layers of silicon oxide, formed, for example, by a thermal oxidation process, and / or may contain layers of silicon nitride, formed, for example, by low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced galvanic vapor deposition (PECVD). Etching the structure of Fig. 4A can include a dry etching process, a wet etching process, or a combination thereof.

[0062] The dry etching process can involve the use of etchants containing an oxygen-containing gas, a fluorine-containing gas (for example, CF4, SF6, CH2F2, CHF3, and / or C2F6), a chlorine-containing gas (for example, Cl2, CHCl3, CCl4, and / or BCl3), a bromine-containing gas (for example, HBr and / or CHBR3), ammonia gas (NH3), an iodine-containing gas, other suitable etching gases, and / or plasmas, or combinations thereof. The dry etching process can be carried out at a high bias voltage in the range of approximately 150 V to approximately 350 V, at a high-frequency power in the range of approximately 10 W to approximately 50 W, at a pressure of approximately 5 Torr to approximately 50 Torr, at a temperature in the range of approximately 25°C to approximately 40°C, and for a duration in the range of approximately 10 s to approximately 40 s.

[0063] The wet etching process can include etching in dilute hydrofluoric acid (DHF), potassium hydroxide solution (KOH solution), ammonia (NH3), a solution containing hydrofluoric acid (HF), nitric acid (HNO3) and / or acetic acid (CH3COOH), or combinations thereof.

[0064] After etching the stacked layer 108*, fin structures 108A*-108B* with fin base sections 119A-119B, each with vertical dimensions along a Z-axis in the range of approximately 40 nm to approximately 60 nm, can be formed, as shown in the Fig. Figures 5A-5B show stacks of first and second semiconductor layers 120 and 122 formed on fin-based sections 119A-119B. These stacks can have respective vertical dimensions H3 and H4 along a Z-axis in the range of about 5 nm to about 30 nm and respective horizontal dimensions W3 and W4 along a Y-axis in the range of about 5 nm to about 50 nm. The ratios of H1 / W1 and H2 / W2 can each be in the range of about 0.2 to about 5. In some embodiments, the dimensions H3-H4 and W3-W4 can be equal or different. In some embodiments, the ratios of H1 / W1 and H2 / W2 can be equal or different.

[0065] As in Fig. As can be seen in section 3, passivation layers are formed on the fin structures in operation 310. For example, passivation layers 109A-109B can be formed on the fin structures 108A*-108B*, as shown in the Fig. 6A-6B described. The process for forming passivation layers 109A-109B on the fin structures 108A*-108B* can be the area-wide deposition of a passivation layer 109 on the structure of Fig. 5A, using one or more precursor gases containing fluorine, chlorine, nitrogen, oxygen, hydrogen, deuterium, NH3, and / or hydrogen sulfide (H2S), in an ALD or CVD process. The one or more precursor gases can have a flow rate of approximately 10 sccm to approximately 1500 sccm during the full-area deposition process. The full-area deposition process can be carried out at a pressure of approximately 10 Torr to approximately 20 atmospheres, at a temperature in the range of approximately 100°C to approximately 300°C, and for a period of approximately 10 s to approximately 120 min. The sections of the full-area deposition of passivation layer 109 on the fin structures 108A*-108B* can each be referred to as passivation layers 109A-109B.

[0066] As in Fig. As shown in Figure 3, 315 STI regions are formed on the passivation layers during operation. For example, STI regions 138 can be formed on passivation layers 109A-109B, as shown in the Fig. 7A-7B described. The formation of STI regions 138 may include: (i) deposition of a layer of nitride material (not shown) on the structure of Fig. 6A, (ii) Deposition of a layer of oxide material (not shown) on the layer of nitride material, (iii) Deposition of a layer of insulating material (not shown) on the layer of oxide material, (iv) Annealing of the insulating material layer, (v) Chemical-mechanical polishing (CMP) of the nitride and oxide material layers and the annealed insulating material layer, and (vi) Back-etching of the polished structure to form STI regions 138 of Fig. 7A.

[0067] The layers of nitride and oxide materials can be deposited using a suitable oxide and nitride deposition process, such as ALD or CVD. In some embodiments, the insulating layer may contain silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), or a dielectric material with a low k-value. In some embodiments, the insulating layer can be deposited using a CVD process, a high-density plasma (HDP) CVD process, using silane (SiH4) and oxygen (O2) as reaction precursors. In some embodiments, the insulating layer can be formed using a subatmospheric CVD process (SACVD) or a high aspect ratio process (HARP), where the process gases may contain tetraethoxysilane (TEOS) and / or ozone (O3).

[0068] In some embodiments, the insulating layer can be formed by depositing flowable silicon oxide using a flowable continuous vapor deposition (FCVD) process. The FCVD process can be followed by a wet annealing process. The wet annealing process can involve annealing the deposited insulating layer in steam at a temperature in the range of approximately 200 °C to approximately 700 °C for a period of approximately 30 min to approximately 120 min. The wet annealing process can be followed by a chemical process material removal (CMP) process to remove sections of the nitride, oxide, and insulating material layers in order to essentially coplanarize the top surfaces of the nitride, oxide, and insulating material layers with the top surfaces of the fin structures 108A*-108B*. The CMP process can be followed by an etching process to re-etch the nitride, oxide, and insulating material layers to remove STI regions 138. Fig. 7A to form.

[0069] The re-etching of layers of nitride, oxide, and insulating materials can be carried out by a dry etching process, a wet etching process, or a combination thereof. In some embodiments, the dry etching process may involve the use of plasma dry etching with a gas mixture containing octafluorocyclobutane (C4F8), argon (Ar), oxygen (O2), and helium (He), fluoroform (CHF3) and He, carbon tetrafluoride (CF4), difluoromethane (CH2F2), chlorine (Cl2) and O2, hydrogen bromide (HBr), O2, and He, or a combination thereof, at a pressure in the range of about 1 mTorr to about 5 mTorr. In some embodiments, the wet etching process may involve treatment with dilute hydrofluoric acid (DHF), an ammonium peroxide mixture (APM), a sulfur peroxide mixture (SPM), hot deionized water (DI water), or a combination thereof.In some embodiments, the wet etching process may involve the use of ammonia (NH3) and hydrofluoric acid (HF) as etchants and of inert gases such as argon (Ar), xenon (Xe), helium (He), or a combination thereof. In some embodiments, the flow rate of HF and NH3 used in the wet etching process may each be in the range of approximately 10 sccm to approximately 100 sccm. In some embodiments, the etching process may be carried out at a pressure in the range of approximately 5 mTorr to approximately 100 mTorr and at a high temperature in the range of approximately 50°C to approximately 120°C.

[0070] As in Fig. As shown in Figure 3, in operation 320 protective oxide layers are formed on the passivation layers, and polysilicon structures are formed on the protective oxide layers and the STI regions. For example, protective oxide layers 740A-740B can be formed on respective passivation layers 109A-109B, and polysilicon structures 112A*-112B* can be formed on respective protective oxide layers 740A-740B and the STI regions 138, as shown in the Fig. 7A-7B described.

[0071] The process for forming protective oxide layers 740A-740B can involve the area-wide deposition of a layer of oxide material (not shown) on the structure of Fig. The process comprises 6A, followed by a high-temperature annealing process and an etching process. The oxide layer may contain silicon dioxide and can be deposited over the entire surface using a suitable deposition process, such as CVD, ALD, plasma-enhanced ALD (PEALD), physical vapor deposition (PVD), or electron beam evaporation. In some embodiments, the oxide layer can be deposited over the entire surface using PEALD at an energy level in the range of approximately 400 W to approximately 500 W and at a temperature in the range of approximately 300 °C to approximately 500 °C. The deposit of the oxide layer can be followed by a dry annealing process under oxygen gas flow at a temperature in the range of approximately 800 °C to approximately 1050 °C. The concentration of the oxygen precursor can be in the range of approximately 0.5% to approximately 5% of the total gas flow rate.In some embodiments, the tempering process can be a flash process, with a tempering time ranging from approximately 0.5 s to approximately 5 s. The etching process for forming the protective oxide layers 740A-740B need not necessarily follow the tempering process and can also be performed during the formation of the polysilicon structures 112A*-112B*, as described below, or as a separate etching process after the formation of the polysilicon structures 112A*-112B*.

[0072] The annealing of the oxide material layer deposited across the entire surface for the oxide protective layers 740A-740B can be followed by the formation of polysilicon structures 112A*-112B*, as shown in the Fig. Figures 7A-7B are shown. During subsequent processing, the polysilicon structures 112A*-112B* can be replaced in a gate replacement process to form the respective gate structures 112A-112B. In some embodiments, the process for forming the polysilicon structures 112A*-112B* can include the full-surface deposition of a layer of polysilicon material on the annealed layer of oxide material for protective oxide layers 740A-740B and the etching of the full-surface deposition of polysilicon material by structured hard mask layers 742A-742B formed on the polysilicon material layer. In some embodiments, the polysilicon material can be undoped, and the hard mask layers 742A-742B can have an oxide layer and / or a nitride layer. The oxide layer can be formed using a thermal oxidation process, and the nitride layer can be formed by LPCVD or PECVD.Hard mask layers 742A-742B can protect the polysilicon structures 112A*-112B* from subsequent processing steps (for example, during the formation of inner spacers 113A-113, outer spacers 114A-114B, epitaxial fin regions 110A-110B, the ILD layer 118 and / or the ESL 116).

[0073] The full-surface deposition of the polysilicon layer can involve CVD, PVD, ALD, or other suitable deposition processes. In some embodiments, the etching of the full-surface polysilicon layer can involve a dry etching process, a wet etching process, or a combination thereof. In some embodiments, the etching of the full-surface polysilicon layer can involve four etching steps. The first polysilicon etching step can involve the use of a gas mixture containing hydrogen bromide (HBr), oxygen (O₂), fluoroform (CHF₃), and chlorine (Cl₂). The second polysilicon etching step can involve the use of a gas mixture containing HBr, O₂, Cl₂, and nitrogen (N₂) at a pressure of approximately 45 mTorr to approximately 60 mTorr.The third polysilicon etching step may involve the use of a gas mixture containing HBr, O₂, Cl₂, N₂, and argon (Ar) at a pressure of approximately 45 mTorr to approximately 60 mTorr. The fourth polysilicon etching step may also involve the use of a gas mixture containing HBr, O₂, Cl₂, and N₂ at a pressure of approximately 45 mTorr to approximately 60 mTorr. Along with the polysilicon material, the fourth polysilicon etching step, according to some embodiments, may remove portions of the tempered, full-surface deposited layer of oxide material for the protective oxide layers 740A-740B that are not covered by the polysilicon structures 112A*-112B*. The first polysilicon etching step may have a higher polysilicon etch rate than the second, third, and / or fourth polysilicon etching steps.The first polysilicon etching step can be used to etch unwanted sections of the fully deposited polysilicon layer over the fin structures 108A*-108B*. The second, third, and fourth polysilicon etching steps can be used to etch unwanted sections of the fully deposited polysilicon layer within the high aspect ratio spaces 743.

[0074] In some embodiments, the vertical dimensions of the polysilicon structures 112A*-112B* along a Z-axis on the top surfaces of the fin structures 108A*-108B* can be in a range of about 40 nm to about 60 nm. The polysilicon structures 112A*-112B* can have an aspect ratio of at least about 9, where the aspect ratio is the ratio of a vertical dimension along a Z-axis to a horizontal dimension along a Y-axis of the polysilicon structures 112A*-112B*. In some embodiments, the horizontal dimensions between the centerlines of adjacent polysilicon structures 112A*-112B* along a Y-axis (for example, the spacing) can be in a range of about 30 nm to about 70 nm.

[0075] After the formation of the polysilicon structures 112A*-112B*, the sections of the deposited oxide layer that are not covered by the polysilicon structures 112A*-112B* can be removed by a dry or wet etching process if they were not removed during the fourth polysilicon etching step to preserve the structure of the Fig. to form 7A-7B. The structure of the Fig. 7A-7B features polysilicon structures 112A*-112B* and protective oxide layers 740A-740B, which are placed on stacks of nanostructured regions 120B and 122B respectively ( Fig. 7B) are deposited, and exhibits stacks of nanostructured regions 120A and 122A ( Fig. 7A), extending from both sides of the polysilicon structures 112A*-112B* along an X-axis.

[0076] In some embodiments, the protective oxide layers 740A-740B can have vertical dimensions (for example, a thickness on the top surfaces of the fin structures 108A*-108B*) along a Z-axis and horizontal dimensions (for example, a thickness on the side walls of the fin structures 108A*-108B*) along a Y-axis in the range of about 1 nm to about 3 nm. In some embodiments, the vertical dimensions can be at least as large as the horizontal dimensions. The presence of protective oxide layers 740A-740B allows the etching of polysilicon material from spaces 743 with a high aspect ratio (for example, an aspect ratio greater than 1:15, 1:18, or 1:20) without substantially etching and / or damaging the fin structures 108A*-108B* during the formation of polysilicon structures 112A*-112B*.

[0077] As in Fig. As shown in Figure 3, in Operation 325, external spacers are formed on the sidewalls of the polysilicon structures and on passivation layers. For example, external spacers 114A-114B can be formed on the sidewalls of the polysilicon structures 112A*-112B* and on sections of the passivation layers 109A-109B that are not covered by polysilicon structures 112A*-112B*, as shown in the Fig. 8A-8B described. The process for forming outer spacers 114A-114B can be the area-wide deposition of a layer of an insulating material (for example, an oxide or nitride material) on the structure of Fig. 7A by a CVD, PVD or ALD process, followed by photolithography and an etching process (for example, reactive ion etching or another dry etching process using a chlorine- or fluorine-based etchant).

[0078] As in Fig. As shown in Figure 3, in Operation 330, internal spacers and epitaxial fin regions are formed on the fin structures. For example, internal spacers 113A-113B and epitaxial fin regions 110A-110B can be formed on sections of the fin structures 108A*-108B* (for example, the nanostructured regions 120A and 122B, respectively) that are not located beneath the respective polysilicon structures 112A*-112B*, as shown in the Fig. 9A-13D described. The ones in the Fig. The processing steps illustrated in Figures 9A-13D describe the sequential formation of internal spacers 113A-113B and the sequential formation of epitaxial regions 110A-110B for FETs 102A-102B with different conductivities. For example, FET 102A may be n-type, and FET 102B may be p-type. Before the formation of the internal spacers 113A and the epitaxial regions 110A of FET 102A, FET 102A may be protected by structuring a photoresist layer 946 onto FET 102B, as shown in the figures. Fig. 9B-9C shown. The photoresist layer 946 is in the Fig. 9A-12A not shown for the sake of clarity.

[0079] The process for forming the inner spacers 113A of the FET 102A can involve etching sections of the outer spacers 114A from the stack of nanostructured regions 120A and 122A, which extend from both sides of the polysilicon structure 112A* along an X-axis. The etching process can be a dry etching process using etching gases such as CH4, O2, and CH3F. The flow rate ratio of CH4:O2:CH3F can range from approximately 1:1:1 to approximately 1:2:4. The etching process can be carried out at a high bias voltage in the range of approximately 300 V to approximately 450 V.

[0080] The process for forming inner spacers 113A can further include etching the nanostructured regions 122A from the stack of nanostructured regions 120A and 122A after etching the outer spacers 114A. In some embodiments, the nanostructured regions 120A and 122A can contain Si without a substantial amount of Ge or SiGe, respectively (for example, no Ge or SiGe), and the etching of the nanostructured regions 122A can involve the use of a dry etching process that exhibits a higher etch selectivity for SiGe than for Si. For example, halogen-based chemicals can have an etch selectivity that is higher for Ge than for Si. Therefore, halogen gases can etch SiGe faster than Si. In some embodiments, the halogen-based chemicals can include fluorine-based and / or chlorine-based gases.Alternatively, the etching of the nanostructured regions 122A can involve the use of a wet etching process with a higher selectivity for SiGe than for Si. For example, the wet etching process can involve the use of a mixture of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2) (SPM) and / or a mixture of ammonia hydroxide (NH4OH) with H2O2 and deionized (DI) water (APM).

[0081] As a result of etching the nanostructured regions 122A, suspended nanostructured regions 120A with openings 1048 between them can be formed, as shown in the Fig. 10A and Fig. Figure 10D shows that etching the nanostructured regions 122A can generate a linear etch profile 122Bs1 or a curved etch profile 122Bs2 (shown with a curved dashed line) of the sidewalls of the nanostructured regions 122B lying beneath the polysilicon structure 112A*, as shown in Fig. 10D shown. The etching process can be controlled such that the openings 1048 extend along an X-axis at least below the outer spacers 114A and the sidewalls of the nanostructured regions 122B are substantially aligned with the interfaces 114As between the outer spacers 114A and the polysilicon structure 112A*, as shown in Fig. Figure 10D shows that in some embodiments, openings 1048 can further extend along an X-axis beneath the polysilicon structure 112A* such that the sidewalls of the nanostructured regions 122B are located approximately 1 nm to approximately 10 nm away from the interface 114A. Extending openings 1048 beneath the outer spacers 114A or the polysilicon structure 112A* can prevent portions of the nanostructured regions 122B from remaining beneath the outer spacers 114A, or can prevent the formation of the gate structure 112A beneath the outer spacers 114A during the replacement of the nanostructured regions 122B and the polysilicon structure 112A* by the gate structure 112A in subsequent processing (for example, in operation 340).

[0082] The process for forming internal spacers 113A can further enable the area-wide deposition of a layer of dielectric material with a low k-value (not shown) on the structure of Fig. The entire area of ​​the openings 1048 may be filled or partially filled with the layer of low-k dielectric material. The full-area deposition process may employ an ALD process or a CVD process. In some embodiments, the full-area deposition process may comprise multiple cycles of deposition and etching processes. In each cycle, the etching process may follow the deposition process to prevent the formation of vacancies within the layer of low-k dielectric material deposited in the openings 1048 by removing seams that might arise during the filling of the layer of low-k dielectric material within the openings 1048. The etching process in each cycle of the full-area deposition may comprise a dry etching process using a gas mixture of HF and NF3.The HF to NF3 gas ratio can range from approximately 1 to approximately 20. In some formulations, the low-k dielectric material may contain silicon, oxygen, carbon, and / or nitrogen. The low-k dielectric material may include silicon oxycarbonitride (SiOCN), silicon carbonitride (SiCN), silicon oxide carbide (SiOC), polymides, carbon-doped oxides, fluorine-doped oxides, hydrogen-doped oxides, or a combination thereof.

[0083] The process for forming internal spacers 113A can further include etching the area-covering deposited layer of low k-value dielectric material to back-etch the layer of low k-value dielectric material within the openings 1048 to form internal spacers 113A and to remove other sections of the layer of low k-value material from surfaces of the FET 102A, as shown in the Fig. 11A and Fig. Figure 11D shows that the etching of the area-covering layer of low-k dielectric material can involve a dry etching process using a gas mixture of HF and NF3. The HF to NF3 gas ratio can range from about 1 to about 20. In some embodiments, the etching can be performed in two steps. In the first step, the HF to NF3 gas ratio can range from about 1 to about 10. The first step can remove sections of the low-k material layer from surfaces of FET 102A and partially re-etch the low-k material layer within the opening 1048. In the second step, the HF to NF3 gas ratio can be higher than in the first step, ranging from about 5 to about 20. The second step can preserve the structure of the inner spacers 113A, as shown in Figure 11D. Fig. Figure 11D shows that in some embodiments, the interfaces 113As between the inner spacers 113A and the nanostructured regions 122B follow the etch profile of the sidewalls of the nanostructured regions 122B. For example, the interfaces 113As can have a linear profile, as shown in Figure 11D. Fig. 11D shows when the sidewalls of the nanostructured regions 122B have a linear etch profile 122Bs1 ( Fig. 10D), or the interface 113As may have a curved profile (not shown) if the sidewalls of the nanostructured regions 122B have a curved etch profile 122Bs2 ( Fig. 10D and Fig. 11D).

[0084] As in the Fig. As can be seen in Figures 12A-12D, epitaxial fin regions 110A can be grown around the suspended nanostructured regions 120A after the inner spacers 113A have been formed. In some embodiments, the epitaxial fin regions 110A can be grown by: (i) CVD, such as low-pressure CVD (LPCVD), atomic layer CVD (ALCVD), ultra-high vacuum CVD (UHVCVD), reduced-pressure CVD (RPCVD), or any other suitable CVD; (ii) molecular beam epitaxy (MBE); (iii) any other suitable epitaxy process; or (iv) a combination thereof. In some embodiments, the epitaxial fin regions 110A can be grown by an epitaxial deposition / partial etching process, wherein the epitaxial deposition / partial etching process is repeated at least once.In some embodiments, the epitaxial fin regions 110A can be p-type if the nanostructured regions 120A contain SiGe, or they can be n-type if the nanostructured regions 120A contain Si without a significant amount of Ge (for example, no Ge). p-type epitaxial fin regions 110A can contain SiGe and can be in-situ doped during the epitaxial growth process using p-type dopants such as boron, indium, or gallium. For in-situ p-type doping, p-type doping precursors such as diborane (B₂H₆), boron trifluoride (BF₃), and / or other p-type doping precursors can be used. Epitaxial fin regions 110A of the n-type can contain Si without a significant amount of Ge (for example, no Ge) and can be in-situ doped with n-type dopants, such as phosphorus or arsenic, during the epitaxial growth process.For in-situ n-type doping, n-type doping precursors such as phosphine (PH3), arsine (AsH3) and / or other n-type doping precursors can be used.

[0085] In some embodiments, instead of forming epitaxial fin regions 110A around the suspended nanostructured regions 120A, as in the Fig. 12A and Fig. Figure 12D shows epitaxial fin regions 110A being grown on the fin base section 119A, as shown in the Fig. 1E and Fig. 1G shown. The epitaxial fin regions 110A, as for example in Fig. As shown in Figure 1G, suspended nanostructured regions 120A can be grown on the fin base section 119A after the internal spacers 113A have been removed. The process for etching the suspended nanostructured regions 120A can involve a dry etching process using etching gases such as CH4, O2, and CH3F. The flow rate ratio of CH4:O2:CH3F can range from approximately 1:1:1 to approximately 1:2:4. The etching process can be carried out at a high bias voltage in the range of approximately 300 V to approximately 450 V. Alternatively, the etching of the suspended nanostructured regions 120A can involve the use of a wet etching process with higher selectivity for Si than for SiGe. For example, the wet etching process can involve the use of a mixture of (NH4OH) and HCl.

[0086] After the formation of the internal spacers 113A and the epitaxial regions 110A of the FET 102A, the photoresist layer 946 can be removed from the FET 102B, and another photoresist layer 1346 can be structured on the FET 102A (see Fig. 13B and Fig. 13D), to protect the FET 102A during the subsequent processing steps for forming inner spacers 113B and epitaxial regions 110B of the FET 102B, as described in the Fig. 13A-15D described. The photoresist layer 1346 is in the Fig. 13A-15A not shown for the sake of clarity.

[0087] As in the Fig. As shown in Figures 13A-13D, the process for forming the inner spacers 113B can include etching sections of the outer spacers 114B from the stack of nanostructured regions 120A and 122A extending from both sides of the polysilicon structure 112B* along an X-axis, followed by etching the nanostructured regions 120A from the stack of nanostructured regions 120A and 122A. The process for etching the sections of the outer spacers 114B can involve a dry etching process using etching gases such as CH4, O2, and CH3F. The flow rate ratio of CH4:O2:CH3F can range from approximately 1:1:1 to approximately 1:2:4. The etching process can be carried out at a high pre-voltage in the range of approximately 300 V to approximately 450 V. Etching of the nanostructured regions 120A can involve the use of a wet etching process with higher selectivity for Si than for SiGe.For example, the wet etching process can involve the use of a mixture (NH4OH) with HCl.

[0088] As a result of etching the nanostructured regions 120A, suspended nanostructured regions 122A with openings 1348 between them can be formed, as shown in the Fig. 13A and Fig. 13C shown. Furthermore, etching the nanostructured regions 120A can produce a linear etch profile 120Bs1 or an essentially triangular etch profile 120Bs2 (shown with a dashed line) of the sidewalls of the nanostructured regions 120B lying beneath the polysilicon structure 112B*, as shown in Fig. 13C shown. The etching profiles 120Bs2 ( Fig. 13C) and 122BS2 ( Fig. 10D) can differ due to the different crystal structure and / or crystal orientation of the various materials of the nanostructured regions 120B and 122B. For example, nanostructured regions 120B with Si material can have the etch profile 120Bs2, and nanostructured regions 122B with SiGe can have the etch profile 122Bs2.

[0089] The process for etching nanostructured regions 120A can be controlled such that the openings 1348 extend along an X-axis at least below the outer spacers 114B and the sidewalls of the nanostructured regions 120B are substantially aligned with the interface 114Bs between the outer spacers 114B and the polysilicon structure 112B*, as shown in Fig. Figure 13C shows that in some embodiments, openings 1348 can further extend along an X-axis beneath the polysilicon structure 112B* such that the sidewalls of the nanostructured regions 120B are located approximately 1 nm to approximately 10 nm away from the interfaces 114Bs. Extending openings 1348 beneath the outer spacers 114A or the polysilicon structure 112B* can prevent portions of the nanostructured regions 120B from remaining beneath the outer spacers 114B, or can prevent the formation of the gate structure 112B beneath the outer spacers 114B during the replacement of the nanostructured regions 120B and the polysilicon structure 112B* by the gate structure 112B in subsequent processing (for example, in operation 340).

[0090] The process for forming internal spacers 113B can further enable the area-wide deposition of a layer of dielectric material with a low k-value (not shown) on the structure of Fig. 13A encompass until the openings 1348 are filled or partially filled with the layer of low k-value dielectric material. The area deposition process can be similar to that used to deposit the layer of low k-value dielectric material within the openings 1048 to form the inner spacer 113A.

[0091] The process for forming internal spacers 113B can further include etching the area-covering deposited layer of low k-value dielectric material to back-etch the low k-value dielectric material layer within the openings 1348 to form internal spacers 113A and to remove other sections of the low k-value material layer from surfaces of the FET 102B, as shown in the Fig. 14A and Fig. Figure 14C shows that the etching of the area-covering layer of low-k dielectric material can involve a dry etching process using a gas mixture of HF and NF3. The HF to NF3 gas ratio can range from about 1 to about 20. In some embodiments, the etching can be performed in two steps. In the first step, the HF to NF3 gas ratio can range from about 1 to about 10. The first step can remove sections of the low-k material layer from surfaces of FET 102B and partially re-etch the low-k material layer within the aperture 1348. In the second step, the HF to NF3 gas ratio can be higher than in the first step, ranging from about 5 to about 20. The second step can preserve the structure of the inner spacers 113B, as shown in Figure 14C. Fig. Figure 14C shows that in some embodiments, the interfaces 113Bs between the inner spacers 113B and the nanostructured regions 120B follow the etch profile of the sidewalls of the nanostructured regions 120B. For example, the interfaces 113Bs can have a linear profile, as shown in Figure 14C. Fig. 14C shown when the sidewalls of the nanostructured regions 122B have a linear etch profile 122Bs1 ( Fig. 10D), or the interfaces 113Bs can have a triangular profile (not shown) if the sidewalls of the nanostructured regions 122B have a triangular etch profile 122Bs2 ( Fig. 13C and Fig. 14C).

[0092] As in the Fig. As can be seen in 15A-15D, epitaxial fin regions 110B can be grown around the suspended nanostructured regions 122A after the inner spacers 113B have been formed. The epitaxial fin regions 110B can be grown similarly to the epitaxial fin regions 110A, which are shown in relation to the Fig. The epitaxial fin regions 110B, as described in Figures 12A-12D, can be grown. In some embodiments, the epitaxial fin regions 110B can be of the p-type if the nanostructured regions 122A contain SiGe, or they can be of the n-type if the nanostructured regions 122A contain Si without a significant amount of Ge (for example, no Ge). After the formation of the inner spacers 113B and the epitaxial regions 110B, the photoresist layer 1346 can be removed from the FET 102A, as described in Figures 12A-12D. Fig. 15B and Fig. 15D shown.

[0093] Similar to the epitaxial fin regions 110A, in some embodiments, instead of forming epitaxial fin regions 110B around the suspended nanostructured regions 122A, as in the Fig. 15A and Fig. Figure 15D shows epitaxial fin regions 110B being grown on the fin base section 119B, as shown in the Fig. 1E and Fig. 1F shown. The epitaxial fin regions 110B, as for example in Fig. As shown in Figure 1F, the suspended nanostructured regions 122A can be grown on the fin-based section 119B after the internal spacers 113B have been removed. The process of removing the suspended nanostructured regions 122A can involve the use of a dry etching process that exhibits a higher etch selectivity for SiGe than for Si. For example, halogen-based chemicals may have an etch selectivity that is higher for Ge than for Si. Therefore, halogen gases can etch SiGe faster than Si. In some embodiments, the halogen-based chemicals may include fluorine-based and / or chlorine-based gases. Alternatively, the etching of the nanostructured regions 122A can involve the use of a wet etching process with a higher selectivity for SiGe than for Si.For example, the wet etching process may involve the use of a mixture of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2) (SPM) and / or a mixture of ammonia hydroxide (NH4OH) with H2O2 and deionized (DI) water (APM).

[0094] In some embodiments, the process steps for forming the internal spacers 113A-113B can be performed simultaneously without using the photoresist layers 946 and 1346 if both FETs 102A-102B are of the same conductivity type (for example, n-type or p-type). Similarly, the process steps for forming epitaxial fin regions 110A-11B can be performed simultaneously without using the photoresist layers 946 and 1346 after the simultaneous formation of internal spacers 113A-113B if both FETs 102A-102B are of the same conductivity type.

[0095] As in Fig. As shown in Figure 3, nanostructured core-mantle channel regions are formed between the epitaxial fin regions in Operation 335. For example, the nanostructured core-mantle channel regions 121 and 123 can be formed sequentially in regions of the fin structures 108A*-108B*, which lie beneath the polysilicon structures 112A*-112B*, as shown in the Fig. 16A-23D described. Prior to the formation of nanostructured core-mantle channel regions 121 and 123, the ESL 116 can be applied to the structure of Fig. 15A can be deposited, and the ILD 118 can be deposited on the ESL 116.

[0096] In some embodiments, the ESL 116 can be formed from materials containing SiNx, SiOx, SiON, SiC, SiCN, BN, SiBN, SiCBN, or a combination thereof. The formation of the ESL 116 can involve the full-surface deposition of a material layer for the ESL 116 onto the structure of Fig. 15A including the use of PECVD, sub-atmospheric chemical vapor deposition (SACVD), LPCVD, ALD, high-density plasma (HDP), plasma-enhanced atomic layer deposition (PEALD), molecular layer deposition (MLD), plasma impulse chemical vapor deposition (PICVD) or other suitable deposition methods.

[0097] Following the full-surface deposition of the material layer for the ESL 116, a full-surface deposition of a dielectric material layer for the ILD 118 can be performed. In some embodiments, the dielectric material can be silicon oxide. The dielectric material layer can be deposited using a deposition process suitable for flowable dielectric materials (for example, flowable silicon oxide, flowable silicon nitride, flowable silicon oxynitride, flowable silicon carbide, or flowable silicon oxycarbide). Flowable silicon oxide can be deposited, for example, using an FCVD process. The full-surface deposition process can be followed by thermal annealing of the deposited dielectric material layer in steam at a temperature in the range of approximately 200°C to approximately 700°C for a period of approximately 30 minutes to approximately 120 minutes.Thermal annealing can be followed by a CMP process to coplanarize the top surfaces of the ESL 116, the ILD 118, the outer spacers 114A-114B and the polysilicon structures 112A*-112B*, as shown in . Fig. 16A shown. During the CMP process, the hard mask layers 742A-742B can be removed.

[0098] Following the CMP process, nanostructured core regions 121A of the FET 102A can be formed, as shown in the Fig. 17B-18B and 17D-18D. The process for forming nanostructured core regions 121A can comprise the following sequential steps: (i) forming a masking layer 1650 (for example, a photoresist layer or a nitride layer) on the FET 102B, as shown in the Fig. 16A-16C shown, (ii) etching of the polysilicon structure 112A* and the protective oxide layer 740A from the structure of Fig. 16A, (iii) Removal of the nanostructured regions 122B from the structure of Fig. 16A, to the structure of Fig. 17A to form, and (iv) etching the nanostructured regions 120B of the structure of Fig. 17A to form nanostructured core regions 121A, as in the Fig. 18B and Fig. 18D shown. In some embodiments, the polysilicon structure 112A* and the protective oxide layer 740A can be etched using the first, second, third, and / or fourth polysilicon etching step as described in Operation 320. In some embodiments, nanostructured regions 122B can be removed using a wet etching process or a dry etching process similar to that used for the nanostructured regions 122A, which are described with reference to the Fig. The nanostructured regions 122B described in Figures 10A-10D are used. As a result of etching the nanostructured regions 122B, openings 1752 are formed around the nanostructured regions 120B, as described in Figures 10A-10D. Fig. 17B and Fig. Figure 17D shows that the nanostructured regions 120B can be selectively etched using a wet etching process with a higher selectivity for Si than for SiGe to reduce the dimensions of the nanostructured regions 120B along a Z-axis and / or a Y-axis. For example, the wet etching process can involve the use of a mixture of (NH4OH) and HCl. As a result of the wet etching process, nanostructured core regions 121A with rectangular cross-sections can be formed, as shown in Figure 17D. Fig. 18B shown. In some embodiments, the rectangular cross-sections of the nanostructured core regions 121A can be modified to have circular or elliptical cross-sections by applying a thermal tempering process to the structure of Fig. 18A is carried out. The thermal annealing process can include the annealing of nanostructured core regions 121A in hydrogen at a temperature in the range of approximately 600°C to approximately 700°C and at a pressure in the range of approximately 10 Torr to approximately 30 Torr for a period of approximately 50 seconds to approximately 90 seconds. The parameters and etchant for the formation of nanostructured core regions 121A can be controlled such that the fin regions 120A lying beneath the epitaxial fin regions 110A are not removed.

[0099] Following the wet etching process to form nanostructured core regions 121A with rectangular cross-sections ( Fig. 18B) or the thermal annealing process for forming nanostructured core regions 121A with circular or elliptical cross-sections (not shown) can form nanostructured mantle regions 123A on nanostructured core regions 121A with rectangular cross-sections, as in the Fig. 19B and Fig. 19D shown, or epitaxially grown on nanostructured core regions 121A with circular or elliptical cross-sections (not shown) to form nanostructured core-mantle channel regions 121 ( Fig. 19B and Fig. 19D). In some embodiments, nanostructured cladding regions 121B can be epitaxially grown by an epitaxial deposition / partial etching process, wherein the epitaxial deposition / partial etching process is repeated at least once. Such a repeated deposition / partial etching process is also referred to as a cyclic deposition-etch (CDE) process. In some embodiments, nanostructured cladding regions 121B can be epitaxially grown by selective epitaxial growth (SEG), wherein an etching gas is added to promote the selective growth of semiconductor material on nanostructured core regions 121A, but not on other surfaces of the structure. Fig. 19A.

[0100] In some embodiments, the epitaxial growth can result in nanostructured mantle regions 121B with rhomboid cross-sections, as in Fig. 19B shown, and are formed with surface planes exhibiting a (111)-crystal orientation. In some embodiments, the rhomboid cross-sections of the nanostructured mantle regions 121B can be modified to have circular or elliptical cross-sections by modifying the structure of Fig. 19A is subjected to a thermal annealing process. The thermal annealing process can include annealing nanostructured shell regions 121B in hydrogen at a temperature in the range of approximately 600°C to approximately 700°C and at a pressure in the range of approximately 10 Torr to approximately 30 Torr for a period of approximately 50 seconds to approximately 90 seconds.

[0101] After the formation of nanostructured core-mantle channel regions 121, nanostructured core-mantle channel regions 123 of the FET 102B can be formed, as shown in the Fig. 21A-22D shown. The process for forming nanostructured core-mantle channel regions 123 can comprise the following successive steps: (i) removal of the masking layer 1650, (ii) formation of a masking layer 1850 (for example, a photoresist layer or a nitride layer) within the opening 1752 (in the Fig. 17B and Fig. (shown in 17D), to protect the nanostructured core-mantle channel regions 121, as shown in the Fig. 20B and Fig. 20D shown, (iii) etching of the polysilicon structure 112B* and the protective oxide layer 740B, (iv) removal of the nanostructured regions 120B from the structure of Fig. 19A for forming the structure of Fig. 20A, (v) Etching of nanostructured regions 122B of the structure of Fig. 20A for forming nanostructured core regions 123A, as in the Fig. 21B-21C shown, and (vi) epitaxial growth of nanostructured mantle regions 123B on nanostructured core regions 123A, as shown in the Fig. 22B-22C shown.

[0102] Similar to the etching of the polysilicon structure 112A* and the protective oxide layer 740A, the polysilicon structure 112B* and the protective oxide layer 740B can be etched using the first, second, third, and / or fourth polysilicon etching steps described in Operation 320. In some embodiments, nanostructured regions 120B can be etched using a wet etching process similar to that used for the nanostructured regions 120A described in relation to the Fig. 13A-13D. As a result of etching the nanostructured regions 120B, openings 1852 are formed around the nanostructured regions 122B, as described in the Fig. Figures 20B-20C show that the nanostructured regions 122B can be selectively etched using a dry etching process with a higher etch selectivity for SiGe than for Si to reduce the dimensions of the nanostructured regions 122B along a Z-axis and / or a Y-axis. For example, halogen-based chemicals may have an etch selectivity that is higher for Ge than for Si. Therefore, halogen gases can etch SiGe faster than Si. In some embodiments, the halogen-based chemicals may include fluorine-based and / or chlorine-based gases. Alternatively, the selective etching of the nanostructured regions 122B may involve the use of a wet etching process with a higher selectivity for SiGe than for Si. For example, the wet etching process may involve the use of a mixture of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2) (SPM) and / or a mixture of ammonia hydroxide (NH4OH) with H2O2 and deionized (DI) water (APM).The parameters and etchants for the formation of nanostructured core regions 123A can be controlled in such a way that the fin regions 122A lying under the epitaxial fin regions 110B are not removed.

[0103] As a result of the etching process, nanostructure core regions 123A with rectangular cross-sections can be formed, as shown in Fig. 21B shown. In some embodiments, the rectangular cross-sections of the nanostructured core regions 123A can be modified to have circular or elliptical cross-sections by applying a thermal tempering process to the structure of Fig. 21A is carried out. The thermal annealing process can include annealing nanostructured core regions 123A in hydrogen at a temperature in the range of approximately 600°C to approximately 700°C and at a pressure in the range of approximately 10 Torr to approximately 30 Torr for a period of approximately 50 seconds to approximately 90 seconds. Following the etching process to form nanostructured core regions 123A with rectangular cross-sections ( Fig. 18B) or the thermal annealing process for forming nanostructured core regions 123A with circular or elliptical cross-sections (not shown) can form nanostructured mantle regions 123B on nanostructured core regions 123A with rectangular cross-sections, as in the Fig. 22B-22C shown, or epitaxially grown on nanostructured core regions 123A with circular or elliptical cross-sections (not shown) to form nanostructured core-mantle channel regions 123 ( Fig. 22B-22C). In some embodiments, the nanostructured mantle regions 123A can be epitaxially grown using a CDE process or a SEG process, similar to the one used for the epitaxial growth of nanostructured mantle regions 121B.

[0104] In some embodiments, the epitaxial growth can result in nanostructured mantle regions 123B with rhomboid cross-sections, as in Fig. 22B shown, and are formed with surface planes exhibiting a (111)-crystal orientation. In some embodiments, the rhomboid cross-sections of the nanostructured mantle regions 123B can be modified to have circular or elliptical cross-sections by modifying the structure of Fig. 22A is subjected to a thermal annealing process. The thermal annealing process can include annealing nanostructured cladding regions 123B in hydrogen at a temperature in the range of approximately 600°C to approximately 700°C and at a pressure in the range of approximately 10 Torr to approximately 30 Torr for a period of approximately 50 seconds to approximately 90 seconds. After formation of the nanostructured core-cladding channel regions 123 of the FET 102B, the masking layer 1850 can be removed from the opening 1752 to reveal the structure of the Fig. to form 23A-23D.

[0105] As in Fig. As shown in Figure 3, in operation 340 GAA (Gate-All-Around) structures are formed on the nanostructured core-mantle channel regions. For example, the gate structures 112A-112B can be formed such that they wrap around the nanostructured core-mantle channel regions 121 and 123, as shown in the Fig. 23A-23D and 1A-1D are described. The process for forming gate structures 112A-112B can include the following successive steps: (i) over-area deposition of a layer of dielectric material for the gate dielectric layers 128A-128B on the structure of Fig. 23A, (ii) depositing a layer of exit work metal for the gate exit work metal layers 130A-130B over the entire surface of the dielectric material layer, and (iii) depositing a layer of conductive material for the gate metal filler layers 132A-132B over the entire surface of the exit work metal layer until the openings 1752 and 1852 are filled. In some embodiments, as in Fig. As shown in Figure 1B, the layers of dielectric material and exit work metal can each form conformal layers within openings 1752 and 1852 (as shown in the Fig. 23B-23D shown).

[0106] The dielectric material layer for the gate dielectric layers 128A-128B may contain silicon oxide and may be formed by CVD, atomic layer deposition (ALD), physical vapor deposition (PVD), electron beam evaporation, or other suitable processes. In some embodiments, the dielectric material layer may comprise: (i) a layer of silicon oxide, silicon nitride, and / or silicon oxynitride; (ii) a high k-value dielectric material, such as hafnium oxide (HfO₂), TiO₂, HfZrO, Ta₂O₃, HfSiO₄, ZrO₂, or ZrSiO₂; (iii) a high k-value dielectric material comprising oxides of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, or Lu; or (iv) a combination thereof. Dielectric layers with high k-values ​​can be formed by ALD and / or other suitable methods.

[0107] The exit work metal layer for exit work metal layers 130A-130B can contain Al, Cu, W, Ti, Ta, TiN, TaN, NiSi, CoSi, Ag, TaC, TaSiN, TaCN, TiAl, TiAlN, WN, metal alloys, and / or combinations thereof. In some embodiments, the exit work metal layer can contain Al-doped metal, such as Al-doped Ti, Al-doped TiN, Al-doped Ta, or Al-doped TaN. The exit work metal layer can be deposited using a suitable process such as ALD, CVD, PVD, plating, or combinations thereof. The conductive material layer for the gate electrodes 132 can contain Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, WN, Cu, W, Co, Ni, TiC, TiAlC, TaAlC, metal alloys and / or combinations thereof and can be formed by ALD, PVD, CVD or other suitable deposition processes.The deposited layers of dielectric material, exit work metal and conductive material can be planarized by a CMP process to achieve the structure of . Fig. 1A to form. The CMP process can essentially coplanarize the top surfaces of the gate dielectric layers 128A-128B, the gate exit working metal layers 130A-130B, and the gate metal filler layers 132A-132B with the top surface of the ILD layer 118, as shown in the Fig. Shown 1A-1D.

[0108] The formation of the gate structures 112A-112B can be followed by the formation of other elements such as S / D contacts, gate contacts, vias, interconnect metal layers, dielectric layers, passivation layers, etc., which are not shown for the sake of clarity.

[0109] This disclosure provides exemplary structures and methods for improving charge carrier mobility (for example, hole and / or electron mobility) in FET devices (for example, FETs 102A-102B). By increasing the charge carrier mobility, the switching speeds and drive currents of FET devices can be increased, leading to faster and improved performance of the FET devices. The exemplary structures and methods provide channel regions with core-cladding nanostructures (for example, nanostructured core-cladding channel regions 121 and 123) between source / drain regions (S / D regions) (for example, S / D regions 126A-126B) of FET devices.In some embodiments, the core-cladding nanostructures can feature nanostructured core regions (for example, nanostructured core regions 121A and 123A) around which epitaxially grown nanostructured cladding regions (for example, nanostructured cladding regions 121B and 123B) are surrounded. The core-cladding nanostructures can be configured to induce tensile or compressive stresses in the channel regions for n- or p-type FET devices. This tensile or compressive stress can be induced in the channel regions by, for example, doping the nanostructured core or cladding regions or by using lattice-mismatched semiconductor materials for the nanostructured core or cladding regions. Such induced stress in the channel regions can improve the mobility of charge carriers within the channel regions.The core-cladding nanostructures can further be configured to tune the energy bandgap of the channel regions and / or modify the crystal orientation of the surface planes of the channel regions based on the conductivity type of the FET devices, in order to improve the charge carrier mobility in the channel regions. The channel regions with core-cladding nanostructures described here can increase the switching speeds and drive currents of FET devices by, for example, approximately 20% to 40% and approximately 30% to 50%, respectively, compared to FET devices without such core-cladding nanostructures.

[0110] In some embodiments, a semiconductor device comprises a substrate, a stack of nanostructured layers with first and second nanostructured regions arranged on the substrate, and nanostructured cladding regions surrounding the second nanostructured regions. The nanostructured cladding regions and the second nanostructured regions contain semiconductor materials that are distinct from one another. The semiconductor device further comprises first and second source / drain (S / D) regions arranged on the substrate and a gate-all-around (GAA) structure positioned between the first and second S / D regions. Each of the first and second S / D regions has an epitaxial region surrounding each of the first nanostructured regions, and the GAA structure surrounds each of the nanostructured cladding regions.

[0111] In some embodiments, a semiconductor device comprises a first and a second FET. The first FET has a stack of first nanostructured layers arranged on a substrate. Each of the first nanostructured layers has a first and a second nanostructured region. The first FET further comprises first nanostructured cladding regions surrounding the second nanostructured regions. The first nanostructured cladding regions and the second nanostructured regions contain semiconductor materials that are distinct from each other. The first FET also includes a first epitaxial region surrounding each of the first nanostructured regions and a first gate-all-around (GAA) structure arranged on the stack of first nanostructured layers. The GAA structure surrounds each of the first nanostructured cladding regions.The second FET features a stack of second nanostructured layers arranged on the substrate. Each of the second nanostructured layers has third and fourth nanostructured regions. The second FET further features second nanostructured cladding regions surrounding the fourth nanostructured regions. The second nanostructured cladding regions and the fourth nanostructured regions contain different semiconductor materials, and the first and second nanostructured cladding regions contain different material compositions. The second FET also includes a second epitaxial region surrounding each of the third nanostructured regions and a second GAA structure arranged on top of the stack of second nanostructured layers.The second epitaxial region is of a different conductivity type than the first epitaxial region, and the GAA structure is placed around each of the second nanostructured mantle regions.

[0112] In some embodiments, a method for fabricating a semiconductor device comprises: forming a stack of nanostructured layers with first and second nanostructured regions on a substrate; modifying the second nanostructured regions to form nanostructured core regions; epitaxially growing nanostructured sheath regions surrounding the nanostructured core regions; growing first and second epitaxial regions surrounding each of the first nanostructured regions; forming a gate-all-around (GAA) structure between the first and second epitaxial regions surrounding each of the nanostructured sheath regions; and forming first and second inner spacers along the sidewalls of the gate subregions of the GAA structure. The gate subregions are embedded in the stack of nanostructured layers.

[0113]

Claims

[1] comprising a semiconductor device: a substrate (106); a stack of nanostructured layers (120, 122) with first nanostructured regions (120A, 122A) and second nanostructured regions (121A, 123A) on the substrate (106); nanostructured mantle regions (121B, 123B) that are wrapped around the second nanostructured regions (121A, 123A), wherein - the nanostructured mantle regions (121B, 123B) and the second nanostructured regions (121A, 123A) exhibit semiconductor materials that are different from each other, and - the nanostructured mantle regions (121B, 123B) have surface planes with a first crystal orientation and the second nanostructured regions (121A, 123A) have surface planes with a second crystal orientation that is different from the first crystal orientation; a first S / D region (126A, 126B) and a second S / D region (126A, 126B) on the substrate (106), wherein the first S / D region (126A, 126B) and the second S / D region (126A, 126B) each have an epitaxial region (110A, 110B) that is wrapped around each of the first nanostructured regions (120A, 122A); and a GAA structure (112A, 112B) that is positioned between the first S / D region (126A, 126B) and the second S / D region (126A, 126B) and is wrapped around each of the nanostructured mantle regions (121B, 123B). [2] Semiconductor device according to claim 1, wherein the nanostructured cladding regions (121B, 123B) and the second nanostructured regions (121A, 123A) have structural compositions that are different from each other. [3] Semiconductor device according to claim 1 or 2, wherein the nanostructured cladding regions (121B, 123B) and the second nanostructured regions (121A, 123A) have cross-sections that are different from each other. [4] Semiconductor device according to claim 1, wherein the first crystal orientation is a (111) crystal orientation and the second crystal orientation is a (100) crystal orientation. [5] Semiconductor device according to one of the preceding claims, wherein the semiconductor material of the nanostructured cladding regions (121B, 123B) has a lattice mismatch with respect to the semiconductor material of the second nanostructured regions (121A, 121B). [6] Semiconductor device according to one of the preceding claims, further comprising: a first inner spacer (113A, 113B) that is arranged between an epitaxial subregion (110AS, 110BS) of the first S / D region (126A, 126B) and a gate subregion (112As, 112Bs) of the GAA structure (112A, 112B); and a second inner spacer (113A, 113B) that is positioned between an epitaxial subregion (110AS, 110BS) of the second S / D region (126A, 126B) and the gate subregion (112As, 112Bs) of the GAA structure (112A, 112B). [7] Semiconductor device according to one of the preceding claims, further comprising a passivation layer (109A, 109B) arranged on side walls of the first nanostructured regions (120A, 122A). [8] comprising a semiconductor device: a first field-effect transistor (102A), FET, which has the following features: - a stack of first nanostructured layers (120) on a substrate (106), each of the first nanostructured layers (120) having first nanostructured regions (120A) and second nanostructured regions (121A); - first nanostructured sheath regions (121B) that are wrapped around the second nanostructured regions (121A), wherein the first nanostructured sheath regions (121B) and the second nanostructured regions (121A) have semiconductor materials that are different from each other; - a first epitaxial region (110A) that is wrapped around each of the first nanostructured regions (120A); and - a first GAA structure (112A) arranged on the stack of first nanostructured layers (120) and wrapped around each of the first nanostructured mantle regions (121B); and a second FET (102B) which has the following features: - a stack of second nanostructured layers (122) on the substrate (106), wherein - each of the second nanostructured layers (122) comprises third nanostructured regions (122A) and fourth nanostructured regions (123A), and - the second nanostructured layers (122) have a different material composition than the first nanostructured layers (120); - second nanostructured sheath regions (123B) that are wrapped around the fourth nanostructured regions (123A), wherein the second nanostructured sheath regions (123B) and the fourth nanostructured regions (123A) have semiconductor materials that are different from each other, and wherein the first nanostructured sheath regions (121B) and the second nanostructured sheath regions (123B) have material compositions that are different from each other; - a second epitaxial region (110B) wrapped around each of the third nanostructured regions (122A), wherein the second epitaxial region (110B) is of a different conductivity type than the first epitaxial region (110A); and - a second GAA structure (112B) that is arranged on the stack of the second nanostructured layers (123A) and is wrapped around each of the second nanostructured mantle regions (123B). [9] Semiconductor device according to claim 8, wherein the second nanostructured regions (121A) and the fourth nanostructured regions (123A) have material compositions that are different from each other. [10] Semiconductor device according to any one of the preceding claims 8 to 9, wherein the first nanostructured regions (121B) and the second nanostructured cladding regions (123B) have structural compositions that are different from each other. [11] Semiconductor device according to any one of the preceding claims 8 to 10, wherein the first FET (102A) further comprises a first inner spacer (113A) and a second inner spacer (113A) arranged within the stack of first nanostructured layers (120). [12] Semiconductor device according to any one of the preceding claims 8 to 11, wherein the second FET (102B) further comprises a third inner spacer (113b) and a fourth inner spacer (113B) arranged within the stack of second nanostructured layers (122). [13] Method for manufacturing a semiconductor device comprising: Forming a stack of nanostructured layers (120, 122) with first nanostructured regions (120A, 122A) and second nanostructured regions (121A, 123A) on a substrate (106); Modifying the second nanostructured regions (121A, 123A) to form nanostructured core regions (121A, 123A); epitaxial growth of nanostructured mantle regions (121B, 123B) wrapped around the nanostructured core regions (121A, 123A), wherein the nanostructured mantle regions (121B, 123B) have surface planes with a first crystal orientation and the second nanostructured regions (121A, 123A) have surface planes with a second crystal orientation that is different from the first crystal orientation; Growing first epitaxial regions (110A, 110B) and second epitaxial regions (110A, 110B) that are wrapped around each of the first nanostructured regions (120A, 122A); Forming a GAA structure (112A, 112B) between the first epitaxial regions (110A, 110B) and second epitaxial regions (110A, 110B) that are wrapped around each of the nanostructured sheath regions (121B, 123B); and Forming a first inner spacer (113A, 113B) and a second inner spacer (113A, 113B) along side walls of gate subregions (112As, 112Bs) of the GAA structure (112A, 112B), wherein the gate subregions (112As, 112Bs) are embedded in the stack of nanostructured layers (120, 122). [14] Method according to claim 13, wherein the modification of the second nanostructured regions (121A, 123A) comprises selective etching of the second nanostructured regions (121A, 123A) to form the nanostructured core regions (121A, 123A) with vertical dimensions that are smaller than the vertical dimensions of the first nanostructured regions (120A, 122A). [15] Method according to claim 13 or 14, wherein the epitaxial growth of nanostructured shell regions (121B, 123B) wrapped around the nanostructured core regions (121A, 123A) comprises epitaxial growth of a semiconductor material different from the nanostructured core regions (121A, 123A). [16] Method according to any one of the preceding claims 13 to 15, wherein the epitaxial growth of nanostructured shell regions (121B, 123B) comprises epitaxial growth of a semiconductor material with a lattice constant that is different from a lattice constant of a semiconductor material of the nanostructured core regions (121A, 123A). [17] Method according to any one of the preceding claims 13 to 16, wherein forming the stack of nanostructured layers (120, 122) comprises: epitaxial growth of a first semiconductor layer (120) and a second semiconductor layer (122) of different composition in an alternating configuration on the substrate (106); and Etching of the first semiconductor layer (120) and the second semiconductor layer (122) to form a first nanostructured layer (120) and a second nanostructured layer (122). [18] Method according to claim 17, wherein forming the GAA structure (112A, 112B) comprises: Etching of the second nanostructured layers (122) to form openings between adjacent first nanostructured layers (120); Deposition of a layer of a gate dielectric material (128A, 128B) within the openings; and Deposition of a layer of electrically conductive material (132A, 132B) onto the layer of gate dielectric material (128A, 128B) to fill the openings.

Images