Integrated chip with memory cell with magnetic access selection device and method for its manufacture

Abstract

Integrated chip, featuring: an MTJ device (109) with a first electrode (105, 108) and a second electrode (105, 108); and an access selection device (101) for the MTJ device (109) comprising a first metal structure (104) and a second metal structure (102) separated from each other by several non-metallic layers (103); wherein one of the first metal structure (104) and the second metal structure (102) is coupled to the second electrode (105, 108); and the first metal structure (104) has a polarized ferromagnetic layer, wherein the first metal structure (104) is an electrode for the access selection device (101), wherein the access selection device (101) is a bipolar selection switch, wherein the several non-metallic layers (103) have two insulators (103a, 103b) with different band gap energies, wherein one insulator (103b) of the two insulators (103a, 103b) which have different band gap energies is an oxide of a metal of the polarized ferromagnetic layer and is directly adjacent to the polarized ferromagnetic layer.

Description

GENERAL STATE OF THE ART

[0001] Many electronic components contain electronic memory designed for data storage. Electronic memory can be volatile or non-volatile. Volatile electronic memory uses electricity to maintain data, while non-volatile memory is capable of storing data without electricity. Magnetoresistive random-access memory (MRAM) is a type of non-volatile memory that has long been the subject of active interest.

[0002] Prior art relating to the subject matter of the invention can be found, for example, in US 2018 / 0 122 825 A1, US 2018 / 0 240 845 A1, US 2012 / 0 280 339 A1, US 2014 / 0 301136 A1, US 2009 / 0 027 976 A1 and DE 10 2019 127 079 A1.

[0003] The invention provides for an integrated chip according to claim 1, an integrated chip according to claim 8, and a method according to claim 12. Embodiments are specified in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 presents a schematic diagram of a memory circuit with memory cells, comprising a magnetic tunnel junction device (MTJ device) and an access selection device with a polarized magnetic layer, which is configured to substantially reduce a switching time for the MTJ device according to some embodiments of this disclosure. Fig. Figure 2A shows a trace of a magnetic field alignment vector for the free layer of an MTJ device during switching. Fig. Figure 2B shows another trace of a magnetic field alignment vector for the free layer of an MTJ device during switching, which, compared to Fig. Figure 2A shows how an initial tilt angle reduces the number of precession cycles in a switching operation. The Fig. Figures 3A-3D show cross-sectional views of some embodiments of integrated circuits according to this disclosure with memory cells comprising an MTJ device and an access selection device with a polarized magnetic layer designed to substantially reduce the switching time for the MTJ device. Fig. Figure 4 represents a block diagram of a memory circuit comprising a memory array with multiple memory cells, each having an access selection device comprising a bipolar selection switch. Fig. Figure 5 shows a cross-sectional view according to some embodiments of an integrated chip with memory cells, which includes a magnetic tunnel junction (MTJ) device and an access selection device with a polarized magnetic layer designed to substantially reduce the switching time for the MTJ device. The Fig. Enumerations 6-14 describe some embodiments of a method for forming an integrated chip with memory cells comprising a magnetic tunnel junction (MTJ) device and an access selection device with a polarized magnetic layer designed to substantially reduce the switching time for the MTJ device. The Fig. References 15-16 describe some further embodiments of a method for forming an integrated chip with memory cells, comprising a magnetic tunnel junction device (MTJ device) and an access selection device with a polarized magnetic layer designed to substantially reduce the switching time for the MTJ device. Fig. Figure 17 presents a flowchart for some embodiments of a method for forming an integrated chip with memory cells comprising a magnetic tunnel junction (MTJ) device and an access selection device with a polarized magnetic layer designed to substantially reduce the switching time for the MTJ device. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below for the sake of simplicity. For example, the formation of a first feature over or on top of a second feature in the following description may have embodiments in which the first and second features are formed in direct contact, and may also have embodiments in which additional features are formed between the first and second features such that the first and second features cannot be in direct contact. Furthermore, this disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves the purpose of simplification and clarity and does not in itself imply any relationship between the various discussed embodiments and / or configurations.

[0006] Furthermore, spatial terms such as "below," "below," "lower," "above," "upper," and the like, used herein for the sake of simplicity, may be used to describe the relationship of one element or feature to another element(s) or feature(s) as illustrated in the figures. These spatial terms are intended to encompass different orientations of the component during use or operation, in addition to the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatial descriptors used herein may be interpreted accordingly.

[0007] Magnetic tunnel junction devices (MTJ devices) are a type of MRAM device featuring an MTJ vertically arranged between conductive electrodes. The MTJ comprises a fixed layer separated from a free layer by a tunnel barrier layer. The fixed layer is magnetic with a static orientation (i.e., fixed), while the free layer is magnetic with an orientation that can be switched between a configuration parallel to and antiparallel to the fixed layer. The parallel configuration provides a low-ohmic state, digitally storing data as a first data state (e.g., a logic "1"). The antiparallel configuration provides a high-ohmic state, digitally storing data as a second data state (e.g., a logic "0").

[0008] Typically, MTJ devices are arranged in rows and columns within a memory array. A read or write operation is performed on an MTJ device within the memory array by activating word rows and bit rows to provide a voltage and / or current to the selected MTJ device. An access selection device for an MTJ device allows selective current flow through the selected MTJ device in one of two opposite directions. This is because the polarization orientation of the free layer in an MTJ device switches between antiparallel and parallel configurations, providing either a high or low resistive state depending on the direction of the applied current. For example,A current flowing from a lower electrode to an upper electrode can give an MTJ device an anti-parallel configuration, resulting in a high ohmic state, while a current flowing from the upper electrode to the lower electrode can give the MTJ device a parallel configuration, resulting in a low ohmic state.

[0009] One type of access selector device for MTJ devices is a MOSFET transistor. While a MOSFET transistor offers good performance, the relatively high voltage and / or current used during write operations on an MTJ device can cause the MOSFET transistor to be relatively large compared to the MTJ device. The large size of the MOSFET transistor, however, limits how small memory cells within a memory array can be. Another type of access selector device has two unipolar selectors (i.e., devices that each allow current to flow in only one direction during normal operation). A further type of access selector device is a bipolar selector switch. A bipolar selector switch formed by a stack of thin films can be significantly smaller than a MOSFET.

[0010] An integrated chip according to this disclosure comprises a memory cell including a magnetic tunnel junction (MTJ) device and an access selector. The MTJ device includes a free layer and a fixed layer. The access selector comprises a first metallic structure and a second metallic structure separated from each other by one or more non-metallic layers. According to these teachings, the first metallic structure includes a polarized magnetic layer. Like the fixed layer, the polarized magnetic layer has a magnetic orientation that is static or fixed. The magnetic orientation of the polarized magnetic layer is generally different from that of the fixed layer. In some embodiments, the magnetic orientation of the polarized magnetic layer is generally orthogonal to that of the fixed layer.The magnetic field generated by the polarized magnetic layer extends through the free layer, tilting its magnetic orientation away from one direction of current flow and thus significantly reducing the switching time for the MTJ device. In some of these teachings, the access selection device is a bipolar selector switch. In some of these teachings, the polarized magnetic layer is integrated into an electrode of the bipolar selector switch. In some of these teachings, the bipolar selector switch has a dielectric layer formed by oxidizing a section of the polarized magnetic layer. Forming the dielectric layer by oxidizing the polarized magnetic layer results in a simplified process and facilitates the integration of the bipolar selector switch into the MTJ device.In some of these designs, both the access selection device and the MTJ component are formed by a stack of material layers. A memory cell in an integrated chip according to these designs can be efficiently manufactured, compact, and exhibit good write speeds.

[0011] Fig. Figure 1 shows a schematic diagram of a memory cell 100 according to some embodiments of this disclosure, comprising an access selection device 101 and a magnetic tunnel junction (MTJ) device 109. The access selection device 101 has a polarized magnetic layer 104a configured to substantially reduce the switching time for the MTJ device.

[0012] The MTJ component 109 has an MTJ 107 arranged between a first electrode 108 and a second electrode 105. The first electrode 108 is coupled to a word line WL, and the second electrode 105 is coupled to an access selection device 101, which modulates the access (e.g., read access and / or write access) to the MTJ component 109. The access selection device 101 is further coupled to a bit line BL. In some embodiments, the access selection device 101 is arranged between the BL and the MTJ component 109. In some alternative embodiments, the access selection device 101 is arranged between the WL and the MTJ component 109.

[0013] In some embodiments, the MTJ 107 comprises a fixed layer 107c separated from a free layer 107a by a dielectric tunnel barrier layer 107b. The fixed layer 107c has a fixed magnetic polarization, while the free layer 107a has a magnetic polarization that can be changed by a switching operation to be either parallel (i.e., a "P" state) or antiparallel (i.e., an "AP" state) with respect to the magnetic polarization of the fixed layer 107c. The switching operation can operate via the tunnel magnetoresistance (TMR) effect. A relationship between the magnetic polarizations of the fixed layer 107c and the free layer 107a defines an ohmic state of the MTJ 107, thus enabling the MTJ 107 to store a data state.

[0014] In some embodiments, the polarization of the fixed layer 107c is perpendicular (in a first direction 110 or a second direction 112). In some embodiments, the fixed layer 107c comprises cobalt (Co), iron (Fe), boron (B), nickel (Ni), ruthenium (Ru), iridium (Ir), platinum (Pt), or the like. In some embodiments, the dielectric tunnel barrier 107b comprises magnesium oxide (MgO), aluminum oxide (Al₂O₃), or the like. In some embodiments, the free layer 107a comprises cobalt (Co), iron (Fe), boron (B), or the like. In some embodiments, the first electrode 108 and the second electrode 105 comprise one or more of titanium, tantalum, tungsten, titanium nitride, tantalum nitride, or the like.

[0015] The access selection device 101 can be a bipolar selection device comprising a first electrode 104, which is a metal structure, and a second electrode 102, which is another metal structure, separated from the non-metal structure 103. The non-metal structure 103 can be one or more layers of suitable insulators or semiconductors. In some embodiments, the non-metal structure 103 comprises an insulator that is an oxide of a ferromagnetic metal, such as cobalt oxide (CoO₂). X ), a nickel oxide (NiO X ), an iron oxide (FeO X) or the like. In some embodiments, the non-metallic structure 103 has an insulator that is an intrinsic oxide, such as an oxide of hafnium oxide (HfO2), titanium oxide (TiO2), aluminum oxide (Al2O3), or the like. In some embodiments, the non-metallic structure 103 has a layer that is an insulator, and an access selection device 101 is a metal-insulator-metal (MIM) bipolar selector switch. In some embodiments, the non-metallic structure 103 has a first insulator 103a and a second insulator 103b, and the access selection device 101 is a bipolar selector switch (MIIM). In some embodiments, the first insulator 103a has a first bandgap energy, and the second insulator 103b has a second bandgap energy that is different from the first bandgap energy. In some embodiments, the first insulator 103a is titanium oxide (TiO2) or the like.In some of these embodiments, the second insulator 103b is an oxide of a magnetic metal. In some of these embodiments, the oxide of a magnetic metal is a cobalt oxide (CoO). X ), an iron oxide (FeO X ), a nickel oxide (NiO X ) or the like. For example, the oxide of a magnetic metal could be Co3O4.

[0016] In some embodiments, the non-metallic structure 103 includes a semiconductor layer, and an access selector 101 is a bipolar metal-semiconductor (MSM) selector switch. Suitable semiconductors for the access selector 101 may include silicon (Si), germanium (Ge), silicon-germanium (SiGe), oxide semiconductors such as indium gallium zinc oxide (IGZO), Group III-V materials such as indium gallium arsenide (InGaAS), or the like. In some embodiments, the non-metallic structure 103 includes multiple semiconductor layers. In some embodiments, the non-metallic structure 103 includes a mixture of insulator and semiconductor layers. Numerous layers of different materials can facilitate the provision of the desired rectification features for the access selector 101.

[0017] During the operation, the access selection device 101 allows currents driven by comparatively large voltage differences to pass through with relatively low resistance. The current can proceed through the MTJ component 109 either in the first direction 110 (e.g., from the word line WL to the bit line BL) or in the second direction 112, which is opposite to the first direction 110 (e.g., from the bit line BL to the word line WL). Current passing through the MTJ component 109 along the first direction 110 is used to write a first data state (e.g., a logic "0") to the MTJ component 109. Current passing through the MTJ component 109 along the second direction 112 is used to write a second data state (e.g., a logic "1") to the MTJ component 109. The access selection device 101 exhibits a considerably greater resistance to currents driven by smaller voltage differences.Thus, the access selection device 101 reduces leakage currents through the MTJ component 109 when the memory cell 100 is not selected.

[0018] The first electrode 104 and the second electrode 102 of the access selection device 101 can comprise one or more metals, such as titanium (Ti), tantalum (Ta), tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), cobalt (Co), or copper (Cu). According to some aspects of these teachings, one of the first electrode 104 and the second electrode 102 has a polarized magnetic layer. The polarized magnetic layer can be a ferromagnetic layer. A ferromagnetic layer can be cobalt (Co), iron (Fe), nickel (Ni), or the like, or an alloy, such as cobalt-iron-boron (CoFeB), or the like, or a multilayer ferromagnetic structure, such as cobalt-iron / nickel-iron (CoFe / NiFe), or the like.In some embodiments, the polarized magnetic layer has a polarization parallel to a plane of the polarized ferromagnetic layer, which is a polarization orthogonal to both the first direction 110 and the second direction 112. In some embodiments, one of the first electrodes 104 and the second electrode 102 of the access selection device 101 has a polarized ferromagnetic layer and a metal. For example, the first electrode 104 can have the polarized magnetic layer 104a and a non-magnetic layer 104b, which is a metal. In a more specific example, the polarized magnetic layer 104a can be cobalt (Co) or the like, and the non-magnetic layer 104b can be titanium (Ti) or the like.

[0019] The polarized magnetic layer 104a generates a magnetic field 114 that is effective in tilting a magnetic field in the free layer 107a away from one direction of current flow, thereby reducing the write time (switching time) for the MTJ device 109. Fig. 2A and Fig. Section 2B explains these effects. As shown in diagram 200a of the Fig. As shown in Figure 2A, a polarization direction 201a for a magnetic field of the free layer 107a does not move along a direct path when transitioning from a first direction 203a to a second direction 205a, but precesses around an axis 209 to trace a spiral. The axis of this spiral 209 is aligned with the direction of current flow, which can be the first direction 110 or the second direction 112. The time required for precessing is called the incubation period for a writing operation. The incubation period can, for example, range from approximately 5 nanoseconds to approximately 10 nanoseconds. As shown in Fig. As shown in Figure 2B, the number of precessions and consequently the incubation period can be significantly reduced if the starting direction of the polarization is tilted slightly away from the axis.

[0020] In the absence of the polarized magnetic layer 104a, the magnetic field of the free layer 108a is effectively approximately parallel to the axis 209 and initially moves very slowly away from the axis 209 with numerous precessions. The polarized magnetic layer 104a causes the magnetic field of the free layer 107a to be initially tilted, which can greatly shorten the incubation time. In some embodiments, the polarized magnetic layer 104a tilts the magnetic field of the free layer 107a by approximately one degree to approximately five degrees. In some embodiments, the polarized magnetic layer 104a tilts the magnetic field of the free layer 107a sufficiently to reduce the incubation time by half or more. In some embodiments, the tilting reduces the incubation time by a factor of eight or more. A slight tilt may be sufficient to achieve these results.

[0021] The Fig. Figures 3A-3D represent cross-sectional views 300, 320, 340 and 360 of integrated chips according to various embodiments of this disclosure, each comprising a memory cell having an MJT device and an access selection device with a middle structure arranged between two metal structures, the middle structure having a polarized magnetic layer that generates a magnetic field effective to reduce a number of precession cycles traversed by a free layer of the MTJ device during switching.

[0022] Fig. Figure 3A shows a cross-sectional view 300 of an integrated chip with a dielectric structure 304 arranged on a substrate 302. The dielectric layer 304 has several stacked interdielectric layers (ILD layers) and surrounds a first memory cell 305. undA second memory cell 305b is located laterally adjacent to the first memory cell 305a. The first memory cell 305a and the second memory cell 305b each have an access selection device 101 and an MTJ device 109 configured to store a data state. Within each of the first memory cell 305a and the second memory cell 305b, both the access selection device 101 and the MTJ device 109 are formed by a single vertical stack of thin films or layers. The access selection device 101 is a bipolar selector switch comprising a polarized magnetic layer 104a that generates a magnetic field 114a effective at tilting the polarization of the free layer 107a away from the direction of current flow (either the first direction 110 or the second direction 112). This effect can occur regardless of whether the free layer 107a is in the parallel or the anti-parallel configuration.The non-magnetic layer 104b of the first electrode 104 is in contact with the second electrode 105 of the MTJ device 109. These adjacent layers can be formed by a single layer of a material.

[0023] The dielectric structure 304 further surrounds several metal interconnect layers, including adjacent interconnect layer 306a and interconnect layer 306b. The first memory cell 305a and the second memory cell 305b are located between interconnect layers 306a and 306b. Interconnect layers 306a and 306b may include interconnect wires and interconnect vias. The interconnect wires and interconnect vias comprise a conductive material (e.g., copper, aluminum, tungsten, or the like). The interconnect wires and interconnect vias may further include a diffusion barrier layer and / or an adhesion layer surrounding the conductive material.

[0024] Fig. Figure 3B shows a cross-sectional view 320 of an integrated chip according to some other embodiments of this disclosure. In the cross-sectional view 320, a first memory cell 305c and a second memory cell 305d are arranged within the dielectric structure 304. Each has the access selection device 101 and the MTJ device 109. The polarized magnetic layer 104a of the access selection device 101 generates a magnetic field 114b that is effective in tilting the polarization of the free layer 107a away from a direction of current flow, regardless of whether the free layer 107a is in the parallel or anti-parallel configuration. The first memory cell 305c and the second memory cell 305d differ from the first memory cell 305a and the second memory cell 305b of cross-sectional view 300 of the Fig. 32A, in that the MTJ component 109 is arranged above the access selection device 101. In the component shown in cross-sectional view 320, the second electrode 102 of the MTJ component 109 is in contact with the first electrode 108 of the access selection device 101. These electrodes can be formed by a single layer of material. In other words, an upper electrode for one component can provide a lower electrode for the other component.

[0025] As illustrated by a comparison of cross-sectional views 300 and 320, the layers of the access selection device 101 can be formed either on top of the layers of the MTJ device 109 or below the layers of the MTJ device 109. The polarized magnetic layer 104a of the access selection device 101 can be located on the MTJ device 109 on the side of the non-metallic structure 103 or on the opposite side. The free layer 107a of the MTJ device 109 can be located closer to the access selection device 101 than the fixed layer 107c, or further away. Notwithstanding these alternatives, the effectiveness of the polarized magnetic layer 104a in increasing the writing speed may increase if the polarized magnetic layer 104a is located closer to the free layer 107a.

[0026] Fig. Figure 3C shows a cross-sectional view 340 of another integrated chip having laterally arranged memory cells 305e and 305f, each containing the MTJ device 109 and the access selector 101. The access selector 101 can be located laterally from the MTJ device 109 in each of the memory cells 306e and 305f. While the MTJ device 109 is located between the interconnect layers 306a and 306b, the access selector 101 in this embodiment is furthermore located between the interconnect layers 306b and 306c. The access selection device 101 is a bipolar selection device comprising a polarized magnetic layer 104a which generates a magnetic field 114c which is effective in tilting the polarization of the free layer 107a away from the direction of current flow (either the first direction 110 or the second direction 112).

[0027] Fig. Figure 3D shows a cross-sectional view 360 of another integrated chip having laterally arranged memory cells 305g and 305h, each of which has the MTJ device 109 and an access selector 361. The access selector 361 has a first unipolar selector 377 and a second unipolar selector 365. The first unipolar selector 377 and the second unipolar selector 365 are each configured to allow the current to pass through in a single direction during normal operation (e.g., outside of a breakdown). For example, the first unipolar selector 377 is configured to allow the current to pass through the MTJ device 109 in the first direction 110 (e.g.,The second unipolar selector switch 365 is configured to allow current to pass through the MTJ component 109 along a second direction 112, opposite to the first direction 110 (e.g., from bit line BL1 to the second word line WL2). When current passes through the MTJ component 109 along the first direction 110, a first data state (e.g., a logic "0") can be written to the MTJ component 109. When current passes through the MTJ component 109 along the second direction 112, a second data state (e.g., a logic "1") can be written to the MTJ component 109.

[0028] In some embodiments, the first unipolar selector switch 377 and the second unipolar selector switch 365 are diodes (e.g., PN diodes, PiN diodes, Schottky diodes, oxide semiconductor diodes, or the like). In some embodiments, the MTJ device 109 is accessed for read and write operations using applied voltage differentials greater than a threshold value of the diodes. In other embodiments, one or both of the first unipolar selector switch 377 and the second unipolar selector switch 365 are wire-based selectors, power converters, varistor-type selectors, Ovonik threshold switches (OTS), doped chalcogenide-based selectors, Mott effect-based selectors, mixed ionic electronic conductive-based selectors (MIEC selectors), field-supported superliner threshold selectors (FAST selectors), or the like.In some embodiments, the first unipolar selector switch 377 and the second unipolar selector switch 365 are of the same unipolar selector switch type. In other embodiments, the first unipolar selector switch 377 and the second unipolar selector switch 365 are of different unipolar selector switch types. In some embodiments, for example, the first unipolar selector switch 377 can be a diode and the second unipolar selector switch can be a wire-based selector switch.

[0029] An electrode for the first unipolar selector switch 377 has an electrode with a magnetic layer 375 that generates a magnetic field 114d effective in tilting the polarization of the free layer 107a away from the direction of current flow (either the first direction 110 or the second direction 112), thereby shortening an incubation period for writing the MTJ device 109. In other embodiments, the magnetic layer 375 is located elsewhere within the access selector device 361. For example,The magnetic layer 375 can be all or part of a lower electrode 379 of the first unipolar selector switch 377, a crossbar 371, a via 373 connecting the MTJ device 109 to the crossbar 371a, a via connecting the second unipolar selector switch 365 to the crossbar 371, a lower electrode 367 for the second unipolar selector switch 365, or an upper electrode 363 for the second unipolar selector switch 365.

[0030] Fig. Figure 4 shows a block diagram of some embodiments of a memory circuit 400, comprising a memory array with multiple memory cells, each of which has an access selection device with bipolar selection switches.

[0031] The memory circuit 400 comprises a memory array 402 with several memory cells 404. a,1 -404 c,4 The multiple memory cells 404 a,1 -404 c,4are arranged in rows and / or columns within the memory array 402. For example, the first row of memory cells comprises memory cells 404. a,1 -404 c,1 , while a first column of memory cells 404 a,1 -404 a,4 includes the multiple memory cells 404 a,1 -404 c,4 Each MTJ component 109 is coupled to an access selection device 101, which has a polarized magnetic layer 104a that reduces write times for the respective MTJ component 109. The access selection device 101 is configured to selectively control access to an MTJ component 109 within one or more memory cells 404. a,1 -404 c,4 to provide the current to flow through the selected storage cells 404 a,1 -404 c,4 with simultaneous inhibition of leakage currents by unselected cells 404 a,1 -404 c,4 to enable.

[0032] The memory array 402 is coupled to control the circuit via multiple bit rows BL1-BL4 and multiple word rows WL1-WL3. In some embodiments, the control circuit includes a bit row decoder 406 coupled to the multiple bit rows BL1-BL4 and a word row decoder 408 coupled to the multiple word rows WL1-WL3. In some embodiments, the control circuit may further include a read amplifier 410 coupled to the memory array 402 via multiple word rows WL1-WL3. The read amplifier 410 is configured to read data from the multiple memory cells 404. a,1 -404 c,4 to read out.

[0033] To access the MTJ component 109 of a memory cell 404 a,1 -404 c,4 The bit-line decoder 406 is for selectively applying a first voltage to one or more bit lines BL1-BL4 based on a first address S ADDR1designed to receive from a control circuit 412, while the word line decoder 408 is designed to selectively apply a second voltage to one or more word line(s) WL1-WL3 based on a second address S ADDR2 to apply the voltages received by the control circuit 412. The applied voltages cause a current to flow through the access selection device 101 and the MTJ component 109 of the selected memory cell 404. a,1 -404 c,4 initiate.

[0034] Fig. Figure 5 presents a cross-sectional view of an integrated chip 500 according to some other aspects of these teachings, with a memory array having a plurality of memory cells, each cell having an MTJ device and an access selection device with a polarized magnetic layer that reduces the write time of the MTJ. The polarized magnetic layer of any of the memory cells can also contribute to reducing the write time for the MTJs of one or more adjacent cell(s). The integrated chip 500 can be modified to incorporate the concepts described in relation to any cross-sectional view 300 of the Fig. 3A, cross-sectional view 320 of the Fig. 3B, cross-sectional view 340 of the Fig. 3C and 360° cross-sectional view of the Fig. are described in 3D.

[0035] The integrated chip 500 comprises a substrate 202, which includes an embedded memory region 508 and a logical region 510. A dielectric structure 204 is arranged above the substrate 202. The dielectric structure 204 comprises several stacked interdielectric layers (ILD layers) 512a-512f, which are vertically separated from each etch-stop layer 513a-513e. In some embodiments, the several stacked ILD layers 512a-512f comprise one or more silicon dioxide(e), SiCOH, a fluorosilicate glass, a phosphate glass (e.g., borophosphate silicate glass), or the like. In some embodiments, the etch-stop layers 513a-513e comprise a nitride (e.g., silicon nitride), a carbide (e.g., silicon carbide), or the like.

[0036] Within the embedded memory region 508, several memory cells 305i are arranged, each of which has an access selection device 505 coupled to the MTJ device 109. The access selection device 505 has a first metal structure 509 and an upper electrode 501, separated from each other by one or more non-metallic layer(s) 506. The first metal structure 509 comprises a polarized magnetic layer 504 with a polarization parallel to a plane of the polarized ferromagnetic layer. In some embodiments, the one or more non-metallic layer(s) 506 have a first dielectric layer 503, which is in contact with the polarized magnetic layer 504 and is an oxidation product of the polarized magnetic layer 504.In some embodiments, the one or more non-metallic layer(s) 506 further comprises a second dielectric layer 502 with a different bandgap energy from the first dielectric layer 503. In some embodiments, the access selection device 505 is a bipolar selector switch.

[0037] The MTJ component 109 includes an MTJ 107 arranged between a first electrode 511 and a second electrode 507. In some embodiments, sidewall spacers 530 are arranged along opposite sides of the MTJ 107. In some embodiments, the sidewall spacers 530 extend to flank the sidewalls of the access selection device 505. The sidewall spacers 530 may have curved outermost sidewalls facing away from the MTJ 107. In various embodiments, the sidewall spacers 530 comprise silicon nitride, silicon dioxide (SiO2), silicon oxynitride (e.g., SiON), or the like. In some embodiments, an encapsulation layer 534 is arranged over the sidewall spacers 530. In some embodiments, the encapsulation layer 534 comprises an oxide (e.g. silicon-rich oxide), a nitride (e.g. silicon nitride), a carbide (e.g. silicon carbide) or the like.

[0038] In some embodiments, an upper electrode via 536 extends through the encapsulation layer 534 to contact the upper electrode 501 of the memory cell 305i. The upper electrode via 536 couples the second electrode 105 to an interconnect wire 514c. In some embodiments, the upper electrode via 536 comprises aluminum, copper, tungsten, or the like. In some embodiments, a second interconnect wire 514b is arranged below the memory cell 305i and separated from the memory cell 305i by a lower insulating structure 520 and the fourth etch-stop layer 513d. A lower electrode via 524 may extend through the lower insulating structure 520 to couple the first electrode 511 to the second interconnect wire 514b.

[0039] The lower insulation structure 520 may comprise one or more layers of different insulators. In some embodiments, the lower insulation structure 520 comprises a silicon-rich oxide layer or the like. In some embodiments, the lower insulation structure 520 has a greater (i.e., more extended) thickness in the logic region 510 than in the embedded memory region 508. In some embodiments, the lower insulation structure 520 comprises a layer of silicon carbide, silicon nitride, or the like. In some embodiments, the lower insulation structure 520 comprises the encapsulation layer 534. In some embodiments, the lower insulation structure 520 comprises a layer of tetraethyl orthosilicate (TEOS) or the like.

[0040] In some embodiments, the second interconnect wire 514b is coupled to a word line WL. Alternatively, the second interconnect wire 514 can be a word line. In some embodiments, the second interconnect wire 514c is coupled to a bit line BL1 or BL2. In some embodiments, the second interconnect wire 514c itself provides the bit line. The memory cell 305i is formed within the fifth ILD layer 512e. Alternatively, the memory cell 305i can be formed within another ILD layer above or below the fifth ILD layer 512.

[0041] Within the logic region 510, one or more additional interconnect layers are arranged within the dielectric structure 204. The one or more additional interconnect layers comprise a conductive contact 540, an interconnect wire 542, and an interconnect via 544. The one or more additional interconnect layers are coupled to a logic component 538 located within the substrate 202. In some embodiments, the logic component 538 may comprise a transistor device (e.g., a MOSFET, a bipolar junction transistor (BJT), a high electron mobility transistor (HEMT), or the like).

[0042] The Fig. Figures 6-14 show cross-sectional views 600-1400, which depict a method for forming an integrated chip with an access selection device having a bipolar selector switch having a polarized magnetic layer, effective in reducing the write time for an associated MTJ device according to some embodiments of this disclosure. Although the Fig. 6-14, which describe a procedure, will make it clear that the procedures described in the Fig. The structures disclosed in 6-14 are not limited to such a procedure, but instead exist as independent structures of the procedure. Although the Fig. While 6-14 describe specific structures and compositions for the MTJ component and the access selection device, the method can easily be extended to other structures and compositions within the scope of this disclosure.

[0043] As shown in the cross-sectional view 600 of the Fig. As shown in Figure 6, a lower insulating structure 605 is formed above a metal interconnect structure 601, which in turn is formed above the substrate 220. In various embodiments, the substrate 202 can be any type of semiconductor body (e.g., silicon, SiGe, SOI), such as a semiconductor wafer and / or one or more dies on a wafer, as well as any type of semiconductor and / or associated epitaxial layers. The metal interconnect structure 601 can have one or more ILD layers separated by etch-stop layers and surrounding conductive wires, vias, and the like. The ILD layers can have one or more dielectric materials, such as silicon dioxide (SiO2), SiCOH, a fluorosilicate glass, a phosphate glass (e.g., borophosphate silicate glass), or the like.The conductive material that forms wires, vias and the like within the metal interconnect structure 601 can be a metal (e.g. aluminum, copper, tungsten) formed by a deposition process (e.g. CVD, PVD, PE-CVD, ALD).

[0044] In some embodiments, the lower insulating structure 605 is formed and then selectively structured to define lower electrode vias 602 over interconnect wires 514b or similar conductive features within a metal interconnect structure 601. In some embodiments, the lower insulating structure 605 includes a fourth etch-stop layer 513d or any other etch-stop layer and a first dielectric layer 522 arranged above the etch-stop layer. The first dielectric layer 522 may comprise one or more silicon carbide, silicon-rich oxide, TEOS (tetraethyl orthosilicate), or the like.

[0045] As shown in the cross-sectional view 700 of the Fig. As shown in Figure 7, the MTJ device stack 717 can be formed above the lower insulating structure 605. The MTJ device stack 717 can comprise a lower electrode structure 715, an MTJ stack 709, and an upper electrode layer 701. In some embodiments, the lower electrode structure 715 has a lower electrode layer 711 that lies above a lower electrode via layer 713. The lower electrode via layer 713 can lie above the lower insulating structure 605 and fill the opening 602. The MTJ stack 709 can comprise a fixed layer 707, a dielectric barrier tunnel layer 705, and a free layer 703. In some embodiments, the fixed layer 707 is arranged between the free layer 703 and the lower electrode structure 715. In other embodiments (not shown), the free layer 703 is arranged between the fixed layer 707 and the lower electrode structure 715.The upper electrode layer 701 is formed above the MTJ stack 709.

[0046] As shown in the cross-sectional view 800 of the Fig. As shown in Figure 8, a ferromagnetic layer 801 can be formed over the MTJ device stack 717. In some embodiments, the thickness of the ferromagnetic layer 801 is between approximately 5 nm and approximately 200 nm. In other embodiments, the thickness of the ferromagnetic layer 801 is between approximately 15 nm and approximately 50 nm. In some embodiments, the ferromagnetic layer 801 is formed with polarization using a crystal growth process or the like. In other embodiments, the ferromagnetic layer 801 is polarized after formation. In some embodiments, the ferromagnetic layer 801 has a high coercivity so that it more readily becomes a static layer that retains its polarization over the lifetime of each resulting device.

[0047] As shown in the cross-sectional view 900 of the Fig. As shown in Figure 9, the ferromagnetic layer 801 can be partially oxidized to form a first dielectric layer 901. In some embodiments, the first dielectric layer has a thickness between approximately 2 nm and approximately 40 nm. In some embodiments, the first dielectric layer has a thickness between approximately 5 nm and approximately 20 nm. In some embodiments, the oxidation process reduces the thickness of the ferromagnetic layer 801 to between approximately 5 nm and approximately 60 nm. In some embodiments, the oxidation process reduces the thickness of the ferromagnetic layer 801 to between approximately 10 nm and approximately 30 nm. Any suitable oxidation process can be used.In some embodiments, oxidation is achieved by contact of the ferromagnetic layer 801 with oxygen. In some embodiments, oxidation is achieved by contact of the ferromagnetic layer 801 with a plasma containing oxygen-containing ions or molecules. In some embodiments, oxidation is achieved by allowing the ferromagnetic layer 801 to trap oxygen from an oxide layer arranged above the ferromagnetic layer 801.

[0048] As shown in the cross-sectional view 1000 of the Fig. As shown in section 10, additional layers can be placed above the one shown in the cross-sectional view 900. Fig. The structure shown in Figure 9 is applied to form a bipolar selection stack 1007. The bipolar selection stack 1007 can comprise the ferromagnetic layer 801, non-metallic layers 1005, and an upper electrode layer 1003. The non-metallic layers 1005 can comprise the first dielectric layer 901 and a second dielectric layer 1001, the second dielectric layer having a bandgap energy different from that of the first dielectric layer 901. In some embodiments, the second dielectric layer 1001 has a thickness between approximately 2 nm and approximately 40 nm. In some embodiments, the second dielectric layer 1001 has a thickness between approximately 5 nm and approximately 20 nm. In some embodiments, the upper electrode layer 1003 has a thickness between approximately 5 nm and approximately 60 nm.In some embodiments, the upper electrode layer 1003 has a thickness between approximately 10 nm and approximately 30 nm.

[0049] As shown in the cross-sectional view 1100 of the Fig. As shown in Figure 11, a mask layer 1101 can be formed, and the bipolar selection stack 1007 can be selectively etched according to the mask layer 1101 to define memory cells 305i. The mask layer 1101 can be silicon nitride, silicon carbide, or the like. The etching defines an access selection device 505 from the bipolar selection stack 1007. The structuring to define the access selection device 505 includes defining the upper electrode 501 from the upper electrode layer 1003, the second dielectric layer 502 from the second dielectric layer 1001, and the first dielectric layer 503 from the first dielectric layer 901. The access selection device 505 also includes the first metal structure 509, which has a polarized magnetic layer 504 defined by the ferromagnetic layer 801.The first metal structure 509 can also be considered to contain all or part of the second electrode 507, which is defined by the upper electrode layer 701. Etching with the mask layer 1101 can further define sections of MTJ devices 109, which feature the definition of the second electrode 507 by the upper electrode layer 701 and all or some of the MTJs 107 from the MTJ stack 709. The parts of the MTJ 107 that are defined by the MTJ stack 709 by etching the... Fig. 11 can be formed, comprising the free layer 107a, the dielectric tunnel barrier 107b and / or the fixed layer 107c.

[0050] As shown in the cross-sectional view 1200 of the Fig. 12 shown, are adjacent to the memory cells 305i, as in the cross-sectional view 1100 of the Fig. Figure 11 shows side wall spacers 530. The side wall spacers 530 flank the access selection device 505 and extend to flank sections of the MTJs 107 that have at least the dielectric tunnel barriers 107b. Also shown in cross-sectional view 1200 of the Fig. As shown in Figure 12, the sidewall spacers 530 provide a masking function for selective etching, which completes the definition of the MTJ devices 109 from the MTJ stack 709. The selective etching defines first electrodes 511 from the lower electrode layer 711 and lower electrode vias 524 from the lower electrode via layer 713. As a result, the edges of the first electrodes 511 can be aligned with the sidewall spacer 530. The etching can remove the mask layer 1101.

[0051] As shown in the cross-sectional view 1300 of the Fig. As shown in Figure 13, an encapsulation layer 534 can be formed over the memory cells 305i and the side wall spacer 530. The encapsulation layer 534 flanks the sides of both the MTJ component 109 and the access selection device 505. As shown in the cross-sectional view 1400 of the Fig. As shown in Figure 14, a fourth ILD layer 512d can be formed above the encapsulation layer 534. The fourth ILD layer 512d can be structured to define openings that are subsequently filled with metal to define electrode vias 536 and interconnect wires 514c. The resulting structure can form a section of the Fig. The 5 integrated chips shown form 500.

[0052] In the example of the integrated chip 500, the memory cells 305i are shown with a single set of sidewall spacers 530 and a single encapsulation layer 534. In various embodiments, additional sidewall spacers, additional encapsulation layers, and one or more cover layers can be used for purposes such as preventing cross-contamination between layers of bipolar selection stack 1007 and / or layers of the MTJ device stack 717 during structuring, which facilitates the structuring of the bipolar selection stack 1007 and / or MTJ device stack 717 and ensures that the vias 536 land on the upper electrodes 501 without causing short circuits.

[0053] The Fig. Figures 15-16 show cross-sectional views 1500-1600 of some embodiments of another method for forming an integrated chip with an access selection device, which includes a bipolar selector switch having a polarized magnetic layer effective in reducing the write time for an associated MTJ device. As shown in cross-sectional view 1500 of the Fig. As shown in Figure 15, the formation of the bipolar selector switch can begin with the formation of a third dielectric layer 1501 and a ferromagnetic layer 1503 over an MTJ device stack 717. The third dielectric layer 1501 has an oxide. As shown in the cross-sectional view 1600 of the Fig. As shown in Figure 16, a fourth dielectric layer 1601 can then be formed by partial oxidation of the ferromagnetic layer 1503. The oxidation can occur by trapping oxygen from the third dielectric layer 1501. In the resulting bipolar selection stack 1605, the upper electrode layer 701 of the MTJ stack 709 can serve as the lower electrode, the ferromagnetic layer 1503 can serve as the upper electrode, and the third dielectric layer 1501 and the fourth dielectric layer 1601 can serve as the non-metallic layers 1005 that separate the upper electrode from the lower electrode.

[0054] Fig. Document 17 provides a flowchart of some embodiments of a method 1700 for forming an integrated chip with a memory cell, comprising an MTJ device and an access selection device, wherein the access selection device has a polarized magnetic layer effective in reducing the write time for an associated memory cell. While the method 1700 is presented and described below as a series of actions or events, it should be understood that the presented sequence of such actions or events is not to be interpreted in a restricted sense. Some actions, for example, may occur in a different order and / or simultaneously with other actions or events apart from those presented and / or described herein.Furthermore, not all actions described necessarily implement one or more aspects or embodiments of the description herein. Additionally, one or more actions shown herein may be performed in one or more separate actions and / or phases.

[0055] Action 1701 forms an MTJ component stack above a substrate. The cross-sectional view 700 of the Fig. Figure 7 shows an embodiment corresponding to action 1701, in which the MTJ component stack 717 is formed over the substrate 220.

[0056] The plot 1703 forms an electrode layer for a bipolar selection stack that has a magnetic layer. The cross-sectional view 800 of the Fig. Figure 8 shows an embodiment corresponding to action 1703, in which the magnetic layer is the ferromagnetic layer 801. The cross-sectional view 1500 of the Fig. Figure 15 shows another example where the magnetic layer is the ferromagnetic layer 1503. The layers of the bipolar selection stack can be seen, as in the cross-sectional views 800-1000 and 1500-1600 of the Fig. Figures 8-10 and 15-16 show that the MTJ device stack layers are formed directly above the layers of the MTJ device stack 717. In some alternative embodiments, the layers of the MTJ device stack 717 are formed above the layers of the bipolar selector switch. In other embodiments, the MTJ device stack and the access selector switch may have a different spatial relationship.

[0057] Action 1705 oxidizes a section of the magnetic layer to form a dielectric layer for a bipolar selection stack. Cross-sectional view 900 of the Fig. Figure 9 shows an example in which the dielectric layer 901 is formed by partial oxidation of the ferromagnetic layer 801. The cross-sectional view 1600 of the Fig. Figure 16 shows another example in which the fourth dielectric layer 1601 is formed by partial oxidation of the ferromagnetic layer 1503.

[0058] Action 1707 forms the remaining layers of the bipolar selection stack. The cross-sectional view 1000 of the Fig. Figure 10 shows an example in which the bipolar selection stack 1007 is completed by forming the second dielectric layer 1001 and the upper electrode layer 1003 over the first dielectric layer 901. The cross-sectional view 1600 of the Fig. Figure 16 shows another example in which the bipolar selection stack 1007 can be completed by oxidizing a section of the ferromagnetic layer 1503 to form the fourth dielectric layer 1601.

[0059] Action 1709 is a structuring process for creating individual components from the bipolar selection stack and the MTJ component stack. The cross-sectional view 1100 of the Fig. Figure 11 shows an example in which structuring defines the access selection device 505 and partially defines the MTJ component 109 for each memory cell 305i.

[0060] The action 1711 forms side wall spacers that abut the individual building elements formed by the structuring of action 1709. The cross-sectional view 1200 of the Fig. Figure 12 shows an example in which the side wall spacers 530 are formed adjacent to the access selection device 505 and sections of the MTJ component 109, which has the dielectric tunnel barrier 107b for each storage cell 305i.

[0061] Action 1713 uses sidewall spacers formed by action 1711 to structure a lower electrode layer for the memory cells. Cross-sectional view 1200 of the Fig. Figure 12 shows an example in which the side wall spacers 530 are used to structure the first electrode 511 and the bottom electrode via 524 is used for each memory cell 305i.

[0062] The 1715 component forms an encapsulation layer that covers the sides of the bipolar selector switch and the MTJ component of each memory cell. The cross-sectional view 1300 of the Fig. Figure 13 shows an example in which the encapsulation layer 534 covers the sides of the access selection device 505 and the MTJ component 109 of each memory cell 305i.

[0063] The component 1715 forms a via that constitutes the upper electrode of the memory cell. The cross-sectional view 1400 of the Fig.Figure 14 shows an example in which the via 536 is made to contact the upper electrode 511 in each memory cell 305i.

Claims

[1] Integrated chip comprising: an MTJ device (109) with a first electrode (105, 108) and a second electrode (105, 108); and an access selection device (101) for the MTJ device (109) comprising a first metal structure (104) and a second metal structure (102) separated from each other by several non-metallic layers (103); wherein one of the first metal structure (104) and the second metal structure (102) is coupled to the second electrode (105, 108); and the first metal structure (104) has a polarized ferromagnetic layer, wherein the first metal structure (104) is an electrode for the access selection device (101), wherein the access selection device (101) is a bipolar selection switch, wherein the several non-metallic layers (103) have two insulators (103a, 103b) with different band gap energies, wherein one insulator (103b) of the two insulators (103a, 103b) which have different band gap energies is an oxide of a metal of the polarized ferromagnetic layer and is directly adjacent to the polarized ferromagnetic layer. [2] Integrated chip according to claim 1, wherein the MTJ device (109) and the access selection device (101) are formed by a stack of material layers. [3] Integrated chip according to claim 2, wherein the polarized ferromagnetic layer has a polarization parallel to a plane of the polarized ferromagnetic layer. [4] Integrated chip according to claim 3, wherein the MTJ device (109) has a fixed layer with perpendicular magnetic polarization. [5] Integrated chip according to one of the preceding claims, wherein the first metal structure (104) has an electrode layer that is different from the polarized ferromagnetic layer. [6] Integrated chip according to one of the preceding claims, wherein the polarized ferromagnetic layer is configured such that it tilts a direction of polarization of a free layer of the MTJ device (109). [7] Integrated chip according to any one of the preceding claims, wherein: the MTJ device (109) has a free layer and a fixed layer; and the polarized ferromagnetic layer is designed such that it has a magnetic field which extends through the free layer in such a way as to reduce the switching time for the MTJ device (109). [8] Integrated chip comprising: a magnetic MTJ device (109) arranged within a dielectric structure (304) over a substrate (302), wherein the MTJ device (109) has an MTJ arranged between a first MTJ electrode (105, 108) and a second MTJ electrode (105, 108); and a bipolar selector switch, BS, (101) having a middle structure (103) arranged between a first BS electrode (104) and a second BS electrode (102), wherein the second BS electrode (102) is coupled to the first MTJ electrode (105, 108) or is an integral part of the first MTJ electrode (105, 108), the middle structure (103) is several layers of insulators, with two of the insulators (103a, 103b) having different bandgap energies and one of the first BS electrodes (104) and the second BS electrode (102) has a polarized magnetic layer, wherein the layer (103b) directly adjacent to the polarized magnetic layer of the multiple layers of insulators is an oxide of a metal of the polarized magnetic layer. [9] Integrated chip according to claim 8, wherein the polarized magnetic layer has a polarization parallel to a plane of the polarized magnetic layer. [10] Integrated chip according to claim 8 or 9, wherein the first BS electrode (104) has the polarized magnetic layer. [11] Integrated chip according to any one of claims 8 to 10 above, wherein: the MTJ device (109) has a free layer and a fixed layer; and the polarized magnetic layer is designed such that it has a magnetic field that is effective in reducing the number of precession cycles that the free layer of the MTJ device (109) undergoes during switching. [12] Method for forming an integrated chip comprising: Forming an MTJ device (109) over a semiconductor substrate (302), wherein the MTJ device (109) has an MTJ arranged between a first electrode (105, 108) and a second electrode (105, 108); and Forming a bipolar selector switch (101) for the MTJ component (109); wherein the bipolar selector switch (101) has a layer of ferromagnetic material with fixed polarization and the bipolar selector switch (101) is coupled to the second electrode (105, 108), wherein: the bipolar selector switch, BS, (101) comprises a non-metal layer or several non-metal layers (103) arranged between a first BS electrode (104) and a second BS electrode (102) and the formation of the bipolar selector switch (101) involves oxidizing a section of the layer of ferromagnetic material to form one non-metal layer or one (103b) of the several non-metal layers (103). [13] Method according to claim 12, wherein the bipolar selector switch (101) is formed directly above or below the MTJ component (109). [14] Method according to claim 12 or 13, wherein the MTJ device (109) has a fixed layer with a polarization that is nearly orthogonal to the fixed polarization of the layer of ferromagnetic material.

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