Integrated circuit device with redistribution pattern

Abstract

Integrated circuit device (1, 2) comprising: a wiring structure (MS) comprising a plurality of wiring layers (ML) having a multilayer wiring structure and a plurality of via contact plugs (MV), and a first inter-wiring insulating layer (210) configured to surround the wiring structure (MS) on a substrate (110); a second inter-wiring insulating layer (220) and a plurality of redistribution via contact plugs (RV) connected to the wiring structure (MS) through the second inter-wiring insulating layer (220), on the first inter-wiring insulating layer (210); a plurality of redistribution patterns (RL) comprising a plurality of pad patterns (RL-P) and a plurality of dummy patterns (RL-D) on the second inter-wiring insulating layer (220), wherein each of the plurality of pad patterns (RL-P) and each of the plurality of dummy patterns (RL-D) has a thickness greater than a thickness of each of the plurality of wiring layers (ML); and a cover insulating layer (230) arranged to cover a portion of the plurality of redistribution patterns (RL), wherein the plurality of dummy patterns (RL-D) extend in lines in a horizontal direction parallel to the substrate (110) and are completely surrounded by the second inter-wiring insulating layer (220) and the covering insulating layer (230) so as to be electrically insulated from each other, wherein the plurality of dummy patterns (RL-D) are spaced apart from each other in a longitudinal direction (X) at first intervals in the longitudinal direction (SDL) and in a width direction (Y) at first intervals in the width direction (SDW), and wherein each of the plurality of dummy patterns (RL-D) has a first width (WD) and a first length (LD) and extends in the horizontal direction.

Description

BACKGROUND1. Area

[0001] The present disclosure relates to an integrated circuit device and, more particularly, to an integrated circuit device having a redistribution pattern. 2. Description of the state of the art

[0002] With the advancement of the electronics industry and user demands, electronic devices have multiple functions and large capacities, and are becoming smaller and lighter. Therefore, integrated circuit devices used in electronic devices must have a high degree of integration. To stably supply power to highly integrated circuit devices or to ensure the reliability of electrical connections between integrated circuit devices and electronic devices, redistribution patterns are introduced, which are electrically connected to wiring structures comprising wiring layers and via contact plugs.

[0003] US 2011 / 0 241 202 A1 discloses the following: An integrated circuit structure comprises a semiconductor chip, a metal pad at a major surface of the semiconductor chip, and an underbump metallurgy (UBM) above and in contact with the metal pad. A metal bump is formed above the UBM and electrically connected to it. A dummy pattern is formed at the same level and from the same metallic material as the metal pad.

[0004] DE 10 2019 117 792 A1 discloses the following: A semiconductor device comprises a semiconductor substrate including a chip region and a peripheral region around the chip region; a lower dielectric layer and an upper dielectric layer on the semiconductor substrate; a redistribution chip pad penetrating the upper dielectric layer on the chip region and connected to a chip pad; a process monitoring structure on the peripheral region; and dummy elements in the peripheral region having an upper surface lower than an upper surface of the upper dielectric layer. SUMMARY

[0005] One aspect is to provide an integrated circuit device having a redistribution pattern designed to increase the reliability of the integrated circuit device.

[0006] The scope of the invention is defined by the appended claims.

[0007] According to one aspect of one or more embodiments, an integrated circuit device is provided. The integrated circuit device comprises: a wiring structure comprising a plurality of wiring layers with a multilayer wiring structure and a plurality of via plugs, and a first inter-wiring insulating layer configured to surround the wiring structure on a substrate; a second inter-wiring insulating layer and a plurality of redistribution via plugs connected to the wiring structure through the second inter-wiring insulating layer on the first inter-wiring insulating layer;a plurality of redistribution patterns including a plurality of pad patterns and a plurality of dummy patterns on the second inter-wiring insulating layer, each of the plurality of pad patterns and each of the plurality of dummy patterns having a thickness greater than a thickness of each of the plurality of wiring layers;and a cover insulating layer configured to cover a portion of the plurality of redistribution patterns, wherein the plurality of dummy patterns extend in lines in a horizontal direction parallel to the substrate and are completely surrounded by the second inter-wiring insulating layer and the cover insulating layer so as to be electrically insulated from each other. The plurality of dummy patterns are spaced apart from each other at first intervals in a longitudinal direction and at first intervals in a width direction, each of the plurality of dummy patterns having a first width and a first length and extending in the horizontal direction.

[0008] According to one aspect of one or more embodiments, an integrated circuit device is provided, comprising a wiring structure comprising a plurality of wiring layers with a multilayer wiring structure and a plurality of via contact plugs, and a first inter-wiring insulating layer configured to surround the wiring structure on a substrate; a second inter-wiring insulating layer and a plurality of redistribution via contact plugs connected to the wiring structure through the second inter-wiring insulating layer on the first inter-wiring insulating layer;a plurality of redistribution patterns including a plurality of pad patterns, a plurality of dummy patterns, and a plurality of power patterns on the second inter-wiring insulating layer, each of the plurality of pad patterns, the plurality of dummy patterns, and the plurality of power patterns having a thickness of not less than twice a thickness of each of the plurality of wiring layers; a cover insulating layer configured to cover the plurality of dummy patterns and the plurality of power patterns and not cover at least a portion of the plurality of pad patterns;and a plurality of connection terminals each connected to the plurality of pad patterns, wherein the plurality of dummy patterns are in the shape of lines extending in a horizontal direction parallel to the substrate and are completely surrounded by the second inter-wiring insulating layer and the covering insulating layer so as to be electrically insulated from each other. The plurality of dummy patterns are spaced apart from each other at first intervals in a longitudinal direction and at first intervals in a width direction, each of the plurality of dummy patterns having a first width and a first length and extending in the horizontal direction.

[0009] According to one aspect of one or more embodiments, an integrated circuit device is provided, comprising a device layer comprising a plurality of semiconductor devices on a substrate; a wiring structure comprising a plurality of wiring layers with a multi-layer wiring structure having a topmost wiring layer and a plurality of via plugs on the device layer; a first inter-wiring insulating layer configured to surround the wiring structure on the device layer; a second inter-wiring insulating layer on the first inter-wiring insulating layer and the wiring structure; a plurality of redistribution via plugs connected to the topmost wiring layer through the second inter-wiring insulating layer; a plurality of redistribution patterns,comprising a plurality of pad patterns, a plurality of dummy patterns, and a plurality of power patterns, wherein each of the plurality of pad patterns is connected to one of the plurality of redistribution via contact plugs on the second inter-wiring insulating layer, each of the plurality of dummy patterns has the shape of a line extending in a horizontal direction parallel to the substrate, and each of the plurality of power patterns is connected to at least two of the plurality of redistribution via contact plugs and has a thickness of not less than twice a thickness of the uppermost wiring layer; a cover insulating layer configured to cover the plurality of dummy patterns and the plurality of power patterns; and a plurality of connection terminals each connected to the plurality of pad patterns,wherein each of the plurality of connection terminals comprises a conductive column and a conductive cap configured to cover an upper surface of the conductive column, wherein the plurality of dummy patterns are completely surrounded by the second inter-wiring insulating layer and the cover insulating layer and are electrically insulated from each other, and wherein, of an upper surface, side surfaces, and a lower surface of each of the plurality of power patterns, a portion not connected to the at least two redistribution via contact plugs is covered with the second inter-wiring insulating layer and the cover insulating layer. The plurality of dummy patterns are spaced apart from each other at first intervals in a longitudinal direction and at first intervals in a width direction.wherein each of the plurality of dummy patterns has a first width and a first length and extends in the horizontal direction., BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Various embodiments will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which: Fig. 1A and Fig. 1B are a top view of a layout diagram and a cross-sectional view illustrating an integrated circuit device according to embodiments; Fig. 2A is a plan view of a layout diagram, and Fig. 2B to 2C are cross-sectional views illustrating an integrated circuit device according to embodiments; Fig. 3 is a top view of a layout diagram illustrating an integrated circuit device according to embodiments; Fig. 4 is a top view of a layout diagram illustrating an integrated circuit device according to embodiments; Fig. 5A and Fig. 5B are a top view of a layout diagram and a cross-sectional view illustrating an integrated circuit device according to embodiments, respectively; Fig. 6 is a top view of a layout diagram illustrating an integrated circuit device according to embodiments; Fig. 7A and Fig. 7B are a plan view of a layout diagram and a cross-sectional view illustrating an integrated circuit device according to embodiments; and Fig. 8 is a flowchart illustrating a method of manufacturing an integrated circuit device according to embodiments. DETAILED DESCRIPTION

[0011] In this specification, the phrase “at least one element of A or B” includes “only A”, “only B” and “both A and B”.

[0012] Fig. 1A and Fig. 1B are a top view of a layout diagram and a cross-sectional view, respectively, illustrating an integrated circuit device according to embodiments. In detail, Fig. 1B is a cross-sectional view along the line IB-IB' in Fig. 1A.

[0013] Referring to Fig. 1A and Fig. 1B, an integrated circuit device 1 includes a device layer 130 comprising a plurality of semiconductor devices 120 on a substrate 110. The substrate 110 may, for example, comprise silicon (Si). Alternatively, in some embodiments, the substrate 110 may comprise a semiconductor element such as germanium (Ge) or a compound semiconductor such as a silicon carbide (SiC), a gallium arsenide (GaAs), an indium arsenide (InAs), or an indium phosphide (InP). Alternatively, in some embodiments, the substrate 110 may have a silicon-on-insulator (SOI) structure. For example, the substrate 110 may comprise a buried oxide (BOX) layer. The substrate 110 may include a conductive region, for example, a well or a structure doped with impurities.Alternatively, in some embodiments, the substrate 110 may include various device isolation structures, such as a shallow trench isolation (STI) structure. The substrate 110 may include an active area and an inactive area opposite the active area.

[0014] A device layer 130 comprising the plurality of semiconductor devices 120 may be arranged on the active area of ​​the substrate 110. In Fig. 1B illustrates that the plurality of semiconductor devices 120 are formed in a portion of the device layer 130 on the active area of ​​the substrate 110. However, embodiments are not limited thereto. However, in some embodiments, for example, the plurality of semiconductor devices 120 may be formed over a portion of the active area of ​​the substrate 110 and the device layer 130.

[0015] At least some of the plurality of semiconductor devices 120 may be transistors. For example, at least some of the plurality of semiconductor devices 120 may be bipolar transistors (BJTs) or field-effect transistors (FETs). For example, at least some of the plurality of semiconductor devices 120 may be planar transistors or FinFET transistors. If at least some of the plurality of semiconductor devices 120 are FinFET transistors, a plurality of fin-type active regions may protrude on the substrate 110 and extend in parallel in a horizontal direction (an X direction or a Y direction).

[0016] In some embodiments, the plurality of semiconductor devices 120 may be different types of separate devices for forming a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, an electrically erasable read-only memory (EEPROM) device, a phase-change random access memory (PRAM) device, a magnetic random access memory (MRAM) device, or a resistive random access memory (RRAM) device. For example, the plurality of semiconductor devices 120 may be different types of separate devices for forming a high-bandwidth memory (HBM) DRAM device, and the integrated circuit device 1 may be the HBM DRAM device.

[0017] In other embodiments, the plurality of semiconductor devices 120 may form a logic cell. The logic cell may be formed differently to include a plurality of circuit devices, such as a transistor and a register. The logic cell may, for example, form an AND, NAND, OR, NOR, Exclusive OR (XOR), Exclusive NOR (XNOR), an inverter INV, an adder ADD, a buffer BUF, a delay DLY, a filter FIL, a multiplexer MXT / MXIT, or an OR / AND / INVERTER (OAI) and AND / OR (AO), an AND / OR / INVERTER (OAI), a D-type flip-flop, a reset flip-flop, a master-slave flip-flop, or a latch. The logic cell may form standard cells that perform a desired logic function, such as a counter or a buffer. For example, the integrated circuit device 1 may be a central processing unit (CPU), a graphics processor (GPU), or an application processor (AP).

[0018] The device layer 130 may include the plurality of semiconductor devices 120, a conductive line and a conductive contact plug for connecting the plurality of semiconductor devices 120, and an interlayer insulating layer filling a space between the plurality of semiconductor devices 120, the conductive line, and the conductive contact plug. The device layer 130 may be formed in various types and shapes from conductive material, semiconductor material, and insulating material. In some embodiments, the interlayer insulating layer filling the conductive line and the conductive contact plug may comprise an oxide.

[0019] Wiring patterns MS and a first inter-wiring insulating layer 210 surrounding the wiring patterns MS may be arranged on the substrate 110 on which the device layer 130 is formed.

[0020] The wiring structures MS may include a plurality of wiring layers ML and a plurality of via contact plugs MV connected to the plurality of wiring layers ML. The plurality of wiring layers ML may have a multi-layer wiring structure including the plurality of wiring layers ML positioned at different levels within the device layer 130. A connection relationship between the plurality of wiring layers ML and the plurality of via contact plugs MV connected in Fig. 1B is for illustrating the multilayer wiring structure as an example and may not represent an actual connection relationship.

[0021] In the present documents, “level” means a height in a vertical direction (a Z direction) with respect to the main surface, for example, an upper surface of the substrate 110. That is, positioned at “the same” level or a “uniform” level means a position where the height in the vertical direction (the Z direction) with respect to the main surface of the substrate 110 is the same or uniform, and positioned at “low” or “high” levels means positions where the height in the vertical direction (the Z direction) with respect to the main surface of the substrate 110 is small or large, respectively.

[0022] The wiring structures MS may comprise a metal material such as aluminum (Al), copper (Cu), or tungsten (W). In some embodiments, the wiring structures MS may comprise wiring barrier layers or wiring metal layers. The wiring barrier layers may be formed from a nitride or an oxide of a metal such as titanium (Ti), tantalum (Ta), ruthenium (Ru), manganese (Mn), or cobalt (Co), or W, or from an alloy such as cobalt tungsten phosphide (CoWP), cobalt tungsten boron (CoWB), or cobalt tungsten boron phosphide (CoWBP). The wiring metal layers may comprise at least one element of W, Al, Ti, Ta, Ru, Mn, or Cu.

[0023] Each of the plurality of wiring layers ML may have a thickness of no more than 0.5 µm. In some embodiments, each of the uppermost wiring layers ML-T located at the uppermost end of the plurality of wiring layers ML may have a thickness of no more than about 0.5 µm, and each of the remaining wiring layers ML may have a thickness of no more than about 0.3 µm, which is less than the thickness of each of the uppermost wiring layers ML-T.

[0024] Some of the topmost wiring layers ML-T arranged at the uppermost ends of the plurality of wiring layers ML may serve as sub-pads electrically connected to pad patterns RL-P of the plurality of redistribution patterns RL. A plurality of connection terminals 300 may be arranged on the pad patterns RL-P, respectively. Others of the topmost wiring layers ML-T may serve as wiring lines for electrically connecting the plurality of wiring layers ML and the plurality of via plugs MV forming the wiring structures MS.

[0025] Via plugs MV arranged at the lowermost ends of the plurality of via plugs MV may extend from lower surfaces of the plurality of wiring layers ML toward the device layer 130. The wiring structures MS may be electrically connected to the plurality of semiconductor devices 120. The plurality of via plugs MV may extend from the lower surfaces of the plurality of wiring layers ML having the multilayer wiring structure and positioned at different levels toward the substrate 110.

[0026] Some of the plurality of via plugs MV may connect the plurality of wiring layers ML positioned at different levels to each other, and others of the plurality of via plugs MV may connect some of the plurality of wiring layers ML and the plurality of semiconductor devices 120 to each other, or connect some of the plurality of wiring layers ML and the substrate 110 to each other. For example, via plugs MV located at the lowermost ends of the plurality of via plugs MV may connect wiring layers ML located at the lowermost ends of the plurality of wiring layers ML and the plurality of semiconductor devices 120 or the substrate 110 to each other.

[0027] The first interwiring insulating layer 210 may have a multilayer structure in which a plurality of low-k dielectric insulating layers are stacked to correspond to the multilayer wiring structure of the plurality of wiring layers ML. In some embodiments, the first interwiring insulating layer 210 may be formed of an insulating material having a dielectric constant lower than that of Si oxide. For example, in some embodiments, the first interwiring insulating layer 210 may include an ultra-low-K (ULK) layer having a very low dielectric constant K of about 2.2 to about 2.4. The ULK layer may include a SiOC layer or a SiCOH layer. The first interwiring insulating layer 210 may be referred to as a low-k dielectric insulating layer.

[0028] In other embodiments, the first inter-wiring insulating layer 210 may have a multi-layer structure in which an insulating material having a dielectric constant less than that of Si oxide and another insulating material having a dielectric constant equal to or greater than that of Si oxide are stacked. For example, at least one of the multi-layer structure of the first inter-wiring insulating layer 210 may include an oxide layer or a nitride layer. For example, the first inter-wiring insulating layer 210 may include an etch stop layer formed of a nitride, which is used in a process for forming the plurality of wiring layers ML. However, a ratio of the etch stop layer formed of a nitride to the first inter-wiring insulating layer 210 may be very low.

[0029] A second inter-wiring insulating layer 220 and redistribution via contact plugs RV connected to the wiring patterns MS through the second inter-wiring insulating layer 220 may be formed on the wiring patterns MS and the first inter-wiring insulating layer 210.

[0030] A second interwiring insulating layer 220 may comprise an oxide layer, a nitride layer, a carbide layer, a polymer, or a combination thereof. The second interwiring insulating layer 220 may be formed from an insulating material having a greater dielectric constant than that of the first interwiring insulating layer 210. For example, the second interwiring insulating layer 220 may be formed from an oxide. In some embodiments, the second interwiring insulating layer 220 may be formed from a tetraethyl orthosilicate (TEOS). In some embodiments, a level of a top surface of the second interwiring insulating layer 220 may be generally uniform.

[0031] In some embodiments, the redistribution via plugs RV may comprise a barrier layer and a metal layer. The barrier layer may be formed from a nitride or an oxide of a metal such as Ti, Ta, Ru, Mn, Co, or W, or an alloy such as CoWP, CoWB, or CoWBP. The metal layer may comprise at least one of W, Al, Ti, Ta, Ru, Mn, or Cu.

[0032] In Fig. 1B illustrates that the uppermost wiring layers ML-T of the plurality of wiring layers ML are arranged on the first inter-wiring insulating layer 210 such that lower surfaces of the uppermost wiring layers ML-T and a lower surface of the second inter-wiring insulating layer 220 are positioned at the same level. However, embodiments are not limited thereto. In some embodiments, upper surfaces of the uppermost wiring layers ML-T may be positioned at the same level as an upper surface of the first inter-wiring insulating layer 210.

[0033] The plurality of redistribution patterns RL may be arranged on the second inter-wiring insulating layer 220 and the redistribution via plugs RV. A thickness of each of the plurality of redistribution patterns RL may have a value greater than that of the thickness of the plurality of wiring layers ML. For example, the thickness of each of the plurality of redistribution patterns RL may have a value of not less than twice that of each of the plurality of wiring layers ML. In some embodiments, the thickness of each of the plurality of redistribution patterns RL may be about 1 µm to about 5 µm. In some embodiments, a ratio between a planar area of ​​the plurality of redistribution patterns RL and a planar area of ​​intervals between the plurality of redistribution patterns RL may be about 3.5:1 to about 4.5:1.

[0034] The plurality of redistribution patterns RL may include a plurality of pad patterns RL-P and a plurality of dummy patterns RL-D. In some embodiments, the plurality of redistribution patterns RL may include a barrier layer and a metal layer. The barrier layer may be formed from a nitride or an oxide of a metal such as Ti, Ta, Ru, Mn, Co, or W, or an alloy such as CoWP, CoWB, or CoWBP. The metal layer may include at least one element selected from W, Al, Ti, Ta, Ru, Mn, or Cu.

[0035] Lower surfaces of the plurality of pad patterns RL-P may respectively contact upper surfaces of the redistribution via plugs RV, so that the plurality of pad patterns RL-P may respectively be electrically connected to the wiring patterns MS through the plurality of redistribution via plugs RV. Lower surfaces of the plurality of dummy patterns RL-D may contact an upper surface of the second inter-wiring insulating layer 220, so that the plurality of dummy patterns RL-D may be electrically insulated from the wiring patterns MS with the second inter-wiring insulating layer 220 therebetween.

[0036] The plurality of pad patterns RL-P may be arranged in at least one column in the horizontal direction (the X direction or the Y direction). In some embodiments, the plurality of pad patterns RL-P may be arranged horizontally in a matrix. The plurality of connection terminals 300 may be connected on the plurality of pad patterns RL-P, respectively. For example, the plurality of pad patterns RL-P may be center pads arranged two-dimensionally at a center of the integrated circuit device 1. However, embodiments are not limited thereto. In some embodiments, the plurality of pad patterns RL-P may be edge pads arranged two-dimensionally so as to be adjacent to edges of the integrated circuit device 1.

[0037] Each of the plurality of dummy patterns RL-D may have the shape of a line extending in the first horizontal direction (the X direction) or the second horizontal direction (the Y direction). Fig. 1A illustrates that the plurality of dummy patterns RL-D have the shape of lines extending in the same direction, that is, the horizontal direction (the X direction). However, embodiments are not limited thereto. For example, some of the plurality of dummy patterns RL-D have the shape of lines extending in the first horizontal direction (the X direction), and the remaining dummy patterns RL-D have the shape of lines extending in the second horizontal direction (the Y direction) perpendicular to the first horizontal direction (the X direction).

[0038] Each of the plurality of dummy patterns RL-D may have the shape of a line extending with a width of not less than 20 µm and a length of not less than about 100 µm. For example, each of the plurality of dummy patterns RL-D may have a length of about 100 µm to about 400 µm. For example, a ratio between the length and width of each of the plurality of dummy patterns RL-D may be about 5:1 to about 20:1. The plurality of dummy patterns RL-D may be arranged at intervals of not more than about 10 µm. In some embodiments, a ratio between a planar area of ​​the plurality of dummy patterns RL-D and a planar area of ​​intervals between the plurality of dummy patterns RL-D may be about 3.5:1 to about 4.5:1.

[0039] In Fig. 1A illustrates that the plurality of dummy patterns RL-D extend with the same width and the same length. However, embodiments are not limited thereto. In some embodiments, the ratio between the length and the width of each of the plurality of dummy patterns RL-D is about 5:1 to about 20:1, and a length or a width of each of some of the plurality of dummy patterns RL-D may have a different value than that of a length or a width of any other of the plurality of dummy patterns RL-D.Alternatively, in some embodiments, the ratio between the planar area of ​​the plurality of dummy patterns RL-D and the planar area of ​​the intervals between the plurality of dummy patterns RL-D may be about 3.5:1 to about 4.5:1, and the length or width of each of the plurality of dummy patterns RL-D may be a different value than that of the length or width of each of the plurality of dummy patterns RL-D.

[0040] Each of the plurality of pad patterns RL-P may be two-dimensionally square or two-dimensionally rectangular. In some embodiments, a ratio between a planar area of ​​the plurality of pad patterns RL-P and a planar area of ​​intervals between the plurality of pad patterns RL-P may have the same value as the ratio between the planar area of ​​the plurality of dummy patterns RL-D and the planar area of ​​the intervals between the plurality of dummy patterns RL-D. For example, the ratio between the planar area of ​​the plurality of pad patterns RL-P and the planar area of ​​the intervals between the plurality of pad patterns RL-P may be about 3.5:1 to about 4.5:1.

[0041] In some embodiments, the plurality of redistribution patterns RL may further comprise, in addition to the plurality of pad patterns RL-P and the plurality of dummy patterns RL-D, a redistribution pattern for transmitting power and / or a redistribution pattern for transmitting a signal.

[0042] A cover insulating layer 230 may be formed on the second inter-wiring insulating layer 220 and the plurality of redistribution patterns RL. The cover insulating layer 230 may cover the plurality of dummy patterns RL-D of the plurality of redistribution patterns RL.

[0043] The plurality of dummy patterns RL-D may be completely surrounded by the second inter-wiring insulating layer 220 and the cover insulating layer 230, and may be spaced apart from each other and electrically insulated. Furthermore, the plurality of dummy patterns RL-D may be completely surrounded by the second inter-wiring insulating layer 220 and the cover insulating layer 230, and may be electrically insulated from the other conductive components of the integrated circuit device 1. For example, the upper and side surfaces of the plurality of dummy patterns RL-D may be covered with the cover insulating layer 230, and the lower surfaces of the plurality of dummy patterns RL-D may be covered with the second inter-wiring insulating layer 220.In some embodiments, the upper surfaces of the plurality of dummy patterns RL-D may be covered with the cover insulating layer 230, and the side and bottom surfaces of the plurality of dummy patterns RL-D may be covered with the second inter-wiring insulating layer 220.

[0044] The cover insulating layer 230 may not cover some of the upper surfaces of the plurality of pad patterns RL-P of the plurality of redistribution patterns RL. The plurality of connection terminals 300 may be arranged on the remaining portions of the upper surfaces of the plurality of pad patterns RL-P that are not covered with the cover insulating layer 230 and are exposed. Some of the lower surfaces of the plurality of pad patterns RL-P may be covered with the second inter-wiring insulating layer 220, and the remaining portions of the lower surfaces of the plurality of pad patterns RL-P that are not covered with the second inter-wiring insulating layer 220 may be connected to the plurality of redistribution via plugs RV, respectively. The cover insulating layer 230 may cover side surfaces of the plurality of pad patterns RL-P.In some embodiments, the side surfaces of the plurality of pad patterns RL-P may be covered with the second inter-wiring insulating layer 220.

[0045] The capping insulating layer 230 may be formed, for example, from photosensitive polyimide (PSPI). In some embodiments, the capping insulating layer 230 may have a multilayer structure in which at least two insulating layers are stacked. For example, the capping insulating layer 230 may have a multilayer structure in which a layer formed from a nitride and a layer formed from PSPI are stacked.

[0046] Alternatively, in some embodiments, the capping insulating layer 230 may be formed from, for example, an oxide. In some embodiments, the capping insulating layer 230 may be formed from TEOS. The capping insulating layer 230 may have a multilayer structure in which at least two insulating layers are stacked. For example, the capping insulating layer 230 may have a multilayer structure in which a layer formed from a nitride and a layer formed from TEOS are stacked.

[0047] Although the plurality of redistribution patterns RL are formed to be thick in the integrated circuit device 1, since the plurality of redistribution patterns RL have a two-dimensionally uniform thickness, that is, a ratio between a planar area of ​​the plurality of redistribution patterns RL and a planar area of ​​the intervals between the plurality of redistribution patterns RL is about 3.5:1 to about 4.5:1, it is possible to prevent the integrated circuit device 1 from being bent due to the plurality of redistribution patterns RL. Therefore, the reliability of the integrated circuit device 1 can be increased, and the reliability of an electrical connection between the plurality of connection terminals 300 arranged on the plurality of pad patterns RL-P and an external device can be increased.

[0048] When the plurality of redistribution patterns RL are formed to be thick, it may be difficult to detect defects in the plurality of redistribution patterns RL because distortion may occur in planar shapes of the plurality of redistribution patterns RL due to grain boundaries between metal layers constituting the plurality of redistribution patterns RL. However, since the plurality of redistribution patterns RL in the integrated circuit device 1 includes the plurality of dummy patterns RL-D having a large width and length, distortion occurring in the planar shapes of the plurality of redistribution patterns RL due to the grain boundaries can be minimized. Since defects that may occur in the plurality of redistribution patterns RL can be easily detected, the integrated circuit device 1 can be formed without defects.

[0049] Fig. 2A is a plan view, and Fig. 2B to 2C are cross-sectional views illustrating an integrated circuit device according to embodiments. In detail, Fig. 2A is a plan view of a layout diagram showing an enlargement of region IIA from Fig. 1A, and Fig. 2B and Fig. 2C are cross-sectional views along line IIB-IIB' and line IIC-IIC' of Fig. 2A.

[0050] Referring to Fig. 2A, the plurality of redistribution patterns RL may include the plurality of pad patterns RL-P and the plurality of dummy patterns RL-D. As in Fig. As shown in FIG. 2C, the plurality of redistribution via plugs RV may be connected to the lower surfaces of the plurality of pad patterns RL-P, respectively. The plurality of connection terminals 300 may be connected to the upper surfaces of the plurality of pad patterns RL-P, respectively. The plurality of pad patterns RL-P may electrically connect the plurality of connection terminals 300 and the plurality of redistribution via plugs RV, respectively.

[0051] Each of the plurality of dummy patterns RL-D may have the shape of a line extending in the first horizontal direction (the X direction) or the second horizontal direction (the Y direction).

[0052] Each of the plurality of dummy patterns RL-D may have the shape of a line extending with a first width WD and a first length LD. For example, the first width WD may have a value of not less than about 20 µm. For example, the first length LD may have a value of about 100 µm to about 400 µm. In some embodiments, a ratio between the first length LD and the first width WD may be about 5:1 to about 20:1.

[0053] The plurality of dummy patterns RL-D can be arranged in a longitudinal direction at first intervals SDL in the longitudinal direction (ie in the X direction in Fig. 2A) and in a width direction in first intervals SDW in the width direction (ie the Y-direction in the example from Fig. 2A). Each of the first longitudinal intervals SDL and each of the first widthwise intervals SDW may have a value of no more than half (1 / 2) of the first width WD. For example, the first longitudinal interval SDL may have a value of no more than 10 µm. For example, the first widthwise interval SDW may have a value of no more than 10 µm. In some embodiments, the first longitudinal interval SDL and the first widthwise interval SDW may have the same or similar values.

[0054] In some embodiments, the ratio between the planar area of ​​the plurality of dummy patterns RL-D and the planar area of ​​the intervals between the plurality of dummy patterns RL-D may be about 3.5:1 to about 4.5:1. Fig. 2A, as an example, a planar pattern area AD of one of the plurality of dummy patterns RL-D and a planar interval area AS of an interval corresponding to an average of one dummy pattern RL-D are shown. A ratio between the pattern area AD and the interval area AS may be about 3.5:1 to about 4.5:1.

[0055] Each of the plurality of pad patterns RL-P may be two-dimensionally square or two-dimensionally rectangular. A width and height of a square of each of the plurality of pad patterns RL-P and the intervals between the plurality of pad patterns RL-P may be selected according to a width of each of the plurality of connection terminals 300 and intervals between the plurality of connection terminals 300. The width of each of the plurality of connection terminals 300 and the intervals between the plurality of connection terminals 300 may be different in consideration of an electrical connection between the integrated circuit device 1 ( Fig. 1A and Fig. 1B) and an external device.

[0056] For example, the width and height of the square of each of the plurality of pad patterns RL-P may have the same value as the first width WD, as shown in Fig. 2A. However, embodiments are not limited thereto. In some embodiments, the width and height of the square of each of the plurality of pad patterns RL-P may have a value greater than that of the first width WD. In other embodiments, the width and height of the square of each of the plurality of pad patterns RL-P may have a value less than that of the first width WD.

[0057] In some embodiments, the ratio between the planar area of ​​the plurality of pad patterns RL-P and the planar area of ​​the intervals between the plurality of pad patterns RL-P may have the same value as the ratio between the planar area of ​​the plurality of dummy patterns RL-D and the planar area of ​​the intervals between the plurality of dummy patterns RL-D. For example, the ratio between the planar area of ​​the plurality of pad patterns RL-P and the planar area of ​​the intervals between the plurality of pad patterns RL-P may be about 3.5:1 to about 4.5:1.

[0058] Referring to Fig. 2B and Fig. 2C, each of the plurality of dummy patterns RL-D may be completely surrounded by the second inter-wiring insulating layer 220 and the cover insulating layer 230 so as to be electrically isolated from the outside and may be electrically floating. Therefore, the plurality of dummy patterns RL-D may be spaced apart from each other and electrically insulated, and may be electrically insulated from the other conductive components of the integrated circuit device 1.

[0059] Each of the uppermost wiring layers ML-T arranged at the uppermost ends of the plurality of wiring layers ML may have a first thickness TML1, and each of the remaining wiring layers, except for the uppermost wiring layer ML-T of the plurality of wiring layers ML, may have a second thickness TML2. For example, the first thickness TML1 may have a value of not more than 0.5 µm. For example, the second thickness TML2 may have a value less than that of the first thickness TML1. For example, the second thickness TML2 may have a value of not more than 0.3 µm. Fig. 2B and Fig. 2C illustrates that the remaining wiring layers, except for the uppermost wiring layers ML-T of the plurality of wiring layers ML, have the same thickness. However, embodiments are not limited to this. For example, among the remaining wiring layers, except for the uppermost wiring layers ML-T of the plurality of wiring layers ML, one or more wiring layers ML may have different thicknesses from one another.

[0060] Each of the plurality of redistribution patterns RL may have a third thickness TRL. In some embodiments, the third thickness TRL may have a value of no less than twice that of the first thickness TML1. For example, the third thickness TRL may be about 1 µm to about 5 µm.

[0061] The cover insulating layer 230 may surround side surfaces of the dummy pattern RL-D and the pad pattern RL-P. The cover insulating layer 230 may cover the upper surface of the dummy pattern RL-D. The cover insulating layer 230 may cover a part of the upper surface of the pad pattern RL-P and may cover the remaining part, as shown in Fig. 2C.

[0062] On the part exposed without being covered with the cover insulating layer 230 of the upper surface of each of the plurality of pad patterns RL-P, the connection terminal 300 may be arranged as shown in Fig. 2C. In some embodiments, the capping insulating layer 230 and the connection terminal 300 may be spaced apart from each other. Between the capping insulating layer 230 and the connection terminal 300, the upper surface of each of the plurality of pad patterns RL-P may be exposed to the outside without being covered by the capping insulating layer 230 and the connection terminal 300.

[0063] The capping insulation layer 230 may include a first capping insulation layer 232 and a second capping insulation layer 234 provided on the first capping insulation layer 232. The first capping insulation layer 232 may conformally cover the upper surface of the second inter-wiring insulation layer 220 and some surfaces of the plurality of redistribution patterns RL (e.g., at least a part of an upper surface and side surfaces of the redistribution pattern RL). For example, the first capping insulation layer 232 may be formed of a nitride. The second capping insulation layer 234 may cover the first capping insulation layer 232. The second capping insulation layer 234 may be thicker than the first capping insulation layer 232. For example, the second capping insulation layer 234 may be formed of PSPI. Alternatively, in some embodiments, the second capping insulation layer 234 may be formed of an oxide, such as TEOS.

[0064] The connection terminal 300 may include a conductive pillar 310 provided on the pad pattern RL-P and a conductive cap 320 covering an upper surface of the conductive pillar 310, as shown in Fig. 2C.

[0065] In some embodiments, the conductive pillar 310 may include a base pillar 312 and a cover pillar 314 formed on an upper surface of the base pillar 312. The cover pillar 314 may cover the upper surface of the base pillar 312. The base pillar 312 may include, for example, copper (Cu), and the cover pillar 314 may include, for example, at least one of nickel (Ni), Cu, palladium (Pd), platinum (Pt), or gold (Au). In some embodiments, the cover pillar 314 may include Ni. In other embodiments, the cover pillar 314 may have a multi-layer structure including a first layer including Ni and a second layer covering the first layer and including Cu.

[0066] The conductive cap 320 can cover the integrated circuit device 1 ( Fig. 1A and Fig. 1B) to an external device (not shown), and can electrically connect the integrated circuit device 1 and the external device. The conductive cap 32 can comprise, for example, at least one of tin (Sn), indium (In), bismuth (Bi), antimony (Sb), Cu, silver (Ag), Au, zinc (Zn), or lead (Pb).

[0067] In Fig. 2C illustrates that the redistribution via plug RV, the topmost wiring layer ML-T on which the redistribution via plug is disposed, and the connection terminal 300 are aligned in the vertical direction (the Z direction). However, embodiments are not limited thereto. In other embodiments, in the pad pattern RL-P, a portion contacting the connection terminal 300 and a portion connected to the redistribution via plug RV may be spaced apart from each other in the horizontal direction (the X direction, the Y direction, or an XY direction). In this configuration, at least some of the plurality of connection terminals 300 and the plurality of redistribution via plugs RV corresponding to each other may not be aligned in the vertical direction (the Z direction).In this configuration, at least some of the plurality of pad patterns RL-P may serve as redistribution layers for horizontally distributing the plurality of connection terminals 300, instead of arranging the plurality of uppermost wiring layers ML-T on which the plurality of redistribution via contact plugs RV are arranged to serve as sub-pads.

[0068] Fig. 3 is a top view of a layout diagram illustrating an integrated circuit device according to embodiments. Like reference numerals refer to like elements throughout. In the description of Fig. 3 is a repeated description of elements previously described with reference to Fig. 1A to 2C have been omitted for the sake of conciseness.

[0069] Referring to Fig. 3, an integrated circuit device 1a includes a plurality of redistribution patterns RLa. The plurality of redistribution patterns RLa may include a plurality of pad patterns RL-P and a plurality of dummy patterns RL-D.

[0070] The plurality of pad patterns RL-P may be arranged to form at least one column in the horizontal direction (the X direction or the Y direction). In some embodiments, the plurality of pad patterns RL-P may be arranged horizontally in a matrix. The plurality of connection terminals 300 may each be connected to the plurality of pad patterns RL-P.

[0071] Each of the plurality of dummy patterns RL-D may have the shape of a line extending in the first horizontal direction (the X direction) or the second horizontal direction (the Y direction). The plurality of dummy patterns RL-D may have the shape of lines extending in different directions. For example, some of the plurality of dummy patterns RL-D may have the shape of lines extending in the first horizontal direction (the X direction), and others of the plurality of dummy patterns RL-D may have the shape of lines extending in the second horizontal direction (the Y direction) perpendicular to the first horizontal direction (the X direction), as shown in Fig. 3 shown.

[0072] Each of the plurality of dummy patterns RL-D may have the shape of a line extending with a width of not less than 20 µm and a length of about 100 µm to about 400 µm. For example, a ratio between the length and width of each of the plurality of dummy patterns RL-D may be about 5:1 to about 20:1. The plurality of dummy patterns RL-D may be arranged at intervals of not more than about 10 µm. In some embodiments, a ratio between a planar area of ​​the plurality of dummy patterns RL-D and a planar area of ​​intervals between the plurality of dummy patterns RL-D may be about 3.5:1 to about 4.5:1.

[0073] Of the plurality of dummy patterns RL-D, some dummy patterns RL-D extending in the first horizontal direction (the X direction) and other dummy patterns RL-D extending in the second horizontal direction (the Y direction) may have the same width and length. However, embodiments are not limited thereto. In some embodiments, the ratio between the length and width of each of the plurality of dummy patterns RL-D is about 5:1 to about 20:1, and a length or width of each of some dummy patterns RL-D extending in the first horizontal direction (the X direction) may have a different value than that of a length or width of respective other dummy patterns RL-D extending in the second horizontal direction (the Y direction).Alternatively, in some embodiments, although the ratio between the length and width of each of the plurality of dummy patterns RL-D extending in the same direction is about 5:1 to 20:1, each of the plurality of dummy patterns RL-D may have a different length and / or width.

[0074] Fig. 4 is a top view of a layout diagram illustrating an integrated circuit device according to embodiments. Fig. 5A and Fig. 5B are respectively a plan view of a layout diagram and a cross-sectional view showing the integrated circuit device of Fig. 4 according to embodiments. In detail, Fig. 5A is a plan view of a layout diagram showing an enlargement of a region VA of Fig. 4, and Fig. 5B is a cross-sectional view along a line VB-VB' of Fig. 5A. Like reference numerals refer to like elements throughout. A description for Fig. 4 to 5B, previously described with reference to Fig. 1A to 3 was given, was possibly omitted for the sake of conciseness.

[0075] Referring to Fig. 4, an integrated circuit device 2 includes a plurality of redistribution patterns RLa. The plurality of redistribution patterns RLa may include a plurality of pad patterns RL-P, a plurality of power patterns RL-W, and a plurality of dummy patterns RL-D.

[0076] The plurality of pad patterns RL-P may be arranged in at least one column in the horizontal direction (the X direction or the Y direction). In some embodiments, the plurality of pad patterns RL-P may be arranged horizontally in a matrix. The plurality of connection terminals 300 may each be connected to the plurality of pad patterns RL-P.

[0077] Each of the plurality of dummy patterns RL-D may have the shape of a line extending in the first horizontal direction (the X direction) or the second horizontal direction (the Y direction). In some embodiments, the plurality of dummy patterns RL-D may have the shape of lines extending in different directions.

[0078] Each of the plurality of dummy patterns RL-D may have the shape of a line extending with a width of not less than 20 µm and a length of about 100 µm to about 400 µm. For example, a ratio between the length and width of each of the plurality of dummy patterns RL-D may be about 5:1 to about 20:1. The plurality of dummy patterns RL-D may be arranged at intervals of not more than about 10 µm. In some embodiments, a ratio between a planar area of ​​the plurality of dummy patterns RL-D and a planar area of ​​intervals between the plurality of dummy patterns RL-D may be about 3.5:1 to about 4.5:1.

[0079] In Fig. 4 illustrates that the plurality of dummy patterns RL-D extend with the same width and length. However, embodiments are not limited thereto. In some embodiments, the ratio between the length and width of each of the plurality of dummy patterns RL-D may be about 5:1 to about 20:1, and a length or a width of each of some of the plurality of dummy patterns RL-D may have a different value than that of a length or a width of any other of the plurality of dummy patterns RL-D. Alternatively, in some embodiments, the ratio between the planar area of ​​the plurality of dummy patterns RL-D and the planar area of ​​the intervals between the plurality of dummy patterns RL-D may be about 3.5:1 to about 4.5:1, and the length or width of each of the plurality of dummy patterns RL-D may be a different value than that of a length or width of any other of the plurality of dummy patterns RL-D.

[0080] In some embodiments, a ratio between a planar area of ​​the plurality of pad patterns RL-P and a planar area of ​​intervals between the plurality of pad patterns RL-P may have a value that is the same as that of the ratio between the planar area of ​​the plurality of dummy patterns RL-D and the planar area of ​​the intervals between the plurality of dummy patterns RL-D. For example, the ratio between the planar area of ​​the plurality of pad patterns RL-P and the planar area of ​​the intervals between the plurality of pad patterns RL-P may be about 3.5:1 to about 4.5:1.

[0081] Each of the plurality of power patterns RL-W may have the shape of a line extending linearly in the first horizontal direction (the X direction) or in the second horizontal direction (the Y direction), or it may have the shape of a line extending in the first horizontal direction (the X direction) and the second horizontal direction (the Y direction). The power patterns RL-W that have the shape of a line extending in the first horizontal direction (the X direction) and the second horizontal direction (the Y direction) may be referred to as curved or kinked. Fig. 4, it is exemplified that the plurality of power patterns RL-W extending in the second horizontal direction (the Y direction) and the first horizontal direction (the X direction) are curved once. However, embodiments are not limited to this. For example, some of the plurality of power patterns RL-W may have the shape of lines extending in the first horizontal direction (the X direction). Alternatively, in some embodiments, for example, others of the plurality of power patterns RL-W may have the shape of lines with portions that are curved no less than twice and that extend in the first horizontal direction (the X direction) and the second horizontal direction (the Y direction).

[0082] Each of the plurality of pad patterns RL-P may be electrically connected to a redistribution via plug RV and a connection terminal 300. The plurality of dummy patterns RL-D may not be connected to the redistribution via plug RV and the connection terminal 300 and may be electrically isolated from the redistribution via plug RV and the connection terminal 300. Each of the plurality of power patterns RL-W may be electrically connected to at least two redistribution via plugs RV.

[0083] Referring to Fig. 4 and Fig. 5A, a portion of the plurality of dummy patterns RL-D may have the shape of a line extending with the first width WD and the first length LD. For example, the first width WD may have a value of not less than about 20 µm. For example, the first length LD may have a value of about 100 µm to about 400 µm. In some embodiments, the ratio between the first length LD and the first width WD may be about 5:1 to about 20:1. Another portion of the plurality of dummy patterns RL-D may have the shape of a line extending with the first width WD and a length LD1 that is shorter than the first length LD. For example, the length LD1 may be shorter than the first length LD by a width WW of the power pattern RL-W and an interval SWW, which is described in more detail below.

[0084] The plurality of dummy patterns RL-D may be spaced apart in a longitudinal direction at first intervals SDL in the longitudinal direction and in a width direction at first intervals SDW in the width direction. For example, the first interval SDL in the longitudinal direction may have a value of no more than 10 µm. For example, the first interval SDW in the width direction may have a value of no more than 10 µm. In some embodiments, the first interval SDL in the longitudinal direction and the first interval SDW in the width direction may have the same value or similar values.

[0085] In some embodiments, the ratio between the planar area of ​​the plurality of dummy patterns RL-D and the planar area of ​​the intervals between the plurality of dummy patterns RL-D may be about 3.5:1 to about 4.5:1.

[0086] Each of the plurality of power patterns RL-W may have the shape of a line extending with a second width WW and a second length LW, or may extend by curving with a second width WW and a second length LW. For example, the second width WW may have a value of not less than about 20 µm. For example, the second length LW may have a value of about 100 µm to about 400 µm. In some embodiments, a ratio between the second length LW and the second width WW may be about 5:1 to about 20:1.

[0087] The plurality of power patterns RL-W may be spaced from the dummy patterns RL-D in a longitudinal direction at second intervals SWL in the longitudinal direction and in a width direction at second intervals SWW in the width direction. For example, the second interval SWL in the longitudinal direction may have a value of no more than 10 µm. For example, the second interval SWW in the width direction may have a value of no more than 10 µm. In some embodiments, the second interval SWL in the longitudinal direction and the second interval SWW in the width direction may have the same value or similar values.

[0088] In some embodiments, a ratio between a planar area of ​​the plurality of power patterns RL-W and a planar area of ​​intervals between the plurality of power patterns RL-W may have a value that is the same as that of the ratio between the planar area of ​​the plurality of dummy patterns RL-D and the planar area of ​​the intervals between the plurality of dummy patterns RL-D. In some embodiments, the ratio between the planar area of ​​the plurality of power patterns RL-W and the planar area of ​​the intervals between the plurality of power patterns RL-W may be about 3.5:1 to about 4.5:1.

[0089] In some embodiments, a ratio between a length and a width of each of the plurality of power patterns RL-W may be about 5:1 to about 20:1, and a length or a width of each of the plurality of power patterns RL-W may have a different value than that of a length or a width of each other of the plurality of power patterns RL-W. Alternatively, in some embodiments, the ratio between the planar area of ​​the plurality of power patterns RL-W and the planar area of ​​the intervals between the plurality of power patterns RL-W may be about 3.5:1 to about 4.5:1, and the length or the width of each of the plurality of power patterns RL-W may have a different value than that of the length or the width of each other of the plurality of power patterns RL-W.

[0090] Each of the plurality of power patterns RL-W may be electrically connected to at least two redistribution via plugs RV. At least two redistribution via plugs RV may be connected to a bottom surface of each of the plurality of power patterns RL-W. Each of the plurality of power patterns RL-W may be electrically connected to a power-supplied connection terminal 300 of the plurality of connection terminals 300 through the wiring pattern MS and the via plug RV. For example, the power-supplied connection terminal 300 of the plurality of connection terminals 300 may be electrically connected to the power pattern RL-W through the pad pattern RL-P, a via plug RV, the top wiring layer ML-T, and another via plug RV.A power pattern RL-W is electrically connected to at least two redistribution via contact plugs RV and can transmit power supplied to the connection terminal 300 to the integrated circuit device 2.

[0091] In some embodiments, a power pattern RL-W may be connected to another via plug RV connected to a topmost wiring layer ML-T connected by a pad pattern RL-P and a via plug RV and at least two other via plugs RV. Therefore, a power pattern RL-W may be electrically connected to portions of the topmost wiring layer ML-T positioned two-dimensionally in another portion of the integrated circuit device 2 by at least two other via plugs RV.

[0092] As in Fig. As shown in Figure 5B, an upper surface and side surfaces of each of the plurality of power patterns RL-W may be completely covered with the cover insulating layer 230. In the lower surface of each of the plurality of power patterns RL-W, a portion to which at least two via plugs RV are not connected may be covered with the second inter-wiring insulating layer 220.

[0093] For example, when the plurality of pad patterns RL-P on which the plurality of connection terminals 300 are arranged are center pads arranged two-dimensionally in the center of the integrated circuit device 2, as shown in Fig. 4, or edge pads arranged two-dimensionally to be adjacent to edges of the integrated circuit device 2, power loss may occur while power is two-dimensionally transmitted through some of the plurality of connection terminals 300 to a portion of the integrated circuit device 2 spaced apart from the plurality of pad patterns RL-P, or power is two-dimensionally transmitted to other portions of the integrated circuit device 2 through a power pattern RL-W. However, according to various embodiments, power may be transmitted to the integrated circuit device 2 through a power pattern RL-W that is a redistribution pattern RL with a large thickness and width, thereby minimizing power loss.Since power is transmitted to the integrated circuit device 2 with minimized power loss, high-speed operation of the integrated circuit device 2 can be implemented.

[0094] Although a plurality of redistribution patterns RLa including the plurality of power patterns RL-W is formed to be thick in the integrated circuit device 2 according to various embodiments in order to minimize power loss for implementing high-speed operation, since the plurality of redistribution patterns RLa have a two-dimensionally uniform thickness, that is, a ratio between a planar area of ​​the plurality of redistribution patterns RLa and a planar area of ​​the intervals between the plurality of redistribution patterns RLa is about 3.5:1 to about 4.5:1, it is possible to prevent the integrated circuit device 2 from being bent due to the plurality of redistribution patterns RLa.Therefore, the reliability of the integrated circuit device 2 can increase, and the reliability of an electrical connection between the plurality of connection terminals 300 arranged on the plurality of pad patterns RL-P and an external device can increase.

[0095] When the plurality of redistribution patterns RLa are formed to be thick, it may be difficult to detect defects in the plurality of redistribution patterns RLa because distortion may occur in planar shapes of the plurality of redistribution patterns RLa due to grain boundaries between metal layers constituting the plurality of redistribution patterns RL. However, since the plurality of redistribution patterns RLa in the integrated circuit device 2 according to various embodiments includes the plurality of dummy patterns RL-D and the plurality of power patterns RL-W having a large width and length, distortion occurring in the planar shapes of the plurality of redistribution patterns RLa due to the grain boundaries can be minimized. Since a defect that may occur in the plurality of redistribution patterns RLa can be easily detected, the integrated circuit device 2 can be formed without defects.

[0096] Fig. 6 is a top view of a layout diagram illustrating an integrated circuit device according to embodiments. Fig. 7A and Fig. 7B are a top view of a layout diagram and a cross-sectional view, respectively, illustrating an integrated circuit device according to embodiments. In detail, Fig. 7A is a plan view of a layout diagram showing an enlargement of section VIIA of Fig. 6, and Fig. Figure 7B is a cross-sectional view along line VIIB-VIIB' of Fig. 7A. Like reference numerals refer to like elements throughout. A description for Fig. 6 to 7B, previously described with reference to Fig. 1A to 5B was given, may have been omitted for the sake of conciseness.

[0097] With reference to Fig. 6, an integrated circuit device 3 includes a plurality of redistribution patterns RLb. The plurality of redistribution patterns RLb may include a plurality of pad patterns RL-P, at least one power pattern RL-W, a plurality of signal patterns RL-S, and a plurality of dummy patterns RL-D.

[0098] The plurality of pad patterns RL-P may be arranged in at least one column in the horizontal direction (the X direction or the Y direction). The plurality of connection terminals 300 may be connected to the plurality of pad patterns RL-P, respectively. Each of the plurality of dummy patterns RL-D may have the shape of a line extending in the first horizontal direction (the X direction) or the second horizontal direction (the Y direction). Each of the plurality of power patterns RL-W may have the shape of a line extending linearly in the first horizontal direction (the X direction) or the second horizontal direction (the Y direction), or may have the shape of a line extending with a curvature.

[0099] In some embodiments, a ratio between a planar area of ​​the plurality of pad patterns RL-P and a planar area of ​​intervals between the plurality of pad patterns RL-P, a ratio between a planar area of ​​the plurality of dummy patterns RL-D and a planar area of ​​intervals between the plurality of dummy patterns RL-D, and a ratio between a planar area of ​​the plurality of power patterns RL-W and a planar area of ​​intervals between the plurality of power patterns RL-W may have the same value.

[0100] Each of the plurality of signal patterns RL-S may have the shape of a line extending linearly in the first horizontal direction (the X direction) or in the second horizontal direction (the Y direction), or it may have the shape of a line extending with a curvature. In Fig. 6, the plurality of signal patterns RL-S are exemplified as lines extending in the first horizontal direction (the X direction). However, embodiments are not limited thereto. For example, in some embodiments, a portion of the plurality of signal patterns RL-S may be in the form of lines extending in the second horizontal direction (the Y direction). Alternatively, in some embodiments, for example, a portion of the plurality of signal patterns RL-S may be in the form of lines having portions that are curved no less than once and that extend in the first horizontal direction (the X direction) and the second horizontal direction (the Y direction).

[0101] One end of each of the plurality of signal patterns RL-S (e.g., an inner end in the Fig. 7A-7B) may be connected to a redistribution via contact plug RV, and the other end (e.g., an outside end in the example shown in Fig. 7A-7B), each of the plurality of signal patterns RL-S may be connected to a pad pattern RL-P. The redistribution via contact plug RV may be connected to a bottom surface of one end of each of the plurality of signal patterns RL-S. A connection terminal 300 may be disposed on the pad pattern RL-P, which is connected to the other end of each of the plurality of signal patterns RL-S.

[0102] Between the plurality of pad patterns RL-P, the redistribution via contact plug RV may not be connected to a bottom surface of a pad pattern RL-P that is connected to the other end of one of the plurality of signal patterns RL-S. Between the plurality of pad patterns RL-P, the redistribution via contact plug RV may be connected to a bottom surface of a pad pattern RL-P that is not connected to one of the plurality of signal patterns RL-S.

[0103] Each of the plurality of signal patterns RL-S may have the shape of a line extending linearly or extending with a curvature having a third width WS and a third length LS. For example, the third width WS may have a value less than that of the first width WD and the second width WW. For example, the third length LS may have a value of about 100 µm to about 400 µm. In some embodiments, a ratio between the third length LS and the third width WS may have a value greater than that of a ratio between the first length LD and the first width WD.

[0104] The plurality of signal patterns RL-S may be spaced from the other patterns by a third interval SLL in the longitudinal direction and a third interval SSW in the width direction. More specifically, the plurality of signal patterns RL-S may be spaced from the plurality of pad patterns RL-P, the plurality of dummy patterns RL-D, or the other signal patterns RL-S by third intervals SSL in the longitudinal direction and third intervals SSW in the width direction. For example, the third interval SSL in the longitudinal direction may be equal to or larger than the first interval in the longitudinal direction (SDL in Fig. 2A or Fig. 5A). For example, the third interval SSW in the latitude direction may have a larger value than that of the first interval SDW in the latitude direction and the second interval SWW in the latitude direction.

[0105] In some embodiments, a ratio between a planar area of ​​the plurality of signal patterns RL-S and a planar area of ​​intervals between the plurality of signal patterns RL-S may have a different value than that of a ratio between the planar area of ​​the plurality of dummy patterns RL-D and the planar area of ​​the intervals between the plurality of dummy patterns RL-D. For example, the ratio between the planar area of ​​the plurality of signal patterns RL-S and the planar area of ​​intervals between the plurality of signal patterns RL-S may have a larger value than that of the ratio between the planar area of ​​the plurality of dummy patterns RL-D and the planar area of ​​the intervals between the plurality of dummy patterns RL-D.

[0106] Fig. 8 is a flowchart illustrating a method of manufacturing an integrated circuit device according to embodiments. In detail, Fig. 8 is a flowchart illustrating a method for manufacturing the integrated circuit devices 1, 1A, 2 and 3 shown in Fig. 1 to 7B. A description for Fig. 8, which was previously referred to in Fig. 1A to 7B was given, may have been omitted for the sake of conciseness. Fig. 8 is made with reference to Fig. 1A to 7B.

[0107] Referring to Fig. 8, in operation S100, semiconductor devices are formed on a substrate 110. For example, the device layer 130 comprising the plurality of semiconductor devices 120 is formed on the substrate 110. The substrate 110 may, for example, comprise silicon (Si). Alternatively, in some embodiments, the substrate 110 may comprise a semiconductor element such as Ge or a semiconductor compound such as SiC, GaAs, InAs, or InP.

[0108] At least some of the plurality of semiconductor devices 120 may be transistors. In some embodiments, the plurality of semiconductor devices 120 may be different types of separate devices for forming a DRAM device, an SRAM device, a flash memory device, an EEPROM device, a PRAM device, an MRAM device, or an RRAM device. For example, the plurality of semiconductor devices 120 may be different types of separate devices for forming a high-bandwidth memory (HBM) DRAM device, and the integrated circuit devices 1, 1a, 2, and 3 may be the HBM DRAM devices.

[0109] In other embodiments, the plurality of semiconductor devices 120 may form a logic cell. For example, integrated circuit devices 1, 1a, 2, and 3 may be CPUs, GPUs, or APs.

[0110] A wiring structure is formed in operation S200. For example, the wiring structure MS and the first inter-wiring insulating layer 210 surrounding the wiring structure MS may be formed on the substrate 110 on which the device layer 130 is formed. The wiring structure MS may include the plurality of wiring layers ML and the plurality of via plugs MV connected to the plurality of wiring layers ML.

[0111] In some embodiments, each of the uppermost wiring layers ML-T arranged at the uppermost ends of the plurality of wiring layers ML may have a first thickness TML1, and each of the remaining wiring layers ML may have a second thickness TML2 having a value less than that of the first thickness TML1. For example, the first thickness TML1 may have a value of no more than 0.5 µm. For example, the second thickness TML2 may have a value less than that of the first thickness TML1, that is, a value of no more than about 0.3 µm.

[0112] Redistribution patterns are formed in operation S300. For example, the second inter-wiring insulating layer 220 and the redistribution via plug RV connected to the wiring pattern MS through the second inter-wiring insulating layer 220 may be formed on the wiring pattern MS and the first inter-wiring insulating layer 210, and a plurality of redistribution patterns RL, RLa, and RLb may be formed on the second inter-wiring insulating layer 220 and the redistribution via plug RV.

[0113] The plurality of redistribution patterns RL, RLa, and RLb may have a third thickness TRL. The third thickness TRL may have a value not less than twice that of the first thickness TML1. For example, the third thickness TRL may be about 1 µm to about 5 µm.

[0114] In some embodiments, the plurality of redistribution patterns RL may include the plurality of pad patterns RL-P and the plurality of dummy patterns RL-D. In some embodiments, the plurality of redistribution patterns RLa may include the plurality of pad patterns RL-P, the plurality of power patterns RL-W, and the plurality of dummy patterns RL-D. In other embodiments, the plurality of redistribution patterns RLb may include the plurality of pad patterns RL-P, the at least one power pattern RL-W, the plurality of signal patterns RL-S, and the plurality of dummy patterns RL-D.

[0115] After forming the plurality of redistribution patterns RL, RLa, and RLb, an automatic visual inspection (AVI) can be performed in operation S400. For example, an automatic visual inspection (AVI) can be performed on the plurality of redistribution patterns RL, RLa, and RLb.

[0116] When the plurality of redistribution patterns RL, RLa, and RLb are formed to have a third thickness TRL that is large, it may be difficult to detect defects in the plurality of redistribution patterns RL, RLa, and RLb because distortion may occur in planar shapes of the plurality of redistribution patterns RL, RLa, and RLb due to grain boundaries between metal layers constituting the plurality of redistribution patterns RL, RLa, and RLb.

[0117] However, since the plurality of redistribution patterns RL, RLa, and RLb according to the presently disclosed embodiments include the plurality of dummy patterns RL-D and the plurality of power patterns RL-W having a larger width and length than those of the plurality of pad patterns RL-P or the plurality of signal patterns RL-S, distortion occurring on the planar surfaces of the plurality of redistribution patterns RL, RLa, and RLb due to grain boundaries can be minimized. Therefore, a defect that may occur in the plurality of redistribution patterns RL, RLa, and RLb can be easily detected.Although faults are not directly detected in the plurality of pad patterns RL-P or the plurality of signal patterns RL-S having a smaller width and length, faults in the plurality of redistribution patterns RL, RLa, and RLb can be determined because faults can be detected by the plurality of dummy patterns RL-D and / or the plurality of power patterns RL-W having a larger width and length.

[0118] Therefore, the integrated circuit devices 1, 1a, 2 and 3 can be formed without defects and with improved reliability.

Claims

[1] Integrated circuit device (1, 2) comprising: a wiring structure (MS) comprising a plurality of wiring layers (ML) having a multilayer wiring structure and a plurality of via contact plugs (MV), and a first inter-wiring insulating layer (210) configured to surround the wiring structure (MS) on a substrate (110); a second inter-wiring insulating layer (220) and a plurality of redistribution via contact plugs (RV) connected to the wiring structure (MS) through the second inter-wiring insulating layer (220), on the first inter-wiring insulating layer (210); a plurality of redistribution patterns (RL) comprising a plurality of pad patterns (RL-P) and a plurality of dummy patterns (RL-D) on the second inter-wiring insulating layer (220), wherein each of the plurality of pad patterns (RL-P) and each of the plurality of dummy patterns (RL-D) has a thickness greater than a thickness of each of the plurality of wiring layers (ML); and a cover insulating layer (230) arranged to cover a portion of the plurality of redistribution patterns (RL), wherein the plurality of dummy patterns (RL-D) extend in lines in a horizontal direction parallel to the substrate (110) and are completely surrounded by the second inter-wiring insulating layer (220) and the covering insulating layer (230) so as to be electrically insulated from each other, wherein the plurality of dummy patterns (RL-D) are spaced apart from each other in a longitudinal direction (X) at first intervals in the longitudinal direction (SDL) and in a width direction (Y) at first intervals in the width direction (SDW), and wherein each of the plurality of dummy patterns (RL-D) has a first width (WD) and a first length (LD) and extends in the horizontal direction. [2] The integrated circuit device (1, 2) according to claim 1, wherein each of the first intervals in the longitudinal direction (SDL) and each of the first intervals in the width direction (SDW) has a value of not more than 1 / 2 of the first width (WD). [3] The integrated circuit device (1, 2) according to claim 2, wherein the plurality of redistribution patterns (RL) further comprises a plurality of power patterns (RL-W) each extending linearly and having a second width (WW) and a second length (LW), and wherein a lower surface of each of the plurality of power patterns (RL-W) is connected to at least two of the plurality of redistribution via contact plugs (RV), and an upper surface and side surfaces of each of the plurality of power patterns (RL-W) are covered with the cover insulating layer (230). [4] The integrated circuit device (1, 2) according to claim 3, wherein both a ratio between the first length (LD) and the first width (WD) and a ratio between the second length (LW) and the second width (WW) is 5:1 to 20:

1. [5] The integrated circuit device (1, 2) according to claim 3, wherein each of the first length (LD) and the second length (LW) has a value of not less than 100 µm and each of the first width (WD) and the second width (WW) has a value of not less than 20 µm. [6] The integrated circuit device (1, 2) according to claim 3, wherein each of the first intervals in the longitudinal direction (SDL) and each of the first intervals in the width direction (SDW) has a value of not more than 10 µm. [7] The integrated circuit device (1, 2) according to claim 3, wherein one of the plurality of power patterns (RL-W) is electrically connected to one of the plurality of connection terminals (300) through one of the plurality of redistribution via contact plugs (RV), one of the plurality of wiring layers (ML), another of the plurality of redistribution via contact plugs (RV), and one of the plurality of pad patterns (RL-P). [8] The integrated circuit device (1, 2) according to claim 1, wherein a thickness of each of the plurality of redistribution patterns (RL) has a value of not less than twice a thickness of each of the plurality of wiring layers (ML). [9] The integrated circuit device (1, 2) according to claim 8, wherein the thickness of each of the plurality of redistribution patterns (RL) has a value of not less than 1 µm, and a thickness of an uppermost wiring layer (ML-T) arranged at the uppermost end of the plurality of wiring layers (ML) has a value of not more than 0.5 µm. [10] The integrated circuit device (1, 2) according to claim 1, wherein a ratio between a planar area of ​​the plurality of redistribution patterns (RL) and a planar area of ​​intervals between the plurality of redistribution patterns (RL) is 3.5:1 to 4.5:

1. [11] Integrated circuit device (1, 2) comprising: a wiring structure (MS) comprising a plurality of wiring layers (ML) having a multilayer wiring structure and a plurality of via contact plugs (MV) and a first inter-wiring insulating layer (210) configured to surround the wiring structure (MS) on a substrate (110); a second inter-wiring insulating layer (220) and a plurality of redistribution via contact plugs (RV) connected to the wiring structure (MS) through the second inter-wiring insulating layer (220) on the first inter-wiring insulating layer (210); a plurality of redistribution patterns (RL) comprising a plurality of pad patterns (RL-P), a plurality of dummy patterns (RL-D), and a plurality of power patterns (RL-W) on the second inter-wiring insulating layer (220), wherein each of the plurality of pad patterns (RL-P), the plurality of dummy patterns (RL-D), and the plurality of power patterns (RL-W) has a thickness of not less than twice a thickness of each of the plurality of wiring layers (ML); a cover insulating layer (230) configured to cover the plurality of dummy patterns (RL-D) and the plurality of power patterns (RL-W) and not to cover at least a portion of the plurality of pad patterns (RL-P); and a plurality of connection terminals (300) each connected to the plurality of pad patterns (RL-P), wherein the plurality of dummy patterns (RL-D) extend in lines in a horizontal direction parallel to the substrate (110) and are completely surrounded by the second inter-wiring insulating layer (220) and the covering insulating layer (230) so as to be electrically insulated from each other, wherein the plurality of dummy patterns (RL-D) are spaced apart from each other in a longitudinal direction (X) at first intervals in the longitudinal direction (SDL) and in a width direction (Y) at first intervals in the width direction (SDW), and wherein each of the plurality of dummy patterns (RL-D) has a first width (WD) and has a first length (LD) and extends in the horizontal direction. [12] The integrated circuit device (1, 2) according to claim 11, wherein a ratio between a planar area of ​​the plurality of redistribution patterns (RL) and a planar area of ​​intervals between the plurality of redistribution patterns (RL) is 3.5:1 to 4.5:

1. [13] The integrated circuit device (1, 2) according to claim 11, wherein a part of a lower surface of each of the plurality of power patterns (RL-W) is covered with the second inter-wiring insulating layer (220), and at least two of the redistribution via plugs (RV) are connected to a remaining part not covered with the second inter-wiring insulating layer (220), and wherein an upper surface and side surfaces of each of the plurality of power patterns (RL-W) are covered with the capping insulating layer (230). [14] The integrated circuit device (1, 2) according to claim 11, wherein each of the first intervals in the longitudinal direction (SDL) and each of the first intervals in the width direction (SDW) has a value of not more than 1 / 2 of the first width (WD). [15] Integrated circuit device (1, 2) according to claim 14, wherein a ratio between the first length (LD) and the first width (WD) is 5:1 to 20:

1. [16] Integrated circuit device (1, 2) comprising: a device layer (130) comprising a plurality of semiconductor devices (120) on a substrate (110); a wiring structure (MS) comprising a plurality of wiring layers (ML) with a multilayer wiring structure having a topmost wiring layer (ML-T) and a plurality of via contact plugs (MV) on the device layer (130); a first inter-wiring insulating layer (210) configured to surround the wiring structure (MS) on the device layer (130); a second inter-wiring insulating layer (220) on the first inter-wiring insulating layer (210) and the wiring structure (MS); a plurality of redistribution via contact plugs (RV) connected to the topmost wiring layer (ML-T) through the second inter-wiring insulating layer (220); a plurality of redistribution patterns (RL) comprising a plurality of pad patterns (RL-P), a plurality of dummy patterns (RL-D), and a plurality of power patterns (RL-W), wherein each of the plurality of pad patterns (RL-P) is connected to one of the plurality of redistribution via contact plugs (RV) on the second inter-wiring insulating layer (220), each of the plurality of dummy patterns (RL-D) extends in a line in a horizontal direction parallel to the substrate (110), and each of the plurality of power patterns (RL-W) is connected to at least two of the plurality of redistribution via contact plugs (RV) and has a thickness of not less than twice a thickness of the uppermost wiring layer (ML-T); a cover insulating layer (230) configured to cover the plurality of dummy patterns (RL-D) and the plurality of power patterns (RL-W); and a plurality of connection terminals (300) each connected to the plurality of pad patterns (RL-P), each of the plurality of connection terminals (300) comprising a conductive column (310) and a conductive cap (320) configured to cover an upper surface of the conductive column (310), wherein the plurality of dummy patterns (RL-D) are completely surrounded by the second inter-wiring insulating layer (220) and the cover insulating layer (230) and are electrically insulated from each other, and wherein, of an upper surface, side surfaces and a lower surface of each of the plurality of power patterns (RL-W), a portion not connected to the at least two redistribution via contact plugs (RV) is covered with the second inter-wiring insulating layer (220) and the cover insulating layer (230), wherein the plurality of dummy patterns (RL-D) are spaced apart from each other in a longitudinal direction (X) at first intervals in the longitudinal direction (SDL) and in a width direction (Y) at first intervals in the width direction (SDW), and wherein each of the plurality of dummy patterns (RL-D) has a first width (WD) and a first length (LD) and extends in the horizontal direction. [17] The integrated circuit device (1, 2) according to claim 16, wherein intervals between the plurality of dummy patterns (RL-D) each have a value of not more than 1 / 2 of a width (WD) of each of the plurality of dummy patterns (RL-D). [18] The integrated circuit device (1, 2) according to claim 16, wherein both a ratio between a planar area of ​​the plurality of dummy patterns (RL-D) and a planar area of ​​intervals between the plurality of dummy patterns (RL-D) and a ratio between a planar area of ​​the plurality of power patterns (RL-W) and a planar area of ​​intervals between the plurality of power patterns (RL-W) is 3.5:1 to 4.5:

1. [19] The integrated circuit device (1, 2) according to claim 16, wherein a ratio between a length and a width of each of the plurality of dummy patterns (RL-D) is 5:1 and 20:

1. [20] The integrated circuit device (1, 2) according to claim 16, wherein each of the plurality of dummy patterns (RL-D) extends with a width of not less than 20 µm and a length of 100 µm to 400 µm.

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