BSI chip with a rear alignment mark

Abstract

Procedure, comprehensive: Forming image sensors (26) in a semiconductor substrate (24), wherein a first alignment mark (32C) is formed near a front face (24A) of the semiconductor substrate (24); Performing a backside polishing process to thin the semiconductor substrate (24); Forming a second alignment mark (56; 60) on the back (24B') of the semiconductor substrate (24); Forming a third alignment mark (70), wherein the formation of the third alignment mark (70) comprises etching the semiconductor substrate (24) to form trenches (66) extending from the back side (24B') of the semiconductor substrate (24) into the semiconductor substrate (24) and depositing a dielectric layer (68) to fill the trenches (66); and Forming a feature (92, 94) on the back side of the semiconductor substrate (24B'), wherein the feature is formed using the second alignment mark (60) and / or the third alignment mark (70) for alignment.

Description

STATE OF THE ART

[0001] Solid-state image sensors operate by sensing light. Typically, solid-state image sensors comprise complementary metal-oxide-semiconductor (CMOS) and charge-coupled device (CCD) sensors, which are widely used in various applications, such as digital still cameras (DSCs), mobile phone cameras, digital video (DVs), and digital video recorders (DVRs). These solid-state image sensors use an array of image sensing elements, with each image sensing element including a photodiode and other elements to absorb light and convert the sensed light into digital data or electrical signals.

[0002] Front-illumination CMOS image sensors (FSI CMOS image sensors) and back-illumination CMOS image sensors (BSI CMOS image sensors) are two types of CMOS image sensors. FSI CMOS image sensors are operable to detect light projected from their front surfaces, while BSI CMOS image sensors are operable to detect light projected from their back surfaces. When light is projected into FSI CMOS image sensors or BSI CMOS image sensors, photoelectrons are generated and then sensed by light sensing devices in the pixels of the image sensors. The more photoelectrons generated, the higher the quantum efficiency (QE) of the image sensors, thus improving the image quality of CMOS image sensors.

[0003] An image sensor and a corresponding manufacturing method are known from US 2013 / 0069190 A1. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying figures. It should be noted that, in accordance with industry standard practice, various features are not drawn to scale. Indeed, the dimensions of the various features may be arbitrarily exaggerated or reduced for the sake of clarity. Fig. 1 to 16 illustrate cross-sectional views of intermediate stages in forming an image sensor chip according to some embodiments. Fig. 17 shows the circuit diagram of a pixel of an image sensor according to some embodiments. Fig. 18 shows a top view of the zoning of an image sensor chip according to some embodiments. Fig. 19 shows an example of an alignment mark according to some embodiments. Fig. 20 illustrates alignment marks and the processes that may use the alignment marks, according to some embodiments. Fig. 21 illustrates a process flow for forming an image sensor chip according to some embodiments. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments, or examples, for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition is for the purpose of simplicity and clarity and does not, in itself, prescribe any relationship between the various embodiments and / or configurations discussed.

[0006] In addition, terms relating to spatial relativity, such as "underlying," "beneath," "lower," "overlying," "upper," and the like, may be used herein for ease of discussion to describe the relationship of one element or feature to another element or feature(s) as illustrated in the figures. The terms relating to spatial relativity are intended to encompass various orientations of the device being used or operated in addition to the orientation illustrated in the figures. The device may be oriented in a different manner (rotated 90 degrees or oriented differently), and the terms relating to spatial relativity used herein may be equally construed accordingly.

[0007] A backside illumination (BSI) image sensor chip and the method of forming the same are provided according to some embodiments of the present disclosure. The intermediate stages in forming the BSI image sensor chip are illustrated according to some embodiments of the present disclosure. Some variations of some embodiments are discussed. Embodiments discussed herein are intended to provide examples to enable making or using the subject matter of this disclosure, and one of ordinary skill in the art will readily understand modifications that may be made while remaining within the contemplated scope of various embodiments. Like reference numerals are used to refer to like elements throughout the various views and embodiments.Although embodiments of methods may be discussed as being performed in a particular order, other embodiments of methods may be performed in any logical order. According to some embodiments of the present disclosure, a backside alignment mark is formed on the backside of the BSI image sensor chip, and the backside alignment mark is formed by aligning it with a frontside alignment mark. The backside alignment mark is formed at a time when it is still possible to view the frontside alignment mark from the backside. In the backside processes for forming the BSI image sensor chip, the backside alignment mark may be used for alignment.

[0008] Fig. 1 to 16 show cross-sectional views of intermediate stages in the formation of a backside alignment mark(s) according to some embodiments of the present disclosure. The corresponding processes are also schematically shown in the Fig. The process flow 200 shown in Figure 21 is reproduced.

[0009] Fig. 1 shows the formation of an initial structure of an image sensor chip 22, which may be a portion of a wafer 20 having multiple image sensor chips 22 therein. The image sensor chip 22 includes a semiconductor substrate 24. According to some embodiments of the present disclosure, the semiconductor substrate 24 is a crystalline silicon substrate. According to other embodiments of the present disclosure, the semiconductor substrate 24 includes an elemental semiconductor such as germanium, a compound semiconductor including silicon carbon, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide, an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP, or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used.Throughout the specification, a main surface 24A of the substrate 24 is referred to as a front surface of the semiconductor substrate 24, and a main surface 24B is referred to as a back surface of the semiconductor substrate 24. The surfaces 24A and 24B may be located on a (100) or (001) surface plane.

[0010] Isolation regions 32, alternatively referred to as STI (shallow trench isolation) regions 32, are formed to extend into the semiconductor substrate 24 to define regions (such as active regions). According to some embodiments of the present disclosure, the STI regions 32 include multiple portions having different functions. For example, the STI regions 32 include an STI grid 32A, a landing pad 32B for forming a metal pad, and a front-side alignment mark 32C. The STI grid 32A represents a grid for forming an image sensor array therein. The landing pad 32B may be a pad sufficiently large to accommodate a metal pad, as will be discussed in subsequent sections. The front side alignment mark 32C may have structured STI areas that have a unique structure, which is why they act as an alignment mark.The alignment mark 32C may be used for alignment purposes when forming front-side structures. According to some embodiments of the present disclosure, the height H1 of the alignment mark 32C may range between approximately 100 nm (approximately 1,000 Å) and approximately 200 nm (approximately 2,000 Å). According to some embodiments of the present disclosure, the alignment mark 32C is formed in a metal pad region 112 (. Fig. 18). According to other embodiments, the alignment mark 32C is formed in any other region including a scribe frame region 114, a pixel region 100 (if clearances are available) in which image sensors are arranged, or the like. Fig. 19 shows an example top view of an alignment mark having the structure that may be adopted by alignment mark 32C according to some embodiments of the present disclosure. For example, the stripes and a cross may be STI regions or the spaces between the STI regions. Alignment mark 32C may also adopt any other usable structures.

[0011] With reference to Fig. 1, image sensors 26 are formed extending from the front surface 24A into the semiconductor substrate 24. Forming the image sensors 26 may include implantation processes. The image sensors 26 are configured to convert light signals (photons) into electrical signals. The image sensors 26 may be photosensitive metal-oxide-semiconductor (MOS) transistors, photosensitive diodes, or the like. Throughout the description, the image sensors 26 are alternatively referred to as photodiodes 26, although they may be other types of image sensors. According to some embodiments of the present disclosure, the photodiodes 26 form an image sensor array. Each of the photodiodes 26 may be located in a grid unit of the grid formed by the STI regions 32A.

[0012] Fig. 1 also shows pixel units 30 having at least some portions in the active areas defined by the STI grid 32A. Fig. 17 shows a circuit diagram of an example of a pixel unit 30. According to some embodiments of the present disclosure, the pixel unit 30 includes a photodiode 26 having an anode coupled to electrical ground GND and a cathode coupled to a source of a transfer gate transistor 34. The drain of the transfer gate transistor 34 may be coupled to a drain of a reset transistor 38 and a gate of a source follower 42. The reset transistor 38 has a gate coupled to a reset line RST. A source of the reset transistor 38 may be coupled to a pixel supply voltage VDD. A floating diffusion capacitor 40 may be coupled between the source / drain of the transfer gate transistor 34 and the gate of the source follower 42. The reset transistor 38 is used to preset the voltage on the floating diffusion capacitor 40 to VDD.A drain of source follower 42 is coupled to a supply voltage VDD. A source of source follower 42 is coupled to a row selector 43. Source follower 42 provides a high-impedance output for pixel unit 30. Row selector 43 acts as the select transistor of the respective pixel unit 30, and the gate of row selector 43 is coupled to select line SEL.

[0013] With further reference to Fig. 1 is a transistor as an example of the devices (such as transistors 34, 38, 42 and 44 in Fig. 17) in the pixel unit 30. For example, the transfer gate transistor 34 in Fig. 1 as an example. According to some embodiments of the present disclosure, each of the photodiodes 26 is electrically coupled to a first source / drain region of the transfer gate transistor 34, which includes a gate 28 and a gate dielectric 31. The gate dielectric 31 contacts the front surface 24A of the substrate 24. The first source / drain region of the transfer gate transistor 34 may be shared by corresponding connected photodiodes 26. The floating diffusion capacitor 40 is formed in the substrate 24, for example, by implanting a p-type impurity and an n-type impurity into the substrate 24 to different depths to form a pn junction that acts as the floating diffusion capacitor 40.The floating diffusion capacitor 40 may be formed in a second source / drain region of the transfer gate transistor 34, and therefore, one of the capacitor plates of the floating diffusion capacitor 40 is electrically coupled to the second source / drain region of the transfer gate transistor 34. The photodiodes 26, the respective transfer gate transistors 34, and the floating diffusion capacitors 40 in the same active region form the pixel units 30, as also shown in FIG. Fig. 1 marked.

[0014] Fig. 18 shows a schematic zoning scheme of the BSI chip 22 according to some embodiments of the present disclosure, and Fig. 1 shows the cross-sectional view obtained from the reference cross-section 1-1 as shown in Fig. 18. The BSI chip 22 may have a pixel area 110 in which the pixel units ( Fig. 1), wherein the pixel units are also formed as an array. Scribing frame regions 114 are formed as a grid throughout the respective wafer to separate the BSI image sensor chips 22 from each other. The metal pad region 112 (which also represents a perimeter region) is formed between the scribing frame region 114 and the pixel region 110. According to some embodiments of the present disclosure, a perimeter region 112 may be formed as a ring surrounding the pixel region 110, as shown in Fig. 18. According to alternative embodiments, instead of forming a ring, the perimeter region 112 extends to one side, two sides, or three sides of the pixel region 110, but not to the remaining side(s).

[0015] With further reference to Fig. 1, a contact etch stop layer 29 is formed on the substrate 24 and transistors, such as the transfer gate transistors 34. The CESL 29 may be formed from silicon oxide, silicon nitride, silicon carbon nitride, or the like, or multiple layers thereof. The CESL 29 may be formed using a conformal deposition process, such as atomic layer deposition (ALD) or chemical vapor deposition (CVD). An interlayer dielectric layer (ILD) 33 is formed over the CESL 29. The ILD 33 may include a dielectric material formed, for example, using flowable chemical vapor deposition (FCVD), spin-on coating, CVD, or other deposition process. The ILD 33 may also be formed from an oxygen-containing dielectric material comprising an oxide, such assilicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG) or the like.

[0016] A front-side interconnect structure 44 is formed over the semiconductor substrate 24. The front-side interconnect structure 44 is used to electrically connect the devices in the image sensor chip 22 to each other and to other package components. The front-side interconnect structure 44 includes dielectric layers 46 and metal lines 48 and vias 50 in the dielectric layers 46. Throughout this description, the metal lines 48 in a same dielectric layer 46 are collectively referred to as a metal layer. The front-side interconnect structure 44 may include multiple metal layers. According to some embodiments of the present disclosure, the dielectric layers 46 include low-k dielectric layers. The low-k dielectric layers have low k values, for example, lower than 3.8 and possibly lower than approximately 3.0.

[0017] A surface dielectric layer 52 is formed on a top dielectric layer of wafer 20. Surface dielectric layer 52 may be formed from a non-low-k dielectric material having k values ​​greater than or equal to approximately 3.8. According to some embodiments of the present disclosure, surface dielectric layer 52 is formed from or includes silicon oxide.

[0018] Bond pads 54 are further formed on the top surface of wafer 20. Bond pads 54 may be formed of or comprise copper. Bond pads 54 may also include barrier layers surrounding the copper. The top surfaces of bond pads 54 may be coplanar with the top surface of surface dielectric layer 52.

[0019] Next, with reference to Fig. 2 the wafer 20 is bonded to a wafer 120. The corresponding process is described as process 202 in the Fig. 21. According to some embodiments of the present disclosure, bonding is performed using hybrid bonding. Accordingly, the surface dielectric layer 52 in wafer 20 is bonded to a surface dielectric layer 252 in wafer 120 via fusion bonding, forming, for example, SO-Si interconnects. The bond pads 54 of wafer 20 are also formed to metal pads 254 in wafer 120 via direct metal-to-metal bonding.

[0020] According to some embodiments of the present disclosure, wafer 120 includes chips 222 further including logic circuits 226 therein. Logic circuits 226 may include the application circuitry used for processing and utilizing the electrical signal acquired from BSI chip 22. For example, logic circuits 226 may include one or more image signal processing (ISP) circuits used to process the image-related signals acquired from image sensor chip 22. The image signal processing (ISP) circuits may include analog-to-digital converters (ADCs), correlated double sampling (CDS) circuits, row decoders, and the like. The circuits in wafer 120 are electrically and signally connected to the image sensor circuits in wafer 20 via bond pads 54 and 254.

[0021] With further reference to Fig. 2, a backside grinding process is performed to grind back the backside 24B to thin the semiconductor substrate 24. The corresponding process is described as process 204 in the Fig. 21. The resulting back surface is shown as 24B' in Fig. 2. The thickness of the substrate 24 can be reduced to less than approximately 20 µm or less than approximately 15 µm so that light from the back surface 24B' can penetrate the semiconductor substrate 24 and reach the photodiodes 26. To improve the light receiving efficiency, the thickness T1 of the substrate 24 is maintained at a relatively large value, for example, greater than approximately 6 µm.

[0022] Fig. 3 shows the formation of an alignment mark 56 having one or more trenches extending from the back surface 24B' into the semiconductor substrate 24. The corresponding process is described as process 206 in the Fig. 21. The trenches may be formed using a dry etching process, which may be carried out using process gases such as C2F6, CF4, SO2, the mixture of HBr, Cl2 and O2, the mixture of HBr, Cl2 and O2, or the mixture of HBr, Cl2, O2 and CF2, etc. The structure of the alignment mark 56 may take on any distinguishable structure that meets the requirements of Fig. 19. The depth D1 of the alignment mark 56 may range between approximately 180 nm (approximately 1,800 Å) and approximately 200 nm (approximately 2,000 Å). The position of the alignment mark 56 is determined using the alignment mark 32C as the alignment mark. Alternatively, the alignment mark 56 is formed using the alignment mark 32C for alignment.

[0023] According to some embodiments of the present disclosure, the alignment mark 56 is formed in the metal pad region 112 ( Fig. 18). According to other embodiments, the alignment mark 56 is formed in any other region including the scribe frame region 114, the pixel region 100 (if clearances are available), or the like. The alignment mark 56 may be vertically aligned with the alignment mark 32C or may be horizontally offset from the alignment mark 32C.

[0024] Fig. Figure 4 shows the formation of backside high absorption areas 58 (BSHA areas). The BSHA areas 58 have the function of focusing light to improve light absorption. The corresponding process is described as process 208 in the Fig. 21. According to some embodiments of the present disclosure, there may be a single or multiple (such as two, three, four, or more) BSHA regions 58 overlapping the same pixel unit 30. According to some embodiments of the present disclosure, forming the BSHA regions 58 includes forming an etch mask over the semiconductor substrate 24. The etch mask has openings aligned with the pixel units, each opening corresponding to a BSHA region 58 to be formed. Forming the etch mask may be performed using one of the alignment mark 32C or the alignment mark 56 for alignment (positioning). The semiconductor substrate 24 is then etched through the opening to form a plurality of pyramid-shaped openings, which may be achieved using a wet etching process such that etching along the lattice direction results in the pyramid-shaped openings.Next, a transparent material, which may be silicon oxide or a similar transparent material, is deposited and filled into the openings. A planarization process, such as a chemical mechanical polishing (CMP) or a mechanical polishing process, is then performed, resulting in BSHA areas 58.

[0025] According to some embodiments of the present disclosure, at the same time that the openings 56 are filled, the alignment mark 56 is also filled with the same material, thereby forming an alignment mark 60. According to alternative embodiments, instead of filling the openings 56 at the same time that the BSHA regions 58 are formed, the openings 56 may be masked during the filling process and filled with other materials in a later process. For example, the openings 56 in the Fig. 6 and / or Fig. 8, and the resulting alignment mark 60 is formed from the same material as that of the dielectric layers 64 ( Fig. 6) and / or 68 ( Fig. 8).

[0026] With reference to Fig. 5, DTI areas 62 (deep trench isolation) are formed. The corresponding process is described as process 210 in the Fig. 21. According to some embodiments of the present disclosure, forming the DTI regions 62 includes etching the semiconductor substrate 24 and filling the resulting trenches with a high-k dielectric material, such as Ta2O5, an opaque material, such as a metal (e.g., tungsten), or combinations thereof. The DTI regions 62 function to prevent light penetration and function to prevent crosstalk of light signals. According to some embodiments of the present disclosure, the DTI regions 62 form a grid, wherein the grid lines of the DTI regions 62 are vertically aligned with the grid lines of the STI grid 32A.

[0027] Fig. 6 shows the formation of a dielectric layer 64. The corresponding process is described as process 212 in the Fig. 21. According to some embodiments of the present disclosure, the dielectric layer 64 is a high-k dielectric layer, which may be made of or include aluminum oxide (Al2O3), hafnium oxide (HfO2), tantalum oxide (Ta2O3), or the like. The thickness of the dielectric layer 64 may range from about 3 nm (about 30 Å) to about 8 nm (about 80 Å). The deposition process may include chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or the like.

[0028] Next, as in Fig. 7, trenches 66 are formed. The corresponding process is shown as process 214 in the Fig. 21. The formation of the trenches 66 can be carried out using a dry etching process. The trenches 66 can take on any distinguishable structure that Fig. 19 as an example. The depth D2 of the trenches 66 may range between approximately 180 nm (approximately 1,800 Å) and approximately 200 nm (approximately 2,000 Å). The position of the trenches 66 is determined using either the alignment mark 32C or the alignment mark 60 as the alignment mark. The trenches 66 may be vertically aligned with the alignment mark 32C or they may be horizontally offset from the alignment mark 32C.

[0029] Fig. 8 shows the formation of a dielectric layer(s) 68 and the filling of the trenches 66 to form an alignment mark 70. The corresponding process is described as process 216 in the Fig. 21. According to some embodiments of the present disclosure, the dielectric layer 68 is a single layer or a composite layer comprising multiple layers. For example, the dielectric layer 68 may be or include a hafnium oxide layer, and may or may not include a tantalum oxide layer (Ta2O5 layer) over the hafnium oxide layer. The thickness of the hafnium oxide layer may range between approximately 3 nm (approximately 30 Å) and approximately 8 nm (approximately 80 Å). The thickness of the tantalum oxide layer may range between approximately 30 nm (approximately 300 Å) and approximately 80 nm (approximately 800 Å). The deposition process may include CVD, PECVD, ALD, or the like. Depending on the widths of the trenches, the trenches 66 may be fully filled at this time, or they may be partially filled and are covered by subsequently deposited layers, such asa dielectric layer 72 in . Fig. 9, further filled.

[0030] Fig. 9 shows the formation of a dielectric layer 72. The corresponding process is described as process 218 in the Fig. 21. According to some embodiments of the present disclosure, the dielectric layer 72 is formed from silicon oxide or a similar transparent material. The thickness of the dielectric layer 72 may range between approximately 100 nm (approximately 1,000 Å) and approximately 200 nm (approximately 2,000 Å). The deposition process may include CVD, PECVD, ALD, or the like.

[0031] Fig. 10 illustrates the formation of a metal grid 76, a metal grounding structure 78, a dielectric layer 74, and trenches 80 according to some embodiments of the present disclosure. The formation process may include etching the dielectric layers 72, 68, and 64 to form one or more openings such that the semiconductor substrate 24 is exposed. The opening(s) may also extend into the semiconductor substrate 24. Next, metallic materials are deposited. According to some embodiments of the present disclosure, the metallic materials include an adhesion layer 73 and a metallic material 75 on the adhesion layer 73. The adhesion layer 73 may include a titanium layer, a titanium nitride layer, or a composite layer including a titanium layer and a titanium nitride layer over the titanium layer.The adhesion layer 73 may have a thickness ranging between approximately 40 nm (approximately 400 Å) and approximately 60 nm (approximately 600 Å). The metallic material 75 may comprise tungsten, chromium, or the like and may have a thickness ranging between approximately 150 nm (approximately 1.5 kÅ) and approximately 250 nm (approximately 2.5 kÅ).

[0032] After deposition, a patterning process is performed using etching, and the metallic material 75 and the adhesion layer 73 are patterned as a metal grid 76 and a ground structure 78. The corresponding process is described as process 221 in the Fig. 21. As viewed from the top of the metal grid 76, the metal grid 76 includes a plurality of first stripes extending in a first direction and a plurality of second stripes extending in a second direction perpendicular to the first direction, the plurality of second stripes being connected to the plurality of first stripes. The grid openings in the metal grid 76 further overlap the grid openings of the DTI region 62 and the STI grid 32A so that light can pass through and be restricted therein and reach the underlying photodiodes 26. The ground structure 78 extends into the openings in the dielectric layers 72, 68, and 64 to physically and electrically contact the semiconductor substrate 24.

[0033] After forming the metal grid 76 and the grounding structure 78, the dielectric layer 74 is deposited. The corresponding process is described as process 223 in the Fig. 21. According to some embodiments of the present disclosure, the dielectric layer 74 is formed from silicon oxide or a similar transparent material. The thickness of the dielectric layer 74 may range between approximately 400 nm (approximately 4,000 Å) and approximately 600 nm (approximately 6,000 Å). The dielectric layer 74 may be planarized in a CMP process or a mechanical polishing process so that its top surface is planar.

[0034] Next, as also in Fig. 10, trenches 80 are formed. The corresponding process is shown as process 224 in the Fig. 21. The formation may be carried out using a dry etching process. The trenches 80 may take on any distinguishable structure that Fig. 19 as an example. The depth D3 of the trenches 80 may range between approximately 200 nm (approximately 2,000 Å) and approximately 300 nm (approximately 3,000 Å). The depth D3 of the trenches 80 is controlled such that the dielectric layer 74 is not etched through to cause the trenches 80 to undesirably reach the high-k dielectric layers, because this may cause the high-k dielectric layers to be exposed and degraded. The position of the trenches 66 is determined using either the alignment mark 60 or the alignment mark 70 as the alignment mark. Because the semiconductor substrate 24 is thick, it may be difficult to use the alignment mark 32C for aligning the trenches 80. The trenches 80 may be vertically aligned with the alignment mark 32C or they may be horizontally offset from the alignment mark 32C.The trenches 80 can be partially or completely filled in subsequent processes and the corresponding filling is also referred to as alignment mark 80.

[0035] Fig. 11 shows the formation of an opening 82, which is formed by etching dielectric layers formed on the backside of the semiconductor substrate 24 and subsequently etching through the semiconductor substrate 24. The corresponding process is described as process 227 in the Fig. 21. Etching is stopped on STI pad 32B, although overetching may occur, so that opening 82 extends partially into STI pad 32B. The etching is controlled so that STI pad 32B is not etched through. Formation of opening 82 may be performed using alignment mark 80, alignment mark 70, or alignment mark 60 to determine its position.

[0036] Next, as in Fig. 12, a dielectric layer 84 is formed as a blanket layer having some portions extending into the opening 82 and other portions overlapping the dielectric layer 74. The corresponding process is described as process 228 in the Fig. 21. According to some embodiments of the present disclosure, the dielectric layer 84 is formed from silicon oxide, which may be formed using PECVD or other suitable techniques. The thickness of the dielectric layer 84 may range from approximately 150 nm (approximately 1,500 Å) to approximately 250 nm (approximately 2,500 Å). The dielectric layer 84 is sometimes referred to as a passivation layer.

[0037] Fig. 13 shows the formation of an opening(s) 86 at the bottom of the opening 82 by etching the ILD 33 and the CESL 29 and possibly the dielectric layers 46 and the interconnect structure 44. The corresponding process is described as process 230 in the Fig. 21. Accordingly, the metal pad 48A is exposed in the interconnect structure 44. The formation of the openings 86 can be performed using the alignment mark 80, the alignment mark 70, or the alignment mark 60 to determine their position.

[0038] Fig. 14 shows the deposition of a metal layer 88. The corresponding process is described as process 232 in the Fig. 21. According to some embodiments of the present disclosure, the metal layer 88 is formed of or includes copper, AlCu, or the like. The thickness of the metal layer 88 may range between approximately 1 μm and approximately 1.5 μm. The formation process may include, for example, PVD, CVD, or similar processes.

[0039] Next, as in Fig. 15, the metal layer 88 is structured to form a metal pad 90 having at least a portion in the opening 82. The corresponding process is described as process 234 in the Fig. 21. The patterning of the metal layer 88 can be performed using the alignment mark 80, the alignment mark 70, or the alignment mark 60 to determine its position.

[0040] In subsequent processes, as in Fig. 16, additional components, such as color filters 94, are formed. Microlenses 96 are then formed. Each of the image sensors 26 is aligned with one of the color filters 94 and one of the microlenses 96. The formation of the color filters 94 and the microlenses 96 may be aligned with the alignment mark 60, 70, or 80. The image sensor chip 22 (and the corresponding wafer 20) is formed in this manner. There may be a protective layer (not shown) formed on the microlenses, for example, by depositing a conformal silicon oxide layer. In subsequent processes, the image sensor wafer 20 and the wafer 120 are sawn into image sensor chips 22 and device chips 222. An image sensor chip 22 and its bonding device chip 222 are collectively referred to as a package 300.Depending on where the alignment marks 60, 70 and / or 80 are formed, the alignment marks 60, 70 and / or 80 may be left in the image sensor chips 22 or they may be removed (for example, if the alignment marks are formed in the scribe frame area 114 (. Fig. 18). When the package 300 is packaged, a wire bonding process may be performed to form a bond ball 92 on the metal pad 90, with a bond wire 93 being attached to the bond ball 92.

[0041] The foregoing processes show the formation of backside alignment marks 60, 70, and 90 as some examples formed at various stages in forming the backside structure. According to other embodiments, the backside alignment marks may be formed at any other stage, such as after forming the dielectric layers 68 and / or 72. According to some embodiments of the present disclosure, any one, two, or all three of the alignment marks 60, 70, and 90 are formed in any combination, provided that the frontside alignment mark 32C continues to be clearly visible from the backside of the image sensor chip 22 when the first of the backside alignment marks 60, 70, and 80 is formed. The later-formed alignment marks 60, 70, and 90 may or may not be formed using the previously formed alignment marks 60, 70, and 80 as alignment marks.

[0042] In the previous examples, the alignment marks are depicted as being filled with a single material from the immediately overlying layer. It should be understood that, depending on the depths and widths of the trenches used to form the alignment marks, the trenches may or may not be completely filled by a subsequently deposited layer. If they are not completely filled, they will be filled by the subsequently deposited materials.

[0043] Fig. 20 shows embodiments of the timing at which alignment marks are formed and examples of feature formation processes that may use the previously formed alignment marks for alignment. The horizontal straight lines represent the processes and features, and the processes and features at lower positions are performed / formed earlier than the processes shown at upper positions. The cross marked with the letter "A" represents the fact that at the stage of forming the openings 86, the underlying dielectric layers and the semiconductor substrate 24 together may have a total thickness that is too large to align with the alignment mark 32C.The cross labeled "B" represents the fact that at the step of forming openings 86, the underlying dielectric layers and the semiconductor substrate together may have a total thickness that is too great to align with alignment marks 60 and 70. Accordingly, alignment marks 60, 70, and / or 80 are formed to provide additional alignment so that the backside features can be aligned with the previously formed backside alignment marks, which are further aligned with the frontside alignment marks. The arrows without crosses represent the possible alignment operations, with the starting points of the arrows representing the operations performed or the features being formed, and the endpoints representing the alignment marks being used. As shown in FIG. Fig. As illustrated in Figure 20, due to the increased thickness when forming multiple backside features, alignment may need to be performed using later-formed backside alignment marks rather than previously formed backside alignment marks. For example, the formation of metal pad 90 may need to be performed using alignment mark 80, while alignment marks 60 and / or 79 may or may not be usable.

[0044] In the embodiments discussed, as illustrated, backside alignment marks are formed by aligning with the frontside alignment marks. According to other embodiments, backside features may be formed first, then frontside features are formed, and the frontside alignment marks may be formed by aligning with the backside alignment marks.

[0045] According to some embodiments of the present disclosure, as in Fig. 20, the alignment mark 80 may be formed by aligning with the alignment mark 70 or 60. The metal grid 76 may be formed by aligning with the alignment mark 70 or 60, and the DTI regions 62 may be formed by aligning with the alignment mark 60 or the alignment mark 32C. The BSHA regions 58 may be formed by aligning with the alignment mark 32C.

[0046] The embodiments of the present disclosure have several advantageous features. To improve the efficiency of light collection by image sensors, the semiconductor substrate of the image sensors may be left thick (for example, thicker than approximately 6 µm) after the backside grinding process. This causes alignment problems for aligning backside features with the frontside alignment marks. According to some embodiments of the present disclosure, better alignment can be achieved by forming alignment marks on the backside of BSI image sensor chips. Furthermore, multiple alignment marks can be formed on the backside of the BSI image sensor chips, so that alignment can be performed well with the processing of forming the backside structure of the BSI image sensor chips.

[0047] The invention is defined by the main claim and the subordinate claims. Further embodiments of the invention are recited in the dependent claims.

Claims

[1] Method comprising: Forming image sensors (26) in a semiconductor substrate (24), wherein a first alignment mark (32C) is formed near a front side (24A) of the semiconductor substrate (24); performing a back-polishing process to thin the semiconductor substrate (24); Forming a second alignment mark (56; 60) on the back side (24B') of the semiconductor substrate (24); Forming a third alignment mark (70), wherein forming the third alignment mark (70) comprises etching the semiconductor substrate (24) to form trenches (66) extending from the backside (24B') of the semiconductor substrate (24) into the semiconductor substrate (24) and depositing a dielectric layer (68) to fill the trenches (66); and Forming a feature (92, 94) on the backside of the semiconductor substrate (24B'), wherein the feature is formed using the second alignment mark (60) and / or the third alignment mark (70) for alignment. [2] The method of claim 1, further comprising, before etching the semiconductor substrate (24), depositing an additional dielectric layer (64) contacting a back surface (24B') of the semiconductor substrate (24), wherein the trenches (66) penetrate through the additional dielectric layer (64). [3] The method of any preceding claim, further comprising forming deep trench isolation regions (62) extending from a back surface (24B') of the semiconductor substrate (24) into the semiconductor substrate (24), wherein the second alignment mark (56; 60) is formed before the deep trench isolation regions (62) are formed. [4] Method according to one of the preceding claims, further comprising: Forming a metal grid (76) on the back side (34B') of the semiconductor substrate (24); and Depositing a dielectric layer (74) on the metal grid (76); and forming a fourth alignment mark (80), wherein forming the fourth alignment mark (80) comprises etching the dielectric layer to form trenches (80). [5] The method of claim 4, wherein the trenches (80) have a depth (D3) that is less than a thickness of the dielectric layer (74). [6] A method according to any one of the preceding claims, wherein forming the feature (94, 96) comprises: Etching the semiconductor substrate (24) to form a through hole (82) passing through the semiconductor substrate; and Forming a bond pad (90) extending into the through-hole (82), the bond pad (90) being electrically connected to a metal feature on a front side (24A) of the semiconductor substrate (24). [7] The method of any preceding claim, wherein forming the feature comprises forming color filters (94), wherein forming the color filters (94) is performed by using the second alignment mark (56, 60) and / or the third alignment mark (70) for alignment. [8] The method of claim 7, further comprising forming a plurality of transparent layers (72, 74, 84) on the backside (24B') of the semiconductor substrate (24), wherein the color filters (94) are formed over the plurality of transparent layers (72, 74, 84). [9] Method comprising: Forming STI regions (32) in a semiconductor substrate (24), the STI regions (32) having a first alignment mark (32C); Forming image sensors (26) in the semiconductor substrate (24); Performing a back-polishing process from a back side (24B') of the semiconductor substrate (24); Forming a second alignment mark (56, 60) in the semiconductor substrate (24), wherein the second alignment mark (56, 60) is formed by using the first alignment mark (32C) for alignment; and Forming color filters (94) on the back (24B') of the semiconductor substrate (24), the method further comprising: Forming a dielectric layer (64) on a back surface (24B') of the semiconductor substrate (24); and Forming a third alignment mark (70) extending into the dielectric layer (64) and the semiconductor substrate, wherein the formation of the color filters (94) is performed by using the second alignment mark (56, 60) and / or the third alignment mark (70) for alignment. [10] The method of claim 9, further comprising forming a plurality of transparent layers (72, 74, 84) on the backside (24B') of the semiconductor substrate (24), wherein the color filters (94) are formed over the plurality of transparent layers (72, 74, 84). [11] The method of any one of the preceding claims 9 or 10, further comprising forming microlenses (96) on the color filters (94), wherein the microlenses (96) are formed by using the second alignment mark (60) for alignment. [12] The method of any one of the preceding claims 9 to 11, further comprising etching the semiconductor substrate (24) from the backside (24B') of the semiconductor substrate (24) by using the second alignment mark (56, 60) or the third alignment mark (70) for alignment, wherein after etching the semiconductor substrate, an STI pad (32B) is exposed in the STI regions (32). [13] The method of claim 12, further comprising etching the STI pad (32B) to form openings (86) extending through the STI pad (32B), wherein the openings (86) are formed by using the second alignment mark (60) or the third alignment mark (70) for alignment. [14] A method according to any one of the preceding claims, further comprising: Forming a metal grid (76) on the back side (34B') of the semiconductor substrate (24); and Depositing a dielectric layer (74) on the metal grid (76); and forming a fourth alignment mark (80), wherein forming the fourth alignment mark (80) comprises etching the dielectric layer to form trenches (80). [15] The method of claim 14, wherein the trenches (80) have a depth (D3) that is less than a thickness of the dielectric layer (74). [16] A method comprising: Forming a plurality of STI regions (32) in a semiconductor substrate, the STI regions comprising: an STI grid (32A); an STI pad (32B); and a first alignment mark (32C); Forming image sensors (26) in the STI grid; and Forming a second alignment mark (60) from a back side (24B') of the semiconductor substrate (24), wherein the second alignment mark (56; 60; 70; 80; 90) is formed by extending onto the first alignment mark (32C), the method further comprising: Forming a dielectric layer (64) on a back surface (24B') of the semiconductor substrate (24); Forming a third alignment mark (70) extending into the dielectric layer (64) and the semiconductor substrate (24); and Forming color filters (94) on the back side (24B') of the semiconductor substrate (24), wherein the color filters (94) are formed using the second alignment mark (60) and / or the third alignment mark (70) for alignment. [17] The method of claim 16, further comprising forming a deep trench isolation grid (62) in the semiconductor substrate (24), the deep trench isolation grid (62) being vertically aligned with the STI grid (32A), and the deep trench isolation grid (62) being formed using the first alignment mark (32C) for alignment. [18] The method of claim 16 or 17, further comprising forming a deep trench isolation grid (62) in the semiconductor substrate (24), the deep trench isolation grid (62) being vertically aligned with the STI grid (32C), and the deep trench isolation grid (62) being formed using the second alignment mark (60) for alignment. [19] The method according to any one of the preceding claims 16 to 18, wherein the second alignment mark (60) is formed to extend into the semiconductor substrate (24). [20] The method of any preceding claim, further comprising etching the semiconductor substrate (24) from the backside (24B') of the semiconductor substrate (24) by using the second alignment mark (56, 60) or the third alignment mark (70) for alignment, wherein after etching the semiconductor substrate, the STI pad (32B) is exposed in the STI regions (32).

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