Semiconductor device with microelectromechanical system devices with improved cavity pressure uniformity

Abstract

A semiconductor device (100) comprising: an interconnect structure (114) disposed over a semiconductor substrate (104); a dielectric structure (130) disposed over the interconnect structure (114); a plurality of cavities (148) disposed in the dielectric structure (130) and arranged in an array (502) having rows (504) and columns (506); a MEMS substrate (136) disposed over the dielectric structure (130), the MEMS substrate (136) defining upper surfaces of the cavities (148), the MEMS substrate (136) comprising a plurality of movable membranes (150), the movable membranes (150) overlying the respective cavity (148); and a plurality of flow connection channels (152) arranged in the dielectric structure (130), wherein the upper surfaces of the flow connection channels (152) are defined by the MEMS substrate (136),and wherein each of the flow connection channels (152) extends laterally between two adjacent cavities (148) of the cavities (148) such that all cavities (148) are in flow communication with one another, wherein the semiconductor device (100) comprises a buffer tank (1002) arranged in the dielectric structure (130) and arranged vertically between the semiconductor substrate (104) and the MEMS substrate (136), wherein the dielectric structure (130) at least partially defines side walls of the buffer tank (1004), wherein the semiconductor device (100) comprises a buffer tank channel (1004) extending laterally from the buffer tank (1004) to one of the cavities (146), wherein the semiconductor device (100) comprises a sealing structure (1006) extending vertically through the MEMS substrate (136) and into the buffer tank channel (1004), wherein the Sealing structure (1006) seals the buffer tank (1002) against the cavity (148),so that the buffer tank (1002) is not in flow connection with the cavity (148).,

Description

REFERENCE TO RELATED APPLICATION

[0001] The present application claims priority over the preliminary US patent application filed on August 27, 2019, with application number 62 / 892,106, the contents of which are incorporated herein by reference. TECHNICAL BACKGROUND

[0002] Microelectromechanical systems (MEMS) are a technology that integrates miniaturized mechanical and electromechanical elements onto a single chip. MEMS devices are often manufactured using microfabrication techniques. In recent years, MEMS devices have found a wide range of applications. For example, MEMS devices are found in mobile phones (e.g., accelerometers, gyroscopes, digital compasses), pressure sensors, microfluidic elements (e.g., valves, pumps), optical switches (e.g., mirrors), imaging devices (e.g., micromachined ultrasonic transducers (MUTs), etc.). List of characters

[0003] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It is conceivable that, in accordance with industry practice, various features are not shown to scale. Rather, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity and discussion. Fig. Figure 1 shows a cross-sectional view of some embodiments of a semiconductor device with MEMS devices with improved cavity pressure uniformity. Fig. 2A-2C show different views of some embodiments of the semiconductor device of the Fig. 1. Fig. Figures 3A-3C show different views of some other embodiments of the semiconductor device. Fig. 1. Fig. 4A-4C show different views of some further embodiments of the semiconductor device of the Fig. 1. Fig. Figure 5 shows a top view of some further embodiments of the semiconductor device of the Fig. 3A-3C, taken along line BB of the Fig. 3A. Fig. Figure 6 shows a top view of some further embodiments of the semiconductor device of the Fig. 5. Fig. Figure 7 shows a top view of some further embodiments of the semiconductor device of the Fig. 5. Fig. Figure 8 shows a cross-section of some further embodiments of the semiconductor device of the Fig. 1. Fig. Figure 9 shows a cross-section of some further embodiments of the semiconductor device of the Fig. 1. Fig. Figure 10 shows a cross-section of some further embodiments of the semiconductor device of the Fig. 1. Fig. Figure 11 shows a top view of some further embodiments of the semiconductor device of the Fig. 10, recorded along line BB of the Fig. 10. Fig. Figure 12 shows a cross-section of some further embodiments of the semiconductor device of the Fig. 1. Fig. Figure 13 shows a cross-section of some further embodiments of the semiconductor device of the Fig. 1. The Fig. Figures 14-22 show a series of cross-sectional views of some embodiments of a method for manufacturing some embodiments of the semiconductor device of the Fig. 10. Fig. Figure 23 shows a flowchart of some embodiments of a method for manufacturing a semiconductor device with MEMS devices with improved cavity pressure uniformity. DETAILED DESCRIPTION

[0004] The present disclosure is now described with reference to the drawings, in which the same reference numerals are used throughout to refer to the same elements, and in which the structures depicted are not necessarily drawn to scale. It is conceivable that this detailed description and the corresponding drawings do not in any way limit the scope of the present disclosure and that the detailed description and the drawings merely provide some examples to illustrate some of the ways in which the inventive concepts can be embodied.

[0005] This disclosure provides many different embodiments or examples of the implementation of various features of this disclosure. To simplify this disclosure, specific examples of components and arrangements are described below. These are, of course, only examples and are not intended to be limiting. For example, the formation of a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features can be formed between the first and second features, so that the first and second features may not be in direct contact. Furthermore, reference numerals may be repeated in the various examples of this disclosure.This repetition serves the purpose of simplicity and clarity and does not in itself dictate any relationship between the various embodiments and / or configurations discussed herein.

[0006] Furthermore, for the sake of simplicity, spatially relative terms such as "below," "under," "below," "above," "above," and the like may be used here to describe the relationship of one element or feature to one or more other elements or features as shown in the drawings. These spatially relative terms are intended to encompass various orientations of the device in use or operation, in addition to the orientation shown in the drawings. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatially relative descriptors used here may themselves be interpreted similarly.

[0007] In some embodiments, a semiconductor device includes a MEMS transducer. The MEMS transducer has several baseline MEMS devices. The baseline MEMS devices are arranged above a semiconductor substrate of the semiconductor device. Each baseline MEMS device has a cavity and a movable diaphragm. Typically, the cavities are separated from each other (for example, the cavities are spaced apart and are not in flow communication with each other).

[0008] One challenge with the aforementioned MEMS transducer is the discrete cavities with different cavity pressures, which negatively impacts the device performance. For example, one of several MEMS basic devices comprises a first cavity with a first cavity pressure (e.g., a pressure within a first discrete cavity), and a second MEMS basic device comprises a second cavity with a second cavity pressure (e.g., a pressure within a second discrete cavity) that differs from the first cavity pressure. The difference between the pressure in the first cavity and the pressure in the second cavity negatively affects the device performance of the MEMS transducer (e.g., the transmit and receive sensitivity of the MEMS transducer decreases).Differences in cavity pressures can be caused by process variations during the manufacture of the semiconductor device (for example, different outgassing rates, time variations in sealing the cavities, pressure fluctuations in a process chamber, etc.).

[0009] Various embodiments of the present application are directed towards a semiconductor device with MEMS devices featuring improved cavity pressure uniformity. The semiconductor device has an interconnect structure arranged over a semiconductor substrate. A dielectric structure is arranged over the interconnect structure. A MEMS substrate is arranged over the dielectric structure. A first MEMS device is arranged over the interconnect structure. The first MEMS device comprises a first cavity located within the dielectric structure and a first movable membrane of the MEMS substrate positioned over the first cavity. A second MEMS device is arranged over the interconnect structure and spaced laterally from the first MEMS device.The second MEMS device comprises a second cavity arranged within the dielectric structure and a second movable membrane of the MEMS substrate positioned above the second cavity. A flow-connecting channel is arranged within the dielectric structure. The flow-connecting channel extends laterally from the first cavity to the second cavity, so that the first and second cavities are in flow communication. Because the first and second cavities are in flow communication, the pressure in the first cavity (for example, the pressure within the first cavity) is essentially equal to the pressure in the second cavity. Therefore, the flow-connecting channel can improve the device performance of the semiconductor device (for example, increased transmit and receive sensitivity).

[0010] Fig. Figure 1 shows a cross-sectional view of some embodiments of a semiconductor device 100 with MEMS devices with improved uniformity of cavity pressure.

[0011] As in Fig. The semiconductor device shown in 1 comprises the semiconductor device 100 an integrated circuit structure (IC structure) 102 The IC structure 102 includes a semiconductor substrate 104 The semiconductor substrate 104 can include any type of semiconductor body (for example, monocrystalline silicon / CMOS bulk, silicon germanium (SiGe), silicon on insulator (SOI), etc.).

[0012] In some embodiments, one or more IC devices are included. 106 on and / or above the semiconductor substrate 104 arranged. The IC devices 106These can be, for example, active electronic devices (e.g., transistors), passive electronic devices (e.g., resistors, capacitors, inductors, fuses, etc.), any other electronic devices, or any combination thereof. For example, one of the IC devices can be... 106 be a metal oxide semiconductor field-effect transistor (MOSFET) that has a pair of source / drain regions 108 , which are in the semiconductor substrate 104 are arranged, a gate dielectric 110 , which is above the semiconductor substrate 104 and between the source / drain areas 108 is arranged, and a gate electrode 112 includes those above the semiconductor substrate 104 is arranged and above the gate dielectric 110 It is located. For better clarity, only one of the IC devices is shown. 106provided with reference numerals. In further embodiments, the IC structure is 102 a complementary metal-oxide-semiconductor (CMOS) structure and the IC devices 106 are part of a CMOS circuit.

[0013] The IC structure 102 includes a connection structure 114 , a first dielectric structure 116 and a second dielectric structure 124 , which are above the semiconductor substrate 104 and the IC devices 106 are arranged. The intermediate connection structure 114 comprises one or more first conductive contacts. 118 , one or more first conductive vias 120, one or more conductive lines 122 , several second conductive vias 126 and several electrodes 128 The first conductive contacts 118, the first conductive vias 120 and the conductive lines 122are in the first dielectric structure 116 embedded. The second dielectric structure 124 is above the first dielectric structure 116 , the first conductive contacts 118, the first conductive vias 120 and the conductive lines 122 arranged. The second conductive vias 126 and the electrodes 128 are in the second dielectric structure 124 embedded. The first conductive contacts 118, the first conductive vias 120, the conductive lines 122 and the second conductive vias 126 couple the IC devices 106 with the electrodes 128 electrically. For example, the first conductive contacts 118, the first conductive vias 120, the conductive lines couple 122 and the second conductive vias 126one or more of the IC devices 106 electrically with a first electrode 128a the electrodes 128 , one or more of the IC devices 106 with a second electrode 128b the electrodes 128 and / or one or more of the IC devices 106 with a third electrode 128c the electrodes 128 For clarity, only one of the first conductive contacts 118, only one of the first conductive vias 120, only one of the conductive lines are shown. 122 , only one of the second conductive vias 126 and only some of the electrodes 128 Each is provided with a reference mark.

[0014] The first conductive contacts 118, the first conductive vias 120, the conductive lines 122 and / or the second conductive vias 126The electrodes can be, for example, a metal (such as copper (Cu), aluminum (Al), tungsten (W), or the like), polysilicon (such as doped polysilicon), another conductive material, or any combination thereof. 128 These materials can be, for example, a metal (such as Al, Cu, aluminum-copper (AlCu), titanium (Ti), or the like), a metal nitride (such as titanium nitride (TiN)), another conductive material, or any combination thereof. The first dielectric structure 116 It comprises one or more stacked dielectric layers, each of which may contain a low-k dielectric (for example, a dielectric material with a dielectric constant of less than approximately 3.9), an oxide (for example, silicon dioxide (SiO2)), or the like. The second dielectric structure 124It contains one or more stacked dielectric layers, each of which may contain a low-k dielectric (for example, a dielectric material with a dielectric constant of less than about 3.9), an oxide (for example, SiO2), or the like. In some embodiments, the second dielectric structure contains 124 a single layer of SiO2.

[0015] A third dielectric structure 130 is above the connection structure 114 arranged. The third dielectric structure 130 includes a first dielectric layer 132 and a second dielectric layer 134 The second dielectric layer 134 is above the first dielectric layer 132 arranged. In some embodiments, the first dielectric layer covers 132 the electrodes 128 .

[0016] The first dielectric layer 132It can be, for example, a nitride (e.g., silicon nitride (SiN)), an oxide (e.g., SiO2), an oxynitride (e.g., silicon oxynitride (SiOXNY)), another dielectric material, or any combination thereof. The second dielectric layer 134 It can be, for example, an oxide (e.g., SiO2), a nitride (e.g., SiN), an oxynitride (e.g., SiOXNY), another dielectric material, or any combination thereof. In some embodiments, the first dielectric layer can be... 132 be a different dielectric material than the second dielectric layer 134 For example, the first dielectric layer 132 The second dielectric layer can be SiN, and the second dielectric layer can be SiO2. While the third dielectric structure 130 This illustrates that they are the first dielectric layer 132 and the second dielectric layer134 includes the third dielectric structure 130 also have a single dielectric layer, or the third dielectric structure 130 can have any combination of any number of dielectric layers.

[0017] A MEMS substrate 136 is above the third dielectric structure 130 and the IC structure 102 arranged. In some embodiments, the MEMS substrate 136 on the third dielectric structure 130 arranged. In further embodiments, a bond interface exists at an interface between the MEMS substrate. 136 and the third dielectric structure 130 In some embodiments, the MEMS substrate is 136 for example with the third dielectric structure 130connected via a bonding process (for example, fusion bonding), whereby the bond interface is located at the interface between the MEMS substrate 136 and the third dielectric structure 130 is formed. The MEMS substrate 136 The MEMS substrate can be, for example, a semiconductor material (e.g., polysilicon, amorphous silicon, monocrystalline silicon, or the like), an oxide (e.g., SiO2), another suitable MEMS substrate, or any combination thereof. In embodiments where the MEMS substrate 136 The semiconductor material, or the semiconductor material it contains, can be doped or undoped. In further embodiments, the MEMS substrate can be... 136 be a single semiconductor material (for example Si, SiGe, Ge, etc.).

[0018] A third dielectric layer 138 is above the MEMS substrate 136and the third dielectric structure 130 arranged. A third conductive via. 140 extends vertically through the third dielectric layer 138 , the MEMS substrate 136 , the third dielectric structure 130 and the second dielectric structure 124 , in order to at least one of the conductive lines 122 to contact, so that the third conductive via 140 electrically with the connection structure 114 is coupled. In some embodiments, the third conductive via extends 140 laterally across an upper surface of the third dielectric layer 138 .

[0019] In some embodiments, the third conductive via is covered 140 a first through-hole 142 from the third dielectric layer 138 , the MEMS substrate 136, the third dielectric structure 130 and the second dielectric structure 124 is arranged. The first via opening 142 extends vertically through the third dielectric layer 138 , the MEMS substrate 136 , the third dielectric structure 130 and the second dielectric structure 124 , to use one of the conductive lines 122 to expose. The first via opening 142 is at least partially due to the third dielectric layer 138 , the MEMS substrate 136 , the third dielectric structure 130 and one of the conductive lines 122 defined. For example, the sidewalls of the first via opening are 142 through the first side walls of the third dielectric layer 138 , first sidewalls of the MEMS substrate 136 , first side walls of the third dielectric structure 130and first side walls of the second dielectric structure 124 defined, and a lower surface of the first via opening 142 is at least partially defined by a first upper surface of one of the conductive lines 122 defined. In further embodiments, the first dielectric structure 116 at least partially the first via opening 142 define. For example, the lower surface of the first via opening. 142 through the first upper surface of one of the conductive lines 122 and a first upper surface of the first dielectric structure 116 defined. It is conceivable that the third conductive via opening 140 It can be one of several fourth conductive vias that extend vertically through the third dielectric layer. 138 , the MEMS substrate 136 , the third dielectric structure 130and the second dielectric structure 124 extend to include the corresponding conductor tracks of the conductive lines 122 to expose, and it should be noted that the first via opening 142 one of several openings in which the multiple fourth conductive vias run.

[0020] One or more secondary conductive contacts 144 are above the MEMS substrate 136 and the third dielectric layer 138 arranged. For better clarity, only one of the second conductive contacts is shown. 144 provided with a reference numeral. In some embodiments, one or more second conductive contacts extend 144 through the third dielectric layer 138 and contact the MEMS substrate 136 In further embodiments, the second conductive contacts 144 electrically with the MEMS substrate 136coupled. The third conductive via 140 and the second conductive contacts 144 They can be electrically coupled to each other. In further embodiments, the third conductive via is... 140 and the second conductive contacts 144 Parts of a conductive layer that extend continuously across the MEMS substrate 136 extends.

[0021] The third dielectric layer 138 It can be, for example, an oxide (e.g., SiO2), a nitride (e.g., SiN), an oxynitride (e.g., SiOXNY), another dielectric material, or any combination thereof. The third conductive via 140This can be, for example, a metal (such as Al, Cu, AlCu, Ti, silver (Ag), gold (Au), or the like), a metal nitride (such as TiN), another conductive material, or any combination thereof. The second conductive contacts 144 These materials can be, for example, a metal (e.g., Al, Cu, AlCu, Ti, Ag, Au, or the like), a metal nitride (e.g., TiN), another conductive material, or any combination thereof. In some embodiments, the third conductive via is... 140 and the second conductive contact 144 made of the same material.

[0022] The semiconductor device 100 includes several MEMS devices 146 , which are above the semiconductor substrate 104 and the first dielectric structure 116 are arranged. The MEMS devices 146They are spaced laterally apart. The MEMS devices 146 Each includes several cavities 148 , several movable membranes 150 and the electrodes 128 The cavities 148 are spaced laterally from each other. The movable membranes 150 are spaced laterally from each other. The movable membranes 150 are parts of the MEMS substrate 136 , which are designed to perform a movement in response to one or more stimuli (for example, pressure, tension, etc.) (for example, bending). In some embodiments, the electrodes 128 spaced laterally from each other. For clarity, only some of the MEMS devices are shown. 146 , some of the cavities 148 and some of the movable membranes 150 each with its respective reference mark.

[0023] The MEMS devices 146include, for example, a first MEMS device 146a , a second MEMS device 146b and a third MEMS device 146c The first MEMS device 146a is located to the side of the second MEMS device 146b and the third MEMS device 146c spaced apart, and the second MEMS device 146b is located to the side of the third MEMS device 146c spaced apart. The first MEMS device 146a includes a first cavity 148a the cavities 148 , a first movable membrane 150a the movable membranes 150 and the first electrode 128a The second MEMS device 146b includes a second cavity 148b the cavities 148 , a second movable membrane 150b the movable membranes 150 and the second electrode 128b The third MEMS device 146c includes a third cavity 148cthe cavities 148 , a third movable membrane 1500 the movable membranes 150 and the third electrode 128c The first cavity 148a is to the side of the second cavity 148b and the third cavity 148c spaced apart, and the second cavity 148b is to the side of the third cavity 148c spaced apart. The first movable membrane 150a is located to the side of the second movable membrane 150b and the third movable membrane 1500 spaced apart, and the second movable membrane 150b is located laterally to the third movable membrane 150c spaced apart.

[0024] Several flow connection channels 152 are in the third dielectric structure 130 arranged. For clarity, only some of the flow connection channels are shown. 152 with their respective reference symbols. The flow connection channels152 extend laterally between the cavities 148 , so that all cavities 148 They are interconnected by flow. In some embodiments, each of the flow-connecting channels extends 152 laterally between two adjacent cavities of the cavities 148 , so that all cavities 148 are connected to each other. Since the cavities 148 The cavity pressures in the cavities are those that are in flow communication with each other. 148 (for example, the pressures within the cavities) 148 ) essentially the same. Thus, the flow connection channels can 152 the performance of the semiconductor device 100 improve (for example, by increasing transmit and receive sensitivity). In some embodiments, the cavity pressures refer to the pressures within the cavities. 148 on the stationary cavity pressures in the cavities 148(for example, pressures in the cavities) 148 , when the MEMS devices 146 are in a state of equilibrium, for example when the movable membranes 150 are not actively in motion).

[0025] For example, the flow connection channels include 152 a first flow connecting channel 152a and a second flow connecting channel 152b The first flow connection channel 152a is in a first part of the third dielectric structure 130 arranged laterally between the first cavity 148a and the second cavity 148b is arranged. The second flow connection channel 152b is in a second part of the third dielectric structure 130 arranged laterally between the second cavity 148b and the third cavity 148c is arranged. The first flow connection channel 152aextends laterally between the first cavity 148a and the second cavity 148b and the second flow connecting channel 152b extends laterally between the second cavity 148b and the third cavity 148c, so that the first cavity 148a , the second cavity 148b and the third cavity 148c are in flow communication with each other. Thus, a first cavity pressure exists in the first cavity. 148a (for example, pressure in the first cavity) 148a) , a second cavity pressure in the second cavity 148b and a third cavity pressure in the third cavity 148c Essentially the same.

[0026] In some embodiments, the MEMS devices 146 Parts (for example, elements) of a MEMS converter 154 the semiconductor device 100 The MEMS converter 154This could be, for example, a MEMS ultrasonic transducer (such as a capacitive micromachined ultrasonic transducer (CMUT), a piezoelectric micromachined ultrasonic transducer (PMUT), or the like), a MEMS pressure sensor, a MEMS microphone, a MEMS biosensor, a MEMS gas sensor, a MEMS infrared sensor (MEMS IR sensor), or another type of MEMS transducer. The flow connection channels 152 can the device performance of the MEMS converter 154 improve (for example, through increased transmit and receive sensitivity). It is conceivable that the MEMS converter 154 in some embodiments one of several MEMS converters of the semiconductor device 100 is.

[0027] In some embodiments, the MEMS converter 154For example, a CMUT. The CMUT can operate as a transmitter by converting electrical signals into acoustic energy (for example, ultrasound waves), and / or the CMUT can operate as a receiver (for example, a sensor) by converting acoustic energy into electrical signals. When operated as a transmitter, the CMUT can receive acoustic energy by applying an electrical signal (for example, an alternating current signal (AC signal)) through the MEMS devices. 146 transmitted electrostatic forces that deflect the movable membranes 150 This causes the movable membranes 150 to generate acoustic energy. In some embodiments, one or more IC devices can be used. 106 the electrical signal through the MEMS devices 146 apply by sending the electrical signal to the electrodes 128 and the MEMS substrate 136 is established (for example, via the first conductive contacts).118 , the first conductive vias 120 , the conductive lines 122 , the second conductive vias 126 , the third conductive vias 140 and the second conductive contacts 144 When operated as a receiver, the acoustic energy applied to the movable diaphragms causes 150 impacts, causing a deflection of the movable membranes 150 , which makes the MEMS devices 146 output an electrical signal (for example, due to the deflections, the changes in the capacitances between the moving membranes) 150 and the electrodes 128 cause). In some embodiments, one or more IC devices may 106 that from the MEMS devices 146Capture and analyze the emitted electrical signal to derive a physical quantity that corresponds to the extent of the deflection of the movable membranes. 150 related (for example, a distance between an object and the MEMS devices) 146 In other embodiments, the electrodes 128 referred to as scanning electrodes.

[0028] In some embodiments, the MEMS devices 146 The CMUT is configured to operate in conjunction with each other (for example, in sync). In further embodiments, an identical operating voltage can be applied to each of the MEMS devices during operation of the CMUT (for example, as a transmitter and / or receiver). 146 Therefore, differences in the cavity pressures of the MEMS devices can occur. 146The transmit and / or receive sensitivity of the CMUT decreases because the differences in cavity pressures lead to fluctuations in the deflections of the movable diaphragms. 150 lead to this. Since the flow connection channels 152 however, laterally between the cavities 148 extend so that each of the cavities 148 in flow communication with each other, the cavity pressures of the cavities are 148 essentially the same. Therefore, the flow connection channels can 152 Increase the transmit and / or receive sensitivity of the CMUT.

[0029] It is conceivable that the MEMS devices 146 In some embodiments, the CMUT comprises several electrodes (not shown) positioned above the MEMS substrate. 136 are arranged. In such embodiments, the multiple electrodes can 128as the lower electrodes and the multiple electrodes that are placed above the MEMS substrate 136 The electrodes arranged above the lower electrodes are referred to as upper electrodes. In further embodiments of this type, the conductive layer can be electrically coupled to the upper electrodes, so that the CMUT can act as a transmitter (for example, by applying the electrical signals via the MEMS devices). 146 via the upper electrodes and the lower electrodes) and / or as receivers (for example, due to the deflections, the changes in capacitance between the upper electrodes (or the movable membranes) 150 ) and the lower electrodes can work.

[0030] Fig. 2A-2C show different views of some embodiments of the semiconductor device 100 the Fig. 1. Fig. Figure 2A shows a cross-sectional view of some embodiments of the semiconductor device. 100 the Fig. 1 along line AA of the Fig. 2B. Fig. Figure 2B shows a top view of some embodiments of the semiconductor device. 100 the Fig. 1, taken along line BB of the Fig. 2A. Fig. Figure 2C shows a cross-sectional view of some embodiments of the semiconductor device. 100 the Fig. 1, taken along line CC of the Fig. 2A and Fig. 2B.

[0031] As in Fig. The flow connection channels are shown in 2A-2C. 152 at least partially through the third dielectric structure 130 defined. In some embodiments, the third dielectric structure defines 130 at least partially the side walls of the flow connection channels 152In further embodiments, second side walls define the third dielectric structure. 130 at least partially the side walls of the flow connection channels 152 For example, as in Fig. Shown in 2A-2C, they define the first sidewalls of the second dielectric layer. 134 the side walls of the flow connection channels 152 In further embodiments, the side walls of the flow connection channels extend 152 vertically along essentially vertical planes that run parallel to each other.

[0032] In some embodiments, the first upper surfaces define the third dielectric structure. 130 at least partially the lower surfaces of the flow connection channels 152 In further embodiments, the first upper surfaces of the first dielectric layer are defined. 132 at least partially the lower surfaces of the respective flow connection channels152 For example, as in Fig. Shown in 2A-2C, they define the first upper surfaces of the first dielectric layer. 132 the lower surfaces of the flow connection channels 152 In further embodiments, the lower surfaces of the flow connection channels extend 152 laterally along essentially horizontal planes that run perpendicular to their respective pairs of essentially vertical planes. In further embodiments, the lower surfaces of the flow connection channels 152 essentially coplanar.

[0033] In some embodiments, the MEMS substrate is defined 136 at least partially the upper surfaces of the flow connection channels 152 In further embodiments, a first lower surface (or first lower surfaces) of the MEMS substrate is defined (or defined). 136 at least partially the upper surfaces of the flow connection channels152 In such embodiments, the first lower surface (or surfaces) of the MEMS substrate extends 136 laterally between the cavities 148 (or are located there).

[0034] In other embodiments, the flow connection channels can 152 through the third dielectric structure 130 through. In such embodiments, the upper surfaces of the flow connection channels 152 through the third dielectric structure 130 defined. In further such embodiments, the flow connection channels can 152 through the first dielectric layer 132 or the second dielectric layer 134 or the flow connection channels 152 both through the first dielectric layer 132 as well as through the second dielectric layer 134 run through it.

[0035] The cavities148 are at least partially due to the third dielectric structure 130 and the MEMS substrate 136 defined. The MEMS substrate 136 defines at least partially the upper surfaces of the cavities 148 In some embodiments, a second lower surface (or second lower surfaces) of the MEMS substrate is defined. 136 at least partially the upper surfaces of the cavities 148 In further embodiments, the lower surfaces of the movable membranes are defined. 150 at least partially the upper surfaces of the cavities 148 In further embodiments, the second lower surface (or surfaces) of the MEMS substrate is (are) 136 essentially coplanar with the first lower surface (or surfaces) of the MEMS substrate 136 .

[0036] The third dielectric structure 130defines at least partially the side walls of the cavities 148 In some embodiments, the third sidewalls define the third dielectric structure. 130 at least partially the side walls of the cavities 148 For example, as in Fig. Shown in 2A-2C, they define the second sidewalls of the second dielectric layer. 134 the side walls of the cavities 148 .

[0037] In some embodiments, the third dielectric structure is defined 130 at least partially the lower surfaces of the cavities 148 In further embodiments, the second upper surfaces of the third dielectric structure are defined. 130 at least partially the lower surfaces of the cavities 148 For example, as in Fig. Shown in 2A-2C, they define the second upper surfaces of the first dielectric layer. 132 the lower surfaces of the cavities 148In further embodiments, the second upper surfaces of the first dielectric layer 132 and the first upper surfaces of the first dielectric layer 132 essentially coplanar.

[0038] Fig. Figures 3A-3C show different views of some other embodiments of the semiconductor device. 100 FIG. \1. Fig. Figure 3A shows a cross-sectional view of some embodiments of the semiconductor device 100 the Fig. 1 along line AA of the Fig. 3B. Fig. 3B shows a top view of some embodiments of the semiconductor device 100 the Fig. 1, taken along line BB of the Fig. 3A. Fig. Figure 3C shows a cross-sectional view of some embodiments of the semiconductor device. 100 the Fig. 1, taken along line CC of the Fig. 3A and Fig. 3B.

[0039] As in Fig. Shown as 3A-3C, they define the first upper surfaces of the second dielectric layer. 134 at least partially the lower surfaces of the respective flow connection channels 152 For example, define how in Fig. 3A-3C shows the first upper surfaces of the second dielectric layer 134 the lower surfaces of the flow connection channels 152 In further embodiments, second upper surfaces of the second dielectric layer can be 134 at least partially the lower surfaces of the cavities 148 define. In further embodiments, the second upper surfaces of the second dielectric layer are 134 and the first upper surfaces of the second dielectric layer 134 essentially coplanar.

[0040] Fig. Figures 4A-4C show different views of some further embodiments of the semiconductor device 100 the Fig. 1. Fig. Figure 4A shows a cross-sectional view of some embodiments of the semiconductor device. 100 the Fig. 1 along line AA of the Fig. 4B. Fig. 4B shows a top view of some embodiments of the semiconductor device 100 the Fig. 1, taken along line BB of the Fig. 4A. Fig. Figure 4C shows a cross-sectional view of some embodiments of the semiconductor device. 100 the Fig. 1, taken along line CC of the Fig. 4A and Fig. 4B.

[0041] As in Fig. Figures 4A-4C, shown, define in some embodiments the second upper surfaces of the second dielectric structure. 124 at least partially the lower surfaces of the respective flow connection channels 152 For example, define how in Fig. 4A-4C shows the second upper surfaces of the second dielectric structure 124the lower surfaces of the flow connection channels 152 In further embodiments, the second sidewalls define the second dielectric layer. 134 partially the side walls of the respective flow connection channels 152 For example, as shown in the drawings 4A-4C As shown, they define the second sidewalls of the second dielectric layer. 134 and the first side walls of the first dielectric layer 132 the side walls of the flow connection channels 152 .

[0042] Fig. Figure 5 shows a top view of some further embodiments of the semiconductor device. 100 the Fig. 3A-3C, taken along line BB of the Fig. 3A.

[0043] As in Fig. Figure 5 shows the MEMS devices. 146 in a first array 502 arranged to have any number of lines 504 and columns 506exhibits (for example, a 1×2 array, a 2×1 array, a 2×2 array, a 3×3 array, etc.). For example, the first array exhibits 502 a first line 504a , a second line 504b , a third line 504c , a first column 506a , a second column 506b and a third column 506c of MEMS devices 146 open. The cavities 148 are arranged in a second array that corresponds to the first array. In some embodiments, the electrodes are 128 in a third array that corresponds to the second array. In further embodiments, the first array 502 in a first direction D1 to the side of the first via opening 142 be spaced apart. In other embodiments, the first via opening can be 142 within the outermost sides of the first array 502 be arranged and located laterally from the MEMS devices146 be spaced apart, which form the first array 502 form.

[0044] The columns 506 are spaced laterally in the first direction Di, and the lines 504 are laterally in a second direction D2 spaced apart, perpendicular to the first direction D1 The MEMS devices 146 , which the lines 504 forming, are laterally in the first direction D1 spaced apart. For example, the second row includes 504b the first MEMS device 146a , the second MEMS device 146b and the third MEMS device 146c The second MEMS device 146b is in the first direction D1 laterally to the side of the first MEMS device 146a spaced apart, and the third MEMS device 146c is in the first direction D1 laterally to the side of the second MEMS device 146b spaced apart.

[0045] The MEMS devices 146 , which the columns 506 forming, are laterally in the second direction D2 spaced apart. For example, the second column includes 506b the second MEMS device 146b , a fourth MEMS device 146d and a fifth MEMS device 146e The fourth MEMS device 146d includes a fourth cavity 148d the cavities 148 , a fourth movable membrane (not shown) of the movable membranes 150 and a fourth electrode 128d the electrodes 128 The fifth MEMS device 146e includes a fifth cavity 148e the cavities 148 , a fifth movable membrane (not shown) of the movable membranes 150 and a fifth electrode 128e the electrodes 128 The flow connection channels 152 include a third flow connection channel 1520and a fourth flow connecting channel 152d The third flow connection channel 1520 is in the third dielectric structure 130 arranged and extends laterally between the second cavity 148b and the fourth cavity 148d , and the fourth flow connection channel 152d is in the third dielectric structure 130 arranged and extends laterally between the second cavity 148b and the fifth cavity 148e , so that the first cavity 148a , the second cavity 148b , the third cavity 148c , the fourth cavity 148d and the fifth cavity 148e are in flow communication with each other. The second MEMS device 146b is located to the side of the fourth MEMS device 146d in the second direction D2 spaced apart, and the fifth MEMS device 146e is located to the side of the second MEMS device146b in the second direction D2 spaced apart.

[0046] Each of the cavities 148 has a center point (for example, a geometric center point when viewed along line BB in Fig. 3A). The center point of each of the cavities 148 is represented by an "X" in the drawings. In some embodiments, the centers of the cavities are 148 the MEMS devices 146 , which the rows 504 form, aligned along planes that extend laterally in the first direction D1 extend. The planes that extend laterally in the first direction D1 extend laterally in essentially straight lines along the first direction D1 extend. The planes that extend laterally in the first direction D1 extend parallel to each other in the first direction D1 extend.

[0047] For example, the centers of the first cavity are 148a , of the second cavity 148b and the third cavity 148c along a first level P1 aligned, which extend laterally in the first direction D1 extends. In other words, the first level extends P1 laterally in the first direction Di and intersects the centers of the first cavity 148a , of the second cavity 148b and the third cavity 148c The first level P1 extends laterally in the first direction D1 in a generally straight line. A second level P2 extends laterally in the first direction Di in an essentially straight line and parallel to the first plane P1 The second level P2 cuts through the centers of the cavities 148 the MEMS devices 146 , the first row 504a form.

[0048] In some embodiments, the centers of the cavities 148 the MEMS devices 146 , which the columns 506 form, aligned along planes that extend laterally in the second direction D2 extend. The planes that extend laterally in the second direction D2 extend, can extend laterally in the second direction along essentially straight lines D2 extend. The planes that extend laterally in the second direction D2 extend, can extend parallel to each other in the second direction D2 extend.

[0049] For example, the centers of the fourth cavity are 148d , of the second cavity 148b and the fifth cavity 148e along a third level P3 aligned, which extend laterally in the second direction D2 extends. In other words, the third level extends P3laterally in the second direction D2 and intersects the centers of the fourth cavity 148d , of the second cavity 148b and the fifth cavity 148e The third level P3 extends laterally in the second direction D2 along an essentially straight line. A fourth level P4 extends laterally in the second direction D2 along an essentially straight line and parallel to the third plane P3 The fourth level P4 cuts through the centers of the cavities 148 the MEMS devices 146 , which is the first column 506a form.

[0050] Each of the flow connection channels 152 It has a centerline. The centerline of each of the flow connection channels 152 is at an equal distance from opposite side walls of a corresponding flow connecting channel 152arranged. The center lines of each of the flow connection channels 152 extend laterally in a direction perpendicular to the direction in which the opposite side walls of the corresponding flow connection channel are oriented. 152 are spaced apart.

[0051] For example, the first flow connecting channel 152a A first side wall and a second side wall opposite the first side wall. The first side wall is separated from the second side wall in the second direction. D2 spaced apart. A center line of the first flow connection channel 152a runs laterally in the first direction D1 and is positioned at an equal distance from the first side wall and the second side wall. The third flow connection channel 152cIt has a third side wall and a fourth side wall, which is opposite the third side wall. The third side wall is separated from the fourth side wall in the first direction. D1 spaced apart. The center line of the third flow connection channel 1520 extends laterally in the second direction D2 and is positioned at an equal distance from the third side wall and the fourth side wall.

[0052] The opposite side walls of each of the flow connection channels 152 extend laterally between two adjacent cavities of the cavities 148 The opposite side walls of each of the flow connection channels 152 They extend laterally in the same direction as the centerline of their respective flow-connecting channels. In some embodiments, the opposite side walls of the flow-connecting channels extend 152laterally parallel to each other. In further embodiments, the opposing side walls of the flow connection channels extend 152 laterally along essentially straight lines.

[0053] For example, the first side wall and the second side wall of the first flow connection channel extend 152a each side between the first cavity 148a and the second cavity 148b The first side wall and the second side wall of the first flow connection channel 152a extend laterally in the first direction Di, which is aligned with the centerline of the first flow connection channel. 152a agrees, from the first cavity 148a to the second cavity 148b The first side wall and the second side wall of the first flow connection channel 152a extend laterally parallel to each other from the first cavity 148a to the second cavity 148bThe first side wall and the second side wall of the first flow connection channel 152a They each extend laterally along an essentially straight line from the first cavity 148a to the second cavity 148b The third side wall and the fourth side wall of the third flow connection channel 152c extend laterally between the second cavity 148b and the fourth cavity 148d The third side wall and the fourth side wall of the third flow connection channel 152c extend laterally in the second direction D2 , which is connected to the center line of the third flow connection channel 1520 agrees, from the fourth cavity 148d to the second cavity 148b The third side wall and the fourth side wall of the third flow connection channel 152c extend laterally parallel to each other from the fourth cavity 148dto the second cavity 148b The third side wall and the fourth side wall of the third flow connection channel 152c They each extend laterally in an essentially straight line from the fourth cavity 148d to the second cavity 148b .

[0054] In some embodiments, the centerlines of the flow connection channels 152 , which are located laterally between the cavities 148 the MEMS devices extend the rows 504 form, aligned along the planes that extend laterally in the first direction D1 extend. For example, the centerline of the first flow connection channel 152a and the center line of the second flow connection channel 152b along the first level P1 aligned, and the centerlines of the flow connection channels 152 , which are located laterally between the cavities 148 the MEMS devices146 extend to the first row 504a forming are along the second level P2 aligned. In further embodiments, the centerlines of the flow connection channels are 152 , which are located laterally between the cavities 148 the MEMS devices 146 extend, which the columns 506 form, aligned along the planes that extend laterally in the second direction D2 extend. For example, the centerline of the third flow connection channel 1520 and the center line of the fourth flow connection channel 152d along the third level P3 aligned, and the centerlines of the flow connection channels 152 , which are located laterally between the cavities 148 the MEMS devices 146 extend to the first column 506a forming are along the fourth level P4 aligned.

[0055] In some embodiments, a center point of the first via opening 142 aligned along one of the planes that point in the first direction D1 extend. For example, as in Fig. 5 shown, the center point of the first through-hole 142 along the first level P1 aligned. In other words, the first level extends P1 in the first direction D1 and intersects the center point of the first via opening 142 .

[0056] In some embodiments, the outlines of the cavities are 148 In top view, each is circular, as in Fig. 5 shown. In other words, when the semiconductor device 100 as in Fig. Figure 5 shows the outlines of the cavities. 148 Each is circular. In such embodiments, the side walls of the cavities are 148curved. In other designs, the outlines of the cavities can be 148 In top view, it could be, for example, square, rectangular, hexagonal, or any other geometric shape.

[0057] In some embodiments, the outlines of the movable membranes are 150 In top view, each is circular, as in Fig. Figure 5 is shown. In other versions, the outlines of the movable membranes can be... 150 In top view, for example, they may have a square, rectangular, hexagonal, or other geometric shape. In other versions, the top-view contours of the electrodes are... 128 each circular, as in Fig. Figure 5 is shown. In other versions, the outlines of the electrodes may vary. 128 In top view, for example, they may have a square, rectangular, hexagonal or other geometric shape.

[0058] The outlines of the cavities 148in the top view, the outlines of the movable membranes 150 in the top view and the outlines of the electrodes 128 In top view, they can have the same geometric shape (for example, circular) as in Fig. Figure 5 is shown. In other versions, the outlines of the cavities may vary. 148 in the top view, the outlines of the movable membranes 150 in the top view and the outlines of the electrodes 128 They may differ in the top view. For example, the outlines of the cavities may differ. 148 in the top view of the outlines of the movable membranes 150 and / or the outlines of the electrodes 128 differ in the top view.

[0059] Each of the cavities 148 has a cavity length which in the first direction D1 is measured, and a cavity width that is measured in the second direction D2 is measured. In embodiments in which the cavities 148Since they are circular, it is estimated that the cavity lengths and cavity widths correspond to the diameters of the cavities. 148 correspond. The flow connection channels 152 have channel widths that correspond to a distance between the opposite side walls of the flow connection channels 152 correspond. For example, the channel width of the first flow connection channel is 152a a distance between the first side wall and the second side wall of the first flow connection channel 152a The channel widths are smaller than the cavity lengths or the cavity widths. In some embodiments, the channel widths are smaller than both the cavity lengths and the cavity widths.

[0060] The flow connection channels 152 have channel lengths that correspond to a distance at which the flow connection channels 152 laterally between two adjacent cavities of the cavities 148The course of events. For example, the length of the first flow connection channel is... 152a a distance at which the first flow connection channel is located 152a to the side of the first cavity 148a to the second cavity 148b extends. In some embodiments, the channel lengths are shorter than the cavity lengths or the cavity widths. In other embodiments, the channel lengths are shorter than the cavity lengths and cavity widths. In still other embodiments, the channel lengths are longer than the channel widths.

[0061] Fig. Figure 6 shows a top view of some further embodiments of the semiconductor device. 100 the Fig. 5.

[0062] As in Fig. Figure 6 shows the MEMS devices in some embodiments. 146 some of the rows 504 compared to MEMS devices 146 some other series 504 laterally in the first directionD1 postponed. For example, the MEMS devices 146 the first row 504a and the MEMS devices 146 the third row 504c in relation to MEMS devices 146 the second row 504b laterally in the first direction D1 shifted. In such embodiments, the centerlines of the flow connection channels can be 152 and the centers of the cavities 148 , between which such flow connection channels extend laterally, are aligned along planes that extend laterally along essentially straight lines. For example, a fifth flow connection channel extends 1520 laterally between the second cavity 148b and the fourth cavity 148d The centerline of the fifth flow connection channel 152e , the center of the second cavity 148b and the center of the fourth cavity 148dare along a fifth level P5 aligned, extending laterally in an essentially straight line. A sixth flow connection channel. 152f extends laterally between the second cavity 148b and the fifth cavity 148e The centerline of the sixth flow connection channel 152f , the center of the second cavity 148b and the center of the fifth cavity 148e are along a sixth level P6 aligned, extending laterally in an essentially straight line.

[0063] Fig. Figure 7 shows a top view of some further embodiments of the semiconductor device 100 the Fig. 5.

[0064] As in Fig. Figure 7 shows the MEMS devices in some embodiments. 146 some of the columns 506 compared to MEMS devices 146 some other columns506 to the side in the second direction D2 postponed. For example, the MEMS devices 146 the second column 506b compared to MEMS devices 146 the first column 506a and the MEMS devices 146 the third column 506c to the side in the second direction D2 shifted. In such embodiments, the centerlines of the flow connection channels can be 152 and the centers of the cavities 148 The flow-connecting channels, between which such channels extend laterally, are aligned along planes that extend laterally along essentially straight lines. For example, a seventh flow-connecting channel extends 152g laterally between the second cavity 148b and the first cavity 148a The centerline of the seventh flow connection channel 152g , the center of the second cavity 148band the center of the first cavity 148a are along a seventh level P7 aligned, extending laterally in an essentially straight line. An eighth flow connection channel. 152h extends laterally between the second cavity 148b and the third cavity 148c The centerline of the eighth flow connection channel 152h , the center of the second cavity 148b and the center of the third cavity 148c are along an eighth level P8 aligned, extending laterally in an essentially straight line.

[0065] Fig. Figure 8 shows a cross-section of some other embodiments of the semiconductor device 100 the Fig. 1.

[0066] As in Fig. Figure 8 shows a fourth dielectric layer 802 above the first dielectric structure 116, the first conductive contacts 118 , the first conductive vias 120 and the conductive lines 122 arranged. The fourth dielectric layer 802 is vertical between the second dielectric structure 124 and the first dielectric structure 116 arranged. The second conductive vias 126 extend vertically through the fourth dielectric layer 802 In some embodiments, the fourth dielectric layer can 802 for example, it may be a low-k dielectric (for example, a dielectric material with a dielectric constant of less than about 3.9), an oxide (for example, silicon dioxide (SiO2)), or the like, or contain such materials.

[0067] An outgassing prevention layer 804 is vertical between the fourth dielectric layer 802 and the second dielectric structure 124arranged. The second conductive vias 126 extend vertically through the outgassing prevention layer 804 The outgassing prevention layer 804 prevents the outgassing of gases (for example, oxygen, carbon dioxide, or the like) from features (structures, characteristics) of the compound structure 114 , located below the outgassing prevention layer 804 are arranged in the cavities 148 In some versions, the outgassing prevention layer can 804 for example, it may be or contain a nitride (for example, SiN), an oxynitride (for example, SiOXNY), another outgassing prevention material, or any combination thereof.

[0068] One or more gas trapping structures 806 are placed above the outgassing prevention layer 804 arranged. In some embodiments, the gas trap structures are 806in the second dielectric structure 124 arranged. The gas trap structures 806 define at least partially the cavities 148 The gas trapping structures 806 are set up, gases within the cavities 148 to absorb and / or consume. The gas trapping structures 806 These materials can include, for example, Al, Cu, W, Ti, Au, another suitable gas trapping material, or any combination thereof. For clarity, only a few gas trapping structures are shown. 806 each with its respective reference mark.

[0069] In some embodiments, the first upper surfaces of the gas trap structures are defined 806 at least partially first lower surfaces of the cavities 148 and the second upper surfaces of the third dielectric structure 130 define at least partially the second lower surfaces of the cavities 148 , as in Fig. 8 shown. The second lower surfaces of the cavities 148 are each above the first lower surfaces of the cavities 148 arranged. The first lower surfaces of the cavities 148 can occur below the lower surfaces of the flow connection channels 152 be arranged. The second lower surfaces of the cavities 148 can be essentially coplanar with the lower surfaces of the flow connection channels 152 be.

[0070] In some embodiments, the gas trap structures 806 directly below the flow connection channels. 152 arranged. The gas trap structures 806 can at least partially connect the flow channels 152 define. In further embodiments, define second upper surfaces of the gas trap structures. 806 at least partially the lower surfaces of the flow connection channels 152 .

[0071] A first passivation layer 808 is above the MEMS substrate 136 arranged, the third dielectric layer 138 , the third conductive via 140 and the second conductive contacts 144 In some embodiments, the first passivation layer 808 with the third dielectric layer 138 , the third conductive via 140 and the second conductive contacts 144 connected. In further embodiments, the first passivation layer can be 808 for example, an oxide (for example, SiO2), a nitride (for example, SiN), an oxynitride (for example, SiOXNY), another dielectric material, or any combination thereof, or containing these.

[0072] In some embodiments, the electrodes 128a thickness (for example, the distance between an upper and a lower surface) between 1000 angstroms (Ω) and 3000 Ω. In further embodiments, the thickness of the first dielectric layer can be 132 between 20 Å and 500 Å. In further embodiments, the thickness of the second dielectric layer can be 134 between 1000 μm and 4000 μm. In further embodiments, the thickness of the MEMS substrate can be 136 between 4.5 micrometers (µm) and 5.5 µm.

[0073] Fig. Figure 9 shows a cross-section of some other embodiments of the semiconductor device 100 the Fig. 1.

[0074] As in Fig. Figure 9 shows one or more ventilation openings. 902 in the MEMS substrate 136 arranged. The ventilation openings 902 extend vertically through the MEMS substrate 136 , so that the ventilation openings 902in flow connection with the cavities 148 and the flow connecting channels 152 stand. In some embodiments, the ventilation openings extend 902 vertically through the MEMS substrate 136 and each empty into the flow connecting channels 152 In other embodiments, the ventilation openings extend 902 vertically through the MEMS substrate 136 and lead into the cavities 148 The ventilation openings 902 are at least partially due to the MEMS substrate 136 defined. For example, the side walls of the ventilation openings are defined. 902 at least partially through second side walls of the MEMS substrate 136 defined. For clarity, only some of the ventilation openings are shown. 902 each with its respective reference mark.

[0075] One or more plugs 904 are above the MEMS substrate136 arranged and covering the ventilation openings 902 off. For better clarity, only one of the plugs is shown. 904 marked with a reference number. The plugs 904 They each cover the ventilation openings. 902 completely off. The plugs 904 are set up so that they fill the cavities 148 , the flow connection channels 152 and the ventilation openings 902 hermetically seal at a reference system pressure. In some designs, the reference system pressure is less than or equal to 2 standard atmospheres (atm). In other designs, the reference system pressure can be less than 0.1 atm (for example, for a MEMS transducer for operation under high vacuum). In still other designs, the reference system pressure can be between 0.5 atm and 2 atm (for example, for a MEMS transducer for operation under standard pressure). Compared to a semiconductor device 100, which have no ventilation openings 902 exhibits, can be used with the ventilation openings 902 the cavities 148 , the flow connection channels 152 and the ventilation openings 902 They are hermetically sealed at a lower reference system pressure, since the plugs 904 at a lower pressure than the MEMS substrate 136 to the third dielectric structure 130 can be bonded. In embodiments in which the semiconductor device 100 the ventilation openings 902 and the plugs 904 The reference system pressure can be less than 0.1 atm.

[0076] In some versions, the plugs can 904For example, they may be or contain a metal (e.g., Al, Cu, AlCu, Ti, Ag, Au, or the like), a metal nitride (e.g., TiN), an oxide (e.g., SiO2), a nitride (e.g., SiN), an oxynitride (e.g., SiOXNY), or the like. In further embodiments, the connectors may 904 made of the same material as the second conductive contact 144 be formed. In further embodiments, the plugs 904 Part of the conductive layer that extends continuously across the MEMS substrate 136 extends.

[0077] Fig. Figure 10 shows a cross-section of some other embodiments of the semiconductor device 100 the Fig. 1.

[0078] As in Fig. As shown in 10, the semiconductor device includes 100 a buffer tank 1002 The buffer tank 1002 is vertical between the semiconductor substrate 104 and the MEMS substrate136 arranged. One or more buffer tank channels 1004 are in the third dielectric structure 130 arranged. The buffer tank channels 1004 extend laterally from the buffer tank 1002 to some of the cavities 148 One or more sealing structures 1006 extend vertically through the third dielectric layer 138 , the MEMS substrate 136 and the third dielectric structure 130 The sealing structures 1006 blocking the buffer tank channels 1004 completely to ensure hermetic seals between the buffer tank 1002 and the cavities 148 to form a system so that the buffer tank is not in flow contact with the cavities 148 The sealing structures are... 1006 are set up, the cavities 148 and the flow connecting channels 152 to seal hermetically at the reference system pressure.

[0079] In some embodiments, the sealing structures form 1006 one or more sealing structure openings 1008 , which are in the third dielectric layer 138 and the MEMS substrate 136 are arranged. The sealing structure openings 1008 extend vertically through the third dielectric layer 138 and the MEMS substrate 136 , to include parts of the buffer tank channels 1004 to expose the openings of the sealing structure. 1008 are at least partially due to the third dielectric layer 138 and the MEMS substrate 136 defined. For example, the side walls of the sealing structure openings are defined. 1008 at least partially through the second side walls of the third dielectric layer 138 and the second side walls of the MEMS substrate 136 defined. In further embodiments, the openings of the sealing structure are 1008in the third dielectric layer 138 , the MEMS substrate 136 and the third dielectric structure 130 arranged. In further embodiments, the openings of the sealing structure are 1008 partially due to the third dielectric structure 130 defined. For example, the side walls of the openings can be 1008 the sealing structure partially through fourth side walls of the third dielectric structure 130 be defined and / or the lower surfaces of the openings 1008 The sealing structure can be at least partially defined by third upper surfaces of the third dielectric structure. 130 be defined.

[0080] The buffer tank 1002 is at least partially due to the third dielectric structure 130 and the MEMS substrate 136 defined. The MEMS substrate 136 defines at least a partial upper surface of the buffer tank 1002In some embodiments, a third lower surface of the MEMS substrate is defined. 136 at least partially the upper surfaces of the buffer tank 1002 In further embodiments, the third lower surface, the second lower surface (or the second lower surfaces) and the first lower surface (or the first lower surfaces) of the MEMS substrate are 136 essentially coplanar.

[0081] The third dielectric structure 130 defines at least part of the side walls of the buffer tank. 1002 In some embodiments, the third dielectric structure is defined 130 , the second dielectric structure 124 , the outgassing prevention layer 804 and the fourth dielectric layer 802 the side walls of the buffer tank 1002 For example, define how in Fig. 10 shows the fourth side walls of the second dielectric layer 134, the third side walls of the first dielectric layer 132 , the first side walls of the second dielectric structure 124 , the first side walls of the outgassing prevention layer 804 and the first sidewalls of the fourth dielectric layer 802 the side walls of the buffer tank 1002 .

[0082] In some embodiments, the first dielectric structure is defined 116 at least partially a lower surface of the buffer tank 1002 For example, defines how in Fig. 10 shows a second upper surface of the first dielectric structure 116 the lower surface of the buffer tank 1002 It is conceivable that other features of the semiconductor device 100 at least partially the lower surface of the buffer tank 1002 can define (for example, one or more of the conductive lines) 122 , one or more of the gas trap structures 806, the third dielectric structure 130 , the second dielectric structure 124 , the outgassing prevention layer 804 , the fourth dielectric layer 802 etc.).

[0083] In some embodiments, the buffer tank channels 1004 essentially similar features (for example, structural features) to the flow connection channels 152 For example, the buffer tank channels 1004 at least partially through the third dielectric structure 130 defined in the same way as the flow connection channels 152 In further embodiments, the buffer tank channels can be 1004 laterally over a larger distance between the buffer tank 1002 and some of the cavities 148 extend as the flow connecting channels 152 laterally between the cavities 148 extend. The sealing structures 1006They can be, for example, a metal (e.g., Al, Cu, AlCu, Ti, Ag, Au, or the like), a metal nitride (e.g., TiN), an oxide (e.g., SiO2), a nitride (e.g., SiN), an oxynitride (e.g., SiOXNY), or the like, or contain such materials. In some embodiments, the sealing structures can be, for example, a metal (e.g., Al, Cu, AlCu, Ti, Ag, Au, or the like), a metal nitride (e.g., TiN), an oxide (e.g., SiO2), a nitride (e.g., SiN), an oxynitride (e.g., SiOXNY), or the like. 1006 made of the same material as the second conductive contacts 144 and / or the plugs 904 be educated.

[0084] Fig. Figure 11 shows a top view of some further embodiments of the semiconductor device 100 the Fig. 10, recorded along line BB of the Fig. 10.

[0085] As in Fig. Figure 11 shows the MEMS devices. 146 of the first array 502 to the side of the buffer tank 1002 in the first direction D1 spaced apart. The buffer tank 1002It has a fifth side wall and a sixth side wall opposite the fifth side wall. The sixth side wall is laterally adjacent to the fifth side wall in the second direction. D2 spaced apart. In some embodiments, the center of the first cavity is 148a , the center of the second cavity 148b , the center of the third cavity 148c , the center of the fourth cavity 148d and / or the center point of the fifth cavity 148e laterally between the fifth side wall and the sixth side wall of the buffer tank 1002 arranged. In further embodiments, the centers of the cavities are 148 each sideways between the fifth side wall and the sixth side wall of the buffer tank 1002 arranged.

[0086] The buffer tank 1002 has a center point (for example, a geometric center point when viewed along line BB in Fig. 11) The center of the buffer tank 1002 is represented by an "X" in the drawings. In some embodiments, the center point of the buffer tank is 1002 aligned along one of the planes that extend laterally in the first direction D1 extend, or along one of the planes that extend laterally in the second direction D2 extend. For example, as in Fig. As shown in 11, this is the center point of the buffer tank. 1002 along the first level P1 aligned. In other embodiments, the center point of the buffer tank is 1002 arranged laterally between two of the planes, which extend laterally in the first direction D1 or two of the planes that extend laterally in the second direction D2 extend.

[0087] The buffer tank 1002 has a first volume. The cavities 148 and the flow connecting channels 152Together they form a second volume. In other words, the second volume is the sum of the volumes of each of the cavities. 148 and the volume of each of the flow connection channels 152 In some embodiments, the first volume is smaller than the second volume. In other embodiments, the ratio of the first volume to the second volume is between 1:15 and 1:5.

[0088] Each of the buffer tank channels 1004 It has a center line. For clarity, only some of the buffer tank channels are shown. 1004 each with its respective reference mark. The center line of each buffer tank channel. 1004 is at an equal distance from opposite side walls of the corresponding buffer tank channel 1004 arranged. The center lines of each of the buffer tank channels 1004extend laterally in a direction perpendicular to the direction in which the opposite side walls of the corresponding buffer tank channel are oriented. 1004 are spaced apart.

[0089] For example, the buffer tank channel includes 1004 a first buffer tank channel 1004a The first buffer tank channel 1004a It has a seventh side wall and an eighth side wall opposite the seventh side wall. The eighth side wall is located away from the seventh side wall in the second direction. D2 spaced apart. A center line of the first buffer tank channel 1004a runs laterally in the first direction D1 and is positioned at an equal distance from the seventh side wall and the eighth side wall.

[0090] In some embodiments, the center lines of the buffer tank channels 1004 aligned along the planes, each extending laterally in the first direction D1extend. For example, the buffer tank channel includes 1004 a second buffer tank channel 1004b The centerline of the first buffer tank channel 1004a is along the first level P1 aligned, and the centerline of the second buffer tank channel 1004b is along the second level P2 aligned. In other embodiments, the centerlines of the buffer tank channels are 1004 each aligned along the planes that extend laterally in the second direction D2 extend.

[0091] In some embodiments, the planes that extend laterally in the first direction intersect. D1 extend, each the sealing structures 1006 For example, the sealing structures consist of 1006 from a first sealing structure 1006a and a second sealing structure 1006b The first level P1 cuts the first sealing structure 1006a , and the second levelP2 cuts the second sealing structure 1006b In further embodiments, the planes that extend laterally in the first direction intersect. D1 extend, each the centers (for example, geometric centers when viewed along line BB from Fig. 11) the sealing structures 1006 In other embodiments, the planes intersect laterally in the second direction. D2 The sealing structures run 1006 (or the centers of the sealing structures) 1006 ).

[0092] In some embodiments, the buffer tank channels extend 1004 side of the buffer tank 1002 up to the cavities 148 , which are in the first column 506a are arranged. In other embodiments, the buffer tank channels run 1004 side of the buffer tank 1002 to the cavities 148 , which are in the first line 504aare arranged.

[0093] Fig. Figure 12 shows a cross-section of some further embodiments of the semiconductor device 100 the Fig. 1.

[0094] As in Fig. As shown in 12, the semiconductor device 100 in some embodiments the buffer tank 1002 , the buffer tank channels 1004 , the sealing structures 1006 , the ventilation openings 902 and the plugs 904 include.

[0095] Fig. Figure 13 shows a cross-section of some further embodiments of the semiconductor device 100 the Fig. 1.

[0096] As in Fig. As shown in Figure 13, the MEMS devices can 146 each contains several MEMS functional structures 1302 to include. For clarity, only one of the MEMS functional structures is shown. 1302 Designated with a reference symbol. The MEMS functional structures 1302are each above the movable membranes 150 arranged. The MEMS functional structures 1302 They are each located above the electrodes 128 In some embodiments, the MEMS functional structures are 1302 spaced laterally from each other and arranged in a fourth array corresponding to the third array. The MEMS functional structures 1302 Examples include a polymer (e.g., polyimide, SU-8, or similar), a metal oxide (e.g., vanadium oxide (VOX)), a piezoelectric material (e.g., lead zirconate tanate (PZT), aluminum nitride (AlN), or similar), an alloy (e.g., mercury-cadmium telluride (HgCdTe), cadmium-tin telluride (CZT), or similar), a metal (e.g., Au, Ag, platinum (Pt), or similar), or similar.

[0097] The type of MEMS converter 154 depends at least partially on the chemical composition of the MEMS functional structures 1302ab. For example, the MEMS functional structures 1302 be formed from PZT. In such embodiments, the MEMS transducer can 154 For example, it could be a PMUT. On the other hand, the MEMS functional structures can be... 1302 It may be formed from VOX. In such configurations, the MEMS converter can be 154 For example, it could be a MEMS-based IR sensor. It's conceivable that the MEMS transducer 154 is not limited to the types of MEMS converter shown above, but that the MEMS converter 154 It can be any type of MEMS transducer (for example, a MEMS pressure sensor, a MEMS biosensor, a MEMS gas sensor, etc.).

[0098] In some embodiments, a second passivation layer is used. 1304 above the MEMS substrate 136 , the third dielectric layer 138 , the third conductive via 140 , the second conductive contacts 144, the first passivation layer 808 and the MEMS functional structures 1302 arranged. In further embodiments, the second passivation layer 1304 with the first passivation layer 808 and the MEMS functional structures 1302 connected. In further embodiments, the second passivation layer can be 1304 for example, an oxide (for example, SiO2), a nitride (for example, SiN), an oxynitride (for example, SiOXNY), an oxynitride (for example, SiOXNY), another dielectric material, or any combination thereof, or containing these.

[0099] Fig. Figures 14-22 show a series of cross-sectional views of some embodiments of a method for manufacturing some embodiments of the semiconductor device. 100 the Fig. 10.

[0100] As in Fig. Figure 14 shows an IC structure. 102 planned. The IC structure 102includes a semiconductor substrate 104 One or more IC devices 106 are on or above the semiconductor substrate 104 formed. In some embodiments, one or more of the IC arrangements comprise 106 a pair of source and drain areas 108 , a gate dielectric 110 and a gate electrode 112 A first dielectric structure 116 , a fourth dielectric layer 802 , an outgassing prevention layer 804 , a second dielectric structure 124 , a connection structure 114 and one or more gas trapping structures 806 are placed above the semiconductor substrate 104 formed. The intermediate connection structure 114 includes one or more initial conductive contacts 118 , one or more first conductive vias 120 , one or more conductive lines 122, several second conductive vias 126 and several electrodes 128 The IC structure 102 can be manufactured using a CMOS manufacturing process.

[0101] Furthermore presented in Fig. 14 is a third dielectric structure 130 , which are above the IC structure 102 is formed. In some embodiments, the third dielectric structure is 130 on the second dielectric structure 124 , the gas trap structures 806 and the electrodes 128 formed. The third dielectric structure can be a first dielectric layer. 132 and a second dielectric layer 134 include those above the first dielectric layer 132 is arranged. In further embodiments, the first dielectric layer can be 132 on the second dielectric structure 124 , the gas trap structures 806 and the electrodes128 are formed. In further embodiments, the second dielectric layer is 134 on the first dielectric layer 132 educated.

[0102] In some embodiments, a method for forming the third dielectric structure comprises 130 the deposition of the first dielectric layer 132 on the second dielectric structure 124 , the gas trap structures 806 and the electrodes 128 and the covering of the same. The first dielectric layer 132 It can be deposited, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), another deposition method, or a combination of the aforementioned methods. In further embodiments, the first dielectric layer can be 132as a conformal layer with a thickness between 20 Å and 500 Å. Then the second dielectric layer is deposited. 134 on the first dielectric layer 132 deposited. The second dielectric layer 134 It can be deposited, for example, by CVD, PVD, ALD, another deposition method, or a combination of the aforementioned methods. In further embodiments, the second dielectric layer can be 134 can be deposited as a conformal layer with a thickness between 1000 Å and 4000 Å.

[0103] As in Fig. As shown in 15, a second via opening is shown 1502 and a buffer tank opening 1504 above the first dielectric structure 116 formed. The second via opening 1502 is to the side of the buffer tank opening 1504 spaced apart. The second via opening 1502 lays one of the conductive lines122 free.

[0104] In some embodiments, a process for forming the second via opening includes 1502 and the buffer tank opening 1504 the formation of a first structured masking layer (not shown) (for example, positive or negative photoresist, hard mask, etc.) over the third dielectric structure 130 In further embodiments, the first structured masking layer can be formed by placing a masking layer (not shown) on the third dielectric structure. 130 The masking layer is formed, exposed with a structure (for example, by a lithographic process such as photolithography, extreme ultraviolet lithography, or the like), and the masking layer is developed to form the first structured masking layer. Afterward, a first etching process is carried out to remove unmasked parts of the third dielectric structure. 130, the second dielectric structure 124 , the outgassing prevention layer 804 and the fourth dielectric layer 802 to remove, thereby removing the second via opening 1502 and the buffer tank opening 1504 above the first dielectric structure 116 The first etching process can be a dry etching process, a wet etching process, a reactive ion etching (RIE) process, another etching process, or any combination thereof. Subsequently, in some embodiments, the first structured masking layer is removed.

[0105] As in Fig. 16 are shown above the IC structure 102 several cavity openings 1602 , several flow connection channel openings 1604 and one or more buffer tank channel openings 1606 formed. The cavity openings 1602 , the flow connection channel openings 1604and the buffer tank channel openings 1606 are in the third dielectric structure 130 formed. In some embodiments, the cavity openings are 1602 , the flow connection channel openings 1604 and the buffer tank channel openings 1606 above the first dielectric layer 132 and in the second dielectric layer 134 formed. For clarity, only some of the cavity openings are shown. 1602 and only some of the flow connection channel openings 1604 each with its respective reference mark.

[0106] The cavity openings 1602 are positioned at a lateral distance from each other. In some embodiments, the electrodes can 128 be arranged in a third arrangement. The cavity openings 1602 can be formed in a fifth array, corresponding to the third array. The flow connection channel openings 1604are designed in such a way that they extend laterally between the cavity openings 1602 extend so that opposite ends of the flow connection channel openings 1604 into the corresponding cavity openings of the cavity openings 1602 open into. In some embodiments, each of the flow connection channel openings 1604 designed so that they can be positioned laterally between two adjacent cavity openings of the cavity openings 1602 extends so that the opposite ends of each of the flow connection channel openings 1604 into two adjacent cavity openings of the cavity openings 1602 discharge. The buffer tank channel openings 1606 are designed to extend laterally from the buffer tank opening 1504 to some of the cavity openings 1602 extend. In some embodiments, some of the cavity openings 1602 , to which the buffer tank channel openings are connected 1606extend, a group of cavity openings 1602 (for example, a group of cavity openings) 1602 , which are arranged in a row or column of the fifth arrangement), which are closer to the buffer tank opening 1504 are arranged differently than the other cavity openings 1602 .

[0107] In some embodiments, a method for forming the cavity openings includes 1602 , the flow connection channel openings 1604 and the buffer tank channel openings 1606 the formation of a second structured masking layer (not shown) (for example, positive or negative photoresist, hard mask, etc.) over the third dielectric structure 130 , above the first dielectric structure 116 , in the second through-hole 1502 and in the buffer tank opening 1504 . . A second etching process is then carried out to remove unmasked parts of the second dielectric layer.134 to remove, thereby opening the cavities 1602 , the flow connection channel openings 1604 and the buffer tank channel openings 1606 above the first dielectric layer 132 and in the second dielectric layer 134 The second etching process can be a dry etching process, a RIE process, a wet etching process, another etching process, or any combination thereof. In some embodiments, the second structured masking layer is subsequently removed. In other embodiments, the cavity openings are simultaneously created by the second etching process. 1602 and the openings of the flow connection channel 1604 formed. In further embodiments, the cavity openings are formed simultaneously by the second etching process. 1602 , the flow connection channel openings 1604 and the buffer tank channel openings 1606 educated.

[0108] As in Fig. As shown in 17, parts of the first dielectric layer are depicted. 132 removed to remove the gas trap structures 806 to at least partially expose. In some embodiments, a method for removing parts of the first dielectric layer includes 132 , to the gas trap structures 806 to expose at least part of the structure, forming a third structured masking layer (not shown) (for example, positive or negative photoresist, hard mask, etc.) over the third dielectric structure 130 , above the first dielectric structure 116 , in the second through-hole 1502 , in the buffer tank opening 1504 , in the cavity openings 1602 , in the flow connection channel openings 1604 and in the buffer tank channel openings 1606 . . A third etching process is then carried out to remove unmasked parts of the first dielectric layer. 132to remove, thereby removing parts of the first dielectric layer 132 be removed to remove the gas trap structures 806 to at least partially expose the underlying material. The third etching process can be a dry etching process, a RIE process, a wet etching process, another etching process, or any combination thereof. In some designs, the third structured masking layer is then removed.

[0109] As in Fig. Figure 18 shows a MEMS substrate. 136 with the third dielectric structure 130 connected. The MEMS substrate 136 can be attached to the second dielectric layer 134 are bonded. In some embodiments, the MEMS substrate is 136 with the third dielectric structure 130 connected via a fusion bonding process. By bonding the MEMS substrate. 136 to the third dielectric structure 130 are above the IC structure 102several cavities 148 , a buffer tank 1002 , several flow connecting channels 152 and one or more buffer tank channels 1004 formed. For example, if the MEMS substrate 136 with the third dielectric structure 130 The connected area covers the MEMS substrate. 136 completely the buffer tank opening 1504 , the cavity openings 1602 , the flow connection channel openings 1604 and the buffer tank channel openings 1606 (see for example Fig. 17), whereby the buffer tank 1002 , the cavities 148 , the several flow connection channels 152 and one or more buffer tank channels 1004 be formed.

[0110] In some embodiments, a third dielectric layer is present. 138 over one side of the MEMS substrate 136 arranged on the side of the MEMS substrate 136opposite, which is the third dielectric structure 130 is connected. The third dielectric layer 138 can be done via the side of the MEMS substrate 136 are arranged on the side of the MEMS substrate 136 opposite, which is connected to the third dielectric structure 130 is bonded before the MEMS substrate 136 to the third dielectric structure 130 is bonded. In other embodiments, the third dielectric layer can be 138 above the MEMS substrate 136 and the IC structure 102 are formed after the MEMS substrate 136 to the third dielectric layer 138 was bonded. In further embodiments, a method for forming the third dielectric layer comprises 138 above the MEMS substrate 136 and the IC structure 102 the deposition or growth of the third dielectric layer 138on the MEMS substrate 136 for example by CVD, PVD, ALD, thermal oxidation, any other deposition or growth process, or any combination thereof.

[0111] In embodiments in which the semiconductor device 100 not the buffer tank 1002 and / or one or more ventilation openings 902 (see for example Fig. 9) are included, through bonding the MEMS substrate 136 to the third dielectric structure 130 the cavities 148 and the flow connecting channels 152 at a reference system pressure (for example, less than or equal to 2 atm) it is hermetically sealed. In such embodiments, the reference system pressure can be between 0.5 atm and 2 atm (for example, for a MEMS transducer for operation at standard pressure). In further such embodiments, a method for bonding the MEMS substrate comprises 136to the third dielectric structure 130 the introduction of the in Fig. The structure shown in Figure 17 is placed in a process chamber, the process chamber is pumped out so that a fluid (for example, gas) in the process chamber is under a predefined pressure (for example, less than or equal to 2 atm), and the MEMS substrate is bonded. 136 to the third dielectric structure 130 , while the fluid in the process chamber is at the predefined pressure, thus creating the cavities 148 and the flow connecting channels 152 They are hermetically sealed under the pressure of the reference system.

[0112] As in Fig. As shown in 19, one or more sealing structure openings are depicted. 1008 formed, which extend vertically through the MEMS substrate 136 and the third dielectric layer 138 extend. The sealing structure openings 1008 lay parts of the buffer tank channels 1004free. Furthermore, a first through-hole for vias is created. 142 formed, which extends vertically through the third dielectric layer 138 , the MEMS substrate 136 , the third dielectric structure 130 and the second dielectric structure 124 extends. The first via opening 142 lays one of the conductive lines 122 free.

[0113] In some embodiments, a method for forming the sealing structure openings includes 1008 and the first through-hole 142 the formation of a fourth structured masking layer (not shown) (for example, positive or negative photoresist, hard mask, etc.) over the third dielectric layer 138 . . A fourth etching process is then carried out to remove unmasked parts of the third dielectric layer. 138 and the MEMS substrate 136to remove, thereby removing the sealing structure openings 1008 and the first through-hole 142 are formed. The unmasked parts of the third dielectric layer 138 and the MEMS substrate 136 , which are removed to create the first via opening 142 to form, lie above the second via opening 1502 (see for example Fig. 18). In other words, the second via opening 1502 exposed by removing the unmasked parts of the third dielectric layer 138 and the MEMS substrate 136 be removed, thereby removing the first through-hole 1502 is formed. Subsequently, in some embodiments, the fourth structured masking layer can be removed. It is conceivable that in some embodiments the fourth etching process creates one or more vents. 902 (see for example Fig. 9) forms, which extends vertically through the MEMS substrate 136 extend.

[0114] As in Fig. As shown in 20, one or more sealing structures are depicted. 1006 above the IC structure 102 formed, which extends vertically through the third dielectric layer 138 , the MEMS substrate 136 and the third dielectric structure 130 extend. The sealing structures 1006 are each designed in such a way that they fit the sealing structure openings. 1008 line the sealing structures. 1006 are in the buffer tank channels 1004 trained. The sealing structures 1006 are designed to operate the buffer tank channels 1004 between the buffer tank 1002 and the cavities 148 Completely block the sealing structures. 1006 form hermetic seals between the buffer storage 1002 and the cavities 148, so that the buffer storage tank is not in flow contact with the cavities 148 It stands. Furthermore, the sealing structures are airtight. 1006 the cavities 148 and the flow connecting channels 152 at the reference system pressure, it is hermetically sealed.

[0115] In some embodiments, a method for manufacturing the sealing structures includes 1006 placing the in Fig. The structure shown in Figure 19 is placed in a process chamber. The process chamber is then evacuated so that a liquid (for example, gas) in the process chamber is under a predefined pressure (for example, less than or equal to 2 atm). While the liquid in the process chamber is at the predefined pressure, a sealing layer (not shown) is applied over the third dielectric layer. 138 , in the first about opening 142 , in the openings of the sealing structure 1008 and in the channels of the buffer tank1004 The sealing structures seal by depositing the sealing layer in the process chamber while the fluid in the process chamber is at the predefined pressure. 1006 the cavities 148 and the flow connecting channels 152 The sealing layer seals hermetically at the reference system pressure. It can be, for example, a metal (e.g., Al, Cu, AlCu, Ti, Ag, Au, or the like), a metal nitride (e.g., TiN), an oxide (e.g., SiO2), a nitride (e.g., SiN), an oxynitride (e.g., SiOXNY), or the like. The sealing layer can be deposited, for example, by CVD, PVD, ALD, electroless deposition, electrochemical deposition, another deposition method, or any combination thereof.

[0116] A fifth structured masking layer (not shown) (e.g., positive or negative photoresist, hard mask, etc.) is then applied to the sealing layer. A fifth etching process is then performed on the sealing layer to remove unmasked areas and thus reveal the sealing structures. 1006 to form. Subsequently, in some embodiments, the fifth structured masking layer is removed. It is conceivable that in some embodiments the fifth structured masking layer can be formed before the sealing layer is deposited. In such embodiments, after the sealing layer has been applied, a planarization process (for example, chemical-mechanical polishing (CMP)) can be carried out on the sealing layer, thereby improving the sealing structures. 1006 are formed. In embodiments where the vent openings 902 (see for example Fig. 9) in the MEMS substrate 136 are arranged, one or more plugs can be used. 904 (see for example Fig. 9) above the MEMS substrate 136 and above the third dielectric layer 138 be trained to open the ventilation openings 902 to seal. In some embodiments, the sealing structures can 1006 and the plugs 904 are formed simultaneously through the same deposition process.

[0117] In comparison, the structure in Fig. 20 does not include a buffer tank, can be used with the buffer tank 1002 and the buffer tank channels 1004 the cavities 148 and the flow connecting channels 152 (and the ventilation openings) 902) are hermetically sealed at a lower reference system pressure. In such embodiments, the reference system pressure can be less than 0.1 atm (for example, for a MEMS transducer for operation under high vacuum). Before, for example, the sealing structures 1006 to be formed, the buffer tank is available 1002 in flow connection with the cavities 148 , since the buffer tank channels 1004 laterally between the buffer tank 1002 and some of the cavities 148 run. Before the sealing structures 1006 to be formed, have the buffer tank 1002 and the cavities 148 Together, they form a third volume. In other words, the third volume corresponds to the sum of the volumes of the buffer tank. 1002 and the volume of each of the cavities 148 The third volume is larger than the sum of the volumes of each of the cavities. 148 Accordingly, the buffer tank enables 1002and the buffer tank channels 1004 compared to the case where the structure is in Fig. 20 does not include a buffer tank, a hermetic seal of the cavities 148 and the flow connecting channels 152 (and the ventilation openings) 902 ) at the lower reference system pressure (for example, due to the volume dependence of pressure).

[0118] As in Fig. As shown in 21, a third conductive via is used. 140 and one or more second conductive contacts 144 above the MEMS substrate 136 formed. The third conductive via. 140 is formed in such a way that it extends vertically through the third dielectric layer 138 , the MEMS substrate 136 , the third dielectric structure 130 and the second dielectric structure 124 extends to one of the conductive lines 122to contact. One or more second conductive contacts 144 are formed, which are characterized by the third dielectric layer 138 extend and the MEMS substrate 136 contact.

[0119] In some embodiments, a method for forming the third conductive through-contact includes 140 and the second conductive contacts 144 the formation of a sixth structured masking layer (not shown) (for example, positive or negative photoresist, hard mask, etc.) over the third dielectric layer 138 , above the first dielectric structure 116 , above the sealing structures 1006 and in the first through-hole 142 . Afterwards, a sixth etching process (for example, wet etching, dry etching, RIE, etc.) is performed on the third dielectric layer. 138carried out, creating conductive contact openings (and / or trenches) (not shown) in the third dielectric layer 138 are formed, which connect to the second conductive contacts. 144 corresponding. Subsequently, in some embodiments, the sixth structured masking layer is removed.

[0120] Then a conductive layer (not shown) is applied over the third dielectric layer. 138 , above the first dielectric structure 116 , above the sealing structures 1006 , in the first through-hole 142and deposited in the conductive contact orifice (and / or grooves). The conductive layer can be, for example, a metal (e.g., Al, Cu, AlCu, Ti, Ag, Au, or the like), a metal nitride (e.g., TiN), another conductive material, or any combination thereof. The conductive layer can be deposited, for example, by CVD, PVD, ALD, electroless deposition, electrochemical deposition, another deposition method, or any combination thereof. A seventh structured masking layer (not shown) (e.g., positive or negative photoresist, hard mask, etc.) is then formed over the conductive layer. A seventh etching process is then performed on the conductive layer to remove unmasked portions of the conductive layer, thus revealing the third conductive via. 140 and the second conductive contacts 144are formed. Subsequently, in some embodiments, the seventh masking layer is removed.

[0121] It is conceivable that in some embodiments, instead of the seventh etching process, a planarization process (for example, CMP) is carried out on the conductive layer, thereby creating the third conductive via. 140 and the second conductive contacts 144 to be formed. It is also conceivable that in some embodiments the seventh structured masking layer can be formed before the deposition of the conductive layer. In such embodiments, a planarization process (for example, CMP) can be performed on the conductive layer after its deposition, thereby creating the third conductive via. 140 and the second conductive contacts 144 to be formed. It is also conceivable that in some designs the third conductive via is140 , the second conductive contacts 144 , the sealing structures 1006 and the second conductive contacts 144 can be formed simultaneously through the same deposition process.

[0122] As in Fig. As shown in 22, a first passivation layer is formed. 808 above the MEMS substrate 136 , the third dielectric layer 138 , the third conductive via 140 , the second conductive contacts 144 and the sealing structures 1006 formed. In some embodiments, the first passivation layer can 808 be formed as a conformal layer. In further embodiments, a method for forming the first passivation layer comprises 808 the deposition of the first passivation layer 808 on the third dielectric layer 138 , the third conductive via 140, the second conductive contacts 144 and the sealing structures 1006 The first passivation layer 808 can be deposited, for example, by CVD, PVD, ALD, another deposition method, or any combination thereof.

[0123] In some embodiments, after the formation of the first passivation layer 808 the formation of the semiconductor device 100 completed. The semiconductor device 100 includes several MEMS devices 146 , which are above the semiconductor substrate 104 and the IC structure 102 are arranged. The MEMS devices 146 include the cavities 148 , several movable membranes 150 and the electrodes 128 In some embodiments, the MEMS devices 146 Part of a MEMS converter 154 .

[0124] Since the cavities 148and the flow connecting channels 152 The cavities are hermetically sealed at the reference system pressure. 148 the MEMS devices 146 cavity pressures (for example, pressures within the cavities) 148 (after the formation of the semiconductor device is complete). Since the flow connection channels 152 laterally between the cavities 148 extend, the cavities 148 the MEMS devices 146 in flow connection with each other. Since the cavities 148 the MEMS devices 146 The cavity pressures of the cavities are connected to each other by flow. 148 the MEMS devices 146 essentially the same. Therefore, the flow connection channels can 152 the performance of the semiconductor device 100 improve (for example, by increasing transmit and receive sensitivity).

[0125] Fig. Figure 23 shows a flowchart of some embodiments of a method for manufacturing a semiconductor device with MEMS devices featuring improved cavity pressure uniformity. While the flowchart 2300 from Fig. 23. While the sequence of such processes or events is presented and described here as a series of operations or events, it is conceivable that the sequence of such operations or events shown should not be interpreted in a restrictive sense. For example, some operations may occur in different sequences and / or simultaneously with other operations or events not shown and / or described in this diagram. Furthermore, it is conceivable that not all of the operations shown are necessary to implement one or more aspects or embodiments of the description contained herein, and one or more of the operations shown here may be carried out in one or more separate operations and / or phases.

[0126] During the process 2302A dielectric structure is formed over an integrated circuit structure (IC structure), wherein the IC structure comprises a connection structure arranged over a semiconductor substrate. Fig. Figure 14 shows a cross-sectional view of some embodiments that illustrate the process 2302 are equivalent to.

[0127] During the process 2304 Several cavity openings and several flow connection channel openings are formed in the dielectric structure, with each of the flow connection channel openings extending laterally between two adjacent cavity openings. Fig. Figures 15-16 show a series of cross-sectional views of some embodiments that illustrate the process 2304 are equivalent to.

[0128] During the process 2306A MEMS substrate (substrate of a microelectromechanical system) is bonded to the dielectric structure, the bonding of the MEMS substrate to the dielectric structure covering the cavity openings and the openings of the flow connection channels, thereby forming multiple cavities and multiple flow connection channels. Fig. Figures 17-18 show a series of cross-sectional views of some embodiments that illustrate the process 2306 are equivalent to.

[0129] During the process 2308 One or more conductive contacts and a conductive via are formed over the MEMS substrate, the conductive via extending vertically through the MEMS substrate and the dielectric structure, so that the conductive via is electrically coupled to the interconnect structure. Fig. Figures 19-21 show a series of cross-sectional views of some embodiments that illustrate the process 2308 are equivalent to.

[0130] During the process 2310 A passivation layer is formed over the MEMS substrate, the conductive contacts and the conductive via. Fig. 22 shows a cross-sectional view of some embodiments that describe the process 2310 are equivalent to.

[0131] In some embodiments, the present application provides a semiconductor device. The semiconductor device comprises a connection structure arranged over a semiconductor substrate. A dielectric structure is arranged over the connection structure. Several cavities are arranged in the dielectric structure in a row and column array. A MEMS substrate (substrate of a microelectromechanical system) is arranged over the dielectric structure, the MEMS substrate defining the upper surfaces of the cavities, the MEMS substrate comprising several movable membranes, and the movable membranes each lying over the cavities.Several flow connection channels are arranged in the dielectric structure, wherein the upper surfaces of the flow connection channels are defined by the MEMS substrate, and wherein each of the flow connection channels extends laterally between two adjacent cavities, so that all cavities are in flow communication with each other.

[0132] In some embodiments, the present application provides a semiconductor device. The semiconductor device comprises a connection structure arranged over a semiconductor substrate. A dielectric structure is arranged over the connection structure. A MEMS substrate is arranged over the dielectric structure. A first MEMS device is arranged over the semiconductor substrate, the first MEMS device comprising a first cavity arranged in the dielectric structure and a first movable membrane of the MEMS substrate located over the first cavity.A second MEMS device is arranged above the semiconductor substrate, wherein the second MEMS device has a second cavity arranged within the dielectric structure and a second movable membrane of the MEMS substrate located above the second cavity, and wherein the second MEMS device is spaced laterally from the first MEMS device in a first direction. A first flow connection channel is arranged within the dielectric structure, the first flow connection channel extending laterally from the first cavity to the second cavity in the first direction, such that the first cavity and the second cavity are in flow communication with each other.

[0133] In some embodiments, the present application provides a method for manufacturing a semiconductor device. The method comprises receiving an integrated circuit (IC) structure with a first electrode and a second electrode arranged over a semiconductor substrate of the IC structure, the first electrode being laterally spaced from the second electrode. A dielectric structure is formed over the IC structure, the first electrode, and the second electrode. A first cavity opening is formed in the dielectric structure, located over the first electrode. A second cavity opening is formed in the dielectric structure and is located over the second electrode, with a portion of the dielectric structure positioned between the first cavity opening and the second cavity opening.A flow-connecting channel opening is formed in the portion of the dielectric structure, the flow-connecting channel opening extending laterally from the first cavity opening to the second cavity opening. A substrate of a microelectromechanical system, a MEMS substrate, is bonded to the dielectric structure, the bonding of the MEMS substrate to the dielectric structure covering the first cavity opening, the second cavity opening, and the flow-connecting channel opening, thereby forming a first cavity, a second cavity, and a flow-connecting channel, and the flow-connecting channel extending laterally from the first cavity to the second cavity.

[0134] The foregoing outlines the features of various embodiments so that a knowledgeable reader with relevant experience and expertise can better understand the aspects of this disclosure. It should be clear to the knowledgeable reader that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages as the embodiments presented herein. It should also be clear to the knowledgeable reader that such equivalent designs do not deviate from the spirit and scope of this disclosure and that they can incorporate various changes, substitutions, and modifications without deviating from the spirit and scope of this disclosure.

Claims

[1] comprising a semiconductor device: a compound structure arranged over a semiconductor substrate; a dielectric structure that is arranged above the connection structure; multiple cavities arranged in the dielectric structure and arranged in an array which has rows and columns; a MEMS substrate, substrate for a microelectromechanical system arranged above the dielectric structure, wherein the MEMS substrate defines upper surfaces of the cavities, wherein the MEMS substrate comprises multiple movable membranes, and wherein the movable membranes are positioned above the respective cavity; and Several flow connection channels are arranged in the dielectric structure, wherein the upper surfaces of the flow connection channels are defined by the MEMS substrate, and wherein each of the flow connection channels extends laterally between two adjacent cavities of the cavities, such that all cavities are in flow communication with each other. [2] Semiconductor device according to claim 1, wherein each of the cavities has substantially the same cavity pressure. [3] Semiconductor device according to claim 1 or 2, wherein each of the cavities has a circular outline in the top view. [4] Semiconductor device according to one of the preceding claims, wherein opposite side walls of a first flow connection channel of the flow connection channels are defined by opposite side walls of the dielectric structure. [5] Semiconductor device according to claim 4, wherein a lower surface of the first flow connection channel is defined by an upper surface of the dielectric structure. [6] Semiconductor device according to claim 5, wherein the dielectric structure comprises: a first dielectric layer; and a second dielectric layer arranged above the second dielectric layer, wherein the opposite side walls of the first flow connecting channel are defined by the second dielectric layer. [7] Semiconductor device according to claim 6, wherein the lower surface of the first flow connection channel is defined by an upper surface of the first dielectric layer. [8] comprising a semiconductor device: a compound structure arranged over a semiconductor substrate; a dielectric structure that is arranged above the connection structure; a MEMS substrate, substrate for a microelectromechanical system that is arranged above the dielectric structure; a first MEMS device arranged above the semiconductor substrate, wherein the first MEMS device has a first cavity arranged in the dielectric structure and a first movable membrane of the MEMS substrate located above the first cavity; a second MEMS device arranged above the semiconductor substrate, wherein the second MEMS device has a second cavity arranged in the dielectric structure and a second movable membrane of the MEMS substrate located above the second cavity, and wherein the second MEMS device is spaced laterally from the first MEMS device in a first direction; and a first flow connection channel arranged in the dielectric structure, wherein the first flow connection channel extends laterally from the first cavity to the second cavity in the first direction, such that the first cavity and the second cavity are in flow connection. [9] Semiconductor device according to claim 8, wherein: the first cavity has a first length, which is measured in the first direction; the first cavity has a first width which is measured in a second direction perpendicular to the first direction; the first flow connection channel has a second width, which is measured in the second direction; and the second width is smaller than the first width and the first length is smaller. [10] Semiconductor device according to claim 8 or 9, wherein the MEMS substrate defines a first upper surface of the first cavity, a second upper surface of the second cavity and a third upper surface of the first flow connection channel. [11] Semiconductor device according to any one of claims 8 to 10, wherein: the first cavity has a first center point and the second cavity has a second center point; and the first center point, the second center point and the first flow connecting channel are aligned along a first plane which extends in the first direction along an essentially straight line. [12] Semiconductor device according to any one of claims 8 to 11, wherein: the first cavity exhibits a first cavity pressure; and the second cavity has a second cavity pressure that is essentially the same as the first cavity pressure. [13] Semiconductor device according to any one of claims 8 to 12, wherein: the first flow connecting channel has a first side wall and a second side wall opposite the first side wall; the second side wall is spaced away from the first side wall in a second direction that runs perpendicular to the first direction; the first side wall extends vertically along a first essentially vertical plane; the second side wall extends vertically along a second, essentially vertical plane; the first essentially vertical plane extends vertically parallel to the second essentially vertical plane; and The first flow connecting channel has a lower surface that is essentially flat. [14] Semiconductor device according to any one of claims 8 to 13, further comprising: a third MEMS device arranged above the semiconductor substrate, wherein the third MEMS device has a third cavity arranged in the dielectric structure and a third movable membrane of the MEMS substrate located above the third cavity, wherein the third MEMS device is spaced laterally from the first MEMS device in a second direction perpendicular to the first direction, and wherein the second MEMS device is spaced laterally from the third MEMS device in the first direction; and a second flow connection channel arranged in the dielectric structure, wherein the second flow connection channel extends laterally from the first cavity to the third cavity in the second direction, so that the first cavity, the second cavity and the third cavity are in flow connection with each other. [15] Semiconductor device according to claim 14, wherein: The first cavity has a first center point, the second cavity has a second center point, and the third cavity has a third center point; the first center point, the second center point and the first flow connecting channel are aligned along a first plane which extends in the first direction along a substantially straight line; the first center point, the third center point, and the second flow-connecting channel are aligned along a second plane that extends in the second direction along a substantially straight line; and The first plane intersects the second plane at the first midpoint. [16] Semiconductor device according to claim 15, further comprising: a buffer tank positioned above the semiconductor substrate, - wherein the first MEMS device, the second MEMS device and the third MEMS device are spaced laterally from the buffer tank in the first direction; - where the side walls of the buffer tank are at least partially defined by the dielectric structure; - wherein the side walls of the buffer tank have a first side wall and a second side wall opposite the first side wall; - wherein the first side wall is laterally spaced from the second side wall in the second direction; and - wherein the first midpoint, the second midpoint and the third midpoint are arranged laterally between the first side wall and the second side wall; a buffer tank channel arranged in the dielectric structure, wherein the buffer tank channel is aligned with its first center point along the first plane, and wherein the buffer tank channel extends laterally from the buffer tank to the first cavity; and a sealing structure arranged in the buffer tank channel, wherein the sealing structure extends vertically through the MEMS substrate and into the buffer tank channel, the sealing structure sealing the buffer tank against the first cavity so that the buffer tank is not in flow communication with the first cavity, the second cavity or the third cavity. [17] Semiconductor device according to any one of claims 14 to 16, further comprising: a fourth MEMS device arranged above the semiconductor substrate, wherein the fourth MEMS device has a fourth cavity arranged in the dielectric structure and a fourth movable membrane of the MEMS substrate located above the fourth cavity, wherein the first MEMS device, the second MEMS device and the third MEMS device are laterally spaced from the fourth MEMS device in the first direction, and wherein the fourth cavity has a fourth center point aligned with the first center point along the first plane; and a fourth flow-connecting channel arranged in the dielectric structure, wherein the fourth flow-connecting channel is aligned with the first center point along the first plane, and wherein the fourth flow-connecting channel extends from the fourth cavity to the first cavity in the first direction, such that the first cavity, the second cavity, the third cavity and the fourth cavity are in flow communication with each other. [18] Semiconductor device according to claim 17, further comprising: a fifth MEMS device arranged above the semiconductor substrate, wherein the fifth MEMS device has a fifth cavity arranged in the dielectric structure and a fifth movable membrane of the MEMS substrate located above the fifth cavity, wherein the first MEMS device, the second MEMS device, the third MEMS device and the fourth MEMS device are laterally spaced from the fifth MEMS device in the second direction, and wherein the fifth cavity has a fifth center point aligned with the first center point along the second plane; and a fifth flow connection channel arranged in the dielectric structure, wherein the fifth flow connection channel is aligned with the first center point along the second plane, and wherein the fifth flow connection channel extends in the second direction from the fifth cavity to the first cavity, such that the first cavity, the second cavity, the third cavity, the fourth cavity and the fifth cavity are in flow connection with each other. [19] Method for manufacturing a semiconductor device, the method comprising: Obtaining an IC structure, an integrated circuit structure, which has a first electrode and a second electrode which are arranged over a semiconductor substrate of the IC structure, wherein the first electrode is laterally spaced from the second electrode; Forming a dielectric structure over the IC structure, the first electrode and the second electrode; Formation of a first cavity opening in the dielectric structure and above the first electrode; Forming a second cavity opening in the dielectric structure and above the second electrode, wherein part of the dielectric structure is arranged between the first cavity opening and the second cavity opening; Forming a flow-connecting channel opening in that part of the dielectric structure, wherein the flow-connecting channel opening extends laterally from the first cavity opening to the second cavity opening; and Bonding a MEMS substrate, a substrate of a microelectromechanical system, to the dielectric structure, wherein the bonding of the MEMS substrate to the dielectric structure covers the first cavity opening, the second cavity opening and the flow connection channel opening, thereby forming a first cavity, a second cavity and a flow connection channel, and wherein the flow connection channel extends laterally from the first cavity to the second cavity. [20] Method according to claim 19, wherein the first cavity opening, the flow connection channel opening and the second cavity opening are formed simultaneously by an etching process.

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