LITHOGRAPHY MASK WITH AMORPHOUS COVER LAYER

Abstract

Procedure comprising: Forming a multilayer reflective structure (34) over a substrate (30); performing a plasma treatment process on the multilayer reflection structure (34); Depositing or growing an amorphous layer (50) over the multilayer reflective structure (34); and Depositing or growing a capping layer (100) over the amorphous layer (50).

Description

BACKGROUNDThe semiconductor integrated circuit (IC) industry has grown rapidly. Technical advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs, and in order to implement these advances, similar developments in IC processing and manufacturing are needed. As integrated circuit development has advanced, the functional density (i.e., the number of connected devices per chip area) has generally increased, while the geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased.As semiconductor device size continues to decrease, such as nodes decreasing below 20 nanometers (nm), traditional lithography technologies have optical limitations, leading to resolution issues such that desired lithography performance may not be achieved. In comparison, extreme ultraviolet (EUV) lithography can produce much smaller device sizes. However, existing EUV lithography can still face certain challenges. For example, the cover layer of existing EUV masks can be easily damaged, which can reduce the lithography power and / or shorten the service life of the EUV mask.With regard to the prior art, reference is made to U.S. Pat. No. 2015 / 0 010 854 A1 and U.S. Pat. No. 2016 / 0 109 792 A1, both of which describe masks for EUV lithography.Therefore, existing EUV lithography systems and methods, although generally suitable for their intended purpose, are not fully satisfactory in all aspects.BRIEF DESCRIPTION OF THE DRAWINGSAspects of the present disclosure may best be understood from the following detailed description taken in conjunction with the accompanying drawings. It is emphasized that, according to standard industrial methods, various features are not drawn to scale. Indeed, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased. FIG. 1 is a schematic view of a lithography system constructed in accordance with some embodiments of this disclosure. FIGS. 2-13 illustrate cross-sectional views of a lithography mask at various stages of fabrication, in accordance with embodiments of this disclosure. FIG. 14 is a flow diagram illustrating a method of manufacturing and using a lithography mask, in accordance with some embodiments of this disclosure. FIG. 15 is a flow diagram illustrating a method of manufacturing and using a lithography mask, in accordance with some embodiments of this disclosure.DETAILED DESCRIPTIONThe following disclosure provides many different embodiments or examples for implementing different functions of the stated content. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, forming a first feature or a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which further features may be formed between the first and second features such that the first and second features need not be in direct contact. Further, this disclosure may repeat reference numerals and / or letters of the various examples. This repetition is for convenience and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations explained.Further, spatially relative terms such as "below," "below," "lower," "above," "upper," and the like may be used herein for ease of description to describe the relationship of an element or feature to one or more other element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or in another orientation) and the spatially relative terms used herein may also be appropriately construed.Still further, when a number or range of numbers is referred to as "about", "about", and the like, the term is intended to encompass numbers that are within a suitable range that includes the designated number, such as within the range of + / -10% around the described number, or at other values, as will be understood by one of ordinary skill in the art. For example, the term "about 5 nm" encompasses the dimensional range from 4.5 nm to 5.5 nm.Extreme ultraviolet (EUV) lithography is widely used due to its ability to achieve small semiconductor device sizes. However, conventional systems and methods for performing EUV lithography may still face various challenges. For example, conventional EUV systems utilize a lithography mask configured to perform EUV lithography. Among other components, the EUV lithography mask includes a capping layer configured to protect some of the other components (e.g., a multi-layer reflection structure) of the EUV lithography mask. Conventional EUV lithography masks may implement the capping layer using a polycrystalline material. Unfortunately, such a polycrystalline material may be easily damaged during the various EUV lithography processes.For example, a material having a polycrystalline structure has a plurality of crystallites (also referred to as "grains") of various sizes and orientations. A grain boundary may refer to an interface between two such grains or crystallites. During lithography processes, such as dry etching and cleaning (or as a result thereof), the grain boundaries of the polycrystalline capping layer may crack or otherwise be roughened (as opposed to having a smooth, flat surface). These damage to the capping layer may negatively affect lithography performance, for example, with respect to critical dimension (CD) during wafer printing. The damage to the capping layer may also shorten the lifetime of the EUV lithography mask, as the EUV lithography masks with capping layer damage are less well able to resist particle removal by cleaning or e-beam repair. If EUV lithography masks need to be replaced frequently due to excessive damage, this may increase the cost for semiconductor fabrication.In order to alleviate the problems explained above, this disclosure provides an EUV lithography mask having a capping layer with an amorphous structure instead of a polycrystalline structure. The amorphous structure allows the capping layer to better withstand the various EUV lithography processes without being damaged, thereby improving the EUV lithography performance and extending the lifetime of the EUV lithography mask. The various aspects of this disclosure are explained in more detail below with reference to FIGS. 1-15. First, an EUV lithography system according to embodiments of this disclosure will be discussed below with reference to FIG. 1. Next, the details of an EUV mask that is part of the EUV lithography system according to embodiments of this disclosure will be explained with reference to FIGS. 2 to 15.FIG. 1 is a diagram of a schematic view of an EUV lithography system 10 constructed in accordance with some embodiments. The EUV lithography system 10 may also be generically referred to as a scanner configured to perform lithography exposure processes with a respective radiation source and exposure mode. The EUV lithography system 10 is designed to expose a photoresist layer to EUV light or EUV radiation. The photoresist layer is a material sensitive to EUV light. The EUV lithography system 10 employs a radiation source 12 to generate EUV light, such as EUV light having a wavelength of between about 1 nm and about 100 nm. In a particular example, the radiation source 12 generates EUV light having a wavelength centered at about 13.5 nm. Accordingly, the radiation source 12 is also referred to as an EUV radiation source 12.Lithography system 10 also employs an imager 14. In various embodiments, the exposer 14 comprises various refractive optical components, such as a single lens or a lens system having a plurality of lenses (zone plates) or alternatively reflective optics (for the EUV lithography system), such as a single mirror or a mirror system having a plurality of mirrors, for directing light from the radiation source 12 onto a mask stage 16, in particular onto an EUV lithography mask 18 secured to the mask stage 16. In this embodiment, in which the radiation source 12 generates light in the range of the EUV wavelength, the exposer 14 uses reflective optics. In some embodiments, the imager 14 includes a dipole exposure component.In some embodiments, the imager 14 may be operated to configure the mirrors to provide proper exposure of the EUV lithography mask 18. In one example, the mirrors of the illuminator 14 may be switched to reflect EUV light to different exposure positions. In one embodiment, a stage prior to the illuminator 14 may further include other switchable mirrors that are controllable to direct the EUV light to different exposure positions with the mirrors of the illuminator 14. In some embodiments, the imager 14 is configured to apply an on-axis exposure (ONI) to the EUV lithography mask 18. In some other embodiments, the imager 14 is configured to apply an off-axis exposure (OAI) to the EUV lithography mask 18. The dipole imager has a partial coherence σ of at most 0.3 in some embodiments.Lithography system 10 also includes a mask stage 16 configured to secure an EUV lithography mask 18. In some embodiments, the mask stage 16 includes an electrostatic chuck (e-chuck) to secure the EUV lithography mask 18. This is because gas molecules absorb EUV light and the lithography system for EUV lithography patterning is maintained in a vacuum environment in order to avoid EUV intensity loss. In the disclosure, the terms mask, photomask, and reticle are used interchangeably to refer to the same subject matter.In this embodiment, lithography system 10 is an EUV lithography system and EUV lithography mask 18 is a reflective mask. An exemplary structure of the EUV lithography mask 18 is provided for illustration purposes. The EUV lithography mask 18 includes a substrate having a suitable material, such as a low thermal expansion material (LTEM) or fused quartz. In various examples, the LTEM comprises TiO 2- doped SiO 2 or other suitable materials having low thermal expansion. In some embodiments, the LTEM comprises 5 wt % to 20 wt % TiO 2 and has a coefficient of thermal expansion less than about 1.0 x 10 -6 / °C. For example, in some embodiments, the TiO 2- doped SiO 2- material of the LTEM has a coefficient of thermal expansion such that it varies by less than 60 parts per billion for each temperature change by one degree Celsius. Of course, other suitable materials having a thermal expansion coefficient equal to or less than SiO 2 doped with TiO 2- may also be used.The EUV lithography mask 18 also includes a multi-layered reflection structure deposited on the substrate. The multi-layer reflective structure includes multiple film pairs, such as molybdenum-silicon (Mo / Si) film pairs (e.g., a layer of molybdenum over or under a layer of silicon per film pair). Alternatively, the multilayer reflective structure may comprise molybdenum-beryllium (Mo / Be) film pairs or other suitable materials configurable to reflect the EUV light.The EUV lithography mask 18 may further comprise a capping layer disposed on the multi-layered reflection structure to protect the multi-layered reflection structure and / or the layers thereunder. Conventional EUV masks may implement a capping layer having a polycrystalline structure. As explained above, the polycrystalline structure for cap layers may be damaged. For example, the grain boundaries of the polycrystalline capping layer may be roughened or cracked by lithography processes such as etching and cleaning. The damage to the polycrystalline capping layer may cause manufacturing problems, such as poorer critical dimensions (CD). The EUV lithography mask itself may also suffer from a reduced lifetime due to the damage to the polycrystalline capping layer.According to embodiments of this disclosure, the capping layer of the EUV lithography mask 18 has an amorphous structure, rather than a polycrystalline structure. In this regard, amorphous structures are noncrystallizing and may have a well-defined geometric shape because their components are not arranged in an ordered manner. Thus, amorphous structures may not have grain boundaries that exist for polycrystalline structures. Since manufacturing-induced damage usually occurs at the grain boundaries, the lack of grain boundaries of the amorphous capping layer substantially prevents or at least reduces the damage that may occur thereto. As a result, lithography performance may be improved and the lifetime of the EUV lithography mask 18 may be extended, which reduces the cost of semiconductor fabrication.In some embodiments, the amorphous capping layer comprises an amorphous ruthenium (Ru) material. In some embodiments, the amorphous capping layer may further comprise one or more of oxygen, niobium, nitrogen, tantalum, or zirconium. In some embodiments, the amorphous capping layer may be formed by first forming an amorphous layer on the multilayer reflective structure, and therefore after forming the amorphous capping layer on the amorphous layer. In other embodiments, the amorphous capping layer may be formed by first treating the top surface of the multilayer reflective structure (e.g., by treatment with a plasma), and then forming the amorphous capping layer on the treated surface of the multilayer reflective structure. The formation of the amorphous capping layer will be explained in more detail with reference to Figs. 2 to 5.The EUV lithography mask 18 further comprises an absorption layer (also referred to as an absorber layer) arranged over the amorphous capping layer. The absorption layer is patterned to define an integrated circuit (IC) layer. Alternatively, another reflective layer may be deposited over the multilayer reflective structure and is patterned to form an integrated circuit layer, thereby forming an EUV phase shift mask.Lithography system 10 also includes a projection optics module (or projection optics box (POB) 20 for presenting the structure on EUV lithography mask 18 on a target 26 (e.g., a semiconductor substrate) secured to a substrate stage 28 of lithography system 10. The POB 20 includes refractive optics (such as for a UV lithography system) or alternatively reflective optics (such as for the EUV lithography system) in various embodiments. The light that is directed away from the EUV lithography mask 18, diffracted into different diffraction orders, and carries the image of the pattern defined on the mask is captured by the POB 20. The POB 20 may include a magnification of less than one (therefore, the size of the "image" on a target (such as target 26 discussed below) is less than the size of the corresponding "object" on the mask). The imager 14 and the POB 20 are collectively referred to as an optical module of the lithography system 10.Lithography system 10 also includes a pupil phase modulator 22 for modulating the optical phase of light directed away from EUV lithography mask 18 such that the light has a phase distribution on a projection pupil plane 24. In the optical module, there is a plane with a field distribution corresponding to a Fourier transform of the object (in this case, EUV lithography mask 18). This plane is referred to as a projection pupil plane. The pupil phase modulator 22 provides a mechanism for modulating the optical phase of the light on the projection pupil plane 24. In some embodiments, the pupil phase modulator 22 includes a mechanism for adjusting the reflective mirrors of the POB 20 for phase modulation. For example, the mirrors of the POB 20 are switchable and controlled to reflect the EUV light, thereby modulating the phase of the light through the POB 20.In some embodiments, the pupil phase modulator 22 uses a pupil filter placed on the projection pupil plane 24. A pupil filter filters specific spatial frequency components of the EUV light from the EUV lithography mask 18. However, the use of a phase pupil filter is limited in some lithography systems (such as an EUV lithography system) since all materials absorb EUV light.As explained above, lithography system 10 also includes substrate stage 28 to secure a target 26 to be patterned, such as a semiconductor substrate. In this embodiment, the semiconductor substrate is a semiconductor wafer, such as a silicon wafer or other type of wafer. The target 26 is covered with the resist layer that is sensitive to the radiation beam, such as EUV light in the present embodiment. Various components, including those described above, are jointly integrated and may be operated to perform lithography exposure processes. Lithography system 10 may further include or be integrated with (or coupled to) other modules.The EUV lithography mask 18 and the method of making the same are further described in accordance with some embodiments. In some embodiments, the mask fabrication process includes two operations: a blank mask fabrication process and a mask patterning process. During the mask blank fabrication process, a mask blank is formed by depositing appropriate layers (e.g., multiple reflective layers) on an appropriate substrate. The blanket mask is then patterned during the mask patterning process to achieve a desired integrated circuit (IC) layer design. The patterned mask is then used to transfer circuit patterns (e.g., the design of a layer of an IC) to a semiconductor wafer. The structures can be transferred repeatedly to a plurality of wafers by different lithography processes. A set of masks is used to build a complete IC.The EUV lithography mask 18 includes a suitable structure, such as a binary intensity mask (BIM) and phase shift mask (PSM), in various embodiments. An example BIM includes absorptive regions (also referred to as opaque regions) and reflective regions structured to define an IC structure to be transferred to the target. An absorber is present in the opaque regions and incident light is almost completely absorbed by the absorber. In the reflective regions, the absorber is removed and the incident light is diffracted by multilayer (multilayer reflection structure). The PSM may be a matched PSM (Attis) or an alternating PSM (AltPS). An exemplary PSM includes a first reflective layer (such as a reflective multilayer reflective structure) and a second reflective layer patterned according to an IC structure. In some examples, an AttPS typically has a reflectivity of 2% to 15% from its absorber, while an AltPS typically has a reflectivity of greater than 50% from its absorber.FIGS. 2-13 are diagrammatic fragmentary cross-sectional side views of a lithography mask at various stages of manufacture, in accordance with an embodiment of this disclosure. Referring to FIG. 2, the EUV lithography mask 18 is illustrated in more detail in FIG. 1. The EUV lithography mask 18 comprises a substrate 30 made of an LTEM. The LTEM may comprise TiO 2- doped SiO 2 and / or other low thermal expansion materials known in the art. In some embodiments, a conductive layer 32 is further disposed below at a side 42 (also referred to as a back side) of the LTEM substrate 30 to serve as an electrostatic chuck. In one example, the conductive layer 32 comprises chromium nitride (CrN). In other embodiments, other suitable compositions are possible, such as a tantalum-containing material.The EUV lithography mask 18 includes a multi-layered reflection structure 34 disposed over a side 44 (also as a front side) of the LTEM substrate 30. The multi-layer reflective structure 34 may be selected to provide high reflectivity to a selected type of radiation / wavelength. The multilayer reflective structure 34 includes multiple film pairs, such as Mo / Si film pairs (e.g., a layer of molybdenum over or under a layer of silicon per film pair). Alternatively, the multilayer reflective structure 34 may include Mo / Be film pairs or other materials whose refractive index difference is highly reflective at EUV wavelengths.Still referring to FIG. 2, an amorphous layer 50 is formed on the top surface of an uppermost layer of the multilayer reflective structure 34. The amorphous layer 50 helps the layer formed thereon (i.e., the amorphous capping layer) to obtain an amorphous structure. This is because the lattice arrangement (e.g., whether it is a single crystal structure, a polycrystal structure, or an amorphous structure) of a thin film (which will be the capping layer) is substantially affected by the lattice arrangement of the layer thereunder. In other words, when the layer 50 is formed to have an amorphous structure, the layer to be formed thereon (i.e., the capping layer) is likely also to have an amorphous structure. This may be referred to as "substrate alignment", as the amorphous layer 50 may be considered an "amorphous substrate" for an amorphous capping layer to be formed thereon.The amorphous layer 50 may be formed using an amorphous layer formation process 60. In some embodiments, the amorphous film formation process 60 may include an epitaxial growth process. In some other embodiments, the amorphous film formation process 60 may include a deposition process. The deposition process may be an atomic layer deposition (ALD) process, such as an ALD process performed at a low temperature in a range between about 26 degrees Celsius and about 60 degrees Celsius. The deposition process may also include a chemical vapor deposition (CVD) process, such as an atmospheric pressure CVD (APCVD) process, a low pressure CVD (LPCVD) process, a laser enhanced CVD (LECVD) process, and / or a plasma enhanced CVD (PECVD) process. The deposition process may also include a physical vapor deposition (PVD) process, for example an electrically heated evaporation (thermal evaporation) process, a pulsed laser deposition process, an electron beam evaporation process, a molecular beam epitaxy process, an ion beam assisted evaporation process and / or a discharge based deposition process such as sputtering or arc evaporation.The amorphous layer 50 is formed with a thickness 70. The value of the thickness 70 is adjustable by adjusting the various parameters of the amorphous film formation process 60, for example, over a duration of deposition, etc. In some embodiments, the thickness 70 is adjusted to be in a range between about 0.1 nanometers (nm) and about 4 nm, for example, between about 2 nm and about 4 nm. Such a thickness range for the amorphous layer 50 helps ensure that the amorphous layer 50 is sufficiently thick to help the capping layer formed thereon reach the amorphous structure, but not too thick to substantially affect the reflectivity of the multilayer reflective structure 34.In some embodiments, the top layer of the multi-layer reflective structure 34 is a silicon layer, and the amorphous layer 50 is formed directly on the top surface of this top silicon layer of the multi-layer reflective structure 34. In an embodiment, the amorphous layer 50 may include, but is not limited to, amorphous silicon, amorphous silicon oxide (SiO 2) or amorphous silicon nitride (SiN).Referring now to FIG. 3, a capping layer 100 is formed over the amorphous layer 50, for example directly on the top surface of the amorphous layer 50. the capping layer 100 may be formed by a capping layer forming process 110. In some embodiments, the capping layer formation process 110 may include an epitaxial growth process, a CVD process (such as APCVD, LPCVD, LECVD, or PECVD), or a PVD process (such as electrically heated evaporation, pulsed laser deposition, electron beam evaporation, molecular beam epitaxy, ion beam assisted evaporation, sputtering, or arc evaporation).As explained above, the presence of the amorphous layer 50 under the capping layer 100 makes it easier for the capping layer 100 to achieve an amorphous structure. In some embodiments, the capping layer 100 comprises an amorphous material comprising amorphous ruthenium. In other embodiments, the capping layer 100 comprises an amorphous material comprising a ruthenium-based compound that is amorphous. For example, the ruthenium-based compound may include elements such as oxygen (O), niobium (Nb), nitrogen (N), tantalum (Ta), or zirconium (Zr). In some embodiments, the ruthenium-based compound may include: RuO 2, RuNb, RuNbO, RuON, RuN, RuNbON, RuTaON, RuZr, or RuZrO. In embodiments where the ruthenium-based compound is RuNb, the atomic weight of Nb in RuNb is less than or equal to about 50%, for example about 10%, about 20%, about 30%, about 40%, or about 50%. In embodiments where the ruthenium-based compound is RuNbO, the atomic weight of Nb in RuNbO is less than or equal to about 50%, for example about 10%, about 20%, about 30%, about 40%, or about 50%.These above ranges of atomic weight are specifically adapted to optimize the performance of the capping layer. In this regard, ruthenium is a good candidate for the capping layer because it does not react with hydrogen (present in an EUV scanner). However, ruthenium itself may not be as etch resistant as the capping layer 100 in order not to be damaged during the various etching processes used to form the EUV lithography mask 18. Niobium is more etch resistant than ruthenium. Therefore, the addition of niobium to a ruthenium-based compound helps to increase the etching resistance of the capping layer 100. However, if too much niobium is present, such compound can react more strongly with hydrogen, which is undesirable. Here, the atomic weight of less than 50% for niobium in the ruthenium-based compound of the capping layer 100 helps to simultaneously achieve the goal of not reacting with hydrogen present in the EUV scanner and having sufficient etch resistance to resist the various etch processes performed herein.The capping layer 100 is formed with a thickness 120. The value of the thickness 120 is adjustable by adjusting the various parameters of the capping layer formation process 110, for example over a duration of deposition, etc. In some embodiments, the thickness 120 is adjusted to be in a range between about 2.5 nm and about 6 nm, for example between about 2 nm and about 4 nm. Such a thickness range for the capping layer 100 helps to ensure that the capping layer 100 is sufficiently thick to protect the multi-layer reflective structure 34 thereunder, but not too thick to substantially affect the reflectivity of the multi-layer reflective structure 34.It will be appreciated that FIGS. 2-3 illustrate only one embodiment of an amorphous capping layer 100. Another embodiment of forming the amorphous capping layer 100 is seen in Figs. 4 to 5. Referring to FIG. 4, the multi-layer reflective structure 34 is formed over the LTEM substrate 30. A treatment process 200 is performed to treat the top surface of an uppermost layer (e.g., a silicon layer of the uppermost Si / Mo film pair) of the multi-layered reflective structure 34. In other words, if the uppermost layer of the multi-layer reflective structure 34 had not been treated by the treatment process 200, the capping layer to be formed thereon is more likely to have a polycrystalline structure that is not desirable as explained above. Here, the treatment of the uppermost layer of the multilayer reflective structure 34 means that the capping layer to be formed thereon can more easily achieve an amorphous structure. As explained above, an amorphous capping layer is desirable because it reduces imperfections on the EUV mask 18, improves lithography performance, and extends the lifetime of the EUV mask 18.One reason that the treatment of the multilayer reflective structure 34 enables the formation of an amorphous structure includes free energy. When a film is formed on a substrate, there is a free energy area of the substrate, and a free energy of the film and a free energy of an interface between the substrate and the film. A free energy delta may be defined as: the free energy of the film + the free energy of the interface - the free energy of the surface of the substrate. A free energy delta of less than 0 is associated with a Volmer-Weber mode of film formation, in which first "islands" are formed and these islands then fuse into a continuous film. This is undesirable because the film formed in this manner is more likely to have a polycrystalline structure and thus may be easily damaged. On the other hand, a free energy delta of more than 0 is associated with a Frank Van der Merwe mode of film formation, wherein the film is grown (grown) layer by layer, each layer mimicking the structure of the underlying layer. This is more desirable because the layer(s) formed in this manner can more easily achieve the amorphous structure. Here, the treatment process 200 de-wets the top surface of the multi-layered reflection structure 34 and makes the free energy delta higher than 0, enabling the formation of the amorphous film of the capping layer 100 layer by layer.In some embodiments, the treatment process 200 includes applying plasma to the top layer (e.g., a silicon layer of the Si / Mo film pair) of the multi-layer reflective structure 34. The plasma treatment of the upper surface of the multilayer reflective structure 34 removes spots or fats and other contaminants from the upper surface, thereby improving the uniformity of the upper surface. In some embodiments, the plasma process is performed with a temperature range between about 28 degrees Celsius and about 35 degrees Celsius, and with a duration range between about 5 seconds and about 60 seconds. Such a temperature range and a time duration range are not randomly selected, but are specifically configured to optimize the effects of plasma treatment of the uppermost layer of the multilayer reflective structure 34. For example, if the temperature range and / or the time duration range are too long or too short, this may interfere with the formation of the amorphous capping layer over the treated surface of the multilayer reflective structure 34.Referring now to FIG. 5, the capping layer 100 is formed on the top layer of the multi-layer reflective structure 34. Again, the capping layer 100 may be formed using the capping layer forming process 110 explained above, which may include an epitaxial growth process, a CVD process or a PVD process. As explained above, the capping layer 100 has an amorphous structure, and may include Ru, RuO 2, RuNb, RuNbO, RuON, RuN, RuNbON, RuTaON, RuZr, or RuZrO. As explained above, the process parameters of the capping layer formation process 110 may be configured such that the capping layer 100 has the thickness 120, which may be in a range between about 2.5 nm and about 6 nm.It is understood that the embodiment discussed above with reference to FIGS. 2 to 3 and the embodiment discussed above with reference to FIGS. 4 to 5 may be combined to enable the formation of the capping layer 100. For example, in some embodiments, the treatment process 200 may be performed to treat the multi-layer reflective structure 34. Thereafter, the amorphous layer 50 (e.g., an amorphous Si layer, an amorphous SiN layer, or an amorphous SiO 2- layer) may be formed on the treated surface of the multilayer reflective structure 34. The treated surface of the multilayer reflective structure 34 may also allow the formation of the amorphous structure for the amorphous layer 50. Thereafter, the capping layer 100 may be formed on the amorphous layer 50.Regardless of how the capping layer 100 is formed to achieve an amorphous structure, further fabrication processing may be performed to complete the fabrication of the EUV mask 18. For example, referring now to FIG. 6, an absorber layer 240 (also referred to as an absorption layer) is formed over the capping layer 100. In some embodiments, the absorber layer 240 absorbs the EUV radiation directed at the EUV lithography mask 18. In various embodiments, the absorber layer may be formed from tantalum boron nitride (TaN), tantalum boron oxide (TaBO) or chromium (Cr), radium (Ra), or a suitable oxide or nitride (or an alloy) of one or more of the following materials: actinium, radium, tellurium, zinc, copper, aluminum, nickel, and nickel alloys.It should be appreciated that in some embodiments, a buffer layer may optionally be formed between the capping layer 100 and the absorber layer 240. The buffer layer may serve as an etch stop layer in a patterning or repair process of the absorber layer 240. The buffer layer may have different etching properties than the absorber layer disposed above. In some embodiments, the buffer layer may include ruthenium, Ru compounds such as RuB or RuSi, chromium, chromium oxide, or chromium nitride.Referring now to FIG. 7, a photoresist layer 260 is formed over the absorber layer 240 from the back side 44 using a photoresist forming process 270. In some embodiments, the photoresist formation process 270 may include a spin coating process. The photoresist layer 260 may be an EUV photoresist (e.g. sensitive to radiation in the EUV range). The photoresist layer 260 is patterned into multiple portions separated by multiple openings, for example, openings 280, 281, and 282. In some embodiments, the patterning of the photoresist layer 260 may include an electron beam (e-beam) exposure process, a post-exposure firing process, and a photoresist development process.Referring now to FIG. 8, the absorber layer 240 is etched using an etching process 300 with the patterned photoresist layer 260 serving as an etch mask. In other words, the openings 280- 282 are vertically extending through the absorber layer 240 until portions of the capping layer 100 are exposed through the openings 280- 282. In some embodiments, the etching process 300 may include a dry etching process. The capping layer 100 effectively serves as an etch stop layer for the etching process 300. For conventional EUV lithography masks in which the capping layer has a polycrystalline structure, the etching process 300 may damage the capping layer through the grain boundaries of the polycrystalline structure. For example, minute cracks may occur on the exposed upper surfaces of the polycrystalline capping layer, or the exposed portions of the polycrystalline capping layer may have excessively roughened upper surfaces. These deficiencies can have a negative effect on the lithography performance and / or shorten the service life of the EUV lithography mask. In comparison, the capping layer 100 herein is formed to have an amorphous structure that allows it to withstand an etching process 300 without substantially damaging. For example, even after the etch process 300 is performed, the top surfaces of the exposed portions of the capping layer 100 may be substantially flatter and smoother than the polycrystalline capping layer used for conventional EUV lithography masks.Referring now to FIG. 9, a photoresist removal process 320 is performed to remove the patterned photoresist layer 260. In some embodiments, the photoresist removal process 320 includes a photoresist stripping or ash process. The photoresist removal process 320 may also damage the polycrystalline capping layer implemented in conventional EUV lithography masks. However, since the EUV lithography mask 18 herein instead implements an amorphous capping layer, the photoresist removal process 320 may be performed without substantial damage to the capping layer 100.Referring now to FIG. 10, a photoresist formation process 350 is performed to form another patterned photoresist layer 360 over the EUV lithography mask 18. In some embodiments, the photoresist formation process 350 may include a spin coating process. The photoresist layer 360 may be an EUV photoresist (e.g. sensitive to radiation in the EUV range). The photoresist layer 360 is patterned into multiple portions separated by multiple openings, for example, openings 380 and 381. The openings 380-381 expose portions of the absorber layer 240. Patterned photoresist layer 360 also fills openings 280-282. In some embodiments, the patterning of the photoresist layer 260 may include an electron beam (e-beam) exposure process or a laser beam exposure, a post-exposure firing process, and a photoresist development process.Referring now to FIG. 11, an etching process 400 is performed on the EUV lithography mask 18 from the side 44. The patterned photoresist layer 360 serves as a protective layer during the etching process 400 to protect the layers located thereunder from the etching. At this time, the etching process 400 etches away portions of the absorber layer 240, the capping layer 100, the amorphous layer 50 (in embodiments in which the amorphous layer 50 is formed), and the multi-layer reflective structure 34. Therefore, the openings 380- 381 are extended downward (from side 44 to side 42) and through the absorber layer 240, capping layer 100, amorphous layer 50, and multilayer reflective structure 34. The etching process 400 stops when the LTEM substrate 30 has been reached, and portions of the LTEM substrate 30 are thereby exposed through the openings 380- 381.Referring now to FIG. 12, a photoresist removal process 420 is performed to remove the patterned photoresist layer 360. In some embodiments, the photoresist removal process 420 includes a photoresist stripping or ash process. The photoresist removal process 420 may further damage the polycrystalline capping layer implemented in conventional EUV lithography masks. However, since the EUV lithography mask 18 herein instead implements an amorphous capping layer, the photoresist removal process 420 may be performed without substantial damage to the capping layer 100.After performing the photoresist removal process 420, one or more cleaning processes may also be performed to clean the EUV lithography mask 18, for example, to remove impurity particles disposed on the EUV lithography mask 18. Because portions of the capping layer 100 are still exposed by the openings 280- 282, the chemicals (e.g., a solution comprising oxygen and / or hydrogen) used in the one or more cleaning processes would seep into the cracked or roughened surfaces of the capping layer and thereby further damage the capping layer if the capping layer had been reacted using a polycrystalline material. However, since the capping layer 100 herein has been implemented using an amorphous material, the cleaning processes according to embodiments of this disclosure do not cause damage to the capping layer 100.Referring now to FIG. 13, one or more wafer printing processes 470 may be performed using the EUV lithography mask 18. In other words, the EUV lithography mask 18 may be used as a lithography mask in one or more EUV lithography processes to define or pattern various features on a semiconductor wafer. The wafer printing processes 470 may produce degassing products, such as degassing products including carbon, hydrogen, oxygen, etc. These degassing products may contact various components of the EUV lithography mask 18, including the exposed surfaces of the capping layer 100. If the capping layer 100 had been implemented using a polycrystalline material (e.g., in conventional EUV lithography masks), such exposed surfaces may have already been extensively damaged (e.g., excessive roughness or cracks) when the wafer printing processes 470 are performed. It would be easier for outgassing products to adhere to the exposed (and damaged) surfaces of the cover layer, as the roughened surfaces of such cover layer may include outgassing products. The presence of outgassing products on the damaged capping layer surfaces contaminate the EUV lithography mask and would further reduce the performance of the lithography process. For example, the reflectivity of the multilayer reflective structure 34 would be undesirably altered by outgassing products adhering to the capping layer surfaces. Again, the EUV lithography mask 18 of this disclosure does not suffer from this problem, as the amorphous capping layer 100 is substantially free of damage and the outgassing products generated by the wafer printing process 470 therefore do not adhere to the exposed surfaces of the capping layer 100. As a result, this disclosure avoids the undesirable contamination of the EUV lithography mask 18.FIG. 14 is a flow diagram of a method 600 of performing a semiconductor fabrication process in accordance with various aspects of this disclosure.The method 600 includes a step 610 of forming a multi-layer reflective structure over a substrate. In some embodiments, the reflective structure comprises a multilayer structure configured to provide a high reflectivity for a predetermined radiation wavelength, for example, a reflectivity above a predetermined limit.The method 600 includes a step 620 of depositing or roughening an amorphous layer over the multilayer reflective structure. In some embodiments, depositing or growing the amorphous layer includes depositing or growing an amorphous silicon layer, an amorphous silicon oxide layer, or an amorphous silicon nitride layer.The method 600 comprises a step 630 of depositing or roughening a capping layer over the amorphous layer. In some embodiments, depositing or growing the capping layer includes depositing or growing an amorphous material including ruthenium as the capping layer. The amorphous material may further include oxygen, niobium, nitrogen, tantalum, or zirconium.The method 600 comprises a step 640 of performing an EUV lithography process. For example, the substrate, the multilayer reflection structure, the amorphous layer and the capping layer may be portions of an extreme ultraviolet lithography mask (EUV lithography mask). The EUV lithography process may be performed using the EUV lithography mask.It is understood that further processes may be performed before, during, or after steps 610- 640 of the method 600 to complete the fabrication of the lithography mask. For example, prior to depositing or growing the amorphous layer, the method 600 may include a step of performing a plasma treatment process on the multi-layer reflective structure. In some embodiments, the plasma treatment process includes applying Ar plasma, O2plasma, or N2plasma to the multi-layer reflective structure. For simplicity, further steps will not be explained in detail herein.FIG. 15 is a flow diagram of a method 700 of performing a semiconductor fabrication process in accordance with various aspects of this disclosure.The method 700 includes a step 710 of forming a multi-layer reflective structure over a substrate. In some embodiments, the reflective structure comprises a multilayer structure configured to provide a high reflectivity for a predetermined radiation wavelength, for example, a reflectivity above a predetermined limit.The method 700 comprises a step 720 of treating a multilayer reflective structure with plasma. In some embodiments, step 720 comprises treating the multi-layer reflective structure with Ar plasma, O2plasma, or N2plasma.The method 700 comprises a step 730 of forming an amorphous capping layer over the multi-layer reflection structure. Step 730 may be performed after the treatment of the multi-layer reflective structure.The method 700 comprises a step 740 of performing an EUV lithography process. For example, the substrate, the multilayer reflection structure, the cover layer can be portions of an extreme ultraviolet lithography mask (EUV lithography mask). The EUV lithography process may be performed using the EUV lithography mask.It is understood that further processes may be performed before, during, or after steps 710- 740 of the method 700 to complete the fabrication of the lithography mask. For example, after the treatment of step 720, but before forming the amorphous capping layer of step 730, the method 700 may include a step of forming a first layer over the multi-layer reflective structure. The amorphous capping layer is formed over the first layer. In some embodiments, the first layer is formed to have a different type of amorphous material than the amorphous capping layer. For simplicity, further steps will not be explained in detail herein.All in all, this disclosure forms an amorphous capping layer for an EUV lithography mask. The amorphous capping layer may be formed by substrate adjustment, which may include first forming a thin amorphous layer on a multi-layered reflection structure and then forming the amorphous capping layer on the thin amorphous layer using an epitaxial process or a CVD or PVD process. The amorphous capping layer may also be formed by treating the multi-layered reflective structure and then forming the amorphous capping layer on the treated surface of the multi-layered reflective structure using an epitaxial process or a CVD or PVD process.Based on the above explanations, it can be seen that the EUV mask of this disclosure provides advantages over conventional EUV masks. It should be understood, however, that other embodiments may provide other advantages, and that not all advantages are necessarily disclosed herein, and that no particular advantage is required for all embodiments. An advantage is that the EUV lithography mask of this disclosure can achieve a better film quality for the capping layer than conventional EUV lithography masks. As explained above, conventional EUV lithography masks form a polycrystalline capping layer, the grain boundaries of which may be easily damaged due to various etching and / or cleaning processes being performed. The damaged polycrystalline capping layer may result in reduced lithography performance (e.g., poorer critical dimensions). In comparison, the EUV lithography mask herein forms an amorphous capping layer that can resist the damaging effects of the various etching and / or cleaning processes much better than the polycrystalline capping layer. Therefore, the amorphous capping layer has an improved film quality, and therefore the EUV lithography mask herein has an improved lithography performance than conventional EUV lithography masks.Furthermore, since EUV lithography masks are used for wafer printing, outgassing products can be generated. These outgassing products more easily adhere to exposed surfaces of the damaged polycrystalline capping layer of conventional EUV lithography masks, which may degrade lithography performance. Because the amorphous capping layer is substantially free of damaged areas, the outgassing products here are therefore less likely to stick to the EUV lithography mask of this disclosure. As a result, lithography performance is improved.Furthermore, the damaged polycrystalline cover layer of conventional EUV lithography masks can make the conventional EUV mask fail more quickly or at least lead to a deterioration of the EUV lithography mask, so that said mask no longer provides satisfactory performance and should be replaced. In other words, the tendency of the polycrystalline capping layer to damage may shorten the lifetime of the conventional EUV lithography mask. In comparison, the amorphous capping layer herein may substantially extend the lifetime of the EUV lithography mask. Because it may be expensive to replace or repair EUV lithography masks, this disclosure may significantly reduce the cost of manufacture.One aspect of this disclosure relates to an apparatus. The device comprises a substrate. The device includes a multilayer reflective structure disposed over the substrate. The device includes an amorphous capping layer disposed over the multilayer reflective structure.Another aspect of this disclosure relates to a method. The method includes forming a multi-layer reflective structure over a substrate. The method includes depositing or growing an amorphous layer over the multi-layer reflective structure. The method includes depositing or growing a capping layer over the amorphous layer.Yet another aspect of this disclosure relates to a method. The method includes forming a multi-layer reflective structure over a substrate. The method includes treating the multi-layer reflective structure with plasma. The method includes: after the treating, forming an amorphous capping layer over the multi-layer reflective structure.

Claims

A method comprising: forming a multi-layer reflective structure (34) over a substrate (30); performing a plasma treatment process on the multi-layer reflective structure (34); depositing or growing an amorphous layer (50) over the multi-layer reflective structure (34); and depositing or growing a capping layer (100) over the amorphous layer (50).The method of claim 1, wherein the substrate (30), the multilayer reflective structure (34), the amorphous layer (50), and the capping layer (100) are portions of an extreme ultraviolet lithography mask, EUV lithography mask, and wherein the method further comprises: providing the EUV lithography mask to a device that performs an EUV lithography process.The method of claim 1 or 2, wherein depositing or growing the amorphous layer (50) comprises depositing or growing an amorphous silicon layer, an amorphous silicon oxide layer, or an amorphous silicon nitride layer.The method of claim 1 or 2, wherein depositing or growing the capping layer (100) comprises depositing or growing an amorphous material containing ruthenium as the capping layer.The method of claim 4, wherein the amorphous material further comprises: oxygen, niobium, nitrogen, tantalum, or zirconium.The method of any preceding claim, wherein the plasma treatment process comprises applying Ar plasma, O 2- plasma or N 2- plasma.A method comprising: forming a multi-layer reflective structure (34) over a substrate (30); treating the multi-layer reflective structure (34) with plasma; and after the treating, forming an amorphous capping layer (100) over the multi-layer reflective structure.The method of claim 7, further comprising: after treating, but before forming, the amorphous capping layer (100), forming a first layer (50) over the multilayer reflective structure (34), wherein the amorphous capping layer (100) is formed over the first layer.The method of claim 8, wherein the first layer (50) is formed to have a different type of amorphous layer than the amorphous capping layer (100).The method of claim 9, wherein the first layer (50) includes amorphous silicon, amorphous silicon oxide, or amorphous silicon nitride.The method of any of claims 7 to 10, wherein the treating comprises treating the multi-layer reflective structure (34) with Ar plasma, O 2- plasma, or N 2- plasma.The method of any of claims 7 to 11, wherein the amorphous capping layer (100) comprises ruthenium.The method of claim 12, wherein the amorphous capping layer (100) comprises oxygen, niobium, nitrogen, tantalum, or zirconium.The method according to any of the preceding claims, wherein the amorphous capping layer (100) contains Ru, RuO 2, RuNb, RuNbO, RuON, RuN, RuNbON, RuTaON, RuZr or RuZrO.The method of any preceding claim, wherein the amorphous capping layer (100) includes: RuNb, wherein an atomic weight of the Nb is below 50%; or RuNbO, wherein an atomic weight of the Nb is below 50%.The method of any preceding claim, wherein the multilayer reflective structure (34) is formed with a plurality of pairs of silicon and molybdenum films.The method of any preceding claim, wherein an apparatus is formed that is an extreme ultraviolet lithography mask.Use of a device manufactured by a method according to any one of claims 1 to 16 as an extreme ultraviolet lithography mask.

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