Procedure and structure

Abstract

Procedure comprising: Receiving a substrate (220) having a contact layer (245) formed thereon, wherein the contact layer (245) has conductive structures (225, 230); and Forming via openings (250, 255, 275) in a dielectric layer (260) disposed on the contact layer (245), the via openings (250, 255, 275) exposing upper surfaces of the conductive structures (225, 230); Depositing (105) a first metal layer (300) in the via openings (250, 255, 275), wherein the first metal layer (300) is deposited thicker on an upper surface of the conductive structures (225, 230) than on sidewall surfaces of the via openings (250, 255, 275); Exposing (110) the first metal layer (300) to ammonia to form a bilayer (410) on the upper surfaces of the conductive structures (225,230), the bilayer (410) comprising the first metal layer (300) and a nitride (400) of the first metal layer; Exposing (115) the nitride (400) of the first metal layer to an oxygen plasma to convert a portion of the nitride (400) of the first metal layer into an oxide layer (500) of the first metal layer; Removing (120) the oxide layer (500) of the first metal layer; and Forming (125) a semiconductor-containing layer (700) on the nitride (400) of the first metal layer in the bilayer (410').

Description

BACKGROUNDIn an integrated circuit, conductive structures (e.g., metal contacts) are electrically coupled to transistor regions, such as the gate electrode and the source / drain regions, and are configured to propagate electrical signals from and to the transistors. The conductive structures may form one or more layers of metal wiring depending on the complexity of the integrated circuit. U.S. Pat. No. 2018,0 138,123 A1 describes a semiconductor component having a through-connection with a barrier layer. US 2013 0 075 912 A1 describes a method for producing a semiconductor component having a vertical by contacting. U.S. Pat. No. 6,404,054 B1 describes a method for forming a tungsten layer of a semiconductor component on a barrier layer using a tungsten seed layer. U.S. Pat. No. 6,091,148 A describes compounds with transition metals or transition metal nitrides for semiconductor components.BRIEF DESCRIPTION OF THE DRAWINGSAspects of the present disclosure may best be understood from the following detailed description taken in conjunction with the accompanying drawings. It should be noted that, in accordance with practice common in the industry, various features are not drawn to scale. Indeed, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased. FIG. 1 is a method of forming a blocking structure between liner-free vias and a contact layer, in accordance with some embodiments. FIGS. 2-8 are cross-sectional views of intermediate structures during the fabrication of a barrier structure formed between linerless vias and a contact layer, in accordance with some embodiments. FIGS. 9-10 are cross-sectional views of blocking structures formed between linerless vias and a contact layer, in accordance with some embodiments.DETAILED DESCRIPTIONThe following disclosure provides many different embodiments or examples for implementing different features of the subject matter discussed herein. Concrete examples of components and arrangements will be described below in order to simplify the present disclosure. For example, forming a first feature on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features such that the first and second features are not in direct contact. Moreover, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition does not automatically provide a relationship between the various embodiments and / or configurations discussed.Furthermore, spatially relative terms such as "below," "below," "lower," "above," "upper," and the like may be used herein to facilitate the description to describe the relationship of an element or feature to one or more other elements or features as illustrated in the drawings. The spatially relative terms are intended to encompass other orientations of the device in use or operation besides the orientation shown in the drawings. The device may also be otherwise oriented (rotated 90 degrees, or other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.The term "nominal" as used herein refers to a desired or target value of a property or parameter for a component or process operation set during the design phase of a product or process, along with a range of values above and / or below the desired value. The range of values may be due to slight deviations in manufacturing processes and / or tolerances.In some embodiments, the terms "about" and "substantially" may indicate a value of a particular quantity that varies within 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values are merely examples and are not intended to be limiting. It should be understood that the terms "about" and "substantially" may refer to a percentage of the values as interpreted by one of ordinary skill in the art in light of the teachings described herein.Active and passive devices in an integrated circuit (IC) are locally and globally connected to conductive structures such as metal contacts, metal vias, and metal lines. These conductive structures are formed in metallization layers stacked one above the other. The formation of each metallization layer requires multiple operations, including, for example, depositing dielectric and conductive materials, photolithography and etching (e.g., patterning), removing contaminants (e.g., wet cleaning), polishing and planarization, etc. These fabrication operations must be compatible with the materials used in the underlying metallization layers to avoid defects and other integration problems.Conductive structures that do not have barrier or liner layers between a metal fill and surrounding materials (also referred to herein as "liner-free conductive structures") have become attractive because they have lower electrical resistance properties compared to conductive structures with barrier or liner layers. Challenges arise in the production processing of liner-free conductive structures because such structures require filler metals which can be grown on the bottom-up principle ("from bottom to top"). In the bottom-up principle, metal growth begins at nucleation sites at the bottom of the conductive structure. As examples, and not by way of limitation, metals that can be grown by a bottom-up process include molybdenum (Mo), tungsten (W), ruthenium (Ru), iridium (Ir), cobalt (Co), etc. However, since the metal grows from below and fills contact or via openings, gaps may be formed between sidewall surfaces of the contact or via openings and the metal. These gaps may arise, for example, in that the grain of the metal is not aligned with the side wall surfaces of the contact or via openings. These gaps may extend vertically along the sidewall surfaces of the conductive structure and form a path through which chemicals used in subsequent processes may reach and erodible underlying conductive structures. These chemicals may include wet etching chemicals, wet cleaning solutions, chemical mechanical planarization (CMP) slurry, etc.To overcome the deficiencies discussed above, this disclosure relates to a method of forming a barrier structure between linerless conductive structures (e.g., linerless metal vias) and underlying conductive structures (e.g., metal contacts) to prevent mud or other chemicals from processes used in the linerless conductive structures from reaching and erodible the metal fill of underlying conductive structures. In some embodiments, the barrier structure comprises a titanium / titanium nitride (Ti / TiN) bilayer having a silicide or germanide layer thereon. In some implementations, the silicon (Si) or germanium (Ge) incorporated into the barrier structure acts as a seed for subsequent bottom-up growth of the metal fill in the liner-free conductive structures. In some implementations, forming the barrier structure includes, among other things, depositing, nitriding, and oxidizing a titanium (Ti) layer on the sidewall surfaces and bottom surfaces of via or contact openings, and then depositing an amorphous Si or Ge layer. In some embodiments, the method is not limited to Ti layers. For example, other metals such as tantalum (Ta) or nickel (Ni) may also be used.FIG. 1 is a flow diagram of a fabrication method 100 describing the formation process of a barrier structure between a linerless conductive structure and an underlying conductive structure. In some embodiments, the fabrication method 100 forms the aforementioned blocking structure in a bottom surface of a via or contact opening that is subsequently filled with a liner-free conductive material. Other manufacturing operations may also be performed between the various operations of the method 100, and may be omitted, for clarity and ease of description only. These various operations are within the spirit and scope of this disclosure. Moreover, not all operations may be required to practice the present disclosure. Some of the operations may be performed simultaneously or in a different order than shown in FIG. 1. In some embodiments, one or more other operations may be performed in addition to or in place of the operations described herein. The method 100 will be described with reference to FIGS. 2-9, which are for illustration purposes only and are not to scale. Some structures, films, or geometries may have been intentionally enlarged or omitted for purposes of illustration.By way of example, and not limitation, FIG. 2 is a cross-sectional view of a precursor structure 200 used as a starting point for the method 100. In some embodiments, precursor structure 200 includes gate structures 205 / 210 and source / drain (S / D) epitaxial stacks 215 formed on a semiconductor substrate 220. In the example of the precursor structure 200, the gate contact 225 and the S / D contact 230 are disposed on the gate structure 205 and the S / D epitaxial stack 215, respectively, as shown in FIG. 2. In some embodiments, another gate contact (not shown) may be formed on the gate structure 210. The gate structures (e.g., gate structures 205 and 210) and the contacts (e.g., gate contact 225 and S / D contact 230) are electrically insulated by dielectric layers 235 and 240. In some embodiments, the gate contact 225 and the S / D contact 230 together with the dielectric layers 235 and 240 form a contact layer 245, for example a first metallization layer. In FIG. 2, the contacts (e.g., gate contact 225 and S / D contact 230) are shown having a "curved" bottom surface, as opposed to a flat bottom surface. In some embodiments, this may be attributed to the etching process used in the contact opening formation process that recesses (e.g., over-etches) the underlying structure to increase the surface area between the contact and the underlying structure.As shown in FIG. 2, via openings 250 and 255 are formed in a dielectric layer 260 disposed on the dielectric layer 240 of the contact layer 245. Via openings 250 and 255, which may be formed by photolithography and etching operations and have an aspect ratio between about 5:1 and about 8:1, expose top surfaces of gate contact 225 and S / D contact 230. In some embodiments, via openings 250 and 255 are filled with a metal (e.g., Mo, Ru, or W) to form linerless vias connected to respective contacts of underlying contact layer 245. As shown in FIG. 2, vias 250 and 255 may have a "curved" bottom surface with gate contact 225 and S / D contact 230, as discussed above.FIG. 2 further includes a resistor structure 270. Resistor structures (such as resistor structure 270) are passive elements used to reduce current flow, adjust signal levels, divide voltages, etc., for example. In some embodiments, the resistor structure 270 includes TiN or another resistor material such as tungsten nitride (WN). A via 275, like via 250 and 255, is formed in dielectric layer 260 to expose a portion of resistor structure 270. In some embodiments, the resistor structure 270 is embedded in an etch stop layer 280, which facilitates forming the via openings 250, 255, and 275. Similar to via openings 250 and 255, opening 275 is filled with a metal (e.g., Mo, Ru, or W) to form a liner-free via to connect resistor structure 270 to upper metallization layers.In some embodiments, the semiconductor substrate 220 is a bulk semiconductor wafer (e.g., a bulk silicon wafer), a top semiconductor layer of a semiconductor on insulator (SOI) wafer, or a semiconductor fin structure formed on a bulk wafer or an SOI wafer. By way of example, and not limitation, S / D epitaxial stack 215 forms an S / D region for gate structures 205 and 210 and includes one or more epitaxially grown layers, such as boron-doped silicon germanium (B:SiGe) or phosphorus-doped silicon carbon (P:SiC). In some embodiments, gate structures 205 and 210 include multiple layers, which are not shown in FIG. 2 for simplicity. By way of example, and not limitation, these layers may include a gate dielectric stack, one or more work function layers, and a metal fill. The gate structures 205 and 210 are insulated from the epitaxial stack 215 by spacer structures 265, which may include one or more dielectric layers, such as silicon nitride (Si 3 N 4), for example. In some embodiments, dielectric layers 235, 240, and 260 are silicon oxide-based interlayer dielectric (ILD) layers, which may include carbon, hydrogen, and nitrogen. Dielectric layers 235, 240, and 260 may be deposited using a chemical vapor deposition (CVD) process, a plasma enhanced CVD (PECVD) process, or any other suitable deposition process.According to some embodiments, the gate contact 225 and the S / D contact 230 are filled with a metal 270 surrounded by the liner layer 275. By way of example, and not limitation, the metal 270 includes Co and the liner layer 275 includes a Ti / TiN stack. Referring to the S / D contact 230, the Ti layer from the liner layer 275 reacts with the silicon atoms in the S / D epitaxial stack 215 and forms a silicide layer 280 (for example, a titanium silicide layer (TiSi x)), which reduces the contact resistance between the S / D contact 230 and the S / D epitaxial stack 215. In some embodiments, the silicide layer 280 is not limited to TiSi x. For example, the silicide layer 280 may be nickel silicide (NiSi) or cobalt silicide (CoSi).Referring to FIG. 1, the method 100 begins with operation 105 and the process of depositing a Ti layer on sidewall and bottom surfaces of a via opening, such as via openings 250, 255, and 275 of the precursor structure 200 shown in FIG. 2. By way of example, and not limitation, FIG. 3 shows precursor structure 200 after formation of a Ti layer 300 according to operation 105 of method 100. In some embodiments, the deposition process used to form the Ti layer 300 is configured to deposit a thicker Ti layer on horizontal surfaces (e.g., the bottom surfaces of via openings 250 / 255 / 275 and the top surface of dielectric layer 260) and a thinner Ti layer on vertical surfaces (e.g., the sidewall surfaces of via openings 250, 255, and 275). For example, the thickness 310 of the Ti layer 300 on the bottom surface of the via openings 250 / 255 and 275 is greater than the thickness 320 of the Ti layer 300 on sidewall surfaces of the via openings 250 / 255 and 275. Therefore, the bottom coverage of the Ti layer 300 is greater than the sidewall coverage. Deposition techniques that may achieve such a non-conformal deposition profile include, but are not limited to, physical vapor deposition (PVD) techniques, such as ionized metal plasma (IMP) deposition.In some embodiments, the thickness 310 of the Ti layer 300 in the via openings 250 and 255 is in the range between about 5 nm and about 13 nm (e.g., about 10 nm), while the thickness 320 is in the range between 0 nm and less than about 5 nm (e.g., about 2 nm). Thicker (e.g., greater than about 13 nm) or thinner (e.g., less than about 5 nm) Ti layers are possible; however, thinner Ti layers (e.g., less than about 5 nm) may not form a barrier structure with sufficient barrier properties, and thicker Ti layers (e.g., greater than about 13 nm) may unnecessarily increase via resistance. In some embodiments, the process conditions used for Ti layer deposition may be adjusted to achieve the desired bottom and sidewall coverage shown in FIG. 3 based on the aspect ratio of via openings 250 and 255. By way of example, and not limitation, the upper width W of via openings 250 and 255 may be in the range between about 12 nm and about 20 nm. Further, the aspect ratio of via openings 250 and 255 (e.g., the ratio of height H to top width W) may be in the range between about 6 and about 8. In some embodiments, depositing the Ti layer 300 is a blanket deposition (blanket deposition). That is, the Ti layer 300 is deposited globally, i.e., outside the via openings 250 and 255, for example, on top surfaces of the dielectric layer 260 and in the via opening 275, as shown in FIG. 3. In some embodiments, via 275 has a smaller aspect ratio, for example between about 1 and about 3, compared to via 250 and 255.Alternatively, a Ta layer or a Ni layer may be deposited instead of the Ti layer 300. Additionally, the Ta or Ni layer may be deposited with a similar bottom and sidewall coverage as shown for the Ti layer 300 in FIG. 3. For example, the Ta or Ni layer may be deposited by a similar deposition method as used for the Ti layer 300. For illustrative purposes, the method 100 shown in FIG. 1 will be described with a Ti layer. However, based on the disclosure herein, other metal layers such as Ta or Ni may also be used. These metal layers are within the spirit and scope of this disclosure.Referring to FIG. 1, the method 100 continues with operation 110 and the process of treating the Ti layer 300 with ammonia (NH 3) to form TiN. In some embodiments, the NH 3- treatment described in operation 110 is performed in situ with respect to depositing the Ti layer 300. In other words, the NH 3- treatment of operation 110 is performed without vacuum interruption after the deposition of the Ti layer 300. This is intended to avoid oxidation of the deposited Ti layer as a result of a vacuum interruption.In some embodiments, the NH 3- treatment described in operation 110 is a thermal treatment performed at a temperature in the range between about 400° C. and about 450° C. for a duration of about 5 minutes. Treatment temperatures below about 400° C. require longer treatment times, which increases the overall process time and the manufacturing costs. On the other hand, higher treatment temperatures above about 450° C. may not be favorable for the stability of the layers included in the gate structures 205 and 210.In some embodiments, nitriding of the Ti layer 300 (e.g., forming the TiN) starts from the exposed upper surface of the Ti layer 300 and proceeds inward toward the lower surface of the Ti layer 300. In other words, during the NH3treatment described in operation 110, the Ti layer 300 is "converted" into TiN from the upper surface inward. Thus, the treatment in operation 110 may be timed such that thinner portions of the Ti layer 300 at the sidewall surfaces of the via openings 250 and 255 are completely converted to TiN while thicker portions of the Ti layer 300 are partially converted to TiN. Thus, a TiN layer may be formed on the sidewalls of via openings 250, 255, and 275 where Ti layer 300 is thinnest, and a Ti / TiN bilayer may be formed on the top surface of dielectric layer 260 and on the bottom surface of via openings 250, 255, and 275 where Ti layer 300 is thickest. By way of example, and not limitation, FIG. 4 shows precursor structures 200 and Ti layer 300 after forming a TiN layer 400 on sidewall surfaces of via openings 250, 255, and 275 and a Ti / TiN bilayer 410 on the bottom surface of via openings 250 / 255 / 275 and on the top surface of dielectric layer 260. In some embodiments, the thickness of the TiN layer 400 in the Ti / TiN bilayer 410 is about 3 nm and about 9 nm, and the thickness of the Ti layer 300 is between about 2 nm and 4 nm. In other words, the thickness of the Ti / TiN bilayer 410 is in the range between about 5 nm and about 13 nm. If the NH3treatment of operation 110 is extended (e.g., beyond about 5 min), then the Ti layer 300 at the bottom of via openings 250, 255, and 275 may be completely converted to a TiN layer 400, which is undesirable because TiN provides a higher resistance than Ti and a thicker TiN layer increases via resistance. Therefore, the NH 3- treatment time needs to be adjusted so that the TiN layer 400 has a sufficient thickness (e.g., blocking performance) without affecting via resistance. In some embodiments, the duration of the heat treatment may be adjusted based on the sidewall and bottom coverage of the Ti layer 300 and the desired thickness of the TiN in the Ti / TiN bilayer 410. In other words, a shorter treatment (e.g., shorter than about 5 min) would produce a thinner TiN layer 400 in the Ti / TiN bilayer 410 than a longer treatment time (e.g., longer than about 5 min).When Ta or Ni is used instead of Ti, the operation 110 forms a tantalum nitride (TaN) layer or a nickel nitride (Ni 3 N) layer instead of the TiN layer 400. Moreover, aspects of the TaN layer or Ni 3 N layer would be similar to the TiN layer 400 described above; these include, for example, the thickness profile of the TaN or Ni 3 N layer and forming a Ta / TaN or Ni / Ni 3 N bilayer on the bottom surface of the via openings 250, 255, and 275.Referring to FIG. 1, the method 100 continues with operation 115 and the process of exposing the TiN layer 400 to an oxygen plasma. In some embodiments, the oxygen plasma oxidizes the TiN layer 400 and may transition to oxidizing the Ti layer 300 if the duration of the oxidation process is sufficiently long.In some embodiments, the rate of reaction between the ions in the oxygen plasma and the TiN layer (e.g., the rate of oxidation of the TiN layer) is "mass transport" constrained. In other words, the oxidation rate of the TiN layer increases as the number of available oxygen ions increases and decreases as the number of available oxygen ions decreases. Thus, if the process conditions of the oxygen plasma process are configured such that the distribution (e.g., density) of oxygen ions is higher at the top of the via openings and lower at the bottom of the via openings, then a greater number of oxygen ions is available at the top of the via openings than at the bottom for oxidation of the TiN layer 400. This in turn means that the oxidation rate of the TiN layer 400 may increase at the top of the via openings and decrease at the bottom of the via openings.In some embodiments, the oxidation process of operation 115 is configured to form a density gradient of oxygen ions across the thickness of the dielectric layer 260. By way of example, and not limitation, curve 510 shown in FIG. 5 represents a Gaussian ion density profile in the oxygen plasma as a function of depth during operation 115. In this exemplary illustration, the x-axis corresponds to the number of oxygen ions per unit area (e.g., the density of oxygen ions), and the z-axis corresponds to a vertical distance measured from the top surface of the TiN layer 400 on the dielectric layer 260. As shown by the ion density profile of curve 510, the density of oxygen ions is higher at the top of via openings 250 / 255 / 275 and decreases toward the bottom surface of via openings 250, 255 and 275. In some embodiments, the ion density profile shown in FIG. 5 and represented by curve 510 is not limited to this representation, and alternative ion density profiles are possible, such as exponential or linear profiles. These alternative ion density profiles are within the spirit and scope of this disclosure. By way of example, and not limitation, forming a density gradient of oxygen ions across the thickness of the dielectric layer 260 may be achieved by removing any bias voltage applied to the substrate 220 during operation 115.Consequently, the TiN layer 400 disposed on sidewall surfaces of the via holes and the upper surface of the dielectric layer 260 may be completely oxidized, and the TiN layer 400 in the Ti / TiN double layer 410 at the lower surfaces of the via holes 250, 255, and 275 may be partially oxidized due mainly to the oxidation rate difference caused by the density gradient of oxygen ions in the plasma. It should be further noted that the thickness of the Ti / TiN bilayer 410 is reduced by an amount that is approximately equal to the thickness of the TiN oxidized by operation 115. In some embodiments, between about 62% and about 68% of the TiN layer 400 is oxidized during operation 115. By way of example, and not limitation, FIG. 5 shows the resulting TiO 2- layer 500 formed on the Ti / TiN bilayer 410 and thinner than the Ti / TiN bilayer 410 shown in FIG. 4, as discussed above. In some embodiments, the thickness of the TiO 2- layer 500 on the Ti / TiN bilayer 410' is between about 2 nm and 6 nm, the thickness of the TiN layer 400 is between about 1 nm and 3 nm, and the thickness of the Ti layer 300 is in the range between about 2 and 4 nm.In some embodiments, operation 115 is performed at a temperature in the range between about 160° C. and 250° C. In some embodiments, temperatures below about 160° C. may slow or even stop the oxidation reaction. On the other hand, temperatures above 250° C. may increase the oxidation rate in an uncontrollable manner or may compromise the stability of the layers contained in the gate structures 205 and 210. In some embodiments, if an oxygen plasma process is not desired due to feared plasma damage, the oxygen plasma process of operation 115 may be replaced with a thermal process. For example, the TiN layer 400 may be subjected to a anneal process in oxygen in a temperature range between about 350° C. and about 550° C. In some embodiments, the temperature range for the annealing process may be increased compared to the temperature range used in the oxygen plasma process.In cases where Ta or Ni is used, the operation 115 forms a tantalum oxide layer (TaO 5- layer) and a nickel oxide layer (NiO layer), respectively, instead of the TiO 2- layer 500. Furthermore, aspects of the TaO 5- or NiO layer would be similar to the TiO 2- layer 500 described above; this includes, for example, the thickness profile of the TaO 5- or NiO layer inside and outside the via openings 250 and 255.Referring to FIG. 1, the method 100 continues with operation 120 and the process of removing the TiO 2- layer formed during operation 115 with a chlorine-based etch chemical. In some embodiments, the chlorine-based etch chemical includes a metal such as tungsten (e.g., WCl 5), tantalum (TaCl 5), molybdenum (MoCl 5) or niobium (NbCl 5). In some embodiments, the etch chemical is selective to the metal oxide layer to be removed, for example, TiO 2, Ta 2 O 5 or NiO. For example, the selectivity between the metal oxide and other layers (e.g., dielectric layer 260 and Ti layer 300) may be about 100:1 or more. In some embodiments, the etching process is self-limiting when the layer underlying the metal oxide is a metal nitride (e.g., TiO 2 and TiN; Ta 2 O 5 and TaN; or NiO and Ni 3 N), or a dielectric layer such as dielectric layer 260. In accordance with some embodiments, the etching process is performed in a temperature range between about 400° C. and about 550° C. (e.g., between about 400° C. and 500° C.) to ensure that sufficient thermal energy is available for the etching reaction to occur and gaseous byproducts are formed so that they can be drawn from the etched surfaces. In some embodiments, temperatures above about 550° C. may not be desirable because, as discussed above, they may affect the stability of the layers in the gate structures 205 and 210.According to some embodiments, FIG. 6 illustrates the precursor structure 200 after the etching process described in operation 120. In FIG. 6, the TiN layer 400 is bounded on the bottom surface of the via openings 250, 255, and 275 within the TiN bilayer 410'. In addition, as discussed above, the TiN layer 400 in the Ti / TiN bilayer 410' is thinner than the TiN layer 400 in the Ti / TiN bilayer 410 shown in FIG. 4. In some embodiments, the thickness of the Ti / TiN bilayer 410' is about half the thickness 310 of the deposited Ti layer 300 shown in FIG. 3, for example between about 3 nm and about 7 nm. According to some embodiments, the Ti layer 300 and the TiN layer 400 form a barrier structure in the Ti / TiN bilayer 410' that protects the underlying metal 270 in the gate contact 225 and in the S / D contact 230.In some embodiments, the Ti / TiN bilayer 410' formed in the via opening 275 may not be as critical as in the via openings 250 and 255 if the resistor structure 270 includes, for example, TiN or a material that is not prone to erosion. However, in embodiments where the resistor structure 270 includes an erosion-prone material or layer, the Ti / TiN bilayer 410' may be used to protect the resistor structure 270.Referring to FIG. 1, the method 100 continues with operation 125 and the process of depositing an amorphous silicon ("a-Si" or "Si") on Ti / TiN bilayer 410' to form a silicon-containing layer used as a nucleation layer (e.g., seed layer) for bottom-up deposition of the metal in the via openings 250, 255, and 275. In some embodiments, the formed silicon-containing layer may also contain titanium and nitrogen originating from the underlying Ti / TiN bilayer 410'. In some embodiments, Si is deposited with a CVD process that includes a pretreatment with titanium chloride (TiCl 4) at a temperature between about 400° C. and about 550° C., followed by in situ silane soak (SiH 4- soak) at a substantially similar temperature range (e.g., between about 400° C. and about 550° C.). Other suitable deposition methods for the silicon-containing layer may also be used. As discussed above, temperatures above 550° C. should be avoided to protect the layers in the gate structures 205 and 210. Furthermore, temperatures below 400° C. may not be sufficient to decompose the SiH 4- precursor or form the silicon-containing layer.In some embodiments, an amorphous germanium layer ("a-Ge" or "Ge") may be deposited using a similar deposition method instead of Si. The Ge layer deposition may include, for example, a titanium chloride (TiCl 4) pretreatment at a temperature between about 400° C. and about 550° C., followed by in situdeposition of Ge using a monogermane precursor (GeH 4- precursor) at a substantially similar temperature range (for example, between about 400° C. and about 550° C.). By way of example, and not limitation, Ge may be deposited by CVD or any other suitable deposition method. As discussed above, temperatures above 550° C. should be avoided to protect the layers in the gate structures 205 and 210. Furthermore, temperatures below 400° C. may not be sufficient to decompose the GeH 4- precursor or form the germanium-containing layer. In some embodiments, such as in the silicon-containing layer, the formed germanium-containing layer contains titanium and nitrogen originating from the underlying Ti / TiN bilayer 410'.Referring to FIG. 7, during the above-mentioned Si deposition process (or Ge deposition process), a silicon-containing layer (or a germanium-containing layer) 700 is formed on the Ti / TiN double layer 410'. In some embodiments, the silicon-containing barrier layer (or germanium-containing layer) 700 has a thickness between about 1 Å and about 10 Å. According to some embodiments, the above-mentioned deposition temperature (e.g., between about 400° C. and about 550° C.) is sufficient to initiate diffusion of silicon atoms into the underlying TiN to form the silicon-containing layer (or germanium-containing layer) 700, e.g., TiSiN (or TiGeN). In some embodiments, the resulting silicon-containing layer (or germanium-containing layer) also includes silicon-hydrogen bonds (or germanium-hydrogen bonds). By way of example, and not limitation, forming a silicon-containing (or germanium-containing) layer 700 having a thickness greater than about 10 Å may unnecessarily increase via resistance without providing additional advantages, while a thickness less than about 1 Å may not support bottom-up growth of the metal in via openings 250, 255, and 275. In some embodiments, the thickness of the silicon (or germanium) layer 700 may be controlled by process conditions such as the deposition time.In some embodiments, the silicon (or germanium) layer 700 is selectively formed on exposed surfaces of the TiN layer 400 and not on the dielectric layer 260. This is because TiN surfaces, unlike dielectric surfaces, are capable of providing electrons to break up the silicon hydrogen or germanium hydrogen and allow silicon or germanium to bond to the TiN surfaces.As discussed above, other metals may be used in place of Ti, for example, Ta or Ni. When Ta or Ni is used, the silicon (or germanium) layer 700 may include Ta, Si (or Ge), and nitrogen, or Ni, Si (or Ge), and nitrogen. In some embodiments, and depending on the thickness of the Ti layer 300, the silicon (or germanium) layer 700 may also include Co. For example, if the Ti layer 300 is thin (e.g., about 5 nm), the silicon (or germanium) layer 700 may include Ti, Co, nitrogen, and Si (or Ge). When Ta or Ni is used, the silicon-containing (or germanium-containing) layer 700 may include Ta, Co, nitrogen and Si (or Ge), or Ni, Co, nitrogen and Si (or Ge).Referring to FIG. 1, the method 100 continues with operation 130 and the process of growing a liner-free metal directly on the silicon (or germanium) layer 700 to fill the via openings 250, 255, and 275. As discussed above, the silicon (or germanium) layer 700 acts as a nucleation layer for subsequent metal deposition in the via openings 250, 255, and 275. For example, the silicon-hydrogen bonds (or germanium-hydrogen bonds) in the silicon-containing (or germanium-containing) layer 700 may facilitate bottom-up growth of the via metal. For example, in the case of Mo, Mo may be deposited in a temperature range between about 175° C. and about 275° C. and at a pressure between about 1 Torr and about 3 Torr using molybdenum hexafluoride (MoF 6) and hydrogen by CVD. In some embodiments, the thickness of the metal in the deposited state is between about 50 nm and about 150 nm. According to some embodiments, FIG. 8 shows the precursor structure 200 after bottom-up deposition of the via metal 800 (e.g., Mo) and a subsequent CMP process during which the via metal 800 extending outside the vias has been polished such that top surfaces of the via metal 800 and top surfaces of the dielectric layer 260 are substantially coplanar. In some embodiments, the combination of temperature and pressure aids in bottom-up growth of the Mo metal. For example, at higher temperatures (e.g., higher than about 275° C.) and / or higher pressures (e.g., higher than about 3 Torr), the Mo metal may not selectively grow on the silicon (or germanium) layer 700 and may begin to grow on the dielectric layer 260. Under these conditions, bottom-up metal growth may not be possible, and voids may form in liner-free vias 810A and 810B.In some embodiments, in the case of using a metal other than Mo (for example, Ru, Ir, W, or Co), a silicon-containing or Ge-containing layer may not be required, and the metal may be deposited directly on the TiN layer 400 of the Ti / TiN double layer 410'.In some embodiments, via metal 800 is thermally treated to increase its grain size and improve its conductivity. For example, Mo via metal may be thermally treated in hydrogen to increase its grain size by over 75%. In some embodiments, a silicide (or germanide) is formed between the via metal and the silicon-containing (or germanium in the germanium-containing) layer 700 either during processing or during the aforementioned "grain growth" heat treatment. In other words, silicon atoms (or germanium atoms) diffuse into the via metal 800, or metal atoms from the via metal 800 diffuse into the silicon-containing (or germanium-containing) layer 700 to form a silicide (or germanide) having a thickness between about 0.2 nm and 3 nm. In some embodiments, the silicides (or germanides) formed include MoSi or MoGe (when Ge is used). In some embodiments, additional silicides or germanides may be formed including, for example, TiCoSi (or TiCoGe), TaCoSi (or TaCoGe), NiCoSi (or NiCoGe), or a two-element silicide (or germanide) CoSi (or CoGe). In some embodiments, these silicides or germanides may contain nitrogen.In some embodiments, via metal 800 in dielectric layer 260 forms metallization layer 805 with linerless vias 810A and 810B disposed on contact layer 245. In some embodiments, additional metallization layers may be formed on metallization layer 805. For example, referring to FIG. 9, metallization layer 900 may be formed on metallization layer 805. The metallization layer 900 may include dual damascene conductive structures 905A and / or single damascene conductive structures 905B embedded in the dielectric layer 910. By way of example, and not limitation, dual damascene conductive structures 905A and / or single damascene conductive structures 905B may include a metal 915 different from the via metal 800. The metal 915 may be, for example, copper (Cu), a copper alloy (for example, copper-ruthenium (Cu-Ru), copper-aluminum (Cu-Al), copper-manganese (CuMn), etc., or any other suitable metal or alloy. In some embodiments, a barrier layer or stack 920 surrounds sidewall and bottom surfaces of the metal 915 in the metallization layer 900. By way of example, and not limitation, the barrier layer or stack 920 may include Ta and TaN or other suitable layers.In some embodiments, additional layers or features not shown in FIG. 9 have been omitted for simplicity of description. Such layers or features include etch stop layers between dielectric layers 240, 260, and 910; etch stop layers on gate structures 205 and 210; additional gate structures; additional S / D epitaxial layers, additional contacts, doped regions in semiconductor substrate 220, etc. These layers and features fall within the spirit and scope of this disclosure. Furthermore, no restrictions apply to the layout of the contact layer 245 and the metallization layers 805 and 900 in FIG. 9, and other layouts with additional conductive structures and / or sublayers are also possible.For example, FIG. 10 shows a structure 200' having a different metallization layout than the precursor structure 200' shown in FIG. 9. As shown in FIG. 10, structure 200' includes gate structures 1000 having gate contacts 225 thereon and gate structures 1005 having a hard mask (HM) layer 1010 thereon. In some embodiments, the gate contacts of the gate structures 1005 are formed at a location on the gate structures 1005 that is not visible in the cross-sectional view of FIG. 10. FIG. 10 also includes intervening contacts 1015 (e.g., as compared to FIG. 9 ) formed on S / D contacts 230. By way of example, and not limitation, the intervening contacts 1015, similar to the gate contacts 225 and S / D contacts 230 shown in FIG. 9, are filled with metal 270 and a liner layer 275. That is, the S / D contact 230 of FIG. 9 in FIG. 10 has been replaced with two contacts: a shorter S / D contact 230 and an intermediate contact 1015. In some embodiments, additional intermediate contacts 1015 may be connected to S / D contacts 230 not shown in FIG. 10, and one or more S / D contacts 230 may be connected to intermediate contacts 1015 not shown in FIG. 10.Additionally, FIG. 10 includes liner-free vias 810A having different heights. For example, higher liner-free vias 810A are formed on gate contacts 225, and shorter liner-free vias 810A are formed on intermediate contacts 1015. In some embodiments, linerless vias 810A connect gate contacts 225 and intervening contacts 1015 to dual damascene conductive structures 905A and / or single damascene conductive structures 905B of upper metallization layers, as shown in FIG. 10. In some embodiments, linerless vias 810A may be connected to a single damascene conductive structure 905B, as shown in FIG. 10, or to a dual damascene conductive structure 905A.The method 100 may be applied to structures with different metallization schemes to form barrier structures with a silicide (or germanide) and Ti / TiN bilayers or a silicide (or germanide) and Ta / TaN bilayers or a silicide (or germanide) and Ni / NiN bilayers in liner-free conductive structures. In some embodiments, the blocking structures mentioned above may protect underlying conductive structures or layers from erosion caused by subsequent processes, such as chemical cleaning or CMP processes. Thus, the application of the method 100 is not limited to the embodiments described herein and may be implemented with any metallization regime having liner-free conductive structures.Various embodiments according to this disclosure describe a method of forming a barrier structure between liner-free conductive structures (e.g., liner-free metal vias) and underlying conductive structures (e.g., metal contacts) to prevent mud or other chemicals from processes used in the liner-free conductive structures from reaching and erodible a metal fill of underlying conductive structures. In some embodiments, the barrier structure may comprise bilayers of Ti / TiN, Ta / TaN, or Ni / NiN. In some embodiments, the barrier structure also includes silicon or germanium, which serves as a nucleation site for bottom-up growth of the metal fill in the liner-free conductive structures. In some embodiments, the underlying metal includes Co and the liner-free metal includes Mo, W, or Ru. In some embodiments, forming the barrier structure includes, for example, depositing, nitriding, and oxidizing a Ti layer, a Ta layer, or a Ni layer on the sidewall and the bottom surface of via or contact openings.In some embodiments, a method includes: receiving a substrate having a contact layer formed thereon, the contact layer including conductive structures; and forming via openings in a dielectric layer disposed on the contact layer, the via openings exposing top surfaces of the conductive structures. The method also includes: depositing a first metal layer in the via openings, the first metal layer being deposited thicker on top surfaces of the conductive structures than on sidewall surfaces of the via openings; exposing the first metal layer to ammonia to form a bilayer on the top surfaces of the conductive structures, the bilayer including the first metal layer and a nitride of the first metal layer. The method further comprises: exposing the nitride of the first metal layer to an oxygen plasma to convert a portion of the nitride of the first metal layer into an oxide layer of the first metal layer; removing the oxide layer of the first metal layer; and forming a semiconductor-containing layer on the nitride of the first metal layer in the bilayer.In some embodiments, a structure includes a substrate, a first dielectric layer on the substrate, a first conductive structure formed in the first dielectric layer, and an etch stop layer formed on the first dielectric layer. The structure further includes a second dielectric layer formed on a first portion of the etch stop layer and coplanar with a second portion of the etch stop layer, the second portion of the etch stop layer being thicker than the first portion of the etch stop layer. The structure also includes a second conductive structure disposed on the first conductive structure and formed in the second dielectric layer, and a barrier structure including a metal layer, a nitride of the metal layer, and a silicon or germanium containing layer, wherein the barrier structure is disposed between an upper surface of the first conductive structure and a lower surface of the second conductive structure.In some embodiments, a structure includes a semiconductor substrate having a source / drain (S / D) structure and a gate structure thereon. The structure further includes first conductive structures on the S / D and gate structures, second conductive structures on the first conductive structures, and a resistor structure adjacent the second conductive structure with a resistor contact thereon. In addition, the structure includes a blocking structure disposed between the first and second conductive structures and between the resistor structure and the resistor contact, the blocking structure including a metal layer, a metal nitride layer, and a semiconductor-containing layer.

Claims

A method comprising: receiving a substrate (220) having a contact layer (245) formed thereon, the contact layer (245) having conductive structures (225, 230); and forming via openings (250, 255, 275) in a dielectric layer (260) disposed on the contact layer (245), the via openings (250, 255, 275) exposing top surfaces of the conductive structures (225, 230); depositing (105) a first metal layer (300) in the via openings (250, 255, 275), the first metal layer (300) being deposited thicker on a top surface of the conductive structures (225, 230) than on sidewall surfaces of the via openings (250, 255, 275); Exposing (110) the first metal layer (300) to ammonia to form a bilayer (410) on the top surfaces of the conductive structures (225,230), the bilayer (410) comprising the first metal layer (300) and a nitride (400) of the first metal layer; exposing (115) the nitride (400) of the first metal layer to an oxygen plasma to convert a portion of the nitride (400) of the first metal layer into an oxide layer (500) of the first metal layer; removing (120) the oxide layer (500) of the first metal layer; and forming (125) a semiconductor-containing layer (700) on the nitride (400) of the first metal layer in the bilayer (410').The method of claim 1, further comprising: selectively growing (130) a second metal layer (800) on the semiconductor-containing layer (700) to fill the via openings (250, 255, 275); and performing an anneal process on the second metal layer (800) that converts the semiconductor-containing layer (700) to a silicide layer or a germanide layer.The method of claim 2, wherein selectively growing (130) the second metal layer (800) comprises growing molybdenum.The method of any preceding claim, wherein depositing (105) the first metal layer (300) comprises depositing titanium, nickel or tantalum.The method of any preceding claim, wherein exposing (110) the first metal layer (300) to the ammonia comprises converting the first metal layer (300) at the sidewall surfaces of the via openings (250, 255, 275) to the nitride (400) of the first metal layer.The method of any preceding claim, wherein exposing (115) the nitride (400) of the first metal layer to the oxygen plasma comprises oxidizing the nitride (400) of the first metal layer on the sidewall surfaces of the via openings (250, 255, 275) to convert the nitride (400) of the first metal layer into the oxide layer (500) of the first metal layer.The method of any preceding claim, wherein removing (120) the oxide layer (500) of the first metal layer comprises removing (120) the oxide layer (500) of the first metal layer with a chlorine-based chemical.The method of any preceding claim, wherein removing (120) the oxide layer (500) of the first metal layer comprises removing (120) the oxide layer (500) of the first metal layer from the sidewall surfaces of the via openings (250, 255, 275).The method of any preceding claim, wherein forming (125) the semiconductor-containing layer (700) comprises depositing an amorphous silicon layer or an amorphous germanium layer.The method of any preceding claim, wherein depositing (105) the first metal layer (300) to a greater thickness (310) comprises depositing (105) the first metal layer (300) on conductive structures (225,230,270) having one or more of gate contacts (225), source / drain contacts (230), and a resistor structure (270).A structure (200') comprising: a substrate (220); a first dielectric layer (235, 240) on the substrate (220); a first conductive structure (225, 230) formed in the first dielectric layer (235, 240); an etch stop layer (280) formed on the first dielectric layer (235, 240); a second dielectric layer (260) formed on a first portion of the etch stop layer (280) and coplanar with a second portion of the etch stop layer (280), wherein the second portion of the etch stop layer (280) is thicker than the first portion of the etch stop layer (280); a second conductive structure (800) disposed on the first conductive structure (225, 230) and formed in the second dielectric layer (260); and a barrier structure (410') comprising a metal layer (300), a nitride (400) of the metal layer and a silicon- or germanium-containing layer (700), wherein the barrier structure (410') is arranged between an upper surface of the first conductive structure (225, 230) and a lower surface of the second conductive structure (800).The structure (200') of claim 11, further comprising: a resistor layer (270) formed in the second portion of the etch stop layer (280); and a third conductive structure (810B) formed in the second portion of the etch stop layer (280) and disposed on the resistor layer (270), wherein a blocking structure (410') is disposed between an upper surface of the resistor layer (270) and a lower surface of the third conductive structure (810B).The structure (200) of claim 12, wherein the second conductive structure (800) and the third conductive structure (810B) are liner-free conductive structures including molybdenum.The structure (200) of any of claims 11 to 13, wherein the first conductive structure (225,230) comprises a gate contact (225) or a source / drain contact (230) containing cobalt.The structure (200) of any of claims 11 to 14, wherein the silicon or germanium containing layer (700) includes molybdenum (Mo), titanium (Ti), cobalt (Co), tantalum (Ta), nickel (Ni), or a combination thereof.The structure (200) of any of claims 11 to 15, wherein the metal layer (300) includes titanium, tantalum, or nickel.The structure (200) of any of claims 11 to 16, wherein the metal layer (300) has a thickness between about 2 nm and about 4 nm.A structure (200, 200') comprising: a semiconductor substrate (220) having a source / drain structure (215) and a gate structure (205, 210, 1000) thereon; first conductive structures (225, 230) on the source / drain structure (215) and the gate structure (1000); second conductive structures (810A) on the first conductive structures (225, 230); a resistor structure (270) adjacent the second conductive structures (810A) having a resistor contact (810B) thereon; and a blocking structure (410') arranged between the first conductive structure (225, 230) and the second conductive structure (810A) and between the resistor structure (270) and the resistor contact (810B), wherein the blocking structure (410') comprises a metal layer (300), a metal nitride layer (400) and a semiconductor-containing layer (700).The structure (200, 200') of claim 18, wherein the metal layer (300) includes titanium, tantalum, or nickel; wherein the metal nitride (400) includes titanium nitride, tantalum nitride, or nickel nitride; and wherein the semiconductor-containing layer (700) comprises a silicide layer or a germanide layer, wherein the silicide layer and the germanium layer include titanium, tantalum, nickel, cobalt, molybdenum, or combinations thereof.The structure (200) of claim 18 or 19, wherein the metal layer (300) has a thickness between about 2 nm and about 4 nm and the metal nitride layer (400) has a thickness between about 1 nm and about 3 nm.

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