Semiconductor structure and methods for its manufacture

Abstract

Procedure, comprehensive: Providing a structure comprising transistors, an insulating structure (105) which is at least partially over the transistors, two metal pins (170) through the insulating structure (105) and electrically connected to electrodes of the transistors, and a trench (172) wherein the insulating structure (105) and the two metal pins (170) form side walls of the trench (172); Forming a dielectric lining (174) on the side walls of the trench (172) and over the insulating structure (105) and the metal pins (170), wherein the dielectric lining (174) is thicker at one opening section of the trench (172) than at another section of the trench (172) that is deeper than the opening section, so that an air gap (176) is formed inside the trench (172) and the air gap (176) is completely or partially surrounded by the dielectric lining (174); Deposition of a dielectric sacrificial layer (178) over the dielectric lining (174) and over the air gap (176); and Performing a chemical-mechanical planarization process (CMP process) to remove the dielectric sacrificial layer (178) and deepen the dielectric lining (174) until the insulation structure (105) and the metal pins (170) are exposed, leaving the air gap (176) within the trench (172).

Description

STATE OF THE ART

[0001] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous one. As ICs evolved, functional density (the number of interconnected components per unit area) has generally increased, while geometric size (the smallest component or trace that can be produced using a manufacturing process) has decreased. This downscaling process generally provides benefits by increasing manufacturing efficiency and reducing associated costs. However, this downscaling has also increased the complexity of IC fabrication and manufacturing. Therefore, semiconductor manufacturing processes require continuous improvement.One area of ​​improvement is how the stray capacitance can be reduced in the characteristics of field-effect transistors.

[0002] In general, it is desirable to reduce stray capacitance between metal features, such as metal traces and / or metal pins, to increase switching speed, reduce switching power consumption, and / or decrease circuit coupling noise. Certain low-k materials have been proposed as insulators to reduce stray capacitance. However, as semiconductor technology progresses to smaller geometries, the distances between metal features are further reduced, increasing stray capacitance. Therefore, while existing approaches in semiconductor manufacturing have generally been suitable for their intended purposes, they have not been entirely satisfactory in all respects.

[0003] US 2015 / 0037980A1 discloses a method for forming a semiconductor device, comprising forming a cover layer on a metal structure and on an adjacent portion of an insulating layer, wherein the cover layer exhibits first etch selectivity with respect to the insulating layer on the metal structure and second etch selectivity with respect to the insulating layer on the portion of the insulating layer. Furthermore, the method comprises forming a recessed area adjacent to the metal structure by removing the cover layer from the portion of the insulating layer. At least one portion of the cover layer may remain on a top surface of the metal structure after the cover layer has been removed from the portion of the insulating layer.

[0004] US 2015 / 0287628A1 discloses a semiconductor device comprising a substrate with a first region and a second region; first conductive structures arranged on the first region and spaced apart from each other by a first distance; second conductive structures arranged on the second region and spaced apart from each other by a second distance greater than the first distance; and an insulating intermediate layer arranged between the second conductive structures and containing at least one recess region with a width equal to the first distance.

[0005] US 2008 / 0020488A1 discloses a method for manufacturing semiconductor chips with on-chip inductors formed on the back of the chip and connected to integrated circuits on the front of the chip using through-wafer connections. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure is best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. 1A and Fig. Figure 1B shows a flowchart of a process for forming an air-gapped semiconductor device on the back side of a wafer according to different aspects of the present disclosure. Fig. 2A and Fig. Figure 2B illustrates a perspective view and a cross-sectional view of a section of a semiconductor device according to some embodiments in an intermediate step of the manufacturing process according to an embodiment of the method by Fig. 1A and Fig. 1B. Fig. Figure 2C illustrates a perspective view of a section of the semiconductor device in Fig. 2A according to some embodiments. Fig. 2D and Fig. 2E illustrate cross-sectional views of a section of the semiconductor device in Fig. 2C along the AA line or the BB line in Fig. 2C according to one embodiment. Fig. 2D-1 and 2E-1 illustrate cross-sectional views of a section of the semiconductor device in Fig. 2C along the AA line or the BB line in Fig. 2C according to another embodiment. Fig. Figure 3 illustrates a cross-sectional view of a section of the semiconductor device. Fig. 2A in an intermediate step of the manufacturing process according to an embodiment of the method of Fig. 1A and Fig. 1B. Fig. 4, Fig. 5A, Fig. 6A, Fig. 7A, Fig. 8A, Fig. 9A, Fig. 10A and Fig. Figure 11A illustrates perspective views of a section of a semiconductor device according to some embodiments in intermediate steps of the manufacturing process according to one embodiment of the method by Fig. 1A and Fig. 1B. Fig. Figures 5B, 6B, 7B, 8B, 9B, 10B, 11B and 11B-1 illustrate cross-sectional views of a section of a semiconductor device along the section-1 line in Fig. 5A, Fig. 6A, Fig. 7A, Fig. 8A, Fig. 9A, Fig. 10A or 11A according to some embodiments. Fig. Figure 10C illustrates a cross-sectional view of a section of a semiconductor device along the section-2 line in Fig. 10A according to some embodiments. DETAILED DESCRIPTION

[0007] The following disclosure provides many different embodiments, or examples, for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure.

[0008] Furthermore, spatially relative terms such as "underlying," "below," "under," "overlying," "above," and the like may be used herein to facilitate description and to describe the relationship of one element or feature to another element(s) or feature(s), as illustrated in the figures. These spatially relative terms are intended to encompass various orientations of the component in use or operation in addition to the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.Furthermore, when a number within a range is described by "about," "approximately," and the like, the expression includes numbers that are within certain tolerances (such as + / - 10% or other deviations) of the described number, in accordance with the knowledge of a person skilled in the art, considering the specific technology disclosed herein, unless otherwise specified. For example, the expression "about 5 nm" may encompass the dimensional range of 4.5 nm to 5.5 nm, 4.0 nm to 5.0 nm, and so on.

[0009] This disclosure relates generally to a semiconductor fabrication process and its structure. More specifically, it relates to the fabrication of dielectric layer(s) and metal layer(s) on the back side of a structure (such as a wafer), where devices (such as transistors) are fabricated on the front side of the structure. With the advancement of semiconductor technology toward smaller geometries, it is desirable to move some of the connectivity layers to the back side of a wafer, such as power rails that connect to the source and / or drain features of the transistors. This frees up area on the front side of the wafer and further increases device integration. This also presents new challenges.One of the challenges is how to deal with the stray capacitance (or coupling capacitance) between the conductors on the back side, such as metal pins extending from the back side into the source / drain features. The small distance between these conductors could result in large stray capacitance if not properly addressed. According to some embodiments of the present disclosure, the dielectric backside layer(s) is / are provided with air gaps to reduce stray capacitance and increase insulation between conductors. These and other aspects of the present disclosure are further described with reference to the accompanying figures.

[0010] Fig. 1A and Fig. Figure 1B is a flowchart of a process 10 for fabricating a semiconductor device according to different aspects of the present disclosure. Additional processing is taken into account by the present disclosure. Additional operations may be provided before, during, and after process 10, and some of the described operations may be postponed, replaced, or eliminated for additional embodiments of process 10.

[0011] Procedure 10 is below in conjunction with Fig. 2A to Fig. 11B-1 describes different perspective and cross-sectional views of a semiconductor device (or semiconductor structure) 100 at different manufacturing steps according to the method 10 in accordance with some embodiments.In some embodiments, the component 100 is a section of an IC chip, a system-on-a-chip (SoC), or a section thereof, comprising various passive and active microelectronic components such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (PFETs), n-type field-effect transistors (NFETs), FinFETs, nanoplate FETs, nanowire FETs, other types of multigate FETs, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor transistors (CMOS transistors), bipolar transistors (BJTs), side-diffused MOS transistors (LDMOS transistors), high-voltage transistors, high-frequency transistors, memory devices, other suitable components, or combinations thereof. Fig. Sections 2A to 11B-1 have been simplified for clarity to facilitate understanding of the inventive concepts of the present disclosure. Additional features may be added to the component 100, and some of the features described below may be replaced, modified, or eliminated in other embodiments of the component 100.

[0012] In operation 12, procedure 10 ( Fig. 1A) a structure (or a workpiece) of the component 100, of which an embodiment in Fig. 2A and Fig. 2B is illustrated. In particular, it illustrates Fig. 2A a perspective view of a section of component 100 and Fig. Figure 2B illustrates a cross-sectional view of a section of the component 100 according to one embodiment. The component 100 has a substrate 102, a component layer 152 over the substrate 102, and an interconnect structure (or a multilayer interconnect) 162 over the component layer 152. The component 100 may have other layers or features not shown in Figure 2B. Fig. Figure 2A shows how a passivation layer is placed over the interconnect structure 162. The substrate 102 is located on the back side of the device 100, and the interconnect structure 162 is located on the front side of the device 100. In other words, the substrate 102, the device layer 152, and the interconnect structure 162 are arranged one above the other from the back side to the front side of the device 100.

[0013] The substrate 102 is a bulk silicon substrate (bulk-Si substrate) in the present embodiment, such as a silicon wafer. In alternative embodiments, the substrate 102 comprises other elemental semiconductors, such as germanium (Ge); a compound semiconductor, such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP); or an alloy semiconductor, such as silicon germanium (SiGe), silicon germanium carbide (SiGeC), gallium arsenic phosphide (GaAsP), and gallium indium phosphide (GaInP). In some embodiments, the substrate 102 may be silicon-on-insulator (SOI) substrate, be stretched or strained to improve work performance, have epitaxial regions, doped regions, and / or other suitable features and layers.

[0014] The component layer 152 contains active semiconductor regions (such as semiconductor fins) and various active components (e.g., transistors) embedded in or on these active semiconductor regions. The component layer 152 may also contain passive components such as capacitors, resistors, and inductors. Furthermore, the component layer 152 features local interconnects, insulation structures, and other structures. In the Fig. In the embodiment shown in Figure 2B, the semiconductor device 152 has semiconductor fins (or fins) 103 extending upward from the substrate 102, epitaxial features 104 over the semiconductor fins 103, and dielectric insulating features 154 between the active semiconductor regions. The epitaxial features 104 can be source or drain electrodes (S / D electrodes) of transistors. Therefore, they are also referred to as S / D features 104. The semiconductor fins 103 can contain silicon or other suitable semiconductor materials such as silicon germanium. The device layer 152 also has conductors 156 and 158 (such as local interconnects, vias, and / or pins) that provide connectivity with the S / D electrodes of the transistors, as well as gate electrodes, although not shown in this figure. Some of the conductors 158 are connected to the interconnect structure 162.Conductors 156 and 158 may contain copper, tungsten, ruthenium, cobalt or other suitable materials.

[0015] The interconnect structure 162 is located above the component layer 152 and includes conductors 166 (such as metal conductors or metal wires and vias) embedded in one or more dielectric layers 164. The conductors 166 provide connectivity to the components in the component layer 152. The conductors 166 can also provide power rails and ground planes for the component 100. The conductors 166 can contain copper, aluminum, or other suitable materials and can be formed using a single-damascus process, a double-damascus process, or another suitable process.The dielectric layers 164 may contain silicon nitride, silicon oxynitride, silicon nitride with oxygen or carbon elements (O or C elements), tetraethyl orthosilicate oxide (TEOS oxide), undoped silicate glass or doped silicon oxide, such as borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG) and / or other suitable dielectric materials.

[0016] Fig. Figure 2C illustrates a perspective view of a section of the device 100 according to an embodiment, which has a semiconductor fin 103 and a gate stack 118. The fin 103 is generally oriented longitudinally along the “x” direction, and the gate stack 118 is generally oriented longitudinally along the “y” direction perpendicular to the “x” direction. Fig. 2D illustrates a cross-sectional view of a section of component 100 along the AA line in Fig. 2C according to an embodiment which is drawn parallel to and through the fin 103. Fig. Figure 2E illustrates a cross-sectional view of a section of component 100 along the BB line in Fig. 2C according to an embodiment that is parallel to and drawn through gate 118. The embodiment of Fig. 2D and Fig. The transistor illustrated in 2E is a FinFET 101a. Fig. 2D-1 and 2E-1 illustrate cross-sectional views of a section of component 100 along the AA line and the BB line, respectively. Fig. 2C according to another embodiment, wherein the transistor is a gate all-around FET (GAA-FET) 101b. The device 100 can, in different embodiments, comprise any number of fins 103, any number of gate stacks 106, any number of FinFETs and / or GAA-FETs, and other types of devices.

[0017] In relation to Fig. Together with 2C-2E, the component 100 has the substrate 102, over which the fin 103 and the gate stack 118 are formed. The component 100 has an insulation structure 105 (which is part of the insulation structure 154 in Fig. 2B is used to isolate the fin 103 from other active areas or fins. The fin 103 extends from the substrate 102 and over the isolation structure 105. The gate stack 118 is located above the isolation structure 105 and on three sides of the fin 103. The component 100 further features gate spacers 108 on the side walls of the gate stack 118. The epitaxial S / D features 104 are located on the top surface of the fin 103 and on both sides of the gate stack 118.

[0018] The fin 103 can have one or more layers of semiconductor materials, such as silicon or silicon germanium. The fin 103 can be structured by any method. For example, the fin 103 can be structured using one or more photolithography processes, including dual or multiple structuring processes. In general, dual or multiple structuring processes combine photolithography and self-alignment processes, which allows the creation of structures with, for example, smaller spacing than would otherwise be obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and structured using a photolithography process. Spacers are formed along the structured sacrificial layer using a self-alignment process.The sacrificial layer is then removed, and the remaining spacers, or support mandrels, can then be used as a masking element for structuring the fin 103. For example, the masking element can be used to etch depressions in semiconductor layers above or within the substrate 102, while the fin 103 remains on the substrate 102. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. For example, a dry etching process can implement an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBr3), an iodine-containing gas, other suitable gases, and / or plasmas, and / or combinations thereof.For example, a wet etching process may include etching in aqueous hydrofluoric acid (DHF); potassium hydroxide solution (KOH solution); ammonia; a solution containing hydrofluoric acid (HF), nitric acid (HNO3), and / or acetic acid (CH3COOH); or another suitable wet etching agent. Numerous other embodiments of processes for forming the fin 103 may be suitable.

[0019] The S / D features 104 contain epitaxially grown semiconductor materials, such as epitaxially grown silicon, germanium, or silicon germanium. The S / D features 104 can be formed by any epitaxial processes, including chemical vapor deposition (CVD) techniques (for example, gas-phase epitaxy and / or ultra-high vacuum CVD), molecular beam epitaxy, other suitable epitaxial growth processes, or combinations thereof. The S / D features 104 can be doped with n-type and / or p-type dopants. In some embodiments, the S / D features 104 for n-type transistors contain silicon and can be doped with carbon, phosphorus, arsenic, other n-type dopants, or combinations thereof (for example, forming Si:C epitaxial S / D features, Si:P epitaxial S / D features, or Si:C:P epitaxial S / D features).In some embodiments, the S / D features 104 for p-transistors contain silicon germanium or germanium and may be doped with boron, another p-type dopant, or combinations thereof (for example, forming Si:Ge:B epitaxial S / D features). The S / D features 104 may have multiple epitaxial semiconductor layers exhibiting varying degrees of dopant density. In some embodiments, annealing processes (e.g., rapid thermal annealing (RTA) and / or laser annealing) are performed to activate dopants in the epitaxial S / D features 104.

[0020] The insulating structure 105 can comprise silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), fluoride-doped silicate glass (FSG), a low-k dielectric material, and / or another suitable insulating material. In one embodiment, the insulating structure 105 is formed by etching trenches in or above the substrate 102 (e.g., as part of the fin formation process 103), filling the trenches with an insulating material, and performing a chemical-mechanical planarization (CMP) process and / or a back-etching process on the insulating material, leaving the remaining insulating material as the insulating structure 105. Other types of insulating structures may also be suitable, such as field oxide and local oxidation of silicon (LOCOS). The insulating structure 105 can have a multilayer structure, comprising, for example, one or more lining layers (e.g.,silicon nitride) on surfaces of the substrate 102 and the fin 103 and a main insulating layer (e.g. silicon dioxide) over the one or more lining layers.

[0021] In the present embodiment, the gate stack 118 comprises a gate dielectric layer 120 and a gate electrode layer 122 above the gate dielectric layer 120. The gate dielectric layer 120 can be a high-k dielectric material such as HfO₂, HfSiO₂, HfSiO₄, HfSiON₄, HfLaO₂, HfTaO₂, HfTiO₂, HfZrO₂, or HfAlO₂. xThe gate dielectric layer 120 may contain ZrO, ZrO2, ZrSiO2, AlO, AlSiO, Al2O3, TiO, TiO2, LaO, LaSiO, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3 (BTO), (Ba,Sr)TiO3 (BST), Si3N4, hafnium dioxide-alumina alloy (HfO2-Al2O3 alloy), other suitable high-k dielectric material, or combinations thereof. High-k dielectric material generally refers to dielectric materials that have a high dielectric constant, for example, greater than that of silicon dioxide (k ≈ 3.9). The gate dielectric layer 120 may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable processes. In the present embodiment, the gate stack 118 further comprises an interface 106 between the gate dielectric layer 120 and the fin 103. The interface 106 can contain silicon dioxide, silicon oxynitride, or other suitable materials.In some embodiments, the gate electrode layer 122 comprises an n- or p-work function layer and a metal filler layer. For example, an n-work function layer may contain a metal with a sufficiently low effective work function, such as titanium, aluminum, tantalum carbide, tantalum carbide nitride, tantalum silicon nitride, or combinations thereof. For example, a p-work function layer may contain a metal with a sufficiently high effective work function, such as titanium nitride, tantalum nitride, ruthenium, molybdenum, tungsten, platinum, or combinations thereof. For example, a metal filler layer may contain aluminum, tungsten, cobalt, copper, and / or other suitable materials. The gate electrode layer 122 may be formed by CVD, PVD, plating, and / or other suitable processes. Since the gate stack 118 comprises a high-k dielectric layer and metal layer(s), it is also referred to as a high-k metal gate.

[0022] Each of the gate spacers 108 can be a single-layer or multi-layer structure. In some embodiments, the spacers 108 contain a dielectric material, such as silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), other dielectric material, or a combination thereof. In one example, the spacers 108 are formed by deposition and etching processes (e.g., anisotropic etching). In some embodiments, the gate spacers 108 contain La2O3, Al2O3, SiOCN, SiOC, SiCN, SiO2, SiC, ZnO, ZrN, Zr2Al3O9, TiO2, TaO2, ZrO2, HfO2, Si3N4, Y2O3, AlON, TaCN, ZrSi, or other suitable material.

[0023] In the present embodiment, the component 100 further comprises a gate cap 124 above the gate stack 118. The gate cap 124 can contain a material such as La₂O₃, Al₂O₃, SiOCN, SiOC, SiCN, SiO₂, SiC, ZnO, ZrN, TiO₂, TaO₂, ZrO₂, HfO₂, Si₃N₄, Y₂O₃, AlON, TaCN, ZrSi, or other material (other materials). The gate cap 124 can be formed by recessing the gate stack 118 between the opposing gate spacers 108; depositing one or more materials over the recessed gate stack 118; and performing a CMP process on the one or more materials. The gate cap 124 can be deposited by atomic layer deposition (ALD), CVD, and / or other suitable methods.

[0024] The component 100 further comprises a contact etch stop layer (CESL 114) and an interlayer dielectric layer (ILD layer) 116, which form part of the insulation structure 154 in Fig. 2B are. The CESL 114 is deposited over the sidewalls of the spacers 108 and the S / D features 104. The ILD layer 116 is arranged over the CESL 114. The CESL 114 may contain La₂O₃, Al₂O₃, SiOCN, SiOC, SiCN, SiO₂, SiC, ZnO, ZrN, TiO₂, TaO₂, ZrO₂, HfO₂, Si₃N₄, Y₂O₃, AlON, TaCN, ZrSi, or other suitable material (other suitable materials); and may be formed by CVD, PVD, ALD, or other suitable processes. The ILD layer 116 can contain tetraethyl orthosilicate oxide (TEOS oxide), undoped silicate glass or doped silicon dioxide, such as borophosphosilicate glass (BPSG), fluoride-doped fused silica (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials. The ILD 116 can be formed by PECVD (plasma-enhanced CVD), FCVD (flowable CVD), or other suitable methods.

[0025] In some embodiments, such as in Fig. As shown in 2D-1 and 2E-1, the device features 100 gate all-around transistors such as nanoplate FETs or nanowire FETs. Most of the features in Fig. 2D-1 and 2E-1 are the same or similar to those in Fig. 2D and Fig. 2E, where similar reference symbols denote similar features among the figures. With regard to Fig. In embodiments 2D-1 and 2E-1, the device 100 further comprises several layers 103a of semiconductor materials (such as silicon) stacked vertically over the substrate 102 (along the "z" direction) and horizontally connecting the S / D features 104. The layers 103a are channel layers of the transistor and can be considered part of the fin 103. The layers 103a can be in the form of rods, beams, plates, or other shapes in various embodiments. Sections of the gate stack 118 wrap around the multiple layers 103a. The device 100 further comprises internal spacers 108a horizontally between the S / D features 104 and the sections of the gate stack 118, and vertically between the layers 103a.In some embodiments, the internal spacers 108a contain La2O3, Al2O3, SiOCN, SiOC, SiCN, SiO2, SiC, ZnO, ZrN, TiO2, TaO2, ZrO2, HfO2, Si3N4, Y2O3, AlON, TaCN, ZrSi or other suitable material (other suitable materials).

[0026] In operation 14, procedure 10 is attached ( Fig. 1A) the front side of the component 100 on a support substrate 220, as shown in Fig. Figure 3 shows that this makes the component 100 accessible from the back side for further processing. Operation 14 can employ any suitable fastening processes, such as direct bonding, hybrid bonding, using adhesives, or other bonding methods. Operation 14 can further include alignment, annealing, and / or other processes. The support substrate 220 can, in some embodiments, be a silicon wafer. Fig. Figure 3 (as in other figures described below) shows the “z” direction from the back of component 100 to the front of component 100, while the “-z” direction points from the front of component 100 to the back of component 100.

[0027] In operation 16, procedure 10 thins ( Fig. 1A) the component 100 from the back side of the component 102. The thinning process can include a mechanical grinding process and / or a chemical thinning process. A substantial amount of substrate material can first be removed from the substrate 102 during a mechanical grinding process. Subsequently, a chemical thinning process can apply chemical etching to the back side of the substrate 102 to further thin the substrate 102. In the present embodiment, the component 100 is thinned until the active areas (such as the fins 103) and the insulating structure 105 are exposed from the back side of the component 100, as shown in Fig. 4 shown. For the sake of simplicity, it shows Fig. 4 not all components of component 100.

[0028] In operation 18, procedure 10 etches ( Fig. 1A) Holes 168 through the active areas (such as the fins 103) to access some of the S / D features 104 from the rear of the component 100. An example of the component 100 with the holes 168 is shown in Fig. 5A and Fig. 5B shown, where Fig. 5B a cross-sectional view of component 100 along section 1 line in Fig. 5A is. The section-1 line can be the same as the AA line in Fig. 2C. In one embodiment, operation 18 can comprise a variety of processes, such as deposition, photolithography, and etching. For example, operation 18 can form a resist layer over the back of the device 100 (e.g., by spin coating), perform a baking process before exposure, expose the resist using a photomask, perform a baking process after exposure, and develop the exposed resist layer in a developer solution. After development, the structured resist layer (or resist structure) provides openings corresponding to the holes 168. Alternatively, the exposure process can be implemented or replaced by other methods, such as maskless lithography, E-beam writing, ion beam writing, or combinations thereof. Subsequently, the device 100 is etched through the openings in the resist structure to form the holes 168. Afterward, the resist structure is removed, for example, by stripping.The holes 168 can expose source features, drain features, and / or other features of different transistors and active regions. For example, two adjacent holes 168 can expose a source feature and a drain feature of the same transistor, or they can expose a source or drain feature of one transistor and a different source or drain feature of another transistor. A connectivity network can be established on the rear side of the device 100 through the holes 168, providing power and / or signal lines to the transistors already formed on the front side of the device 100.

[0029] In operation 20, procedure 10 forms ( Fig. 1A) Silicide features 169 in the holes 168 and over the S / D features 104 and forms conductors (or metal pins) 170 in the holes 168 and over the silicide features 169, as shown in Fig. 6A and Fig. 6B shown, where Fig. 6B a cross-sectional view of component 100 along section 1 line in Fig. 6A. In one embodiment, the operation 20 comprises depositing one or more metals in the holes 168, performing a tempering process on the device 100 to cause a reaction between the one or more metals and the S / D features 104 to produce the silicide features 169, and removing unreacted portions of the one or more metals, leaving the silicide features 169 exposed in the holes 168. The one or more metals may include titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), platinum (Pt), ytterbium (Yb), iridium (Ir), erbium (Er), cobalt (Co), or a combination thereof (e.g., an alloy of two or more metals) and may be deposited using CVD, PVD, ALD, or other suitable processes.The silicide features 169 can include titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel-platinum silicide (NiPtSi), nickel-platinum-germanium silicide (NiPtGeSi), nickel-germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), or other suitable compounds. In one embodiment, the pins 170 can have a conductive barrier layer on the bottom and side walls of the holes 168 and a metal filler layer above the conductive barrier layer. The conductive barrier layer serves to prevent metal materials of the metal filler layer from diffusing into a dielectric layer that is to be formed adjacent to the pins 170.The conductive barrier layer can contain titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), ruthenium (Ru), or a conductive nitride such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tantalum nitride (TaN), or combinations thereof, and can be formed by CVD, PVD, ALD, and / or other suitable processes. The metal filler layer can contain tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), aluminum (Al), or other metals and can be formed by CVD, PVD, ALD, plating, or other suitable processes. In some embodiments, the conductive barrier layer is omitted in the pins 170. Operation 20 can perform a CMP process to remove excess material from the pins 170 and re-expose the active areas (the fins 103 in this example) from the back side of the device 100.

[0030] In operation 22, procedure 10 etches ( Fig. 1A) the active areas 103 (the fins 103) between the pegs 170 to form ditches 172, as in Fig. 7A and Fig. 7B shown, where Fig. 7B a cross-sectional view of component 100 along section 1 line in Fig. 7A. In one embodiment, Operation 22 can etch the active areas 103 using a self-aligned etching process without the use of an etching mask. For example, Operation 22 can perform an etching process selectively tailored to the materials of the active areas 103 without (or with minimal) etching of the pins 170 and the insulation structure 105. In one embodiment, the active areas 103 have an anti-pierce layer (APT layer) (not shown) located above the channel layer (in the "-z" direction), and Operation 22 can partially or completely remove the APT layer. The trenches 172 extend to a depth h2 from the back side of the device 100, where h2 is equal to or greater than the height h1 of the pins 170 in some embodiments. In some embodiments, the depth h2 is equal to or greater than a combination of the height h1 of the pins 170 and a thickness of the silicide features 169. As in Fig. As shown in Figure 7A, the isolation structure 105 and the pegs 170 form all or part of the side walls of the trenches 172, while the S / D features 104 and the active areas 103 form the bottom of the trenches 172.

[0031] In operation 24, the procedure treats 10 ( Fig. 1B) the surfaces of the trenches 172, for example, with a chemical gas, a solution, or a plasma. The treatment prepares the surfaces of the trenches 172 to more easily obtain an overhang profile in a dielectric lining 174, which is formed in Operation 26, discussed below. For example, Operation 24 can treat the surfaces of the trenches 172 with a plasma containing atoms or ions of nitrogen, fluorine, chlorine, oxygen, hydrogen, and / or argon. For example, the plasma can be prepared using NF3, hydrogen-containing fluorocarbon (CH3). x F y) such as CH3F, HCl, CO2, O2, H2 and / or AR are generated. As a result, some of the F, C, Cl, O, Si and N atoms can be found on the surfaces of the trenches 172. Operation 24 is optional and may be omitted in some embodiments of the method 10.

[0032] In operation 26, procedure 10 is ruled out ( Fig. 1B) a dielectric lining 174 over the insulating structure 105, the pins 170 and within the trenches 172, as shown in Fig. 8A and Fig. 8B shown, where Fig. 8B a cross-sectional view of component 100 along section 1 line in Fig. 8A. In particular, the dielectric lining 174 is formed to have an overhang profile. In other words, the thickness of the dielectric lining 174 is greater at the opening of the trenches 172, proximal to the rear of the component 100, than inside the trench 172, distal to the rear of the component 100. As a result, the opening of the trenches 172 can be closed (or nearly closed) by the dielectric lining 174. Furthermore, the dielectric lining 174 is deposited at the bottom and side walls of the trenches 172 and does not completely fill the trenches 172. An air gap (or cavity or air pocket) 176 is formed inside each of the trenches 172. The air gap 176 can be completely enclosed (or completely sealed) by the dielectric lining 174 alone in some embodiments, or it can be partially enclosed (or partially sealed) by the dielectric lining 174.In different embodiments, the dielectric lining 174 can contain a low-k dielectric material containing Si, O, N, and C, or other porous materials with a low dielectric constant. The dielectric lining 174 can be configured to have a single layer or multiple layers.

[0033] In one embodiment, the dielectric lining 174 is deposited using a chemical vapor deposition process, such as a plasma-enhanced chemical vapor deposition (PECVD) process. For example, the PECVD process can employ plasma generated from SiH4 gas, N2 gas, NH3 gas, and / or other gases to deposit the dielectric lining 174. Various parameters of the PECVD process can be tailored to create the overhang profile in the dielectric lining 174. For example, the composition of the depositing gases, the ratio among the depositing gases, the process pressure, the process temperature, the AC or DC current, or other parameters of the PECVD process can be adjusted.In one example, the ratio of SiH4 gas to N2 or NH3 gas can be adjusted in the range of approximately 5 to 200, the process pressure can be adjusted in the range of approximately 300 mT to approximately 800 mT, and the process temperature can be adjusted in the range of approximately 200°C to approximately 400°C. The process temperature range is chosen to be high enough to deposit the dielectric lining 174, but low enough to protect various features on the front face of the device 100, such as the metal components within the device 100.

[0034] In operation 28, procedure 10 is ruled out ( Fig. 1B) a dielectric layer 178 above the dielectric lining 174, as in Fig. 9A and Fig. 9B shown, where Fig. 9B a cross-sectional view of component 100 along section 1 line in Fig. 9A. The dielectric layer 178 is removed in a later step. Therefore, it is also referred to as a dielectric sacrificial layer 178. As in Fig. 8A and Fig. As shown in Figure 8B, a section of the dielectric lining 174 is deposited on the top surface of the insulating structure 105 and the pins 170. It is desirable to remove this section of the dielectric lining 174 using a CMP process in the present embodiment. However, this section of the dielectric lining 174 may be too thin to be suitable for a CMP process. For this reason, the dielectric layer 178 is deposited to increase the overall thickness of the layers that undergo a CMP process. The dielectric layer 178 may contain tetraethyl orthosilicate oxide (TEOS oxide), undoped silicate glass, or doped silicon dioxide such as borophosphosilicate glass (BPSG), fluoride-doped fused silica (FSG), phosphosilicate glass (PSG), boron-doped silicon dioxide (BSG), and / or other suitable dielectric materials. The dielectric layer 178 can be formed by PECVD or other suitable methods.In particular, due to the overhang profile of the dielectric lining 174, the dielectric layer 178 does not fill the air gap 176 (except for the uppermost section of the air gap 176 if it is not completely sealed by the dielectric lining 174).

[0035] In operation 30, the procedure 10 ( Fig. 1B) a CMP process is carried out to completely remove the dielectric layer 178 and the portion of the dielectric lining 174 deposited on the top of the insulating structure 105 and the pins 170. As a result, the insulating structure 105 and the pins 170 are exposed, as shown in Fig. 10A, Fig. 10B and Fig. 10C shown, where Fig. 10B and Fig. 10C Cross-sectional views of component 100 along section 1 line and section 2 line respectively in Fig. 10A are. In one embodiment, the CMP process can use pins 170 and / or the isolation structure 105 for CMP endpoint detection. Fig. 10B and Fig. Figure 10C also illustrates different dimensions of the dielectric lining 174, the pins 170 and the air gap 176.

[0036] In relation to Fig. 10B and Fig. 10C, the pins 170 in some embodiments can have a height h1 in a range of about 5 nm to about 50 nm, a length w1 in a range of about 5 nm to about 500 nm, a width w6 (which is also the width of the trench 168 in Fig. 5A) in a range of approximately 5 nm to approximately 500 nm. The distance d3 between two adjacent pins 170 can, in some embodiments, be in a range of approximately 10 nm to approximately 500 nm. As discussed previously, the height h2 of the trench 168 is equal to or greater than the height h1 of the pins 170. Furthermore, the distance d3 is greater than the width of the active region 103. This ensures that the pins 170 are isolated from the active region 103 by the dielectric lining 174 and the air gap 176.

[0037] In relation to Fig. In different embodiments, the dielectric lining 174 can have a thickness t1 (at the top surface of the dielectric lining 174) that is less than 10 nm, as in a range of about 0.5 nm to about 10 nm. In different embodiments, the dielectric lining 174 can have a thickness t2 (in the middle or bottom section of the dielectric lining 174) that is less than 10 nm, as in a range of about 0.5 nm to about 10 nm. Furthermore, the thickness t2 is less than t1 in the present embodiment. The thicknesses t1 and t2 are measured along the "x" direction. Furthermore, the dielectric lining 174 can have a thickness t3 (in the bottom section of the dielectric lining 174, measured along the "z" direction) that is less than 10 nm, as in a range of about 0.5 nm to about 10 nm.

[0038] In relation to Fig. In different embodiments, the dielectric lining 174 can have a thickness t4 (at the top surface of the dielectric lining 174) that is less than 10 nm, in a range of approximately 0.5 nm to approximately 10 nm. In different embodiments, the dielectric lining 174 can also have a thickness t5 (in the middle or bottom section of the dielectric lining 174) that is less than 10 nm, in a range of approximately 0.5 nm to approximately 10 nm. Furthermore, in the present embodiment, the thickness t5 is less than t4. The thicknesses t4 and t5 are measured along the y-direction.

[0039] In the discussion above, the upper limit of the thicknesses t1, t2, t3, t4, and t5 (e.g., approximately 10 nm) is chosen such that sufficient space remains for the air gap 176 in the trench 172. Because air has a lower dielectric constant than the material of the dielectric lining 174, having a larger air gap 176 reduces the stray capacitance between the pins 170. The dielectric lining 174 can be made as thin as possible, depending on the deposition technology, but still thick enough to produce the overhang profile discussed previously.

[0040] In relation to Fig. 10B and Fig. In 10C, the air gap 176 has a top opening width w3 along the “x” direction and a top opening width w5 along the “y” direction. In some embodiments, both w3 and w5 can be in a range from 0 nm (i.e., the air gap 176 is completely enclosed by the dielectric lining 174 alone) to about 500 nm (for example, the CMP process in operation 30 can expose a width opening of the air gap 176). Furthermore, the air gap 176 has a width w4 along the “x” direction and a width w7 along the “y” direction in the belly section of the air gap 176. In the present embodiment, w3 is smaller than w4 and w5 is smaller than w7.

[0041] In operation 32, procedure 10 ( Fig. 1B) further manufacturing processes on the back of the component 100. For example, it can form an interconnect structure 190 over the insulation structure 105, the pins 170, the dielectric lining 174, and the air gap 176. An example is shown in Fig. 11A and Fig. 11B shown, where Fig. 11B a cross-sectional view of component 100 along section 1 line in Fig. 11A is. Regarding Fig. 11A and Fig. 11B features the interconnect structure 190 with conductors (such as metal conductors and vias) 194 embedded in one or more dielectric layers 192. The configuration of the interconnect structure 190 can be similar to that of the interconnect structure 162 ( Fig. 2B). In particular, the composition and formation of the conductors 194 and the dielectric layers 192 can be the same as those of the conductors 166 and the dielectric layers 164, respectively. In embodiments where the air gaps 176 are not completely sealed by the dielectric lining 174, they are completely sealed by the dielectric lining 174 and the dielectric layers 192 together. Furthermore, structures similar to the dielectric lining 174 and the air gap 176 can be formed in the interconnect structure 190, such as between some of the conductors 194. Fig. Figure 11B-1 illustrates an embodiment of the device 100 with GAA-FETs after the device 100 has undergone operations 14 to 32. As illustrated, the dielectric lining 174 and the air gap 176 are arranged over the active region 103 and the channel layers 103a. Other aspects of Fig. 11B-1 are the same as those in Fig. 11B. After the back side of the component 100 has been processed, the method 10 can remove the support substrate 220 ( Fig. 3).

[0042] Although not intended as limiting, embodiments of the present disclosure provide one or more of the following advantages. For example, embodiments of the present disclosure form a dielectric lining with an air gap on the back side of a wafer. The dielectric lining and the air gap effectively reduce the stray capacitance between adjacent conductors and increase their insulation. In addition, the air gap can also reduce or eliminate metal loss to and from the conductors, thereby increasing the long-term reliability of the device. Embodiments of the present disclosure can already be integrated into existing semiconductor manufacturing processes.

[0043] In an exemplary aspect, the present disclosure relates to a method comprising providing a structure with transistors, an insulating structure that is at least partially over the transistors, two metal pins passing through the insulating structure and electrically connected to the electrodes of the transistors, and a trench, wherein the insulating structure and the two metal pins form the side walls of the trench. The method further comprises forming a dielectric lining on the side walls of the trench and over the insulating structure and the metal pins, wherein the dielectric lining is thicker at an opening section of the trench than at another section of the trench that is deeper than the opening section, such that an air gap is formed within the trench and the air gap is completely or partially surrounded by the dielectric lining.The process further includes depositing a dielectric sacrificial layer over the dielectric lining and over the air gap, and performing a chemical-mechanical planarization (CMP) process to remove the dielectric sacrificial layer and deepen the dielectric lining until the insulation structure and metal pins are exposed, with the air gap remaining within the trench.

[0044] In some embodiments, the method further comprises forming a dielectric layer over the insulating structure, the dielectric lining, the air gap and the metal pins, wherein the air gap is sealed by the dielectric lining alone or by both the dielectric lining and the dielectric layer; and forming conductors in the dielectric layer, wherein the conductors are electrically connected to the metal pins.

[0045] In some embodiments of the method, the formation of the dielectric lining includes the use of plasma-enhanced chemical vapor deposition (PECVD). In other embodiments, the PECVD includes the application of plasma generated from SiH4 gas and N2 or NH3 gas.

[0046] In some embodiments, the process further includes treating the side walls of the trench with a plasma containing atoms of nitrogen, fluorine, chlorine, oxygen, hydrogen or argon prior to the formation of the dielectric lining.

[0047] In some embodiments of the method, providing the structure includes receiving a workpiece having a substrate with active regions, wherein the isolation structure isolates the active regions, and the transistors are formed over the active regions, wherein the workpiece further has an interconnect structure over the transistors, the substrate being at a rear of the workpiece and the interconnect structure being at a front of the workpiece.The provision of the structure further comprises attaching the front of the workpiece to a support wafer; thinning the workpiece from the back until the insulation structure and active regions are exposed from the back; etching two holes through the active regions to expose the transistor electrodes from the back; forming the two metal pins in the two holes; and etching the active regions between the two metal pins from the back, forming the trench. In another embodiment, the transistors are FinFETs and the active regions have semiconductor fins. In yet another embodiment, the transistors are gate-all-around FETs and the active regions have semiconductor fins.

[0048] In some embodiments of the method, the trench is as deep as or deeper than the metal pins.

[0049] In another exemplary aspect, the present disclosure relates to a method comprising providing a structure having a silicon substrate, an insulating structure over the silicon substrate, one or more semiconductor fins extending from the silicon substrate and over the insulating structure, one or more transistors formed over the one or more semiconductor fins, and an interconnect structure over the one or more transistors, wherein the silicon substrate is at a rear side of the structure and the interconnect structure is at a front side of the structure. The method further comprises attaching the front side of the structure to a support substrate; thinning the structure from the rear side of the structure until the insulating structure and the one or more semiconductor fins are exposed from the rear side of the structure;to etch two holes through the one or more semiconductor fins to expose two source / drain features of the one or more transistors from the rear of the structure; to form two metal pins, each in the two holes; to etch the one or more semiconductor fins between the two metal pins from the rear of the structure, thereby forming a trench; and to form a dielectric lining on the side walls of the trench and over the insulating structure and the metal pins, wherein the dielectric lining is thicker at one opening section of the trench than at another section of the trench that is deeper than the opening section, so that an air gap is formed within the trench.

[0050] In some embodiments of the method, the trench is as deep as or deeper than the metal pins on the back of the structure. In some embodiments, the air gap is completely surrounded by the dielectric lining alone.

[0051] In some embodiments, the method further comprises depositing a dielectric sacrificial layer over the dielectric lining and over the air gap, and performing a chemical-mechanical planarization (CMP) process to remove the dielectric sacrificial layer and deepen the dielectric lining until the insulation structure and the metal pins are exposed, with the air gap remaining within the trench. In another embodiment, after performing the CMP process, the method further comprises forming another interconnect structure over the back side of the structure and over the dielectric lining, the air gap, and the metal pins.

[0052] In some embodiments of the process, the formation of the dielectric lining involves the use of plasma-enhanced chemical vapor deposition (PECVD) with plasma generated from SiH4 gas and NH3 gas.

[0053] In yet another exemplary aspect, the present disclosure relates to a semiconductor structure having a front and a back. The semiconductor structure has an insulating structure on the back; one or more transistors above the insulating structure and on the front, wherein the one or more transistors have source / drain electrodes; a first interconnect structure above the one or more transistors and on the front; two metal pins through the insulating structure and in contact with two of the source / drain electrodes from the back, wherein the two metal pins and the insulating structure form the side walls of a trench; and a dielectric lining on the side walls of the trench, wherein the dielectric lining partially or completely surrounds an air gap within the trench.

[0054] In some embodiments, the semiconductor structure further comprises a second interconnect structure beneath the two metal pins and on the back side. In some embodiments, the dielectric lining is thicker at one open section of the trench than at another section of the trench that is deeper than the open section, oriented from back to front. In some embodiments, the dielectric lining has a thickness of less than 10 nm at the side walls of the trench. In some embodiments, the dielectric lining is in direct contact with the two source / drain electrodes.

Claims

[1] Procedure, encompassing: Providing a structure comprising transistors, an insulating structure (105) which is at least partially over the transistors, two metal pins (170) through the insulating structure (105) and electrically connected to electrodes of the transistors, and a trench (172) wherein the insulating structure (105) and the two metal pins (170) form side walls of the trench (172); Forming a dielectric lining (174) on the side walls of the trench (172) and over the insulating structure (105) and the metal pins (170), wherein the dielectric lining (174) is thicker at one opening section of the trench (172) than at another section of the trench (172) that is deeper than the opening section, so that an air gap (176) is formed inside the trench (172) and the air gap (176) is completely or partially surrounded by the dielectric lining (174); Deposition of a dielectric sacrificial layer (178) over the dielectric lining (174) and over the air gap (176); and Performing a chemical-mechanical planarization process (CMP process) to remove the dielectric sacrificial layer (178) and deepen the dielectric lining (174) until the insulation structure (105) and the metal pins (170) are exposed, leaving the air gap (176) within the trench (172). [2] Method according to claim 1, further comprising: Forming a dielectric layer (192) over the insulating structure (105), the dielectric lining (174), the air gap (176) and the metal pins (170), wherein the air gap (176) is sealed by the dielectric lining (174) alone or by both the dielectric lining (174) and the dielectric layer (192); and Formation of conductors (194) in the dielectric layer (192), wherein the conductors (194) are electrically connected to the metal pins (170). [3] Method according to claim 1 or 2, wherein forming the dielectric lining (174) comprises using plasma-enhanced chemical vapor deposition (PECVD). [4] Method according to claim 3, wherein the PECVD comprises applying plasma generated from SiH4 gas and N2 or NH3 gas. [5] Method according to any of the preceding claims, further comprising, prior to forming the dielectric lining (174): Treating the side walls of the trench (172) with a plasma containing atoms of nitrogen, fluorine, chlorine, oxygen, hydrogen or argon. [6] Method according to any of the preceding claims, comprising providing the structure: Receiving a workpiece having a substrate (102) with active regions (103), wherein the insulation structure (105) insulates the active regions (103), and the transistors are formed over the active regions (103), wherein the workpiece further has an interconnect structure (162) over the transistors, wherein the substrate (102) is at a rear side of the workpiece and the interconnect structure (162) is at a front side of the workpiece; Attaching the front of the workpiece to a carrier wafer (220); Thinning the workpiece from the back of the workpiece until the insulation structure (105) and the active areas (103) are exposed from the back of the workpiece; Etching two holes (168) through the active areas (103) to expose the electrodes of the transistors from the back of the workpiece; Forming the two metal pins (170) in each of the two holes (168); and Etching of the active areas (103) between the two metal pins (170) from the back of the workpiece, forming the trench (172). [7] Method according to claim 6, wherein the transistors comprise FinFETs and the active areas (103) comprise semiconductor fins. [8] Method according to claim 6, wherein the transistors comprise gate all-around FETs and the active areas (103) comprise semiconductor fins. [9] Method according to any of the preceding claims, wherein the trench (172) is as deep as or deeper than the metal pins (170). [10] Procedures, including: Providing a structure comprising a silicon substrate (102), an insulating structure (105) over the silicon substrate, one or more semiconductor fins (103) extending from the silicon substrate (102) and over the insulating structure (105), one or more transistors formed over the one or more semiconductor fins (103), and an interconnect structure (162) over the one or more transistors, wherein the silicon substrate is at a rear side of the structure and the interconnect structure (162) is at a front side of the structure (162); Attaching the front of the structure (162) to a support substrate (220); Thinning the structure from the back of the structure until the insulation structure (105) and the one or more semiconductor fins (103) are exposed from the back of the structure; Etching two holes (168) through the one or more semiconductor fins (103) to expose two source / drain features (104) of the one or more transistors from the back side of the structure; Forming two metal pins (170) each in the two holes (168); Etching of one or more semiconductor fins (103) between the two metal pins (170) from the back of the structure, thereby forming a trench (172); and Forming a dielectric lining (174) on side walls of the trench (172) and over the insulation structure (105) and the metal pins (170), wherein the dielectric lining (174) is thicker at one opening section of the trench (172) than at another section of the trench (172) that is deeper than the opening section, so that an air gap (176) is formed inside the trench (172). [11] Method according to claim 10, wherein the trench (172) is as deep as or deeper than the metal pins (170) from the rear of the structure. [12] Method according to claim 10 or 11, wherein the air gap (176) is completely surrounded by the dielectric lining (174) alone. [13] Method according to any one of the preceding claims 10 to 12, further comprising: Deposition of a dielectric sacrificial layer (178) over the dielectric lining (174) and over the air gap (176); and Performing a chemical-mechanical planarization process (CMP process) to remove the dielectric sacrificial layer (178) and deepen the dielectric lining (174) until the insulation structure (105) and the metal pins (170) are exposed, leaving the air gap (176) within the trench (172). [14] The method of claim 13, further comprising, after carrying out the CMP process: Forming another interconnect structure (190) over the back of the structure and over the dielectric lining (174), the air gap (176) and the metal pins (170). [15] Method according to any one of the preceding claims 10 to 14, wherein forming the dielectric lining (174) comprises using plasma-enhanced chemical vapor deposition (PECVD) with plasma generated from SiH4 gas and NH3 gas. [16] Semiconductor structure having a front and a back side, comprising: an insulation structure (105) on the back; one or more transistors above the insulation structure (105) and on the front side, wherein the one or more transistors have source / drain electrodes; a first interconnect structure above the one or more transistors and on the front side; two metal pins (170) through the insulation structure (105) and in contact with two of the source / drain electrodes (104) from the rear, the two metal pins (170) and the insulation structure (105) forming side walls of a trench (172); and a dielectric lining (174) on the side walls of the trench (172), wherein the dielectric lining (174) partially or completely surrounds an air gap (176) within the trench (172). [17] Semiconductor structure according to claim 16, further comprising: a second interconnect structure (190) under the two metal pins (170) and on the back. [18] Semiconductor structure according to claim 16 or 17, wherein the dielectric lining (174) is thicker at one opening section of the trench (172) than at another section of the trench (172) which is deeper than the opening section, oriented from the back to the front. [19] Semiconductor structure according to any one of the preceding claims 16 to 18, wherein the dielectric lining (174) has a thickness of less than 10 nm at the side walls of the trench (172). [20] Semiconductor structure according to any one of the preceding claims 16 to 19, wherein the dielectric lining (174) is in direct contact with the two of the source / drain electrodes.

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