Method for producing sources / drains in semiconductor devices

Abstract

Procedure, comprehensive: Forming a gate structure (120) over a silicon-on-insulator substrate, SOI substrate (102), wherein the SOI substrate (102) has: a basic semiconductor layer (104); an insulating layer (106) over the base semiconductor layer (104); and an upper semiconductor layer (108) above the insulating layer (106); Deposition of a gate spacer layer (122) over a top surface and along a side wall of the gate structure (120); Etching (126) of the gate spacer layer (122) to define a gate spacer (124) on the side wall of the gate structure (120); after etching the gate spacer layer (122), etching (128) a recess (130) into the upper semiconductor layer (108) using a first etching process (128), wherein the recess (130) does not extend horizontally under the gate spacer (124); after the first etching process (128), extending the recess (130) further into the upper semiconductor layer (108) using a second etching process (132, 136), wherein the first etching process (128) differs from the second etching process (132, 136), wherein after the second process the recess (130) does not extend horizontally below the gate structure (120); and after the second etching process (132, 136), a source / drain region (142) is formed in the recess (130), wherein the source / drain region (142) extends horizontally above and below a lower tip of the gate spacer element (124) and touches it.

Description

GENERAL STATE OF THE ART

[0001] Semiconductor devices are used in a wide variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic equipment. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers onto a semiconductor substrate, and by structuring the various material layers using lithography to form circuit components and elements.

[0002] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, thus allowing more components to be integrated into a given area. However, as minimum feature sizes are reduced, additional problems arise that need to be addressed.

[0003] US Patent 2020 / 0020771A1 discloses a method for forming a source / drain region of a FinFET device. The method comprises a first etching process to etch a recess in a semiconductor fin on one side of a gate stack on a section of the semiconductor fin, and a second etching process to extend the recess further into the semiconductor fin. Subsequently, a source / drain region is formed in the extended recess.

[0004] Further prior art relating to the subject matter of the invention can be found, for example, in US 2014 / 0353741 A1, US 2013 10037919 A1 and DE 10 2009 010 882 A1.

[0005] The present invention is defined by independent claims 1 and 11. Specific embodiments are given in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. The Fig. Figures 1 to 6, 7A, 7B, 7C and 10 to 15 illustrate various intermediate steps in the manufacture of a transistor device according to some embodiments. Fig. Figure 8 illustrates an intermediate step in the manufacture of a transistor device according to some embodiments. Fig. Figure 9 illustrates an intermediate step in the manufacture of a transistor device according to some embodiments. DETAILED DESCRIPTION

[0007] The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Forming a first feature over or on top of a second feature in the following description may, for example, include embodiments in which the first and second features are formed in direct contact, and also embodiments in which additional functions may be formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, the present disclosure may repeat reference numbers and / or symbols in the various examples.This repetition serves the purpose of simplicity and clarity and does not in itself dictate a relationship between the various described embodiments and / or configurations.

[0008] Furthermore, spatially relative terms such as "below," "under," "lower," "above," "upper," and the like may be used herein to facilitate discussion and describe the relationship of one element or feature to one or more other elements or features as illustrated in the figures. These spatially relative terms are intended to encompass, in addition to the orientation shown in the figures, various orientations of the device during its use or operation. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0009] Various embodiments feature a fully depleted silicon-on-insulator (FDSOI) transistor with enhanced source / drain regions (extending, for example, over a top surface of a substrate). The FDSOI transistor can be formed on a top silicon layer of a silicon-on-insulator (SOI) substrate. To create the source / drain regions, the top silicon layer can be etched to define source / drain recesses, for example, using a fluorine-ozone mixing (FOM) process. Etching provides source / drain recesses that allow the source / drain region to extend deeper into the top silicon layer, thereby reducing the parasitic resistance in the resulting transistor and improving its electrical performance.Furthermore, a sufficiently thick section of the upper silicon layer remains below the source / drain region, advantageously providing support for the overlying features during subsequent processing steps. In various embodiments, for example, approximately 1 nm (10 Å) to approximately 5 nm (50 Å), such as approximately 2 nm (20 Å) to approximately 3 nm (30 Å), of the upper silicon layer remains below the source / drain recesses. Therefore, manufacturing defects (e.g., SOI substrate cracking caused by a coefficient of thermal expansion (CTE) mismatch between the upper silicon layer and the underlying buried oxide layer (BOX layer)) can be advantageously reduced.

[0010] While various embodiments related to planar transistors are described herein, it is understood that these embodiments are not limited to planar transistors. For example, various embodiments can also be applied to dual-gate devices, fin field-effect transistor (FinFET) devices, nanostructured devices (also known as gate wrap devices), or the like.

[0011] The Fig. Figures 1 to 6, 7A, 7B, 7C, and 10 to 15 illustrate cross-sectional views of intermediate steps in the fabrication of a device 100 according to various embodiments. In various embodiments, the device 100 can be fabricated as part of a semiconductor wafer with multiple device regions. Transistors are fabricated in each of the device regions, and interconnect structures are formed across the transistors to provide functional circuits. After the functional circuits have been fabricated, individual device regions can be separated from other device regions on the semiconductor wafer using a suitable singulation process. Thus, individual semiconductor dies (sometimes referred to as bare dies) are formed from the circuits of the singulated device regions.

[0012] With reference to Fig. Figure 1 illustrates a substrate 102. The substrate 102 can be a SOI substrate comprising a base semiconductor layer 104, an insulator layer 106, and an upper semiconductor layer 108. In general, an SOI substrate is a layer of semiconductor material (e.g., the upper semiconductor layer 108) formed on an insulator layer (e.g., the insulator layer 106). The base semiconductor layer 104 provides a support substrate on which other features (including the insulator layer 106 and the upper semiconductor layer 108) are formed. In some embodiments, the base semiconductor layer 104 is a silicon substrate or a glass substrate. Other materials may also be used.

[0013] The insulating layer 106 can be, for example, a buried oxide layer (BOX layer), a silicon oxide layer, or the like. In some embodiments, the insulating layer 106 can be relatively thin. As a result, a body bias through the base semiconductor layer 104 can be applied more efficiently to subsequently formed transistors, and the switching speeds of the resulting transistors can be improved. Furthermore, the inclusion of the insulating layer 106 allows a higher bias voltage to be applied, thereby enabling more effective control of the resulting transistors. The electrical behavior of the resulting transistors can be controlled both by their gate and by polarizing the underlying base semiconductor layer 104. Consequently, the resulting transistor can be functionally similar to a dual-gate device.In one embodiment, the thickness T1 of the insulating layer 106 can be in the range of approximately 50 nm to approximately 300 nm. In other embodiments, the insulating layer 106 can have different dimensions.

[0014] The upper semiconductor layer 108 can be a semiconductor layer, such as a silicon layer. In some embodiments, the upper semiconductor layer 108 is relatively thin to improve the mobility of transistors formed on the upper semiconductor layer 108. In one embodiment, the thickness T1 of the upper semiconductor layer 108 can be in the range of approximately 6 nm to approximately 8 nm. In other embodiments, the upper semiconductor layer 108 can have different dimensions. Due to the thinness of the upper semiconductor layer 108, a channel region of the resulting transistor can be completely undoped, and pocket implantation is unnecessary. Furthermore, a thin upper semiconductor layer 108 with an underlying insulating layer 106 limits the electron flow between the source and drain regions of the resulting transistor, thus reducing leakage currents.

[0015] Although one region of substrate 102 is illustrated, it is understood that substrate 102 may have many regions in which different types of devices (e.g., n- and p-devices) are fabricated. Any number of features (e.g., isolation regions and the like) may be arranged between n- and p-device regions. The structures illustrated in the remaining figures may be applicable to both the n-device and p-device regions. Differences (if any) in the structures of the n- and p-device regions are described in the text accompanying each figure.

[0016] In Fig. 2 A dummy dielectric 110 is formed on the upper semiconductor layer 108. The dummy dielectric layer 110 can be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and can be deposited or thermally grown according to acceptable techniques.

[0017] A dummy gate layer 112 is formed over the dummy dielectric layer 110. The dummy gate layer 112 can be a conductive material and can be selected from a group comprising polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metallic nitrides, metallic silicides, metal oxides, and metals. In one embodiment, amorphous silicon is deposited and recrystallized to produce polysilicon. The dummy gate layer 112 can be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), sputtering, or other techniques for depositing conductive materials.

[0018] A mask layer 114 can be deposited over the dummy gate layer 112. The mask layer 114 can, for example, comprise SiN, SiON, or the like. In this example, a single dummy gate layer 112 and a single mask layer 114 are formed. In some embodiments, separate dummy gate layers and separate mask layers can be formed in the n-device regions versus the p-device regions.

[0019] In Fig. 3 can the mask layer 114 (see Fig. 7) The masks 115 can be structured using acceptable photolithography and etching techniques. The structure of the masks 115 can then be transferred to the dummy gate layer 112 to form dummy gate electrodes 118. The structure of the masks 115 can also be transferred to the dummy dielectric layer 110 by an acceptable etching technique to form the dummy gate dielectrics 116. Thus, dummy gates 120 are formed, which have the dummy gate electrodes 118 and the dummy gate dielectrics 116. The dummy gates 120 cover the corresponding channel regions 150 of the upper semiconductor layer 108. The structure of the masks 115 can be used to physically separate each of the dummy gates 120 from adjacent dummy gates. For the sake of simplified illustration, only a single dummy gate 120 is shown, but it is understood that several dummy gates 120 are formed on the substrate 102.

[0020] In some embodiments, the channel regions 150 are undoped. For example, no implantation processes can be carried out on the upper semiconductor layer 108 until subsequently formed source / drain regions have grown (see Fig. 10) In some embodiments, no weakly doped drain regions (LDD regions) are formed in the upper semiconductor layer 108 and no pocket implantation is performed.

[0021] Although a single layer of masks 115 is illustrated, multiple layers of masks 115 can be used in various structuring techniques for forming the dummy gates 120. For example, the dummy gates 120 can be structured using one or more photolithography processes, including dual or multiple structuring processes. Generally, dual or multiple structuring processes combine photolithography and self-alignment processes, making it possible to produce structures with, for example, spacings that are smaller than what is otherwise achievable using a single direct photolithography process. In one embodiment, for example, a sacrificial layer is formed over a substrate and structured using a photolithography process. Spacing elements are formed along the structured sacrificial layer using a self-alignment process.The sacrificial layer is then removed, and the remaining spacer elements can then be used to structure the Dummygates 120.

[0022] In the illustrated embodiment, the masks 115 can remain on the dummy gates 120. In other embodiments, the masks 115 can be removed after the dummy gates 120 have been formed and before other features (e.g., gate spacer layer 122, see Figure 1) have been formed. Fig. 4) be removed.

[0023] In Fig. 4. A gate spacer layer 122 is deposited over and along the sidewalls of the dummy gates 120. In embodiments where the masks 115 are not removed, the gate spacer layer 112 is also deposited over the masks 115. The gate spacer layer 122 is formed by conformal deposition using a suitable process, such as CVD, atomic layer deposition (ALD), or the like. The insulating material of the gate spacer layer 122 can be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, multiple layers thereof, or the like.

[0024] In Fig. 5. The gate spacer layer 122 is structured such that it defines the gate spacers 124 on the sidewalls of the gate stacks 120. The structuring of the gate spacer layer 122 can, for example, include an anisotropic etching process 126. In some embodiments, the etching process 126 is a dry etching process using a suitable etchant, such as a chlorine-based etchant. In some embodiments, the etching process 126 can be a plasma process. In some embodiments, the etching process 126 can be a high-power etching process using RF power in the range of approximately 10 kW to approximately 100 kW. Furthermore, the etching process 126 can be a time-controlled etching process to define the shape of the gate spacers 124. The length of the etching process 126 can, for example, be in the range of approximately 30 s to approximately 150 s.In other embodiments, the etching process 126, which is used to define the spacer elements 124, may include a different set of parameters.

[0025] In Fig. 6. An additional etching process 128 can be applied. The etching process 128 can be carried out in situ (e.g., in the same process chamber) after the etching process 126. In some embodiments, the etching process 128 can be carried out in situ (e.g., in the same process chamber). Fig. The etching process 126 described in Section 5 can damage exposed areas 108' of the upper semiconductor layer 108 (e.g., areas of the upper semiconductor layer 108 that are not covered by the gate stacks 120 or the gate spacer elements 124). The etching process 128 can etch exposed areas 108' of the upper semiconductor layer 108 to reduce surface damage to the upper semiconductor layer 108. For example, the etching process 128 can reduce the roughness of the exposed areas 108' so that subsequently formed source / drain regions (see the source / drain regions 142 in Section 5) are less severely damaged. Fig. 10) can be grown with fewer defects.

[0026] In some embodiments, the etching process 128 is a dry etching process using a suitable etchant, such as a chlorine-based etchant. The etching process 126 can be a plasma process in some embodiments. The etching process 128 can be a low-power etching process, using lower RF power than the etching process 126. For example, the RF power used in the etching process 128 can be in the range of approximately 15 W to approximately 1 kW. Furthermore, the etching process 128 can be a time-controlled etching process. The duration of the etching process 126 can be in the range of approximately 5 s to approximately 150 s, for example. In other embodiments, the etching process 128 can include a different set of parameters.

[0027] In other embodiments, the etching process 128 may include one or more wet etching processes in addition to or instead of the dry etching process. For example, a wet etching process or processes may be applied after the dry etching process, or the wet etching process(s) may be applied instead of the dry etching process. The wet etching process(s) may be cleaning processes that remove surface particles, native oxide layers, or the like that have formed on the exposed surfaces 108' of the upper semiconductor layer 108. The wet etching process(s) may further passivate the exposed surfaces 108' of the upper semiconductor layer 108. Any combination of the following etchants may be used in the wet etching process(s): trisborate-ethylenediaminetetraacetic acid (TBE), sulfur peroxide mixture (SPM), an SC-1 solution (containing, for example, ammonia, deionized water, and hydrogen peroxide), an SC-2 solution (containing, for example,(containing ammonia, deionized water, and hydrogen peroxide) or the like. For example, a first wet etching process using TBE, the SC-1 solution, and the SC-2 solution can be applied to the exposed areas 108', and a second wet etching process using SPM and the SC-1 solution can then be applied to the exposed areas 108'. In embodiments where wet etching processes are used, a drying and centrifugation process can be applied to the semiconductor wafer after the wet process(es).

[0028] A combination of etching processes 126 and 128 can recess the exposed areas 108' of the upper semiconductor layer 108. For example, the etching processes 126 and 128 can form recesses 130 in the upper semiconductor layer 108. The recesses 130 can extend to a depth D1, which is a height difference between a top surface of the upper semiconductor layer 108 and a bottom surface of the recesses 130. In some embodiments, the depth D1 can be in a range of approximately 0.5 nm (5 Å) to approximately 5 nm (50 Å). In some embodiments, the depth D1 can be in a range of more than zero and less than 0.6 nm (6 Å). In other embodiments, the recesses 130 can extend to varying depths. The etching process 128 can be a light etching process to remove the defects on an area of ​​the upper semiconductor layer 108 and to slightly flatten the upper semiconductor layer 108.

[0029] In the etching process 128, the gate spacer elements 124 can mask one or more sections of the upper semiconductor layer 108 that border the gate stacks 120. Therefore, each recess 130 is separated by the upper semiconductor layer 108 from the gate stacks 120 and their underlying dummy gate dielectrics 116. The recesses 130, for example, cannot extend horizontally to the dummy gate dielectrics 116.

[0030] In the Fig. In 7A to 7C, the recesses 130 are extended further into the upper semiconductor layer 108. This extension of the recesses 130 allows subsequently grown source / drain regions to form within the recesses 130 (e.g., the source / drain regions 142, see [reference]). Fig. 10) extend further into the substrate 102. As a result, the electrical performance of the resulting transistor can be improved. For example, it has been observed that the parasitic capacitance of the resulting devices can be reduced compared to source / drain regions that do not extend deep into the substrate 102.

[0031] The enlargement of the recesses 130 can involve a cyclic FOM process. The FOM process can be performed in situ after the etching process 128, or the FOM process can be performed ex situ (e.g., in a different process chamber) than the etching process 128.

[0032] The Fig. 7A and Fig. Figure 7B illustrates a cycle of the FOM process. First, as shown in Fig. Figure 7A illustrates an oxidation process 132 being applied to exposed surfaces of the recesses 130. The oxidation process 132 forms the oxide regions 134 in sections of the upper semiconductor layer 108 that are exposed by the recesses 130. In embodiments where the upper semiconductor layer 108 is a silicon layer, the oxide regions 134 are silicon oxide regions.

[0033] The oxidation process 132 can involve flowing a process gas containing ozone (O3) over surfaces of the recesses 130. The process gas can contain ozone at a concentration ranging from 20 ppm (parts per million) to 40 ppm. In some embodiments, the oxidation process 132 can be carried out for a duration of 20 s to 30 s. The oxidation process 132 can be a self-limiting process. For example, the oxidation process 132 continues to form the oxide regions 134 in the upper semiconductor layer 108 until upper sections of the upper semiconductor layer 108 are saturated with oxygen.Since the recesses 130 are separated from the gate stacks 120 after the etching process 128, and the gate spacer elements 124 also mask one or more sections of the upper semiconductor layer 108 adjacent to the gate stacks 120, each oxide region 134 can still be separated from the gate stacks 120 and the underlying dummy gate dielectrics 116 by the upper semiconductor layer 108. The oxide regions 134 may not extend horizontally to the dummy gate dielectrics 116.

[0034] Next, remove as in Fig. Figure 7B illustrates an etching process 136 on the oxide regions 134. The etching process 136 can be a wet etching using, for example, dilute hydrogen fluoride (dHF). The hydrogen fluoride can be diluted in water (e.g., deionized water or the like) to a dilution in the range of approximately 50:1 to approximately 150:1. In other embodiments, a different etchant can be used. The etching process 136 can be carried out for a duration of 20 to 40 seconds in some embodiments. The etching process 136 can be selective between the oxide regions 134 and the upper semiconductor layer 108, such that the etching process 136 removes the oxide regions 134 without significantly etching the remaining (e.g., non-oxidized) upper semiconductor layer 108.

[0035] Since the oxidation process 132 is a self-limiting process and the etching process 136 is a selective process, the amount of the upper semiconductor layer 108 removed during each cycle of the FOM process can be precisely controlled. The Fig. 7A and Fig. The cycle illustrated in Figure 7B (e.g., the oxidation process 132 and the etching process 136) can be repeated any number of times until the recesses 130 extend to a desired thickness in the upper semiconductor layer 108. In one example, two cycles of oxidation and etching are performed to extend the recesses 130 into the upper semiconductor layer 108. In other embodiments, a different number of cycles can be used.

[0036] After the desired number of cycles of the FOM process have been executed, the resulting structure is in Fig. Figure 7C illustrates this. As a result of the FOM process, the openings 130 extend a depth D2 into the upper semiconductor layer 108. In some embodiments, the depth D2 is in a range of approximately 10 Å to approximately 100 Å, such as between approximately 2 nm (20 Å) and approximately 3 nm (30 Å), or between approximately 1.7 nm (17 Å) and approximately 2.5 nm (25 Å). It has been observed that extending the openings 130 into the upper semiconductor layer 108 to a depth in the above range can improve the electrical performance of the resulting transistor. For example, source / drain regions are subsequently formed (see Figure 7C). Fig. 10) formed in the recesses 130. Deeper recesses 130 (e.g., recesses with the depth shown above) allow source / drain regions to extend further into the upper semiconductor layer 108, which facilitates the diffusion of dopants from the source / drain region into the undoped channel region of the transistor (e.g., region 150, see Figure 10). Fig. 15) reduced. By reducing dopant diffusion, the parasitic resistance of the channel region 150 can be advantageously reduced. For example, simulation data have shown that the parasitic resistance can be reduced by approximately 40 Ω per µm when the recesses 130 have a depth D2 of approximately 20 Å. Simulation data have also shown that for nMOS transistors with source / drain region configurations extending to the depth described above into the upper semiconductor layer 108, a performance improvement of 6% or more can be achieved. Accordingly, the recesses 130 of the upper semiconductor layer 108 extend horizontally to below the gate spacer elements 124 and, after the FOM process, do not extend to the dummy gate dielectrics 116.

[0037] However, it has also been observed that it is desirable for a portion of the upper semiconductor layer 108 to remain below the recesses 130. The recesses 130 may, for example, be separated from the insulator layer 106 by the upper semiconductor layer 108, and the thickness T3 of the upper semiconductor layer 108 between the recesses 130 and the insulator layer 106 may range from approximately 10 Å to approximately 50 Å, such as approximately 20 Å to approximately 30 Å. Due to differences in the CTE of the upper semiconductor layer 108 (which, for example, contains silicon) and the insulator layer 106 (which, for example, contains silicon oxide), the upper semiconductor layer 108 may be prone to cracking if it is too thin. The risk of cracking may be increased in subsequent processes where the wafer is heated. By leaving a section of the upper semiconductor layer 108 in the above thickness range, manufacturing defects (e.g.Cracking) is avoided. It was observed that if the recesses 130 are extended deeper into the upper semiconductor layer 108, such that the thickness T3 lies outside the aforementioned areas, increased cracking in the substrate 102 results.

[0038] The Fig. 7A and Fig. Figure 7B illustrates a method for achieving the embodiment structure of Fig. 7C. Other methods can also be used. For example, illustrates Fig. 8 a method for enlarging the openings 130 in a device according to another embodiment. In Fig. 8 can have a structure similar to that in Fig. 7A and identical reference numbers indicate identical elements formed using identical processes. A dry etching process 138 is used to enlarge the openings 130. In the dry etching process 138, a suitable etchant, such as a chlorine-based etchant, is used. The dry etching process 138 can be a plasma process. In some embodiments, the dry etching process 138 can be a low-power etching process, using, for example, RF power in the range of approximately 15 W to approximately 1 kW. Furthermore, the dry etching process 138 can be a time-controlled etching process. The duration of the dry etching process 138 can, for example, be in the range of 5 s to approximately 150 s. In other embodiments, the dry etching process 138 can include a different set of parameters. The dry etching process 138 results in a structure that corresponds to the one in Fig. The structure illustrated in 7C is similar. Subsequent processing (e.g., as below regarding the Fig. The steps described in sections 10 to 15 can be carried out to complete the device.

[0039] Fig. Figure 9 illustrates another method for enlarging the openings 130. In Fig. 9. A wet etching process 140 is used to enlarge the openings 130. In Fig. 9 can have a structure similar to that in Fig. 7A and identical reference numbers indicate identical elements formed using the same processes. In wet etching process 140, a suitable etchant is used, such as a solution containing H3PO4 or the like. Furthermore, wet etching process 140 can be a time-controlled etching process. The duration of wet etching process 140 can, for example, range from 10 s to approximately 180 s. In other embodiments, wet etching process 140 may include a different set of parameters. Wet etching process 140 results in a structure that corresponds to the one described in Fig. The structure illustrated in 7C is similar. Subsequent processing (e.g., as below regarding the Fig. The steps described in sections 10 to 15 can be carried out to complete the device.

[0040] In Fig. Epitaxial source / drain regions 142 are formed in the recesses 130. The epitaxial source / drain regions 142 can exert a mechanical stress in the corresponding channel regions of the resulting transistor, thereby improving performance. The epitaxial source / drain regions 142 are formed in the upper semiconductor layer 108 such that each dummy gate 120 is arranged between corresponding adjacent pairs of epitaxial source / drain regions 142. In some embodiments, the gate spacer elements 124 are used to separate the epitaxial source / drain regions 142 from the dummy gates 120 by a suitable lateral distance, so that the epitaxial source / drain regions 142 do not short-circuit subsequently formed gates of the resulting transistors.The epitaxial source / drain regions 142 can be described as elevated source / drain regions because they extend over a top surface of the substrate 102. Accordingly, the epitaxial source / drain regions 142 can extend horizontally below and above the lower tips of the gate spacer elements 124, but cannot extend as far as the dummy gate dielectrics 116.

[0041] The epitaxial source / drain regions 142 in the n-fixation regions of the wafer can be formed by masking the p-fixation regions of the wafer and etching the upper semiconductor layer 108 in the n-fixation regions to create the recesses 130 (e.g., as described above) in the upper semiconductor layer 108. The epitaxial source / drain regions 142 in the n-fixation regions are then epitaxially grown in the recesses 130. The epitaxial growth process used to form the epitaxial source / drain regions 142 can be a low-temperature process in some embodiments. For example, the epitaxial growth process can be performed at a temperature of approximately 400 °C to approximately 600 °C. By performing the epitaxy in this temperature range, the stress exerted on the substrate can be advantageously reduced.

[0042] The epitaxial source / drain regions 142 can comprise any acceptable material, such as materials suitable for n-transistors. For example, the epitaxial source / drain regions 142 in the n-device regions can comprise materials such as silicon, silicon carbide, phosphor-doped silicon carbide, silicon phosphide, or the like, which exert tensile stress in the channel regions. The epitaxial source / drain regions 142 in the n-device regions can have surfaces that are raised relative to corresponding surfaces of the upper semiconductor device 108 and may have chamfers.

[0043] The epitaxial source / drain regions 142 in the p-device regions of the wafer can be formed by masking the n-device regions of the wafer and etching the upper semiconductor layer 108 in the p-device regions to create the recesses 130 (e.g., as described above) in the upper semiconductor layer 108. The epitaxial source / drain regions 142 in the p-device regions are then epitaxially grown in the recesses 130. The epitaxial growth process used to form the epitaxial source / drain regions 142 can be a low-temperature process in some embodiments. For example, the epitaxial growth process can be performed at a temperature of approximately 400 °C to approximately 600 °C. By performing the epitaxy in this temperature range, the stress exerted on the substrate can be advantageously reduced.

[0044] The epitaxial source / drain regions 142 can comprise any acceptable material, such as materials suitable for p-transistors. For example, the epitaxial source / drain regions 142 in the p-device regions can comprise materials such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, or the like, which exert compressive stress in the channel regions. The epitaxial source / drain regions 142 in the p-device regions can also have surfaces that are raised relative to corresponding surfaces of the upper semiconductor device 108 and may have chamfers.

[0045] The epitaxial source / drain regions 142 can be implanted with dopants to form source / drain regions, followed by annealing. The source / drain regions can accommodate an impurity concentration of approximately 10 19 cm -3 and approximately 10 21 cm -3exhibiting the following characteristics: The p-dopers can be boron, boron fluoride, indium, or the like. The n-dopers can be, for example, phosphorus, arsenic, antimony, or the like. In some embodiments, the epitaxial source / drain regions 142 can be doped in situ during growth.

[0046] The epitaxial source / drain regions 142 extend to a depth D2 into the upper semiconductor layer 108. As described above, the depth D2 can range from approximately 10 Å to approximately 100 Å. By extending the source / drain regions 142 deeper into the upper semiconductor layer 108, the diffusion of dopants from the source / drain region 142 into the undoped channel region 150 of the transistor can be reduced. By reducing dopant diffusion, the parasitic resistance of the channel region 150 can be advantageously reduced. For example, in simulation data, it was observed that the parasitic resistance can be reduced by approximately 40 Ω per µm when the source / drain regions 142 are extended to a depth D2 of approximately 20 Å.Simulation data also showed that for nMOS transistors with embodiments of source / drain regions 142 extending to the depth D2 described above into the upper semiconductor layer 108, a performance increase of 6% or more can be achieved.

[0047] In Fig. 11 a first interlayer dielectric (ILD) 146 is placed over the in Fig. The structure illustrated in Figure 10 is deposited. The first ILD 146 can consist of a dielectric and be deposited by any suitable process, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Dielectrics can be phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials formed by any acceptable process can be used. In some embodiments, a contact etch stop layer (CESL) 144 is arranged between the first ILD 146 and the epitaxial source / drain regions 142, the masks 115, and the gate spacer elements 124. The CESL 144 can be a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, which has a different etch rate than the material of the overlying first ILD 146.

[0048] In Fig. 12. A planarization process, such as a CMP, can be performed to align the upper surface of the first ILD 146 with the upper surfaces of the dummy gates 120 or the masks 115. The planarization process can also remove the masks 115 on the dummy gates 120 and the gate spacers 126 on the side walls of the masks 115. After the planarization process, the upper surfaces of the dummy gates 120, the gate spacers 126, and the first ILD 146 are at the same level. Accordingly, the upper surfaces of the dummy gates 120 are exposed through the first ILD 146. In some embodiments, the masks 115 can remain, in which case the planarization process levels the upper surface of the first ILD 146 with the upper surfaces of the masks 115.

[0049] In Fig. 13. The dummy gate electrodes 118 and the masks 115, if present, are removed in one or more etching steps, forming the recesses 148. In some embodiments, only the dummy gate electrodes 118 are removed, and the dummy gate dielectrics 116 remain and are exposed through the recesses 148. In some embodiments, the dummy gate dielectrics 116 are removed from the recesses 148 in a first region of a die (e.g., a core logic region) and remain in the recesses 148 in a second region of the die (e.g., an input / output region). In some embodiments, the dummy gate electrodes 118 are removed by an anisotropic dry etching process. The etching process can, for example, include a dry etching process using reaction gas(es), selectively etching the dummy gate electrodes 118 without etching the first ILD 146 or the gate spacer elements 124.Each recess 148 exposes and / or lies above a channel region 150 of the upper semiconductor layer 108. Each channel region 150 is arranged between adjacent pairs of dummy gate dielectrics 116 and can be used as an etch stop layer when the dummy gate electrodes 118 are etched. The dummy gate dielectrics 116 can then optionally be removed after the dummy gate electrodes 118 have been removed.

[0050] In Fig. Gate dielectric layers 152 and gate electrodes 154 for exchange gates are formed. The gate dielectric layers 152 are conformally deposited in the recesses 148, such as on the upper surfaces of the upper semiconductor layer 108 and on side walls of the gate spacer elements 124. The gate dielectric layers 152 can also be formed on the upper surface of the first ILD 146. According to some embodiments, the gate dielectric layers 152 comprise silicon oxide, silicon nitride, or multiple layers thereof. In some embodiments, the gate dielectric layers 152 comprise a high-k dielectric, and in these embodiments, the gate dielectric layers 152 can have a k-value greater than approximately 7.0 and comprise a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof.The formation processes for the gate dielectric layers 152 can include molecular beam deposition (MBD), ALD, PECVD, and the like. In embodiments where sections of the dummy gate dielectrics 116 remain in the recesses 148, the gate dielectric layers 152 comprise a material of the dummy gate dielectrics 116 (e.g., SiO2).

[0051] The gate electrodes 154 are deposited over the gate dielectric layers 152 and fill the remaining portions of the recesses 148. The gate electrodes 154 can be made of a metal-containing material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. The gate electrodes 154 can, for example, have any number of lining layers 154A, any number of output function tuning layers 154B, and a filler material 154C. After the recesses 148 are filled, a planarization process such as CMP can be performed to remove the excess portions of the gate dielectric layers 152 and the gate electrode material 154, with the excess portions located above the top surface of the ILD 146.The remaining material sections of the gate electrodes 154 and the gate dielectric layers 152 therefore form exchange gates of the resulting transistors. The gate electrodes 154 and the gate dielectric layers 152 can together be referred to as a "gate stack".

[0052] The formation of the gate dielectric layers 152 in the n and p regions can occur simultaneously, so that the gate dielectric layers 152 in each region are formed from the same materials, and the formation of the gate electrodes 154 can also occur simultaneously, so that the gate electrodes 154 in each region type are formed from the same materials. In some embodiments, the gate dielectric layers 152 in each region type can be formed by different processes, so that the gate dielectric layers 152 can be made of different materials, and / or the gate electrodes 154 in each region can be formed by different processes, so that the gate electrodes 154 can be made of different materials. Various masking steps can be used to mask and expose suitable regions when using different processes.

[0053] The Fig. 13 and Fig. Figure 14 illustrates an exchange gate process. In other embodiments, the exchange gate process can be omitted and the dummy gate electrodes 118 and the dummy gate dielectrics 116 can be used as the functional gate electrode and gate dielectric layers of the resulting transistor.

[0054] In Fig. In Figure 15, a second ILD 156 is deposited over the first ILD 146. In one embodiment, the second ILD 156 is a flowable film formed by a flowable CVD process. In some embodiments, the second ILD 156 is formed from a dielectric such as PSG, BSG, BPSG, USG, or the like, and can be deposited by any suitable process such as CVD and PECVD. According to some embodiments, prior to the formation of the second ILD 156, the gate stack (including a gate dielectric layer 152 and a corresponding overlying gate electrode 154) is optionally recessed, such that a recess is formed directly above the gate stack and between opposing sections of the gate spacer elements 124, as shown in Figure 15. Fig. Figure 15 illustrates this. A gate mask 155, comprising one or more layers of dielectric material such as silicon nitride, silicon oxynitride, or the like, is filled into the recess, followed by a planarization process to remove excess sections of the dielectric extending over the first ILD 146. The subsequently formed gate contacts 158 penetrate the gate mask 155 to contact the upper surface of the recessed gate electrode 154.

[0055] As also in Fig.As illustrated in Figure 15, the gate contacts 158 and the source / drain contacts 160 are formed through the second ILD 156 and the first ILD 146 according to some embodiments. Openings for the source / drain contacts 160 are formed through the first and second ILDs 146 and 156, and openings for the gate contact 110 are formed through the second ILD 156 and the gate mask 155. The openings can be formed using acceptable photolithography and etching techniques. A lining such as a diffusion barrier, an adhesive layer, or the like, and a conductive material are formed in the openings. The lining can be titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material can be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like.A planarization process such as a CMP can be performed to remove excess material from a surface of the ILD 156. The remaining lining and conductive material form the source / drain contacts 160 and the gate contacts 158 in the openings. An annealing process can be performed to form a silicide at the interface between the epitaxial source / drain regions 142 and the source / drain contacts 160. The source / drain contacts 160 are physically and electrically coupled to the epitaxial source / drain regions 142, and the gate contacts 158 are physically and electrically coupled to the gate electrodes 106. The source / drain contacts 160 and the gate contacts 158 can be formed in different processes or in the same process.Although these are shown as being formed in the same cross-sections, it is understood that each of the source / drain contacts 160 and the gate contacts 158 can be formed in different cross-sections, which can prevent short-circuiting of the contacts.

[0056] Therefore, an embodiment device 100 is formed. The device can have FDSOI transistors with raised source / drain regions 142. The FDSOI transistors can be formed on an upper silicon layer 108 of an SOI substrate 102. To form the source / drain regions 142, the upper silicon layer 108 can be etched to define, for example, source / drain recesses 130 using a multiple etching process. The etching provides source / drain recesses 130 that allow the source / drain region 142 to extend deeper into the upper silicon layer 108, thereby reducing the parasitic resistance in the transistor and improving the electrical performance.Furthermore, at least approximately 1 nm (10 Å) to approximately 5 nm (50 Å) of the upper silicon 108 remains below the source / drain region 142, which advantageously provides a sufficiently thick upper silicon layer 108 to support the overlying features during subsequent processing steps. Therefore, manufacturing defects (e.g., SOI substrate cracking caused by a CTE mismatch between the upper silicon and the underlying buried oxide layer (BOX layer)) can be advantageously reduced.

[0057] In some embodiments, a method comprises forming a gate structure over a silicon-on-insulator (SOI) substrate, wherein the SOI substrate comprises: a base semiconductor layer; an insulator layer over the base semiconductor layer; and an upper semiconductor layer over the insulator layer; depositing a gate spacer layer over a top surface and along a side wall of the gate structure; etching the gate spacer layer to define a gate spacer on the side wall of the gate structure; after etching the gate spacer layer, etching a recess into the upper semiconductor layer using a first etching process; after the first etching process, extending the recess further into the upper semiconductor layer using a second etching process, wherein the first etching process differs from the second etching process; and, after the second etching process, forming a source / drain region in the recess.In some embodiments, the recess extends to a depth of less than 0.6 nm (6 Å) into the upper semiconductor layer after the first etching process and before the second etching process. In some embodiments, the recess extends to a depth of 1 nm (10 Å) to 10 nm (100 Å) into the upper semiconductor layer after the second etching process. In some embodiments, the thickness of the upper semiconductor layer below the recess after the second etching process is in the range of 1 nm (10 Å) to 5 nm (50 Å). In some embodiments, the thickness of the upper semiconductor layer below the recess after the second etching process is in the range of 2 nm (20 Å) to 3 nm (30 Å). In some embodiments, the second etching process is a fluorine-ozone mixed process (FOM).In some embodiments, the FOM process is a cyclic process, and each cycle of the FOM process comprises: oxidizing portions of the top semiconductor layer exposed by the recess using ozone to form an oxide region in the top semiconductor layer; and etching the oxide region using dilute hydrogen fluoride (dHF). In some embodiments, the second etching process is a dry etching process using a chlorine-containing gas. In some embodiments, the second etching process is a wet etching process using H3PO4. In some embodiments, the etching of the gate spacer layer comprises a third etching process, wherein the third and first etching processes are both dry etching processes, and the third etching process is performed at a higher RF power than the first etching process.

[0058] In some embodiments, a method comprises forming a gate stack on a silicon-on-insulator (SOI) substrate, wherein the SOI substrate has an upper semiconductor layer on an insulator layer; forming a gate spacer element on a side wall of the gate stack; after forming the gate spacer element, etching the upper semiconductor layer to define a recess in the upper semiconductor layer; extending the recess further into the upper semiconductor layer using a fluorine-ozone mixing process (FOM process), wherein each cycle of the FOM process comprises: forming an oxide region in the upper semiconductor layer, the oxide region being located on side walls and a bottom surface of the recess; and etching the oxide region; and after the FOM process, growing a source / drain region in the recess.In some embodiments, the source / drain region extends from 1 nm (10 Å) to 10 nm (100 Å) into the upper semiconductor layer. In some embodiments, a portion of the upper semiconductor layer is located below the source / drain region and separates the source / drain region from the insulating layer, with the thickness of this portion of the upper semiconductor layer ranging from 1 nm (10 Å) to 5 nm (50 Å). In some embodiments, the thickness of this portion of the upper semiconductor layer ranges from 2 nm (20 Å) to 3 nm (30 Å).

[0059] In some embodiments, a device comprises a silicon-on-insulator (SOI) substrate, wherein the SOI substrate includes: a base semiconductor layer; an insulator layer above the base semiconductor layer; and an upper semiconductor layer above the insulator layer; a gate stack on the SOI substrate; a source / drain region on one side of the gate stack, wherein the source / drain region extends a first distance into the upper semiconductor layer, the first distance being in a range of 1 nm (10 Å) to 10 nm (100 Å), a portion of the upper semiconductor layer lies below the source / drain region and separates the source / drain region from the insulator layer, and the thickness of the portion of the upper semiconductor layer is in a range of 1 nm (10 Å) to 5 nm (50 Å). In some embodiments, the source / drain region extends over a top surface of the upper semiconductor layer.In some embodiments, the thickness of the upper semiconductor layer section is in the range of 2 nm (20 Å) to 3 nm (30 Å). In some embodiments, the first spacing is in the range of 2 nm (20 Å) to 3 nm (30 Å). In some embodiments, the first spacing is in the range of 1.7 nm (17 Å) to 2.5 nm (25 Å). In some embodiments, the device further comprises a gate spacer element on a side wall of the gate stack, wherein the gate spacer element is located between the source / drain region and the gate stack, and the source / drain region extends beneath the gate spacer element.

Claims

[1] Procedure, encompassing: Forming a gate structure (120) over a silicon-on-insulator substrate, SOI substrate (102), wherein the SOI substrate (102) has: a basic semiconductor layer (104); an insulating layer (106) over the base semiconductor layer (104); and an upper semiconductor layer (108) above the insulating layer (106); Deposition of a gate spacer layer (122) over a top surface and along a side wall of the gate structure (120); Etching (126) of the gate spacer layer (122) to define a gate spacer (124) on the side wall of the gate structure (120); after etching the gate spacer layer (122), etching (128) a recess (130) into the upper semiconductor layer (108) using a first etching process (128), wherein the recess (130) does not extend horizontally under the gate spacer (124); after the first etching process (128), extending the recess (130) further into the upper semiconductor layer (108) using a second etching process (132, 136), wherein the first etching process (128) differs from the second etching process (132, 136), wherein after the second process the recess (130) does not extend horizontally below the gate structure (120); and after the second etching process (132, 136), a source / drain region (142) is formed in the recess (130), wherein the source / drain region (142) extends horizontally above and below a lower tip of the gate spacer element (124) and touches it. [2] Method according to claim 1, wherein after the first etching process (128) and before the second etching process (136) the recess extends to a depth (D1) of less than 0.6 nm in the upper semiconductor layer (108). [3] Method according to claim 1, wherein the recess (130) extends to a depth (D2) of 1 nm to 10 nm in the upper semiconductor layer (108) after the second etching process (132, 136). [4] Method according to claim 1, wherein the thickness (T3) of the upper semiconductor layer (108) under the recess (130) after the second etching process (132, 136) is in a range of 1 nm to 5 nm. [5] Method according to claim 1, wherein the thickness (T3) of the upper semiconductor layer (108) under the recess (130) after the second etching process (132, 136) is in a range of 2 nm to 3 nm. [6] Method according to claim 1, wherein the second etching process is a fluorine-ozone mixing process, FOM process. [7] The method of claim 6, wherein the FOM process is a cyclic process, and wherein each cycle of the FOM process comprises: Oxidizing (132) sections of the upper semiconductor layer (108) exposed by the recess (130) using ozone to form an oxide region (134) in the upper semiconductor layer (108); and etching (136) the oxide region using dilute hydrogen fluoride, dHF. [8] Method according to claim 1, wherein the second etching process is a dry etching process using a chlorine-containing gas. [9] Method according to claim 1, wherein the second etching process is a wet etching process using H3PO4. [10] Method according to claim 1, wherein the etching (126) of the gate spacer layer comprises a third etching process, the third etching process and the first etching process (128) are each dry etching processes and the third etching process is carried out at a higher RF power than the first etching process (128). [11] Procedure, encompassing: Forming a gate stack (120) on a silicon-on-insulator substrate, SOI substrate (102), wherein the SOI substrate (102) has an upper semiconductor layer (108) on an insulator layer (106); Forming (126) a gate spacer element (124) on a side wall of the gate stack (120); after forming the gate spacer element (124), etching (128) the upper semiconductor layer (108) to define a recess (130) in the upper semiconductor layer (108), wherein the recess (130) does not extend horizontally below the gate spacer element (124); Extending the recess (130) further into the upper semiconductor layer (108) using a fluorine-ozone mixing process, FOM process (132, 136), wherein each cycle of the FOM process comprises: Forming (132) an oxide region in the upper semiconductor layer (108), wherein the oxide region is located on side walls and a lower surface of the recess (130); and Etching (136) of the oxide region; wherein the recess (130) does not extend horizontally below the gate stack (120) after the FOM process; and after the FOM process (132, 136), a source / drain region (142) grows in the recess (130), the source / drain region (142) extending horizontally above and below a lower tip of the gate spacer element (124) and touching it. [12] Method according to claim 11, wherein the source / drain region (142) extends to a distance of 1 nm to 10 nm into the upper semiconductor layer (108). [13] Method according to claim 11, wherein a section of the upper semiconductor layer (108) is located below the source / drain region (108) and separates the source / drain region (142) from the insulator layer (106) and a thickness (T3) of the section of the upper semiconductor layer (108) is in a range of 1 nm to 5 nm. [14] Method according to claim 13, wherein the thickness (T3) of the section of the upper semiconductor layer (108) is in a range of 2 nm to 3 nm.

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