Extended through-hole semiconductor structure, device and method

Abstract

Procedure, comprehensive: Formation of a first dielectric layer (410, 511) on a first conductive layer (212); Formation of a second dielectric layer (410, 512) on the first dielectric layer (511); Forming a conductive via (213) extending through the first dielectric layer (410, 511) and the second dielectric layer (410, 512); Forming a third dielectric layer (400, 513) on the second dielectric layer (512); and Forming at least one first conductive section (211) of an inductor (100) in the third dielectric layer (400, 513) and in direct contact with the conductive via (213), wherein the via (213) is electrically connected to the first conductive layer (212); and wherein the first conductive layer (212) is in direct contact with a conductive intermediate via (421) located in a dielectric layer (420); and wherein the conductive interlayer via (421) is in direct contact with a conductive feature (422) which is located in a further dielectric layer; wherein the conductive feature (422) is electrically connected to a metal bottom layer contact (482) located on a substrate (240), further comprising forming a second etch stop layer (505) between the second dielectric layer (512) and the third dielectric layer (400, 513); and Forming an antireflection layer (506) between the second etch stop layer (505) and the third dielectric layer (400, 513).

Description

GENERAL STATE OF THE ART

[0001] Inductors are building blocks for integrated circuits. An inductor manufactured in an integrated circuit process generally includes a conductive spiral coil, input and output traces, and pads, all formed at least partially in the topmost metal layer of an integrated circuit. One performance metric of inductors is a quality factor, or "Q factor." In radio frequency electronics, the Q factor can be thought of as a measure of signal selectivity, the ability to attenuate unwanted signals, particularly those adjacent to a desired frequency band, while simultaneously preserving signals in the desired frequency band. Increasing the Q factor improves signal selectivity and is an important objective in the design of inductors manufactured in integrated circuit processes.

[0002] US 2015 / 0 115 404 A1 relates to a semiconductor device structure comprising a metal-insulator-metal (MIM) capacitor formed on a substrate and an inductor formed on the MIM capacitor.

[0003] US 2020 / 0 144 358 A1 relates to a microelectronic component comprising a chip with terminals extending to a connection surface of the chip and first conductors extending along the connection surface, wherein at least a part of the first lateral conductors is electrically coupled to at least a part of the terminals.

[0004] US 2019 / 0 206 789 A1 relates to a semiconductor device comprising a substrate, a first wiring formed above the substrate, and a coil formed above the first wiring.

[0005] US 2006 / 0 158 302 A1 relates to a method for manufacturing an inductor comprising forming an induction pattern on a substrate and forming an insulation layer on the substrate containing the induction pattern.

[0006] DE 10 2018 124 689 A1 relates to a semiconductor structure comprising a substrate, a first conductive layer, a first conductive via and further conductive layers and conductive vias between the first conductive via and the substrate, wherein an inductor with a high quality factor is formed in the first conductive layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present disclosure are best understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of various features may be arbitrarily exaggerated or reduced for clarity of illustration. Fig. 1 is a plan view of an inductor according to some embodiments. Fig. 2 is a perspective view of adjacent bends of the inductor of Fig. 1 according to some embodiments. Fig. 3 is a circuit diagram of the inductor of Fig. 1 according to some embodiments. Fig. 4 is a cross-sectional diagram of a structure of the inductor of Fig. 1 according to some embodiments. Fig. 5a-5n are cross-sectional diagrams of a process for manufacturing the structure of Fig. 4 according to some embodiments. Fig. 6 is a flowchart of the method for manufacturing the conductive portion according to some embodiments. Fig. 7 is a circuit block diagram of a passive radio frequency device according to some embodiments. Fig. 8 is a circuit block diagram of an active radio frequency device according to some embodiments. Fig. 9 is a circuit block diagram of a voltage controlled oscillator device according to some embodiments. DETAILED DESCRIPTION

[0008] The invention is as defined in the independent claims. The dependent claims relate to corresponding developments. The following disclosure provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact.Additionally, the present disclosure may repeat reference numbers and / or letters throughout the various examples. This repetition is for simplicity and clarity and does not, in itself, establish a relationship between the various embodiments and / or configurations discussed.

[0009] Furthermore, spatial terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein for convenience to describe a relationship of one element or feature to one or more other elements or features illustrated in the figures. The spatial terms are intended to encompass different orientations of the device in use or operation in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90 degrees or in other orientations), and the spatial descriptors used herein may also be interpreted accordingly.

[0010] The term "metal cap layer" may be used herein to refer to the metal layer of an IC chip (or simply "chip") that is most distal to a substrate of the chip and / or the metal layer of the chip over which no further metal layers are formed. The term "metal bottom layer" may be used herein to refer to the metal layer of the chip that is most proximal to the substrate and / or the metal layer of the chip that has no metal layer between it and the substrate. The term "metal interlayer" may be used herein to refer to any metal layer between the metal cap layer and the metal bottom layer.

[0011] The term "top conductive via" can be used here to refer to any conductive via in direct contact with the metal cap layer. The term "intermediate conductive via" can be used here to refer to any conductive via that does not have direct contact with the metal cap layer.

[0012] On-chip inductor quality factor correlates closely with various desirable performance metrics in IC design, including, but not limited to, radio frequency sideband rejection and voltage-controlled oscillator phase noise reduction. Substrate loss and self-resonance are two environmental challenges that impact designers' ability to produce on-chip inductors with high quality factors. An increase in oxide capacitance C ox, the capacitance between the inductor and the substrate over which it is formed effectively reduces both the substrate loss and the self-resonance. Oxide capacitance C ox is the oxide thickness t ox inversely proportional, which suggests that the quality factor can be increased by increasing the oxide thickness t ox of the inductor can be increased.

[0013] Various embodiments of integrated circuit structures and process flows that aim at increasing oxide thickness t ox with a view to reducing the substrate loss factor and self-resonance factor to increase the quality factor of on-chip inductors are described below. In some embodiments, oxide thickness t oxby passing a top conductive via through at least two dielectric layers. In some embodiments, the oxide thickness is increased by passing the top conductive via through at least one etch stop layer positioned between the at least two dielectric layers. The Q-factor for a 0.5 nano-Henry on-chip inductor is greater than about 22 using the structures and processes described herein.

[0014] Fig. 1 is a top view of an inductor circuit 10 according to some embodiments. The inductor circuit 10 is an on-chip inductor in a chip. The inductor circuit 10 is manufactured in an IC manufacturing process. The inductor circuit 10 is located on a substrate of the chip. In some embodiments, the substrate is a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped or undoped with a p-type or n-type dopant. In some embodiments, the substrate is a wafer, such as a silicon wafer. An SOI substrate generally includes a layer of semiconductor material formed on an insulating layer. In some embodiments, the insulating layer is a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is provided on a substrate, typically a silicon or glass substrate.In some embodiments, a multilayer or gradient substrate is used. In some embodiments, the semiconductor material of the substrate includes silicon and / or germanium. In some embodiments, the semiconductor material is a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. In some embodiments, the substrate is an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP. Combinations of the above materials may be used as the substrate in some embodiments.

[0015] The substrate generally includes integrated circuit devices (not shown). In some embodiments, the integrated circuit devices include transistors, diodes, capacitors, resistors, the like, or combinations thereof formed in and / or on the substrate. The integrated circuit devices may be formed using suitable methods.

[0016] The inductor circuit 10 includes an inductor 100 having a suitable shape or architecture. In some embodiments, the inductor 100 may be a symmetrical or generally symmetrical spiral inductor 100 with an octagonally shaped coil (or simply "coil") 130. A first trace 141 and a first pad 142 and a second trace 143 and a second pad 144 provide an input and output connection for an electrical signal to the coil 130. In some embodiments, a first guard ring segment 110 and a second guard ring segment 120 partially surround the spiral inductor 100, as shown in Fig. 1. In some embodiments, the first guard ring segment 110 and / or second guard ring segment 120 may be omitted. In some embodiments, the coil 130 is at least partially formed in the metal cap layer of the chip. Forming the coil 130 in the metal cap layer may reduce parasitic capacitances that generally contribute to the distance or "oxide thickness" (t ox ) between the coil and the substrate over which the coil is formed are inversely proportional.

[0017] Throughout the specification, reference to inductor circuit 10 is not limited to the symmetrical spiral inductor architecture shown in Fig. 1. Other inductor architectures, including at least asymmetric spiral inductors, can be used as inductor 100 in inductor circuit 10 in various embodiments, and the techniques described for improving an inductor's Q-factor are applicable to the other inductor architectures without planning significant modifications. Symmetric spiral inductors generally offer a trade-off between lower self-resonant frequency versus higher inductance, higher Q-factor, and lower series resistance.

[0018] Other inductor shapes, including at least hexagonal, square, or circular, may be used in various embodiments as the inductor 100 in the inductor circuit 10, and the techniques described for improving the inductor Q-factor are applicable to the other inductor shapes without planning significant modifications. While circular inductors have a favorable Q-factor, few or no semiconductor manufacturing processes support shapes that employ curved sides. Square inductors are generally more compact, easy to manufacture, and have higher inductance for a given area, but suffer from a lower Q-factor. Octagonal and hexagonal inductors achieve a desired balance between manufacturability, Q-factor, and inductance. Again, each of the shapes benefits from applying the Q-factor improving techniques described herein.Other examples of a substantially closed geometric structure would include a frame-within-a-frame structure (square or rectangular) or other polygonal spiral structure, an irregularly shaped spiral structure, nested parallelogram or polygon structures, and the like.

[0019] In some embodiments, inductor circuit 10 has a Q factor greater than about 21, greater than about 22, greater than about 23, or greater than about 24. In some embodiments, inductor circuit 10 has an inductance less than about 1 nanohenry, less than about 0.5 nanohenry, or less than about 0.1 nanohenry. A lower inductance may be desirable to achieve a higher operating frequency.

[0020] The spiral inductor 100 of inductor circuit 10 has a coil 130, a first track 141, a first pad 142, a second track 143 and a second pad 144.

[0021] The first coil segment 131 of coil 130 is a first outer ring segment of coil 130. In some embodiments, the first coil segment 131 has at least 3 bends, at least 4 bends, or at least 5 bends. A "bend," as described herein, may refer to a change in direction of a segment of coil 130. A circular inductor would therefore have an infinite number of bends, and a polygonal inductor would have a finite number of bends. In some embodiments, the first coil segment 131 is formed monolithically with the first trace 141. In some embodiments, the first coil segment 131 is electrically connected to the first trace 141 by a conductive via.

[0022] The second coil segment 132 is an inner ring segment of coil 130. In some embodiments, the second coil segment 132 has at least 4 bends, at least 6 bends, or at least 8 bends. In some embodiments, the second coil segment 132 is monolithically formed with the first coil segment 131 and / or the first track 141 or electrically connected thereto by a conductive via.

[0023] The third coil segment 133 is a first bridge segment electrically connected to the first coil segment 131 and the second coil segment 132. In some embodiments, the third coil segment 133 is monolithically connected to the first coil segment 131 and the second coil segment 132 or electrically connected to them through a conductive via.

[0024] The fifth coil segment 135 is a second outer ring segment of coil 130. In some embodiments, the fifth coil segment 135 has at least 3 bends, at least 4 bends, or at least 5 bends. In some embodiments, the fifth coil segment 135 is formed monolithically with the second track 143. In some embodiments, the fifth coil segment 135 is electrically connected to the second track 143 by a conductive via.

[0025] The fourth coil segment 134 is a second bridge segment electrically connected to the fifth coil segment 135 and the second coil segment 132. The fourth coil segment 134 traverses under the third coil segment 133 and is electrically insulated from the third coil segment 133. In some embodiments, the fourth coil segment 134 is formed in at least one metal interlayer.

[0026] The sixth coil segment 136 is a first inter-metal connection region that partially overlaps the second coil segment 132 and the fourth coil segment 134. In some embodiments, the sixth coil segment 136 includes one or more conductive vias and one or more metal contacts extending from the second coil segment 132 to the fourth coil segment 134. The sixth coil segment 136 establishes an electrical connection between the second coil segment 132 and the fourth coil segment 134.

[0027] The seventh coil segment 137 is a second inter-metal connection region that partially overlaps the fifth coil segment 135 and the fourth coil segment 134. In some embodiments, the seventh coil segment 137 includes one or more conductive vias and one or more metal contacts extending from the fifth coil segment 135 to the fourth coil segment 134. The seventh coil segment 137 establishes an electrical connection between the fifth coil segment 135 and the fourth coil segment 134.

[0028] In some embodiments, the first pad 142, the first trace 141, the first coil segment 131, the third coil segment 133, the second coil segment 132, the fifth coil segment 135, the second trace 143, and the second pad 144 ("the segments") are formed in the metal cap layer of the chip. In some embodiments, the segments are further formed in at least one intermediate metal layer and / or the bottom metal layer, with the metal layers included in the segments connected by conductive vias. Forming the segments in more than one metal layer reduces the series resistance of the spiral inductor 100 by effectively increasing a cross-sectional area of ​​the current path through the spiral inductor 100 (resistance is inversely proportional to cross-sectional area), which is desirable in some circuit applications.

[0029] In some embodiments, one of the first pad 142, the first trace 141, the first coil segment 131, the third coil segment 133, the second coil segment 132, the fifth coil segment 135, the second trace 143, and the second pad 144 includes at least one top conductive via extending from the metal cap layer through at least two dielectric layers. Each top conductive via in the spiral inductor 100 is a single continuous structure. In some embodiments, formation of top conductive vias is achieved using no more than one electroless copper plating step.

[0030] The first guard ring segment 110 and the second guard ring segment 120 form a guard ring around the coil 130. The guard ring attenuates radio frequency noise emitted by the coil 130. This attenuation protects nearby circuits that might be susceptible to such electromagnetic interference generated by the coil 130.

[0031] Fig. 2 is a perspective view of adjacent bends of the inductor of Fig. 1 according to some embodiments. Fig. 3 is a circuit diagram of the inductor of Fig. 1 according to some embodiments. Two metal layers are in Fig. 2 for ease of illustration. Other embodiments may include more than two metal layers.

[0032] The inductor section 20 includes a substrate 240 and a dielectric layer 230 on a first side of substrate 240. Portions of the first coil segment 131 and second coil segment 132 are shown in Fig. 2, as well as front and side sections. Equivalent circuit components, including inductance 330, resistance 331, capacitance 332, capacitance 340, resistance 350, and capacitance 360, are shown in the perspective view in Fig. 2 shown one above the other for ease of description.

[0033] The equivalent circuit 30 shown in Fig. 3 is a summarized pi-type physical model for approximating the electrical behavior of on-chip inductors, such as spiral inductor 100.

[0034] Inductance 330 represents the series inductance of spiral inductor 100. A first terminal of inductance 330 is electrically connected to a first terminal of capacitance 332, a first terminal of capacitance 340, and a first interface terminal 310. A second terminal of inductance 330 is electrically connected to a first terminal of resistor 331.

[0035] Resistor 331 represents the series resistance of spiral inductor 100. A first terminal of resistor 331 is electrically connected to the second terminal of inductor 330. A second terminal of resistor 331 is electrically connected to a second terminal of capacitor 332, a first terminal of capacitor 341, and a second interface terminal 320.

[0036] Capacitance 332 represents series capacitance of spiral inductor 100. Capacitance 332 generally represents a model for capacitive coupling in spiral inductor 100. One type of capacitive coupling is in Fig. 2 between first coil segment 131 and second coil segment 132. It is generally assumed that the total capacitive coupling, represented by capacitance 332, is dominated by the crossover of the third coil segment 133 and fourth coil segment 134 of coil 130, as in Fig. 1. A first terminal of capacitance 332 is electrically connected to the first interface terminal 310, the first terminal of inductance 330, and the first terminal of capacitance 340. A second terminal of capacitance 332 is electrically connected to the second terminal of resistor 331, the first terminal of resistor 341, and the second interface terminal 320.

[0037] Capacitance 340 and capacitance 341 represent the oxide capacitance of spiral inductor 100, which is distributed at the first interface terminal 310 and the second interface terminal 320, respectively. The oxide capacitance of spiral inductor 100 is generally represented in the model as uniformly distributed: C ox1 = C ox2 = C ox . Capacitance 340 and capacitance 341 represent capacitance of dielectric layer 230 between first coil segment 131 and substrate 240 and second coil segment 132 and substrate 240, respectively.

[0038] Resistor 350 and resistor 351 represent, as a model, resistance from substrate 240 from dielectric layer 230 to bias terminal 370, corresponding resistance from the second terminal of capacitor 340 to bias terminal 370 and from the second terminal of capacitor 341 to bias terminal 370, respectively. Capacitance 360 ​​and capacitance 361 represent capacitance from substrate 240 from dielectric layer 230 to bias terminal 370, corresponding capacitance from the second terminal of capacitor 340 to bias terminal 370 and from the second terminal of capacitor 341 to bias terminal 370, respectively. Resistor 350 and resistor 351 are generally represented in the model as being evenly distributed: R sub1 = R sub2 = R sub . Capacity 360 and capacity 361 are generally represented in the model as evenly distributed: C sub1 = C sub2 = C sub .

[0039] Q-factor of spiral inductor 100 is approximated by the equivalent circuit 30 as: Q=ωLsRs×RpRp+[(ωLsRs)2]Rs×[1−Rs2(Ci+Cp)Ls−ω2Ls(Ci+Cp)] Rp=1ω2Cox2Rsub+Rsub(Cox+Csub)2Cox2 Cp=Cox1+ω2(Cox+Csub)CsubRsub21+ω2(Cox+Csub)2Rsub2

[0040] The middle term of (1) denotes what is generally known as the substrate loss factor, which is a number less than one, approaching one, since parasitic R p dominates the second term in the denominator. Parasitic resistance R p is expanded as (2). From (2) Rp is obtained by lowering C ox increased. Increased R p increases the substrate loss factor closer to one, which improves the Q-factor.

[0041] The third term of (1) denotes what is generally known as the self-resonance factor, which is also a loss factor less than one. Parasitic capacitance C pis expanded as (3). The natural resonance factor is increased when C p is lowered. (3) becomes C p reduced if C ox is reduced.

[0042] C ox is generally obtained by: Cox=12lwεoxtox

[0043] From (4) is C ox to the inductor area lw and oxide dielectric constant ε ox directly proportional and inversely proportional to the oxide thickness t ox . Increased oxide thickness t ox lowers C ox, thereby reducing the substrate loss factor and the self-resonance factor, thereby increasing the Q-factor. "Oxide thickness" generally refers to the thickness of oxide or other suitable dielectric between spiral inductor 100 and the substrate. Oxide thickness can be measured as the distance between a surface of spiral inductor 100 proximal to the substrate and the substrate itself. A measure of oxide thickness according to various embodiments is described in Fig. 4, marked with “t ox “.

[0044] Using an extended (e.g. higher or deeper) upper conductive via effectively increases the oxide thickness t ox by increasing the distance between the inductor 100 and the substrate. To improve the inductor quality factor and the overall device performance, in some embodiments the oxide thickness t oxby passing an upper conductive via through at least two dielectric layers. In some embodiments, the oxide thickness is further increased by passing the upper conductive via through at least one etch stop layer disposed between the at least two dielectric layers.

[0045] Structure 210 and structure 220, each of which has such an upper conductive via, are shown in Fig. 2. Positioning of via 213, a top conductive via, under the first metal line 211 and second metal line 212 of the first coil segment 131 is shown in Fig. 2 shown. Fig. 5q shows structure 210 according to at least one embodiment. In some embodiments, the first coil segment 131 includes at least ten, at least one hundred, or more structures 210 distributed within the first coil segment 131. Structure 220 is included within the second coil segment 132. Structure 220 is highlighted to illustrate, at a conceptual level, positioning of via 223 under third metal line 221 and fourth metal line 222 of the second coil segment 132. In some embodiments, the second coil segment 132 includes at least ten, at least one hundred, or more structures 220 distributed within the second coil segment 132. In some embodiments, structures similar to structure 210 or structure 220 are included in the first pad 142, the first track 141, the third coil segment 133, the fifth coil segment 135, the second track 143, and / or the second pad 144.

[0046] In some embodiments, an array of structures 210 or structures 220 is distributed throughout spiral inductor 100, with each structure 210 or structure 220 having a width of about 0.1 micrometers to about 10 micrometers, a length of about 0.1 micrometers to about 10 micrometers, and the array having a pitch / spacing of about 0.1 micrometers to about 10 micrometers. Other embodiments may have a greater or lesser length, width, and / or array pitch / spacing. In some embodiments, structures 210 or structures 220 are non-uniformly distributed throughout one or more regions of spiral inductor 100 or inductor circuit 10.

[0047] The via 213 is a top conductive via. The via 213 is in direct contact with the first metal line 211 and in direct contact with the second metal line 212. In some embodiments, the via 213 is or contains a metal such as tungsten, copper, aluminum, gold, silver, alloys thereof, the like, or a combination thereof, and may be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), electroplating, electroless plating, or another suitable method.

[0048] The via 223 is a top conductive via. The via 223 is in direct contact with the third metal line 221 and in direct contact with the fourth metal line 222. In some embodiments, the via 223 is or contains a metal, such as tungsten, copper, aluminum, gold, silver, alloys thereof, the like, or a combination thereof, and may be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), electroplating, electroless plating, or another suitable method.

[0049] Various embodiments of IC structures and process flows directed toward increasing oxide thickness with a view to reducing substrate loss factor and self-resonance factor to increase the quality factor of an on-chip inductor are described below. In some embodiments, the oxide thickness is increased by passing a top conductive via through at least two dielectric layers to increase the distance between the inductor 100 and the substrate. In some embodiments, the oxide thickness is increased by extending the top conductive via through at least one etch stop layer positioned between the at least two dielectric layers. The Q-factor for a 0.5 nanohenry on-chip inductor is greater than about 22 using the structures and processes described herein.

[0050] Fig. 4 is a diagram of a conductive stack 40 according to some embodiments. The stack 40 is illustrated with metal features 211, 212, 422, 432, 442, 452, 462, 472, 482, dielectric layers 400, 410, 415, 420, 425, 430, 435, 440, 445, 450, 455, 460, 465, 470, 475, 480, 485, substrate 240, and conductive vias 213, 421, 431, 441, 451, 461, 471, 481 from a metal bottom layer, through various metal interlayers to a metal cap layer. Seven metal interlayers are shown in Fig. 4. In some embodiments, fewer or more metal interlayers are used.

[0051] Seventeen dielectric layers are in Fig. 4. For the sake of clarity, intermediate functional layers containing etch stop layers, anti-reflection layers and the like are shown in Fig. 4 not shown. In some embodiments, one or more functional layers are included between one or more of the dielectric layers. In some embodiments, the dielectric layer 410 comprises at least dielectric layers 511, 512 and functional layers 501, 502, 503, which in Fig. 5n. In some embodiments, dielectric layers 420, 430, 440, 450, 460, 470, 480 each have a thickness less than the thickness of dielectric layer 410. In some embodiments, dielectric layers 420, 430, 440, 450, 460, 470, 480 have a thickness of less than 700 nm.

[0052] Conductive feature 482 is a metal bottom layer contact in dielectric layer 485. Via 481 is a metal bottom layer via in dielectric layer 480 and directly contacts conductive feature 482. Via 481 and dielectric layer 485 are located on substrate 240. In some embodiments, there is no intervening metal layer between the surface of conductive feature 482 facing substrate 240 and substrate 240.

[0053] Conductive feature 472 is a first interlayer contact in dielectric layer 475. Conductive feature 472 is in direct contact with via 481. Conductive features 462, 452, 442, 432, 422 and second metal line 212 are conductive features of the second, third, fourth, fifth, sixth, and seventh interlayers, respectively. In some embodiments, conductive features 432, 442, 452, 462, and 472 have substantially the same thickness. In some embodiments, the conductive feature 422 has substantially the same thickness as the second metal line 212. In some embodiments, the thickness of conductive features 432, 442, 452, 462, 472 differs from the thickness of the conductive feature 422 and the second metal line 212. In some embodiments, the conductive feature 422 and the second metal line 212 are thicker than conductive features 432, 442, 452, 462, 472.The second metal line 212 and the conductive features 422, 432, 442, 452, 462, 472, 482 are or include at least one conductive material. In some embodiments, the at least one conductive material is or includes a metal, such as tungsten, copper, aluminum, gold, silver, alloys thereof, the like, or a combination thereof, and may be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), electroplating, electroless plating, or another suitable method.

[0054] Via 471 is a first interlayer via in dielectric layer 470. Via 471 is in direct contact with conductive feature 472 and conductive feature 462. Via 461 is a second interlayer via in direct contact with conductive feature 462 and conductive feature 452. Via 451 is a third interlayer via in direct contact with conductive feature 452 and conductive feature 442. Via 441 is a fourth interlayer via in direct contact with conductive feature 442 and conductive feature 432. Via 431 is a fifth interlayer via in direct contact with conductive feature 432 and conductive feature 422.Via 421 is a sixth interlayer via in direct contact with conductive feature 422 and second metal line 212. In some embodiments, vias 421, 431 have substantially the same thickness. In some embodiments, vias 441, 451, 461, 471, 481 have substantially the same thickness. In some embodiments, the thickness of vias 441, 451, 461, 471, 481 differs from the thickness of vias 421, 431. In some embodiments, vias 421, 431 are thicker than vias 441, 451, 461, 471, 481.

[0055] The via 213 is a top conductive via. The thickness of the via 213 is Fig. 4 marked with "t". The thickness of the via 213 is greater than the thickness of any conductive intermediate via between the surface of the via 213 facing the substrate 240 and the substrate 240.

[0056] In some embodiments, the thickness of the via 213 is greater than about 800 nm. In some embodiments, the thickness of the via 213 is in a range from about 800 nm to about 3000 nm. Below 800 nm, the via 213 may not be thick enough to provide sufficient power handling capacity and may also introduce excess intermetallic capacitance between the first metal line 211 and the second metal line 212. Forming the via 213 through a single oxide layer with a thickness greater than 3000 nm may have an adverse effect on process uniformity when etching an opening to the via 213 through the single oxide layer in which the via 213 is formed.

[0057] In some embodiments, the via 213 is extended by at least two dielectric layers 410 to further increase the oxide thickness by further increasing the distance between the inductor 100 and the substrate. The use of two dielectric layers separated by an etch stop layer enables a thicker via 213 while avoiding adverse effects on process uniformity by etching the two dielectric layers in two separate etch operations. In some embodiments, the thickness of the via 213 extending through at least two dielectric layers is in a range of about 1600 nm to 6000 nm. In some embodiments, the via 213 has a thickness of about 4800 nm. The via 213 having a thickness much greater than 800 nm effectively increases t ox , whereby C oxreduced and the quality factor is increased. Additional dielectric layers and etch stop layers can be introduced to further increase the thickness of the via 213. The via 213 with an excessive thickness can introduce undesirable stress on the lower metal layers, which can lead to delamination.

[0058] Fig. 5a to Fig. 5q are diagrams showing intermediate semiconductor structures illustrating a method for fabricating structure 210 of Fig. 2 and Fig. 4 according to some embodiments. Fig. 6 is a flow diagram of the method for manufacturing structure 210 according to some embodiments. Fig. 5a to Fig. 5j generally refer to formation of the via 213. Fig. 5k to Fig. 5n generally refer to the formation of a first metal line 211.

[0059] In Fig. 5a, the second metal line 212 is provided. In some embodiments, the second metal line 212 is a contact or a trace in a metal interlayer. In some embodiments, the formation of the second metal line 212 is achieved at least by defining a feature in a lithography process, removing dielectric material to form an opening substantially corresponding to the feature, depositing or plating a conductive material in and over the opening, and planarizing and / or polishing the conductive material and the dielectric layer.In some embodiments, the at least one conductive material is or includes a metal, such as tungsten, copper, aluminum, gold, silver, alloys thereof, the like, or a combination thereof, and may be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), electroplating, electroless plating, or another suitable method. In some embodiments, a barrier seed layer is formed in the opening prior to depositing or plating the conductive material in the opening.

[0060] Fig. Figure 5b shows a semiconductor intermediate structure after performing operation 600 of the flowchart 60 shown in Fig. 6 is shown. In Fig. 5b, functional layer 501 is formed on the second metal line 212. In some embodiments, functional layer 501 is a first functional layer. In some embodiments, functional layer 501 is a first etch stop layer. For example, as shown in Fig. 6, operation 600 may include forming functional layer 501 by depositing a first etch stop layer (ESL1). Generally, an etch stop layer (ESL) provides a mechanism for stopping an etch process when forming conductive features, such as contacts or vias. An ESL may be formed from a dielectric material having a different etch selectivity than adjacent layers or components. In some embodiments, functional layer 501 includes silicon nitride, silicon carbon nitride, silicon carbon dioxide, carbon nitride, silicon carbide, the like, or a combination thereof, deposited by a suitable deposition process. In some embodiments, the thickness of functional layer 501 is in a range of about 30 nm (300 angstroms) to 100 nm (1000 angstroms).In some embodiments, the functional layer 501 is formed from silicon carbide and has a thickness of approximately 75 nm (750 angstroms). It may be advantageous to use a thick functional layer 501 both to avoid the formation of pores in the functional layer 501 and to limit the thickness of the via 213 and the oxide thickness t. ox An excessively thick functional layer 501 may increase the etching time and volume of etchant consumed to etch through the functional layer 501.

[0061] Fig. Figure 5c shows a semiconductor intermediate structure after performing operation 601 of Fig. 6. In Fig. 5c, the functional layer 502 is formed on functional layer 501. In some embodiments, 502 is a second functional layer. In some embodiments, the functional layer 502 is a second etch stop layer similar to the first etch stop layer. For example, as shown in Fig. 6, process 601 may include forming functional layer 502 by depositing a second etch stop layer (ESL2). In some embodiments, functional layer 502 includes or is silicon nitride, silicon carbon nitride, silicon carbon dioxide, carbon nitride, silicon carbide, the like, or a combination thereof, deposited by a suitable deposition process on functional layer 501. In some embodiments, the thickness of functional layer 502 is in a range of about 30 nm (300 angstroms) to 100 nm (1000 angstroms). In some embodiments, functional layer 502 is formed of the same material as functional layer 501. In some embodiments, functional layer 502 is formed of silicon carbide and has a thickness of about 75 nm (750 angstroms).It may be advantageous to use a thick functional layer 502 both to avoid the formation of pores in the functional layer 502 and to increase the thickness of the via 213 and oxide thickness t. ox An excessively thick functional layer 502 may increase the etching time and volume of etchant consumed when etching through the functional layer 502.

[0062] Fig. Figure 5d shows a semiconductor intermediate structure after performing operation 602 of Fig. 6. In Fig. 5d, the dielectric layer 511 is formed on the functional layer 502. In some embodiments, the dielectric layer 511 is a first dielectric layer. In some embodiments, the dielectric layer 511 is formed from a dielectric material deposited on the functional layer 502 by a suitable deposition process. In some embodiments, the dielectric material may include or be silicon dioxide, a low-k dielectric material (e.g., a material with a lower dielectric constant than silicon dioxide), silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), fluorinated silicate glass (FSG), organosilicate glasses (OSG), SiOxCy, spin-on glass, spin-on polymers, silicon carbon material, a compound thereof, a composite thereof, the like, or a combination thereof. As shown, for example, in Fig. 6, process 602 may include forming a dielectric layer 511 by depositing a first oxide layer (OX1). In some embodiments, the thickness of the dielectric layer 511 is in a range from about 400 nm to about 3000 nm. In some embodiments, the thickness of the dielectric layer 511 is in a range from about 2000 nm to about 3000 nm. In some embodiments, the dielectric layer 511 is formed of USG and has a thickness of about 2500 nm. A thicker dielectric layer 511 is advantageous to reduce the thickness of the via 213 and oxide thickness t ox An excessively thick dielectric layer 511 requires more time and material in production and can also affect process uniformity.

[0063] Fig. Figure 5e shows a semiconductor intermediate structure after performing operation 603 of Fig. 6. In Fig. 5e, functional layer 503 is formed on the dielectric layer 511. In some embodiments, functional layer 503 is a third functional layer. In some embodiments, functional layer 503 is a third etch stop layer. For example, as shown in Fig. 6, operation 603 may include forming the functional layer 503 by depositing a third etch stop layer (ESL3). In some embodiments, the functional layer 503 is formed of a dielectric material. In some embodiments, the functional layer 503 includes or is silicon nitride, silicon carbon nitride, silicon carbon dioxide, carbon nitride, silicon carbide, the like, or a combination thereof, deposited by a suitable deposition process onto the dielectric layer 511. In some embodiments, the thickness of the functional layer 503 is in a range of about 20 nm (200 angstroms) to 100 nm (1000 angstroms). In some embodiments, the functional layer 503 is formed of a different material than the first and second etch stop layers. In some embodiments, the functional layer 503 is formed of silicon nitride and has a thickness of about 50 nm (500 angstroms).It may be advantageous to use a thick functional layer 503 both to avoid the formation of pores in the functional layer 503 and to increase the thickness of the via 213 and oxide thickness t. ox An excessively thick functional layer 503 may increase the etching time and volume of etchant consumed when etching through the functional layer 503.

[0064] Fig. Figure 5f shows a semiconductor intermediate structure after performing operation 604 of Fig. 6. In Fig. 5f, the dielectric layer 512 is formed on the functional layer 503. In some embodiments, the dielectric layer 512 is a second dielectric layer. In some embodiments, the dielectric layer 512 is deposited on the functional layer 503 by a suitable deposition process. In some embodiments, the dielectric layer 512 is formed from a dielectric material. In some embodiments, the dielectric layer 512 contains or is silicon dioxide, a low-k dielectric material, silicon oxynitride, PSG, BSG, BPSG, USG, FSG, OSG, SiOxCy, spin-on glass, spin-on polymers, silicon carbon material, a compound thereof, a composite thereof, the like, or a combination thereof. For example, as shown in Fig. 6, process 604 may include forming a dielectric layer 512 by depositing a second oxide layer (OX2). In some embodiments, the thickness of the dielectric layer 512 is in a range from about 400 nm to about 3000 nm. In some embodiments, the thickness of the dielectric layer 512 is greater than about 500 nm, greater than about 1000 nm, greater than about 2000 nm, or greater than about 30 nm. In some embodiments, the dielectric layer 512 is formed of a same material as the dielectric layer 511. In some embodiments, the dielectric layer 512 is formed of USG and has a thickness of about 2600 nm. In some embodiments, the dielectric layer 512 is formed of USG and has a thickness of about 2500 nm. A thicker dielectric layer 512 is advantageous to reduce the thickness of the via 213 and oxide thickness t oxAn excessively thick dielectric layer 512 consumes more time and material in production and can also impair process uniformity. The combination of dielectric layers 511, 512 and functional layer 503 allows for a greater thickness of the via 213 while splitting the etching of the dielectric layers 511, 512 into two separate processes, which can improve uniformity and yield.

[0065] Fig. Figure 5g shows a semiconductor intermediate structure after performing operation 605 of Fig. 6. In Fig. 5g, the functional layer 504 is formed on the dielectric layer 512. In some embodiments, the functional layer 504 is a fourth functional layer. In some embodiments, the functional layer 504 is a first anti-reflection layer. For example, as shown in Fig. 6, operation 605 may include forming a functional layer 503 by depositing a first anti-reflective layer (AR1). The first anti-reflective layer is used to mitigate reflections from underlying layers that reflect light used in a subsequent lithographic process. In some embodiments, the functional layer 504 includes or is silicon oxide, silicon oxycarbide, silicon oxynitride, hydrocarbon-containing silicon oxide, silicon nitride, titanium nitride, tantalum nitride, titanium-containing material, tantalum-containing material, an organic material, or a combination thereof. In some embodiments, the functional layer 504 includes or is a nitrogen-free material, such as a nitrogen-free oxide. In some embodiments, the functional layer 504 includes or is a nitrogen-free silicon oxycarbide.The functional layer 504 is deposited on the dielectric layer 512 by any suitable technique, such as CVD, plasma-enhanced CVD (PECVD), high-density plasma CVD (HDP-CVD), spin-on coating processes, or the like. In some embodiments, the thickness of the functional layer 504 is in a range of about 30 nm (300 angstroms) to 100 nm (1000 angstroms). In some embodiments, the functional layer 504 is formed of silicon oxynitride and has a thickness of about 60 nm (600 angstroms). The thickness of the functional layer 504 can be chosen to be sufficiently thick to avoid pores and provide a uniform anti-reflection function, while also being sufficiently thin to account for material and deposition costs of the layer, as well as etchant material and time costs for etching the layer, and slurry material and time costs for planarizing / removing the layer.

[0066] Fig. Figure 5h shows a semiconductor intermediate structure formed after performing operation 606 of Fig. 6 is formed. In operation 606, opening 541 is formed. Opening 541 is formed by functional layer 504, dielectric layer 512, functional layer 503, dielectric layer 511, functional layer 502, and functional layer 501. Opening 541 may be formed using a patterned photoresist layer defining an opening structure, followed by a suitable etching process. For example, as shown in Fig. As shown in Figure 6, process 606 may include forming an opening 541 by at least a first lithography process and at least a first etch process (litho+etch 1). Then, the patterned photoresist layer is removed using a suitable stripping process. Opening 541 exposes a portion of the top surface of the second metal line 212 to provide an electrical connection.

[0067] Fig. Figure 5i shows a semiconductor intermediate structure after performing operation 607 of Fig. 6. In Fig. 5i, a conductive pin 531 is formed in the opening 541 and on the functional layer 504. For example, as in Fig. 6, operation 607 may include forming a conductive stud 531 through a first electroless copper plating process (ECP 1). The conductive stud 531 substantially fills the removed portions of the functional layer 504, dielectric layer 512, functional layer 503, dielectric layer 511, functional layer 502, and functional layer 501 that have opening 541 and directly contacts the second metal line 212. In some embodiments, 531 is formed from at least one conductive material. In some embodiments, the at least one conductive material is or includes a metal, such as tungsten, copper, aluminum, gold, silver, alloys thereof, the like, or a combination thereof, and may be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), electroplating, electroless plating, or another suitable method.In some embodiments, the conductive pin 531 is formed using a dual damascene process. In some embodiments, the plating process is an electroless copper plating (ECP) process. In some embodiments, the electroless copper plating process is preceded by forming a seed layer on sidewalls of the removed portions. In some embodiments, the seed layer is a barrier seed layer.

[0068] Fig. Figure 5j shows a semiconductor intermediate structure after performing operation 608 of Fig. 6. In Fig. 5j, the conductive pin 531 is planarized and / or polished to form the first metal line 211. For example, as shown in Fig. 6, operation 608 may include polishing and / or planarizing the conductive pin 531 by a first chemical mechanical polishing (CMP) process. In some embodiments, after the conductive pin 531 has been formed and filled into the opening 541, a chemical mechanical polishing (CMP) process removes excess material of the conductive pin 531 and any remaining masks, such as functional layer 504, such that a top surface of the conductive pin 531 is substantially coplanar with a top surface of the dielectric layer 512, as shown in Fig. 5j. In some embodiments, the thickness of the dielectric layer 512 is reduced by about 20% after performing operation 608. The thickness of the dielectric layer 512 may be reduced by less than about 20% if sufficient planarity can be achieved while polishing away less material of the dielectric layer 512.

[0069] Fig. 5k shows a semiconductor intermediate structure after performing operation 609, operation 610, operation 611 and operation 612 of Fig. 6. Operation 609 includes forming the functional layer 505. In some embodiments, the functional layer 505 is a fifth functional layer. In some embodiments, the functional layer 505 is an etch stop layer. For example, as shown in Fig. 6, operation 609 may include forming functional layer 505 by depositing a fourth etch stop layer (ESL4). In some embodiments, functional layer 505 is formed of a dielectric material. In some embodiments, functional layer 505 includes or is silicon nitride, silicon carbon nitride, silicon carbon dioxide, carbon nitride, silicon carbide, the like, or a combination thereof, deposited by a suitable deposition process on functional layer 512 and conductive via 213. In some embodiments, the thickness of functional layer 505 is in a range of about 20 nm (200 angstroms) to 100 nm (1000 angstroms). In some embodiments, functional layer 505 is formed of a different material than the first and second etch stop layers. In some embodiments, the functional layer 505 is formed of silicon nitride and has a thickness of about 50 nm (500 angstroms).It may be advantageous to use a thick functional layer 505 to avoid the formation of pores in the functional layer 505. An excessively thick functional layer 505 may increase the etching time and volume of etchant consumed when etching through the functional layer 505.

[0070] Process 610 of flowchart 60 of Fig. 6 includes forming the functional layer 506. In some embodiments, functional layer 506 is a sixth functional layer. In some embodiments, functional layer 506 is an anti-reflection layer deposited on functional layer 505. For example, as shown in Fig. 6, operation 610 may include forming the functional layer 506 by depositing a second anti-reflective layer (AR2). In some embodiments, the functional layer 506 is formed from a dielectric material. In some embodiments, the functional layer 506 includes or is silicon oxide, silicon oxycarbide, silicon oxynitride, hydrocarbon-containing silicon oxide, silicon nitride, titanium nitride, tantalum nitride, titanium-containing material, tantalum-containing material, an organic material, or a combination thereof. In some embodiments, the functional layer 506 includes or is a nitrogen-free material, such as a nitrogen-free oxide. In some embodiments, the functional layer 506 includes or is a nitrogen-free silicon oxycarbide.The functional layer 506 is deposited on the functional layer 505 using any suitable technique, such as CVD, plasma-enhanced CVD (PECVD), high-density plasma CVD (HDP-CVD), spin-on deposition, or the like. In some embodiments, the thickness of the functional layer 506 is in a range of approximately 20 nm (200 angstroms) to 100 nm (1000 angstroms). In some embodiments, the functional layer 506 is formed of silicon oxynitride and has a thickness of approximately 60 nm (600 angstroms). The thickness of the functional layer 506 can be chosen to be sufficiently thick to avoid pores and to provide a uniform anti-reflection function, while also being sufficiently thin to account for material and deposition costs of the layer, as well as etchant material and time costs for etching the layer and slurry material and time costs for planarizing / removing the layer.

[0071] Process 611 includes forming the dielectric layer 513. In some embodiments, the dielectric layer 513 is a third dielectric layer deposited on the functional layer 506. In some embodiments, the dielectric layer 513 includes or is silicon dioxide, a low-k dielectric material, silicon oxynitride, PSG, BSG, BPSG, USG, FSG, OSG, SiOxCy, spin-on glass, spin-on polymers, silicon carbon material, a compound thereof, a composite thereof, the like, or a combination thereof. For example, as in Fig. 6, process 611 may include forming dielectric layer 513 by depositing a third oxide layer (OX3). In some embodiments, the thickness of dielectric layer 513 is in a range from about 400 nm to about 3000 nm. In some embodiments, the thickness of dielectric layer 513 is greater than about 500 nm, greater than about 1000 nm, greater than about 2000 nm, greater than about 3000 nm, or greater than about 4000 nm. In some embodiments, dielectric layer 513 is formed of USG and has a thickness of about 3800 nm. The thickness of dielectric layer 513 may be equal to or slightly greater than the desired thickness of the metal capping layer. Excessive thickness of dielectric layer 513 increases planarization time and consumed materials, e.g., slurry, to achieve the desired thickness of the metal capping layer.An excessively thick metal top layer can cause undesirable stress, which may lead to delamination in the intermediate or metal bottom layer(s).

[0072] 612 includes forming the functional layer 507. In some embodiments, the functional layer 507 is a seventh functional layer deposited on the dielectric layer 513. In some embodiments, the functional layer 507 is an anti-reflection layer. For example, as shown in Fig. 6, operation 612 may include forming the functional layer 507 by depositing a third anti-reflective layer (AR3). In some embodiments, the functional layer 507 includes or is silicon oxide, silicon oxycarbide, silicon oxynitride, hydrocarbon-containing silicon oxide, silicon nitride, titanium nitride, tantalum nitride, titanium-containing material, tantalum-containing material, an organic material, or a combination thereof. In some embodiments, the functional layer 507 includes or is a nitrogen-free material, such as a nitrogen-free oxide. In some embodiments, the functional layer 507 includes or is a nitrogen-free silicon oxycarbide. The functional layer 507 is deposited on the functional layer 507 by any suitable technique, such as CVD, plasma-enhanced CVD (PECVD), high-density plasma-CVD (HDP-CVD), spin-on coating process, or the like.In some embodiments, the thickness of the functional layer 507 is in a range of approximately 20 nm (200 angstroms) to 100 nm (1000 angstroms). The thickness of the functional layer 507 can be chosen to be sufficiently thick to avoid voids and provide a uniform anti-reflection function, while also being sufficiently thin to account for the material and deposition costs of the layer, as well as the etchant material and time costs for etching the layer, and the slurry material and time costs for planarizing / removing the layer.

[0073] Fig. Figure 5l shows a semiconductor intermediate structure after performing operation 613 of Fig. 6. In operation 613, opening 542 is formed. Opening 542 is formed by functional layer 507, dielectric layer 513, functional layer 506, and functional layer 505. Opening 542 may be formed using a patterned photoresist layer defining an opening structure, followed by a suitable etching process. For example, as shown in Fig. As illustrated in Figure 6, process 613 may include forming opening 542 by at least a second lithography process and at least a second etch process (litho+etch 2). Then, the patterned photoresist layer is removed using a suitable stripping process. Opening 542 exposes a portion of the top surface of conductive via 213 to provide an electrical connection.

[0074] Fig. Figure 5m shows a semiconductor intermediate structure after performing operation 614 of Fig. 6. In Fig. 5m, the conductive pin 532 is formed in the opening 542 and on the functional layer 507. For example, as in Fig. 6, operation 614 may include forming the conductive stud 532 through a second electroless copper plating process (ECP 2). The conductive stud 532 substantially fills the removed portions of functional layer 507, dielectric layer 513, functional layer 506, and functional layer 505 that include the opening 542 and directly contacts the conductive via 213. In some embodiments, the conductive stud 532 is formed from at least one conductive material. In some embodiments, the at least one conductive material includes or is a metal, such as tungsten, copper, aluminum, gold, silver, alloys thereof, the like, or a combination thereof, and may be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), electroplating, electroless plating, or another suitable method.In some embodiments, the conductive pin 532 is formed using a dual damascene process. In some embodiments, the plating process is an electroless copper plating (ECP) process. In some embodiments, the electroless copper plating process is preceded by forming a seed layer on sidewalls of the removed portions. In some embodiments, the seed layer is a barrier seed layer.

[0075] Fig. 5n shows structure 210 after performing operation 615 of Fig. 6. In Fig. 5n is planarized and / or polished to form 110. For example, in Fig. 6, operation 615 may include polishing and / or planarizing the conductive post 532 by a second chemical mechanical polishing (CMP 2) process. In some embodiments, after the conductive post 532 has been formed and filled into opening 542, chemical mechanical polishing (CMP) removes any excess material of the conductive post 532 and any remaining mask, such as functional layer 507, to have a top surface of the conductive post 532 that is substantially coplanar with a top surface of the dielectric layer 513, as shown in Fig. 5n. In some embodiments, the thickness of dielectric layer 513 is reduced after performing operation 615.

[0076] Fig. 6 is above with reference to Fig. 5a to Fig. 5n. In some embodiments, the flowchart 60 contains more or fewer processes than in Fig. 6. In some embodiments, forming the functional layer 502, which corresponds to operation 601, is omitted. In some embodiments, operation 614 includes at least two electroless copper plating operations. In some embodiments, a bake operation is performed after operation 613 and before operation 614 and / or after operation 614 and before operation 615. Other embodiments may include further functional layer deposition operations and / or bakes.

[0077] Fig. Figure 7 is a circuit block diagram of a passive radio frequency device 70 according to some embodiments. In some embodiments, the passive radio frequency device 70 is a radio frequency identification (RFID) transceiver of an RFID tag. Any RFID tag that does not have an internal power supply is considered "passive." Passive RFID tags extract power from received radio frequency signals, typically from an RFID reader, and reuse the extracted power to transmit a response to the RFID reader.

[0078] Passive radio frequency device 70 may include port 720 for receiving radio frequency signals. In some embodiments, port 720 is electrically connected to or otherwise includes an antenna.

[0079] Port 730 of passive radio frequency device 70 is an output port for transmitting radio frequency signals. In some embodiments, port 730 includes an antenna. In some embodiments, port 730 and port 720 include the same antenna.

[0080] Circuitry 700 of passive radio frequency device 70 is electrically connected to terminal 720 and terminal 730. In some embodiments, circuitry 700 includes one or more of a modulator, a demodulator, a power recovery / extraction circuit, a clock, a control circuit, a processing circuit, an encoding circuit, a decoding circuit, or a memory.

[0081] The passive radio frequency device 70 includes an inductor circuit 10. In some embodiments, the inductor circuit 10 is used to receive the radio frequency signals. The inductor circuit 10 is electrically connected to the circuit 700. The inductor circuit 10 includes at least one via 213 in the dielectric layer 513 and a first metal line 211 that is substantially directly in contact with the via 213 and extends through the dielectric layer 511, dielectric layer 512, and functional layer 503. The inductor circuit 10 has an improved quality factor due to reduced C ox by increased thickness of the upper conductive via, as described above with respect to at least Fig. 3. The passive radio frequency device 70, which includes the inductor circuit 10, has improved sensitivity when receiving the radio frequency signals and also improved ability to reject unwanted radio frequency signals.

[0082] Fig. Figure 8 is a circuit block diagram of an active radio frequency device 80 according to some embodiments. In some embodiments, the active radio frequency device 80 is a radio frequency identification (RFID) transceiver of an RFID tag. Any RFID tag with an internal power supply is considered "active." Active RFID tags generally do not need to draw power from the received radio frequency signals, typically from an RFID reader, and use power from the internal power supply to send a response to the RFID reader. As such, while the active radio frequency device 80 may include many similar electronic components as the passive radio frequency device 70, the configuration of the electronic components in the active radio frequency device 80 may differ significantly from the configuration in the passive radio frequency device 70. As such, in Fig. 8 different reference symbols are used throughout.

[0083] Port 820 of active radio frequency device 80 is an input port for receiving radio frequency signals. In some embodiments, port 820 includes an antenna.

[0084] Port 830 of active radio frequency device 80 is an output port for transmitting radio frequency signals. In some embodiments, port 830 includes an antenna. In some embodiments, port 830 and port 820 include the same antenna.

[0085] Circuitry 800 of active radio frequency device 80 is electrically connected to terminal 820 and terminal 830. In some embodiments, circuitry 800 includes one or more of a modulator, a demodulator, a clock, a control circuit, a processing circuit, an encoding circuit, a decoding circuit, or a memory.

[0086] The power source 810 of the active radio frequency device 80 is electrically connected to the circuit 800. The power source 810 provides power to the circuit 800. In some embodiments, the power source 810 includes at least one battery. In some embodiments, the power source 810 includes a power management circuit.

[0087] The active radio frequency device 80 includes an inductor circuit 10. In some embodiments, the inductor circuit 10 is used to receive the radio frequency signals. The inductor circuit 10 is electrically connected to the circuit 800. The inductor circuit 10 includes at least one via 213 in the dielectric layer 513 and the first metal line 211 that is substantially in direct contact with the via 213 and extends through the dielectric layer 511, dielectric layer 512, and functional layer 503. The inductor circuit 10 has an improved quality factor due to the reduced C ox by the increased thickness of the upper conductive via, as described above with respect to at least Fig. 3. The active radio frequency device 80, which includes the inductor circuit 10, has improved sensitivity when receiving the radio frequency signals and also has improved ability to reject unwanted radio frequency signals.

[0088] Fig. 9 is a circuit block diagram of a voltage-controlled oscillator device 90 according to some embodiments. The voltage-controlled oscillator device 90 outputs a first clock at terminal 920 and a second clock at terminal 930, which is substantially the inverse of the first clock, both at a frequency controlled by a control voltage at terminal 970. The voltage-controlled oscillator device 90 of Fig. Figure 9 illustrates a voltage-controlled oscillator having an inductor circuit 10. In some embodiments, the inductor circuit 10 is used as an on-chip inductor in a voltage-controlled oscillator device that uses a different architecture than that described in Fig. 9 is shown.

[0089] Inverter 900 of voltage-controlled oscillator device 90 outputs a first output signal at terminal 930 that is substantially the inverse of the first clock at terminal 920. An input terminal of inverter 900 for receiving the first clock is electrically connected to an output terminal of inverter 910, a first terminal of inductor circuit 10, a first terminal of capacitor 940, and a first terminal of variable capacitor 950. An output terminal of inverter 900 for outputting the second clock is electrically connected to an input terminal of inverter 910, a second terminal of inductor circuit 10, a second terminal of capacitor 940, and a first terminal of variable capacitor 960.

[0090] Inverter 910 of voltage-controlled oscillator device 90 outputs the first clock at terminal 920, which is substantially the inverse of the second clock at terminal 920. An input terminal of inverter 910 for receiving the second clock is electrically connected to an output terminal of inverter 900, the second terminal of inductor circuit 10, the second terminal of capacitor 940, and the first terminal of variable capacitor 960. An output terminal of inverter 910 for outputting the first clock is electrically connected to the input terminal of inverter 900, the first terminal of inductor circuit 10, the first terminal of capacitor 940, and the first terminal of variable capacitor 950.

[0091] Inductor circuit 10, capacitor 940, variable capacitor 950, and variable capacitor 960 form a variable LC tank circuit tuned by the control voltage at terminal 970. The first terminal of inductor circuit 10 is electrically connected to the input terminal of inverter 900, the output terminal of inverter 910, the first terminal of capacitor 940, and the first terminal of variable capacitor 950. The second terminal of inductor circuit 10 is electrically connected to the output terminal of inverter 900, the input terminal of inverter 910, the second terminal of capacitor 940, and the first terminal of variable capacitor 960.

[0092] Inductor circuit 10 has at least one via 213 in the dielectric layer 513 and a first metal line 211 that is substantially in direct contact with the via 213 and extends through the dielectric layer 511, dielectric layer 512, and functional layer 503. The inductor circuit 10 has an improved quality factor, which improves the C ox by increasing the thickness of the upper conductive via, as above with respect to at least Fig. 3. The voltage-controlled oscillator device 90 exhibits improved phase noise due to the improved quality factor.

[0093] Capacitor 940 of the LC tank circuit is a fixed capacitor. In some embodiments, capacitor 940 is a metal-oxide-metal (MOM) capacitor, a metal-insulator-metal (MIM) capacitor, or the like. The first terminal of capacitor 940 is electrically connected to the input terminal of inverter 900, the first terminal of inductor circuit 10, the first terminal of variable capacitor 950, and the output terminal of inverter 910. The second terminal of capacitor 940 is electrically connected to the output terminal of inverter 900, the second terminal of inductor circuit 10, the first terminal of variable capacitor 960, and the input terminal of inverter 910.

[0094] The variable capacitor 950 of the LC tank circuit is a variable capacitor. In some embodiments, the variable capacitor 950 is a metal oxide semiconductor (MOS) capacitor. The first terminal of the variable capacitor 950 is electrically connected to the input terminal of the inverter 900, the first terminal of the inductor circuit 10, the first terminal of the capacitor 940, and the output terminal of the inverter 910. A second terminal of the variable capacitor 950 is electrically connected to a second terminal of the variable capacitor 960 and terminal 970.

[0095] The variable capacitor 960 of the LC tank circuit is a variable capacitor. In some embodiments, the variable capacitor 960 is a metal oxide semiconductor (MOS) capacitor. The first terminal of the variable capacitor 960 is electrically connected to the output terminal of the inverter 900, the second terminal of the inductor circuit 10, the second terminal of the capacitor 940, and the input terminal of the inverter 910. The second terminal of the variable capacitor 960 is electrically connected to the second terminal of the variable capacitor 950 and terminal 970.

[0096] Additionally, an IC device may include active devices located in or on the substrate 240 and interconnects that directly or indirectly couple at least one of the active device and the inductor 100. A complementary metal-oxide-semiconductor (CMOS) device and other active and / or passive devices may be included in an IC device and / or directly or indirectly coupled to the inductor 100. The inductor 100 may be advantageous in high-frequency applications of the IC device. Furthermore, implementation of the inductor 100 into existing manufacturing processes may be simple and cost-effective. For example, fabrication of the inductor 100 may be achieved by employing existing manufacturing techniques, as well as techniques developed in the future.In addition, one or more of the via 213 or the first metal line 211 may be formed simultaneously with other existing metallization layers, so that incorporating the inductor 100 into existing designs may not require additional process steps.

[0097] Various embodiments of IC structures and process flows that aim at increasing the oxide thickness t ox directed to reducing substrate loss factor and self-resonance factor to improve a quality factor of on-chip inductors are described. Further embodiments of devices that include both passive and active radio frequency identification (RFID) transceivers and a voltage-controlled oscillator (VCO) are also described. To improve the inductor quality factor and overall device performance in some embodiments, the oxide thickness t oxincreased by extending a top conductive via through at least two dielectric layers. In some embodiments, the oxide thickness is further increased by extending the top conductive via through at least one etch stop layer disposed between the at least two dielectric layers. The Q factor for a 0.5 nano-Henry on-chip inductor is greater than about 22 using the structures and processes described herein. Sensitivity of RFID transceivers or phase-noise VCOs is improved due to the inductor's excellent quality factor.

[0098] One embodiment of a device includes a substrate, a first conductive layer, a first conductive via, a plurality of second conductive layers, and a plurality of second conductive vias. The first conductive layer is located on the substrate. The first conductive via is located between the first conductive layer and the substrate and is electrically connected to the first conductive layer. The first conductive via has a thickness greater than about 8 nm. The plurality of second conductive layers are located between the first conductive via and the substrate. The plurality of second conductive vias are located between the first conductive via and the substrate.

[0099] One embodiment of a method includes forming a first dielectric layer on a first conductive layer. A second dielectric layer is formed on the first dielectric layer. A conductive via is formed extending through the first dielectric layer and the second dielectric layer. A third dielectric layer is formed on the second dielectric layer. At least a first conductive portion of an inductor is formed in the third dielectric layer and in direct contact with the conductive via.

[0100] Another embodiment of a device includes a first dielectric layer, a second dielectric layer, a first etch stop layer, a third dielectric layer, and an inductor. The second dielectric layer is located on the first dielectric layer. The first etch stop layer is located between the first dielectric layer and the second dielectric layer. The third dielectric layer is located on the second dielectric layer. The inductor includes a conductive trace in the third dielectric layer and a conductive via in substantially direct contact with the conductive trace and extending through the first dielectric layer, the second dielectric layer, and the first etch stop layer. The circuit is electrically coupled to the inductor.

Claims

[1] Method comprising: Forming a first dielectric layer (410, 511) on a first conductive layer (212); Forming a second dielectric layer (410, 512) on the first dielectric layer (511); Forming a conductive via (213) extending through the first dielectric layer (410, 511) and the second dielectric layer (410, 512); Forming a third dielectric layer (400, 513) on the second dielectric layer (512); and Forming at least a first conductive portion (211) of an inductor (100) in the third dielectric layer (400, 513) and in direct contact with the conductive via (213), wherein the via (213) is electrically connected to the first conductive layer (212); and wherein the first conductive layer (212) is in direct contact with a conductive interlayer via (421) located in a dielectric layer (420); and wherein the conductive interlayer via (421) is in direct contact with a conductive feature (422) located in another dielectric layer; wherein the conductive feature (422) is electrically connected to a metal bottom layer contact (482) located on a substrate (240), further comprising forming a second etch stop layer (505) between the second dielectric layer (512) and the third dielectric layer (400, 513); and Forming an anti-reflection layer (506) between the second etch stop layer (505) and the third dielectric layer (400, 513). [2] The method of claim 1, further comprising: Forming a first etch stop layer (503) between the first dielectric layer (410, 511) and the second dielectric layer (410, 512); wherein the conductive via (213) extends further through the first etch stop layer (503). [3] The method of any one of the preceding claims 1 or 2, further comprising forming a third etch stop layer (501) between the first conductive layer (211) and the first dielectric layer (410, 511). [4] The method of claim 3, further comprising forming a fourth etch stop layer (502) between the third etch stop layer (501) and the first dielectric layer (410, 511). [5] A method according to any one of the preceding claims 1 to 4, further comprising at least one of: Planarizing the conductive via (213); or Planarizing the first conductive section of the inductor (100). [6] Device comprising: a first dielectric layer (410, 511); a second dielectric layer (410, 512) on the first dielectric layer (410, 511); a first etch stop layer (503) between the first dielectric layer (410, 511) and the second dielectric layer (410, 512); a third dielectric layer (513) on the second dielectric layer (512); an inductor (100) comprising: a conductive path (211) in the third dielectric layer (513); and a conductive via (213) that is substantially in direct contact with the conductive trace (211) and extends through the first dielectric layer (511), the second dielectric layer (512) and the first etch stop layer (503); and a circuit (800) electrically coupled to the inductor (100) and configured to send or receive an electrical signal to or from the inductor (100); further comprising an anti-reflection layer (506) between the third dielectric layer (513) and the second dielectric layer (512). [7] The device of claim 6, wherein a thickness of the conductive via (213) is greater than about 800 nm. [8] The device of claim 7, wherein the inductor (100) has an inductance less than about 1 nano-henry. [9] The apparatus of claim 8, wherein the inductor (100) has a quality factor greater than about 23. [10] The device of any one of the preceding claims 6 to 9, further comprising a power source (810) electrically coupled to the circuit (800).

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