SEMICONDUCTOR DEVICES

Abstract

Semiconductor device, comprising: a substrate (100); conductive structures (104b) on the substrate (100), wherein the conductive structures (104b) are spaced apart from each other in a vertical direction perpendicular to a surface of the substrate (100) and an edge of the conductive structures (104b) has a step section such that an end of a conductive structure (104b) does not overlap with conductive structures (104b) arranged above it in the vertical direction; Insulation structures between the conductive structures (104b); Sidewall insulation structures (110) on sidewalls of the conductive structures (104b) to cover the sidewalls of the conductive structures (104b); upper pad structures (114) on top surfaces of the step section of the conductive structures (104b) and top surfaces of sections of the sidewall insulation structures (110); an insulating intermediate layer (118) covering the conductive structures (104b), the insulating structures (102b), the sidewall insulating structures (110) and the upper pad structures (114); and Contact plugs (142) extending through the insulating intermediate layer (118), wherein the contact plugs (142) each contact the upper pad structures (114), wherein the sides of the upper pad structures (114) facing the substrate (100) contact at least one section of the top surfaces of the side wall insulation structures (110), wherein one top surface of each of the upper pad structures (114) is not covered by each of the side wall insulation structures (110), and wherein at least the top surfaces of the upper pad structures (114) and at least side walls of the side wall insulation structures (110) directly contact the insulating intermediate layer (118).

Description

BACKGROUND 1. Area

[0001] The embodiments relate to semiconductor devices. 2. Description of the state of the art

[0002] More recently, a vertical storage device has been considered in which storage cells are stacked vertically from the surface of a substrate. Edge sections of the stacked conductive structures contained within the storage cells can have a step shape, and the top surfaces of the edge sections can each serve as pad structures. A contact plug can be formed on each of the pad structures.

[0003] US 2017 / 0271354A1 discloses: A semiconductor device comprising: a lower conductive pattern; a lower conductive memory chain pattern arranged above the lower conductive pattern; a stack of upper conductive memory chain patterns, the stack being arranged above the lower conductive memory chain pattern; a lower contact pad pattern extending from the lower conductive memory chain pattern; upper contact pad patterns each extending from the upper conductive memory chain patterns; a floating conductive pattern arranged below the lower contact pad pattern, the floating conductive pattern overlapping the lower contact pad pattern; and a contact connector that makes contact with the lower contact pad pattern and overlaps the floating conductive pattern.

[0004] US 2016 / 0218107A1 discloses: A semiconductor device comprises a stacked structure with first conductive layers that are stacked stepwise and first insulating layers that are arranged between the first conductive layers, with undercuts being formed under the first conductive layers and each of the first conductive layers comprising a first region covered by the first conductive layer and a second region extending from the first region, contact pads connected to the second regions of the respective first conductive layers, and an intermediate layer formed on the contact pads that fills the undercuts.

[0005] US 2016 / 0172296A1 discloses: A method for manufacturing a semiconductor device comprises forming a conductive pattern on a substrate, forming a filler insulating layer covering the conductive pattern, forming a contact hole in the filler insulating layer and adjacent to the conductive pattern, forming an opening in the conductive pattern by removing a portion of the conductive pattern adjacent to the contact hole so that the opening is connected to the contact hole, and forming a contact plug that fills the contact hole and the opening. The width of the opening is greater than the width of the contact hole. SUMMARY

[0006] The invention is set out in the accompanying claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The features will be apparent to the person skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which: Fig. 1 and Fig. 2 a cross-sectional view and a top view of a semiconductor device according to exemplary embodiments are; Fig. 3 is a cross-sectional view of a section of a pad structure in the semiconductor device; Fig. 4 to 15 cross-sectional views and top views of stages in a method for manufacturing a semiconductor device according to exemplary embodiments are shown; Fig. 16 and Fig. 17 a cross-sectional view and a top view of a semiconductor device according to exemplary embodiments are; Fig. 18 to 23 cross-sectional views and top views of stages in a method for manufacturing a semiconductor device according to exemplary embodiments are shown; Fig. 24 and Fig. 25 a cross-sectional view and a top view of a semiconductor device according to exemplary embodiments are; and Fig. Figures 26 to 31 show cross-sectional views and top views of stages in a method for manufacturing a semiconductor device according to exemplary embodiments. DETAILED DESCRIPTION

[0008] In the following, a direction that is substantially perpendicular to the top surface of the substrate is defined as a vertical direction. Two directions that are substantially parallel to the top surface of the substrate and intersect each other are defined as the first and second directions, respectively. In exemplary embodiments, the first and second directions may be substantially perpendicular to each other.

[0009] Fig. 1 and Fig. Figure 2 shows a cross-sectional view and a top view of a semiconductor device according to exemplary embodiments. Fig. Figure 3 is a cross-sectional view of a section of a pad structure in the semiconductor device.

[0010] With reference to the Fig. In examples 1 to 3, a substrate 100 can have a first region and a second region. The first region can be a cell region in which memory cells are arranged, and the second region can be a wiring region in which wiring is formed. In one implementation, the second region can be located on sides of the edges of the first region (for example, in the first direction). In an implementation such as in Fig. 1 and Fig. As illustrated in Figure 2, the second region can be located on one side of an edge of the first region. Furthermore, only a portion of the first region needs to be depicted in the drawing. In one implementation, the width in the first direction of the first region can be greater than the width in the first direction of the second region.

[0011] Substrate 100 can, for example, contain a semiconductor material such as silicon or germanium.

[0012] A lower insulating layer 101 can be located on the substrate 100. A conductor structure 106c can be located on the lower insulating layer 101.

[0013] The conductor track structure 106c can extend from the first region to the second region. The conductor track structure 106c can extend horizontally in the first direction to a surface of the substrate 100.

[0014] Several conductor track structures 106c can be spaced apart from each other in the second direction. An opening 134 can be located between the conductor track structures 106c. In one implementation, cell blocks can be divided by the opening 134. In this case, the opening 134 can be located between cell blocks.

[0015] First, the conductor track structure 106c in the first region can be described.

[0016] The conductive structure 106c in the first region can comprise alternately stacked conductive structures 104b and insulating structures 102b. In one implementation, the conductive structures 104b can be spaced apart vertically from a top surface of the substrate 100. In one implementation, each of the conductive structures 104b can have a line or rod shape extending in the first direction.

[0017] The top and bottom surfaces (for example, surfaces facing away from and towards the substrate 100) of the conductive structures 104b and the insulating structures 102b can be essentially flat.

[0018] In one implementation, the conductive structures 104b can have a first thickness t1 in the vertical direction. The insulating structures 102b can have a second thickness t2 in the vertical direction, which is less than the first thickness t1.

[0019] The conductive structures 104b can include a ground selection line (GSL), a string selection line (SSL), and word lines between the ground selection line and the string selection lines.

[0020] The conductive structures 104b may contain polysilicon.

[0021] The conductor track structure 106c in the second region can be described below.

[0022] An edge section or side of the conductor structure 106c in the second region may have a step shape. The conductor structure 106c in the second region may include the insulation structures 102b, the conductive structures 104b, the upper pad structures 114, and the sidewall insulation structures 110.

[0023] The insulating structures 102b and the conductive structures 104b of the conductor structure 106c in the second region can be extended from the insulating structures 102b and the conductive structures 104b of the conductor structure 106c in the first region (and can, for example, be continuous). In one implementation, the insulating structures 102b and the conductive structures 104b in the second region can have the same layer structure as the insulating structures 102b and the conductive structures 104b in the first region. In one implementation, each of the insulating structures 102b can be located vertically between the conductive structures 104b, so that the conductive structures 104b can be vertically spaced from each other by the insulating structures 102b. The conductive structures 104b can extend (for example, longitudinally) in the first direction.

[0024] Furthermore, the edges of the insulating structures 102b and the conductive structures 104b in the second region can have a step shape. The insulating structure 102b that contacts a bottom surface (for example, the side facing the substrate 200) of one of the conductive structures 104b can have a length in the first direction that is greater than the length of the conductive structure 104b located on it. In one implementation, the insulating structure 102b that contacts the bottom surface of one of the conductive structures 104b can project in the first direction from or beyond one of the conductive structures 104b located on the insulating structure 102b.

[0025] In each of the conductive structures 104b in the second region, a section that does not overlap with the conductive structure 104b positioned above it (for example, the adjacent conductive structure 104b that is farther away from the substrate 100 in the vertical direction) can be designated as a step section. At least one section of the step section of each of the conductive structures 104b can serve as a lower pad structure 112. In one implementation, in each of the conductive structures 104b, a section that does not overlap with the conductive structures 104b and the sidewall insulation structures 110 positioned above them can be the lower pad structure 112.

[0026] The sidewall insulation structures 110 can each be located on the sidewalls of the conductive structures 104b. The sidewall insulation structures 110 can each cover sidewalls (for example, of each) of the conductive structures 104b. The sidewall insulation structures 110 can each be located on the insulation structures 102b.

[0027] The sidewall insulation structures 110 can contain an insulating material that exhibits (for example, high) etch selectivity with respect to the conductive structures 104b and the insulating structures 102b (for example, that can be etched at a different rate under the same etching conditions). In one implementation, the sidewall insulation structures 110 can, for example, contain a nitride such as silicon nitride.

[0028] In one implementation, a top surface (for example, a surface facing away from the substrate 100 in the vertical direction) of the sidewall insulation structure 110 and a top surface of the lower pad structure 112 can be essentially coplanar to each other. In another implementation, a bottom surface (for example, facing the substrate 100) of the sidewall insulation structure 110 can be essentially coplanar with a bottom surface of the lower pad structure 112, or the bottom surface of the sidewall insulation structure 110 can be lower than the bottom surface of the lower pad structure 112 (for example, closer to the substrate 100 in the third direction).

[0029] The upper pad structure 114 can cover at least one entire top surface of the lower pad structure 112. In one implementation, the upper pad structure 114 can be located on the top surfaces of the lower pad structure 112 and a portion of the sidewall insulation structure 110. In one implementation, an end portion of the upper pad structure 114 can project in the first direction from an end portion of the underlying lower pad structure 112 or beyond. In one implementation, the end portion of the upper pad structure 114 need not project in the first direction from an end portion of the underlying sidewall insulation structure 110 or beyond.

[0030] The upper pad structure 114 can contain silicon. In one implementation, the upper pad structure 114 can contain polysilicon. The upper pad structure 114 can contain silicon formed by epitaxial growth from the lower pad structure 112.

[0031] In one implementation, the top surface of the upper pad structure 114 can be lower (for example, closer to the substrate 100 in the vertical direction) than the top surface of the sidewall insulation structure 110, which is positioned above a layer of the upper pad structure 114. In another implementation, the thickness (in the vertical direction) of the upper pad structure 114 can be less than the thickness of a structure in which one of the conductive structures 104b and one of the insulation structures 102b are stacked. If the thickness of an upper pad structure is greater than that of the structure in which one of the conductive structures and one of the insulation structures are stacked, a bridging fault between adjacent upper pad structures could occur.

[0032] A structure in which one of the lower pad structures 112 and one of the upper pad structures 114 are stacked can serve as a pad structure 116. A contact plug 142 can be located on the pad structure 116. The vertical thickness of the pad structure 116 can be greater than the first thickness t1 of one of the conductive structures 104b.

[0033] In one implementation, the upper pad structure 114 can be formed on a topmost conductive structure 104b in the conductor structure 106c. In another implementation, the upper pad structure 114 can be formed on or at the top of the conductor structure 106c (which, for example, is furthest away from the substrate 100 in the vertical direction) on the first and second regions.

[0034] A first insulating intermediate layer 118 can cover the conductor track structure 106c. The top surface of the first insulating intermediate layer 118 can be essentially flat. The first insulating intermediate layer 118 can contain silicon oxide.

[0035] A channel structure 130 can pass through the conductor track structure 106c and the first insulating intermediate layer 118 in the first region, and the channel structure 130 can be electrically connected to the substrate 100.

[0036] Furthermore, in one implementation, a semiconductor structure 120 can be formed between the substrate 100 and the channel structure 130. The semiconductor structure 120 can, for example, contain single-crystal silicon or polysilicon.

[0037] The channel structure 130 can comprise a dielectric layer structure 122, a channel 124, a buried insulation structure 126, and an upper conductive structure 128. The channel 124 can have the shape of a hollow cylinder or a cup-shaped form. The channel 124 can contain polysilicon or monocrystalline silicon. The buried insulation structure 126 can fill an interior space of the channel 124. The dielectric layer structure 122 can surround an outer wall of the channel 124. The dielectric layer structure 122 can comprise a tunnel insulation layer, a charge storage layer, and a barrier layer, which are stacked sequentially on the outer wall of the channel 124. The upper conductive structure 128 can be formed on top of the buried insulation structure 126, and the upper conductive structure 128 can be electrically connected to the channel 124.

[0038] A second insulating intermediate layer 132 can be formed on top of the first insulating intermediate layer 118. The first and second insulating intermediate layers 118 and 132 can contain the same material, so that the first and second insulating intermediate layers 118 and 132 can be fused into a single insulating intermediate layer.

[0039] In one implementation, a second insulating structure 136 can fill the opening 134 between the conductive trace structures 106c. In another implementation, a common source trace can be formed through the second insulating structure 136 in the opening 134, and the common source trace can be connected to the substrate 100. The common source trace can be spaced apart from the conductive structures 104b by the second insulating structure 136.

[0040] The contact plugs 142 can pass through the first and second insulating intermediate layers 118 and 132, so that each contact plug 142 can contact the pad structures 116. In one implementation, each contact plug 142 can be electrically connected to the conductive structures 104b. In another implementation, the contact plug 142 can comprise a barrier metal structure and a metal structure.

[0041] The contact plugs 142 can each contact the upper pad structures 114. A bottom surface of the contact plug 142 can be located on a top surface or an inner section of a stacked structure in which the upper pad structure 114 and the lower pad structure 112 are stacked. In one implementation, the bottom surface of the contact plug 142 can be located on the top surface or an inner section of the pad structure 116. In another implementation, the bottom surface of the contact plug 142, which contacts the pad structure 116 positioned relative to an upper step (for example, a step located distal to the substrate 100 in the vertical direction), can be located on a lower inner section of the pad structure 116 (and can, for example, penetrate deeper into the pad structure 116).The underside of the contact plug 142, which contacts the pad structure 116, which is positioned relatively on a lower step (for example, a step which is located in the vertical direction near the substrate 100), can be located on an upper inner section or on the top of the pad structure 116 (and can, for example, penetrate the pad structure 116 at a shallower angle).

[0042] In one implementation, the thickness of a section (for example, a pad or a connection structure) where the underside of the contact plug 142 is positioned can be increased, thus increasing the process margin for the formation of the contact plug 142. In another implementation, defects of the contact plug 142 can be reduced. In yet another implementation, the lack of contact (for example, a break) between the contact plug 142 and the pad structure 116, or a punching defect (where the contact plug 142 extends into a conductive structure below a target pad structure), can be reduced.

[0043] A wiring conductor electrically connected to a top surface of the contact plug 142 can also be formed on the second insulating intermediate layer 132. In one implementation, the wiring conductor can have a linear form extending in the second direction. Wiring conductors electrically connected to the channel structures 130 can also be formed on the second insulating intermediate layer 132.

[0044] Fig. Figures 4 to 15 are cross-sectional views and top views of stages in a method for manufacturing a semiconductor device according to exemplary embodiments.

[0045] Fig. Figures 4 to 6, 8, 9, 11, 13 and 15 are cross-sectional views, and Fig. 7, Fig. 10, Fig. 12 and Fig. 14 are top views.

[0046] As in Fig. As shown in Figure 4, a lower insulating layer 101 can be formed on a substrate 100 that has a first and a second region. First conductive layers 104 and insulating layers 102 can be formed alternately and repeatedly on the lower insulating layer 101 to form a stacked structure. In one implementation, the lower insulating layer 101 and the insulating layers 102 can be formed from an oxide such as silicon oxide, silicon carbonate, or silicon oxyfluoride. In another implementation, the first conductive layers 104 can be formed from polysilicon.

[0047] In one implementation, the lower insulating layer 101, which is in direct contact with the substrate 100, can have a vertical thickness greater than the vertical thickness of any of the insulating layers 102 above it. In another implementation, each of the insulating layers 102 can have a thickness less than the thickness of any of the first conductive layers 104. Reducing the thickness of each of the insulating layers 102 will reduce the height of the stacked structure.

[0048] As in Fig. As shown in Figure 5, sections of the insulating layers 102 and the first conductive layers 104 can be etched to form a first temporary conductor structure 106a, which has a step shape at one edge section. The first temporary conductor structure 106a can comprise temporary conductive structures 104a and temporary insulating structures 102a, stacked alternately. The lower insulating layer 101 can remain on the surface of the substrate 100 by a previously defined thickness, so that the surface of the substrate 100 can be covered by the lower insulating layer 101. In one implementation, the surface of the substrate 100 adjacent to the first temporary conductor structure 106a is not exposed.

[0049] In one implementation, the edge section of the first temporary conductor structure 106a can have a step shape (which, for example, is stepped downwards in the first direction). In one implementation, the edge section of the first temporary conductor structure 106a can have a step shape in each of the first and second directions (which, for example, is stepped downwards).

[0050] A top surface of the temporary insulation structure 102a can be exposed at the step section of the first temporary conductor structure 106a. In one implementation, the temporary insulation structure 102a at the step section can have a thickness less than the thickness of the insulation layer 102 in the deposited form. In another implementation, the temporary insulation structure 102a positioned at the step section can have a thickness that is essentially the same as the thickness of the insulation layer 102 in the deposited form.

[0051] As in Fig. 6 and Fig. As shown in Figure 7, the temporary conductive structure 104a, exposed by a side wall of the first temporary conductive trace structure 106a, can be partially etched to form a conductive structure 104b. In one implementation, an undercut section 108, defined by the conductive structure 104b and the temporary insulating structure 102a positioned on and under the conductive structure 104b, can be formed by the etching process.

[0052] The etching process can be an isotropic etching process. In an implementation, the isotropic etching process can be a wet etching process or an isotropic dry etching process.

[0053] In one implementation, the width (in the first direction) of the undercut section 108 can be approximately 20 nm to approximately 50 nm. To increase the width of the undercut section in the first direction, the length (in the first direction) of the temporary conductive structure 104a can be increased. In this way, the width of the first temporary conductive structure 106a can be increased in the first direction. Maintaining the width of the undercut section 108 in the first direction at approximately 20 nm or more can help prevent bridging defects between the pad structures in a subsequent process. In one implementation, the width of the undercut section 108 in the first direction can be approximately up to approximately 30 nm.

[0054] As in Fig. As can be seen in Figure 8, a side wall insulation structure 110 can be formed to fill the undercut section 108.

[0055] In one implementation, the insulating layer can be conformally formed on a surface of the first preliminary conductor structure 106a to fill the undercut section 108. Subsequently, the insulating layer can be anisotropically etched to form the sidewall insulating structure 110.

[0056] The sidewall insulation structure 110 can comprise an insulating material with high etch selectivity with respect to the conductive structure 104b and the preliminary insulation structure 102a. In one implementation, the sidewall insulation structure 110 can be formed from a nitride such as silicon nitride.

[0057] As in Fig. 9 and Fig. As shown in Figure 10, the preliminary insulation structure 102a can be etched onto the step section of the first preliminary conductive trace structure 106a to form an insulation structure 102b. The etching process can expose a top surface of the step section of the conductive structure 104b and a top surface of the sidewall insulation structure 110. The etching process can include an anisotropic etching process. The sidewall insulation structure 110 can be formed on a sidewall of the conductive structure 104b.

[0058] In one implementation, the sidewalls of the sidewall insulation structure 110 and the sidewalls of the insulation structure 102b can correspond to a sidewall of the step section of the first temporary conductor structure 106a. In another implementation, the top surfaces of the conductive structure 104b and the sidewall insulation structure 110 can be exposed at the step section of the first temporary conductor structure 106a.

[0059] The lower insulating layer 101, which is in contact with the surface of the substrate 100, can retain a predefined thickness after the etching processes. In one implementation, the surface of the substrate 100 can be covered with the lower insulating layer 101.

[0060] In the first preliminary conductor structure 106a, a conductive structure 104b in the first region can serve as a gate structure, and a conductive structure 104b in the second region can be connected to the gate structure. In one implementation, a free-standing step section in the conductive structure 104b in the second region can serve as a lower pad structure 112.

[0061] As in Fig. 11 and Fig. As can be seen in Figure 12, an upper pad structure 114 can be formed on the lower pad structure 112 by a selective epitaxial growth process. The upper pad structure 114 can be formed by growing silicon using the lower pad structure 112 (which contains polysilicon) as a seed. In one implementation, the upper pad structure 114 can contain polysilicon. In another implementation, a second preliminary conductor structure 106b can be formed.

[0062] When the selective epitaxial growth process is performed, the upper pad structure 114 can be grown in a vertical and a lateral direction.

[0063] In one implementation, the upper pad structure 114 can be formed on a top surface of the lower pad structure 112 and a section of a top surface of the side wall insulation structure 110.

[0064] The top surface of the upper pad structure 114 can be lower than the top surface of the sidewall insulation structure 110 positioned above a plane of the upper pad structure 114 (and can, for example, be lower than the top surface of the sidewall insulation structure 110 that borders it laterally in the first direction). If the top surface of the upper pad structure 114 is higher than the top surface of the sidewall insulation structure 110 positioned above a plane, the upper pad structure 114 and the lower pad structure 112 positioned above it can contact each other.

[0065] A structure in which one of the lower pad structures 112 and one of the upper pad structures 114 are stacked can serve as a pad structure 116.

[0066] In one implementation, the upper pad structure 114 can be formed on a top conductive structure 104b (for example, furthest from the substrate 100 in the vertical direction) in the second temporary conductor structure 106b. In another implementation, the conductive structure 104b and the upper pad structure 114 can be stacked on a top surface of the second temporary conductor structure 106b in the first and second regions.

[0067] As in Fig. 13 and Fig. As shown in Figure 14, a first insulating intermediate layer 118 can be formed to cover the second preliminary conductor structure 106b.

[0068] In one implementation, an oxide layer such as silicon oxide, silicon carbonate, or silicon oxyfluoride can be formed on the second temporary conductor structure 106b, and a top surface of the oxide layer can be planarized to form the first insulating intermediate layer 118. The planarization process can include a chemical-mechanical polishing (CMP) process and / or a back-etching process.

[0069] Subsequently, channel holes, which expose the surface of the substrate 100, can be formed in the first region by the second temporary conductor structure 106b and the first insulating intermediate layer 118. Channel structures 130 can be formed in each of the channel holes. In one implementation, a semiconductor structure 120, which is in contact with the substrate 100, can also be formed under each of the channel structures 130.

[0070] In one implementation, a selective epitaxial growth process can be carried out on the substrate 100 exposed through the channel hole to form the semiconductor structure 120. The channel structure 130, comprising a dielectric layer structure 122, a channel 124, a buried insulating structure 126, and an upper conductive structure 128, can be formed on the semiconductor structure 120.

[0071] A second insulating intermediate layer 132 can be formed on top of the first insulating intermediate layer 118 to cover the channel structures 130.

[0072] The second temporary conductor structure 106b and the first and second insulating intermediate layers 118 and 132 can be anisotropically etched to form an opening 134 extending longitudinally in the first direction. In one implementation, cell blocks of the semiconductor device can be separated by the opening 134.

[0073] In one implementation, a second isolation structure 136 can be formed to fill the opening 134. In another implementation, a common source line connected to the substrate can be formed through the second isolation structure 136 in the opening 134. The common source line can be spaced away from the conductive structures 104b by the second isolation structure 136.

[0074] In one implementation, the second preliminary conductor structures 106b can be separated from each other, so that conductor structures 106c can be formed on the sides of the opening 134. The conductor structure 106c can extend in the first direction. The surface of the substrate 100 can be exposed through a bottom surface of the opening 134.

[0075] The conductor structure 106c in the first region can include the insulating structures 102b and the conductive structure 104b. The conductor structure 106c in the second region can include the insulating structures 102b, the conductive structures 104b, the upper pad structures 114, and the sidewall insulating structures 110.

[0076] As in Fig. As shown in Figure 15, the first and second insulating intermediate layers 118 and 132 can be etched to form contact holes 140, each exposing the pad structures 116. In one implementation, a bottom surface of each of the contact holes 140 can expose either the lower pad structure 112 or the upper pad structure 114.

[0077] In one implementation, the pad structures 116 have a stepped shape, and the vertical heights of the top surfaces of the pad structures 116 (relative to the substrate 100, for example) can differ. In one implementation, the contact hole 140 can be formed in the pad structure 116 positioned on an upper level before the contact hole 140 is formed in the pad structure 116 positioned on a lower level during the etching process. The pad structure 116 positioned on the upper level can be over-etched during the etching process. In one implementation, the pad structure 116 can comprise the stacked lower pad structure 112 and upper pad structure 114, and the pad structure 116 can have sufficient thickness. In one implementation, a punching defect, in which the underside of the contact hole 140 extends under or through the underside of the lower pad structure due to over-etching, can be reduced.

[0078] We return to Fig. 1 and Fig. 2. A conductive material can be formed in the contact holes 140 to form contact plugs 142.

[0079] In one implementation, a barrier metal layer can be conformally formed on the surfaces of the contact holes 140 and the second insulating intermediate layer 132, and a metal layer can be formed on the barrier metal layer. The metal layer and the barrier metal layer can be planarized until a top surface of the second insulating intermediate layer 132 is exposed to form the contact plugs 142.

[0080] Wiring leads that are electrically connected to a top surface of the contact plug 142 can also be formed on the second insulating intermediate layer 132. Additionally, wiring leads that are electrically connected to the channel structure 130 can also be formed on the second insulating intermediate layer 132.

[0081] Fig. 16 and Fig. Figure 17 shows a cross-sectional view and a top view of a semiconductor device according to exemplary embodiments.

[0082] The semiconductor device is essentially the same as the semiconductor device described with reference to the Fig. Sections 1 to 3 have been described, with the exception of one form of conductor structure in the second region. Therefore, duplicate descriptions can be omitted or only briefly described.

[0083] As in Fig. 16 and Fig. As can be seen in Figure 17, an edge section of the conductor structure 107b in the second region can have a step shape. The conductor structure 107b in the second region can include the insulating structures 102b, the conductive structures 105a, the upper pad structures 114a, and the sidewall insulating structures 150a. The insulating structures 102b and the conductive structures 105a in the conductor structure 107b in the second region can extend from the insulating structures 102b and the conductive structures 105a in the conductor structure 107b in the first region.

[0084] Edge sections of the insulation structures 102b and the conductive structures 105a in the second region can have a step shape. A step section of each of the conductive structures 105a can serve as a lower pad structure 112a. In one implementation, a section of each of the conductive structures 105a that does not overlap with the conductive structures 104b and the sidewall insulation structures 110 positioned above them can be the lower pad structure 112a.

[0085] The sidewall insulation structure 150a can be formed on a sidewall of the lower pad structure 112a. The sidewall insulation structure 150a can contain an insulating material that has high etch selectivity with respect to the conductive structure 105a. In one implementation, the sidewall insulation structure 150a can be formed from a nitride such as silicon nitride. In another implementation, the sidewall insulation structure 150a can contain silicon oxide. In yet another implementation, the sidewall insulation structure 150a can have a structure in which a silicon oxide layer and a silicon nitride layer are stacked.

[0086] The top surface of the sidewall insulation structure 150a on a sidewall of one of the conductive structures 105a can be higher than the top surface of the conductive structure 105a. In one implementation, the top surface of the sidewall insulation structure 150a on the sidewall of the adjacent conductive structure 105a can project beyond the top surface of one of the conductive structures 105a (and can, for example, project further from the substrate 100 in the vertical direction).

[0087] In one implementation, the width of the sidewall insulation structure 150a in the first direction can be less than approximately half the width of the step section of the conductive structure 105a in the first direction. In another implementation, the width of the sidewall insulation structure 150a in the first direction can be greater than the first thickness of the insulation structure 102b in the first region.

[0088] The upper pad structure 114a can cover at least one top surface of the lower pad structure 112a. The upper pad structure 114a can contain silicon. In one implementation, the upper pad structure 114a can contain polysilicon. The upper pad structure 114a can contain silicon formed by epitaxial growth from the lower pad structure 112a.

[0089] In one implementation, the top surface of the upper pad structure 114a can be coplanar with the top surface of the sidewall insulation structure 150a, or the top surface of the upper pad structure 114a can be lower than the top surface of the sidewall insulation structure 150a. In another implementation, the thickness of the upper pad structure 114a (for example, in the vertical direction) can be less than the thickness of the stacked structure comprising one of the conductive structures 105a and one of the insulation structures 102b.

[0090] In one implementation, the conductive structure 105a and the upper pad structure 114a can be stacked on a top surface of the conductor structure 107b. In one implementation, a top upper pad structure 114a can be located in the conductor structure 107b in either the first or the second region.

[0091] The first insulating layer 118 can cover the conductor track structure 107b. The channel structure 130, which is electrically connected to the substrate 100, can pass through the conductor track structure 107b and the first insulating layer 118 in the first region. The second insulating layer 132 can be formed on top of the first insulating layer 118.

[0092] The contact plugs 142, which extend through the first and second insulating intermediate layers 118 and 132, can each contact the pad structures 116a. The pad structure 116a can comprise the stacked lower pad structure 112a and upper pad structure 114a.

[0093] Fig. Figures 18 to 23 are cross-sectional views and top views of stages in a method for manufacturing a semiconductor device according to exemplary embodiments.

[0094] Fig. 18, Fig. 19, Fig. 21 and Fig. 23 are cross-sectional views, and Fig. 20 and Fig. 22 are top views.

[0095] As in Fig. 18. To see, processes can first be seen, such as those relating to the Fig. Figures 4 to 7 illustrate the steps to form the first temporary conductor structure 106a on the lower insulating layer. The first temporary conductor structure 106a can comprise the conductive structures 105a and the temporary insulating structure 102a, stacked alternately.

[0096] A spacer insulating layer 150 can be conformally formed on the first temporary conductor structure 106a and the lower insulating layer 101. A top surface of the spacer insulating layer 150, formed on at least one section of the step section of the first temporary conductor structure 106a, can be flat.

[0097] If the thickness of the spacer insulating layer 150 is large, a horizontal section of the subsequently formed upper pad structure can be reduced. In one implementation, the thickness of the spacer insulating layer 150 can be less than approximately half the width in the first direction of the step section in the first preliminary conductor structure 106a. If the thickness of the spacer insulating layer 150 is too small, a height of the subsequently formed upper pad structure can be reduced. In one implementation, the thickness of the spacer insulating layer 150 can be greater than a vertical thickness of each of the preliminary insulating structures 102a in the first region.

[0098] The spacer insulating layer 150 can contain an insulating material that has high etch selectivity with respect to the conductive structure 105a. In one implementation, the spacer insulating layer 150 can be formed from a nitride, such as silicon nitride. In another implementation, the spacer insulating layer 150 can be formed from silicon oxide. In yet another implementation, the spacer insulating layer 150 can have a structure in which a silicon oxide layer and a silicon nitride layer are stacked.

[0099] As in Fig. 19 and Fig. As can be seen in Figure 20, the spacer insulation layer 150 can be anisotropically etched to form the sidewall insulation structure 150a on a sidewall of the first preliminary conductor structure 106a.

[0100] The sidewall insulation structure 150a can help to protect the conductive structure 105a and the temporary insulation structure 102a of the step section in the first temporary conductor structure 106a.

[0101] Subsequently, the preliminary insulation structure 102a of the step section can be anisotropically etched into the first preliminary conductor track structure 106a next to the side wall insulation structure 150a to form an insulation structure 102b.

[0102] In one implementation, the conductive structure 105a can be exposed at the step section next to the sidewall insulation structure 150a. The step section in each of the conductive structures 105a can serve as a lower pad structure 112a.

[0103] The top surface of the sidewall insulation structure 150a on the sidewall of the conductive structure 105a can be higher (for example, further away from the substrate 100 in the vertical direction) than the top surface of the stepped section of the conductive structure. In one implementation, the top surface of the sidewall insulation structure 150a on the sidewall of the conductive structure 105a can project from or beyond the top surface of the stepped section of the conductive structure 105. In another implementation, a recess defined by the sidewall insulation structure 150a can be formed on the stepped section of the conductive structure 105.

[0104] As in Fig. 21 and Fig. As shown in Figure 22, a selective epitaxial growth process can be performed on the lower pad structure 112a to form the upper pad structure 114a. The upper pad structure 114a can be formed by growing silicon using the lower pad structure 112a, which contains polysilicon, as a seed. In one implementation, the upper pad structure 114a can contain polysilicon. By performing these processes, a second preliminary conductor structure 107a can be formed.

[0105] In one implementation, the upper pad structure 114a can be formed within the recess created by the sidewall insulation structure 150a. In another implementation, the top surface of the upper pad structure 114a can be coplanar with the top surface of the sidewall insulation structure 150a, or it can be lower than the top surface of the sidewall insulation structure 150a. If the top surface of the upper pad structure 114a is higher than the top surface of the sidewall insulation structure 150a, the upper pad structures could contact each other at different levels due to, or because of, excessive growth of the upper pad structure 114a.

[0106] In one implementation, the upper pad structure 114a can be formed on top of a top conductive structure 105a in the first temporary conductor structure 106a. In another implementation, the conductive structure 105a and the upper pad structure 114a can be stacked on top of the second temporary conductor structure 107a.

[0107] As in Fig. 23 can be seen, the same processes as in Fig. 13 and Fig. Figure 14 illustrates how the process is carried out to form the conductor track structure 107b, the channel structure 130, the first insulating intermediate layer 118, and the second insulating intermediate layer 132. Furthermore, the opening can be formed, and the insulating structure can be formed in the opening.

[0108] Referring again to the Fig. 16 and Fig. 17. The first and second insulating intermediate layers 118 and 132 can be etched to form contact holes, each exposing the pad structures 116a. In one implementation, a bottom surface of each of the contact holes can expose either the lower pad structure 112a or the upper pad structure 114a.

[0109] A conductive layer can be formed in the contact holes, and thus conductive plugs can be formed in the contact holes.

[0110] Fig. 24 and Fig. Figure 25 shows a cross-sectional view and a top view of a semiconductor device according to exemplary embodiments.

[0111] The semiconductor device can be essentially the same as the illustrated semiconductor device, which is related to the Fig. Sections 1 to 3 have been described, with the exception of one form of conductor structure in the second region. Therefore, duplicate descriptions can be omitted or only briefly described.

[0112] As in Fig. 24 and Fig. As shown in Figure 25, an edge section of a conductor track structure 107d in the second region can have a step shape.

[0113] The conductor track structure 107d in the second region can include the insulating structures 103a, the conductive structures 105a, the upper pad structure 114b, and a spacer insulating layer 160. The insulating structures 103a and the conductive structures 105a in the conductor track structure 107d in the second region can extend from the insulating structures 103a and the conductive structures 105a in the conductor track structure 107d in the first region. Edges of the conductive structures 105a in the second region can have a step shape. A section of the step of each of the conductive structures 105a can serve as a lower pad structure 112b.

[0114] The spacer insulation layer 160 can cover an area of ​​a structure in which the insulation structures 103a and the conductive structures 105a are stacked. The spacer insulation layer 160 can conformally cover a surface of the stepped section of the conductive structures 105a.

[0115] The spacer insulating layer 160 can contain an insulating material that has high etch selectivity with respect to the conductive structure 105a. In one implementation, the spacer insulating layer 160 can contain a nitride, such as silicon nitride. In another implementation, the spacer insulating layer 160 can contain silicon oxide.

[0116] In one implementation, the spacer insulating layer 160 can have a thickness of less than approximately half the width in the first direction of the step section of the conductor structure 107d. In another implementation, the thickness of the spacer insulating layer 160 can be greater than the vertical thickness of each of the insulating structures 103a in the first region.

[0117] The spacer insulation layer 160 can include holes 162 (see Fig. 27), which expose the step section of the conductive structures 105a. In one implementation, the holes 162 can pass through the spacer insulation layer 160 and the insulation structure 103a on the step section. The conductive structure 105a, exposed through a bottom surface of the hole 162, can serve as the bottom pad structure 112b.

[0118] The upper pad structure 114b can be formed in any of the holes 162. The upper pad structure 114b can contact the top of the conductive structure 105a. In one implementation, the upper pad structure 114b can be formed on top of the lower pad structure 112b.

[0119] The upper pad structure 114b can contain silicon. In one implementation, the upper pad structure 114b can contain polysilicon. The upper pad structure 114b can contain silicon formed by epitaxial growth from the lower pad structure 112b.

[0120] In one implementation, the upper pad structure 114b can fully fill or partially fill the hole 162. In another implementation, the top surface of the upper pad structure 114b can be coplanar with the upper entrance of the hole 162. In yet another implementation, the top surface of the upper pad structure 114b can be lower than the upper entrance of the hole 162.

[0121] In one implementation, the thickness of the upper pad structure 114b can be less than the thickness of a stacked structure consisting of a single conductive structure 105a and a single insulating structure 103a.

[0122] The upper pad structure 114b can cover a section of the top surface of the step section of the conductive structure 105a. The upper pad structure 114b on the top surface of the step section of the conductive structure 105a can have an isolated (for example, discontinuous) form. In one implementation, the upper pad structure 114b, which has the isolated form, can be stacked on top of the conductive structure 105a in the conductor structure 107d.

[0123] The first insulating layer 118 can cover the conductor track structure 107d. The channel structure 130 can pass through the conductor track structure 107d and the first insulating layer 118 in the first region, and the channel structure 130 can be electrically connected to the substrate 100. The second insulating layer 132 can be formed on top of the first insulating layer 118.

[0124] The contact plugs 142 can pass through the first and second insulating intermediate layers 118 and 132, and the contact plugs 142 can contact the pad structures 116b in which the lower pad structure 112b and the upper pad structure 114b are stacked.

[0125] Fig. Figures 26 to 31 are cross-sectional views and top views of stages in a method for manufacturing a semiconductor device according to exemplary embodiments.

[0126] Fig. 26, Fig. 27 and Fig. 29 are cross-sectional views, and Fig. 28, Fig. 30 and Fig. 31 are top views.

[0127] As in Fig. 26. The same processes can be seen first, as with reference to the Fig. Figures 4 to 7 illustrate the steps to form the first temporary conductor structure 106a on the lower insulating layer. The first temporary conductor structure 106a can comprise the conductive structures 105a and the temporary insulating structure 102a, stacked alternately.

[0128] A spacer insulating layer 160 can be conformally formed on the first temporary conductor structure 106a and the lower insulating layer 101. A top surface of the spacer insulating layer 160, formed on at least one section of the step section in the first temporary conductor structure 106a, can be flat.

[0129] If the thickness of the spacer insulating layer 160 is too great, a horizontal section of the subsequently formed upper pad structure can be reduced. In one implementation, the spacer insulating layer 160 can have a thickness of less than approximately half the width in the first direction of the step section in the first preliminary conductor structure 106a. If the thickness of the spacer insulating layer 160 is too small, a height of the subsequently formed upper pad structure can be reduced. In one implementation, the thickness of the spacer insulating layer 160 can be greater than the vertical thickness of each of the preliminary insulating structures 102a in the first region.

[0130] The spacer insulating layer 160 can contain an insulating material that has high etch selectivity with respect to the conductive structure 105a. In one implementation, the spacer insulating layer 160 can be formed from a nitride, such as silicon nitride. In another implementation, the spacer insulating layer 160 can be formed from silicon oxide.

[0131] As in Fig. 27 and Fig. As shown in Figure 28, the spacer insulating layer 160 on the step section in the first temporary conductor structure 106a and the underlying temporary insulating structure 102a can be etched to form holes 162. The temporary insulating structure 102a can be etched into the insulating structure 103a. A top surface of the conductive structure 105a can be exposed through a bottom surface of each of the holes 162. The conductive structure 105a exposed through the hole 162 can serve as the bottom pad structure 112b.

[0132] As in Fig. 29 and Fig. As shown in Figure 30, a selective epitaxial growth process can be performed on the lower pad structure 112b of the step section to form the upper pad structure 114b. The upper pad structure 114b can be formed by growing silicon using the lower pad structure 112b, which contains polysilicon, as a seed. In one implementation, the upper pad structure 114b can contain polysilicon. By performing these processes, the second preliminary conductor structure 107c can be formed.

[0133] In one implementation, the upper pad structure 114b can be formed in each of the holes 162. In one implementation, the upper pad structure 114b can either fully fill the hole 162 or partially fill the hole 162.

[0134] The upper pad structure 114b on the top of the step section of the conductive structure 105a can have an isolated form.

[0135] An upper pad structure 114b, which has the isolated form, can be formed on a topmost of the conductive structure 105a in the first preliminary conductor structure 106a.

[0136] As in Fig. 31 can be seen, the same processes as in Fig. 13 and Fig. Figure 14 illustrates the process used to form the conductor track structure 107d, the channel structure 130, the first insulating intermediate layer 118, and the second insulating intermediate layer 132. In one implementation, the opening 134 can be formed, and the second insulating structure 136 can be formed within the opening 134.

[0137] Referring again to the Fig. 24 and Fig.25. The first and second insulating intermediate layers 118 and 132 can be etched to form contact holes that expose the pad structure 116b, in which the lower pad structure 112b and the upper pad structure 114b are stacked. In one implementation, a bottom surface of each of the contact holes can expose either the lower pad structure 112b or the upper pad structure 114b.

[0138] A conductive layer can be formed in the contact holes, and thus conductive plugs 142 can be formed in the contact holes.

[0139] In the semiconductor device according to exemplary embodiments, defects in contact plugs associated with the conductive structures can be reduced. The semiconductor device can be used in various electronic products.

[0140] One or more embodiments can provide a vertical storage device.

[0141] One or more embodiments can provide a semiconductor device with fewer process defects.

[0142] In exemplary embodiments, the semiconductor device can include the upper pad structure formed on the step section of the conductive structure. This can reduce the risk of contact failure or punching defects of the contact plug.

Claims

[1] Semiconductor device comprising: a substrate (100); conductive structures (104b) on the substrate (100), wherein the conductive structures (104b) are spaced apart from each other in a vertical direction perpendicular to a surface of the substrate (100) and an edge of the conductive structures (104b) has a step section such that an end of a conductive structure (104b) does not overlap with conductive structures (104b) arranged above it in the vertical direction; Insulation structures between the conductive structures (104b); Sidewall insulation structures (110) on sidewalls of the conductive structures (104b) to cover the sidewalls of the conductive structures (104b); upper pad structures (114) on top surfaces of the step section of the conductive structures (104b) and top surfaces of sections of the sidewall insulation structures (110); an insulating intermediate layer (118) covering the conductive structures (104b), the insulating structures (102b), the sidewall insulating structures (110) and the upper pad structures (114); and Contact plugs (142) extending through the insulating intermediate layer (118), wherein the contact plugs (142) each contact the upper pad structures (114), wherein the sides of the upper pad structures (114) facing the substrate (100) contact at least one section of the top surfaces of the side wall insulation structures (110), wherein one top surface of each of the upper pad structures (114) is not covered by each of the side wall insulation structures (110), and wherein at least the top surfaces of the upper pad structures (114) and at least side walls of the side wall insulation structures (110) directly contact the insulating intermediate layer (118). [2] Semiconductor device according to claim 1, wherein the conductive structures (104b) and the upper pad structures (114) each contain polysilicon. [3] Semiconductor device according to claim 2, wherein the upper pad structures (114) contain polysilicon formed by epitaxial growth from an upper surface of the conductive structures (104b). [4] Semiconductor device according to claim 1, wherein the sidewall insulation structures (110) contain an insulation material which has a high etch selectivity with respect to the conductive structures (104b) and insulation structures (102b). [5] Semiconductor device according to claim 1, wherein the top surfaces of the sidewall insulation structures (110) and the top surfaces of the step sections of the conductive structures (104b) are coplanar to each other. [6] Semiconductor device according to claim 1, wherein an end section of one of the upper pad structures (114) projects laterally over an end section of one of the conductive structures (104b) which contact a side of the upper pad structure (114) facing the substrate (100). [7] Semiconductor device according to claim 1, wherein a top surface of an upper pad structure (114) is located closer to the substrate (100) in the vertical direction than a top surface of an adjacent sidewall insulation structure, which is located one level higher than the upper pad structure (114), is located closer to the substrate (100) in the vertical direction. [8] Semiconductor device according to claim 1, wherein a top surface of a sidewall insulation structure (110) is further away from the substrate (100) in the vertical direction than a top surface of a conductive structure (104b) on a step section that contacts the sidewall insulation structure (110). [9] Semiconductor device according to claim 1, wherein the upper pad structure (114) covers an entire top surface of the step section of the conductive structure (104b) that is not covered by the insulating structures (102b). [10] Semiconductor device according to claim 1, wherein a bottom side of each of the contact plugs (142) is located on a top side or an inner section of a stacked structure comprising the upper pad structure (114) and a lower conductive structure (104b) which contacts the upper pad structure (114). [11] Semiconductor device according to claim 1, wherein one of the insulating structures, which is in contact with a side of an overlying conductive structure (104b) facing the substrate (100), has a length in a first direction parallel to the surface of the substrate (100) which is greater than a length of the overlying conductive structure (104b) in the first direction. [12] Semiconductor device comprising: a substrate (100); conductive structures (104b) on the substrate (100), wherein the conductive structures (104b) are spaced apart from each other in a vertical direction perpendicular to a surface of the substrate (100), wherein the conductive structures (104b) contain polysilicon and an edge of the conductive structures (104b) has a step section such that an end of a conductive structure (104b) does not overlap with conductive structures (104b) arranged above it in the vertical direction; Insulation structures (102b) between the conductive structures (104b); Sidewall insulation structures (110) on the sidewalls of the conductive structures (104a, 104b, 105a) to cover sidewalls of the conductive structures (104b), the sidewall insulation structures (110) being located on the insulation structures (102b); upper pad structures (114) on top surfaces of the step section of the conductive structures (104b) and a section of the sidewall insulation structures (110), wherein the upper pad structures (114) contain polysilicon; an insulating intermediate layer (118) which covers the conductive structures (104a, 104b, 105a), the insulation structures (102b), the sidewall insulation structures (110, 150a) and the upper pad structures (114); a channel structure (130) extending through the conductive structures (104b) and the insulating structures (102b), wherein the channel structure (130) is connected to the substrate (100) and the channel structure (130) comprises a dielectric layer structure (122), a channel (124), a buried insulating structure (126) and an upper conductive structure (128); and contact plugs (142) extending through the insulating intermediate layer (118), wherein the contact plugs (142) each contact the upper pad structures (114), wherein a top surface of an upper pad structure (114) is located closer to the substrate (100) in the vertical direction than a top surface of an adjacent sidewall insulation structure, which is located one level higher than the upper pad structure (114), wherein one of the insulating structures (102b), which is in contact with a side of an overlying conductive structure (104b) facing the substrate (100), has a length in a first direction parallel to the surface of the substrate (100) that is greater than a length of the overlying conductive structure (104b) in the first direction, wherein one top surface of each of the upper pad structures (114) is not covered by each of the side wall insulation structures (110), and wherein at least the top surfaces of the upper pad structures (114) and at least side walls of the side wall insulation structures (110) directly contact the insulating intermediate layer (118). [13] Semiconductor device according to claim 12, wherein a top surface of the side wall insulation structure (110) and a top surface of the lower pad structure are coplanar to each other. [14] Semiconductor device comprising: a substrate (100); conductive structures (104b) on the substrate (100), wherein the conductive structures (104b) are spaced apart from each other in a vertical direction perpendicular to a surface of the substrate (100), wherein the conductive structures (104b) contain polysilicon and an edge of the conductive structures (104b) has a step section such that an end of a conductive structure (104b) does not overlap with conductive structures (104b) arranged above it in the vertical direction; Insulation structures (102b) between the conductive structures (104b); Sidewall insulation structures (110) each on the sidewalls of the conductive structures (104b) to cover sidewalls of the conductive structures (104b); upper pad structures (114) on top surfaces of the step section of the conductive structures (104b), wherein the upper pad structures (114) contain polysilicon; an insulating intermediate layer (118) covering the conductive structures (104b), the insulating structures (102b), the sidewall insulating structures (110, 150a) and the upper pad structures (114); and Contact plugs (142) extending through the insulating intermediate layer (118), wherein the contact plugs (142) each contact the upper pad structures (114), where: a bottom side of each of the contact plugs (142) is located on a top side or inner section of a stacked structure comprising an upper pad structure (114) and a lower conductive structure (104b) which contacts the upper pad structure (114), a thickness of each of the upper pad structures (114) in the vertical direction is less than a thickness in the vertical direction of a structure in which a single conductive structure (104b) and a single insulating structure are stacked, a top surface of the side wall insulation structure (110) and a top surface of the step section of the conductive structure (104b) are coplanar to each other, wherein one top surface of each of the upper pad structures (114) is not covered by each of the side wall insulation structures (110), and wherein at least the top surfaces of the upper pad structures (114) and at least side walls of the side wall insulation structures (110) directly contact the insulating intermediate layer (118). [15] Semiconductor device according to claim 14, wherein an end section of the upper pad structure (114) projects laterally over an end section of the lower conductive structure (104b) which contacts a side of the upper pad structure (114) facing the substrate (100). [16] Semiconductor device according to claim 14, wherein a top surface of the sidewall insulation structure (110) is further away from the substrate (100) in the vertical direction than a top surface of the conductive structure (104b) on a step section contacting the sidewall insulation structure (110) is further away from the substrate (100) in the vertical direction. [17] Semiconductor device according to claim 14, wherein the upper pad structure (114) covers an entire top surface of the step section of the conductive structure (104b) that is not covered by the insulating structures (102b).

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