INTEGRATED CIRCUIT PACKAGE AND METHOD

Abstract

Semiconductor package (400, 500, 600, 700) comprising: a first die (200) directly bonded to a second die (300) at an interface, the interface having a conductor-to-conductor bond; an encapsulation material (114) formed over the first die (200) and around the second die (300); a plurality of vias (204) extending through the first die (200); a dielectric layer (106) over the first die (200), wherein the plurality of vias (204) extend through the dielectric layer (106); a plurality of thermal vias (112) extending through the encapsulation material (114), the plurality of thermal vias (112) being bonded to the dielectric layer (106) and disposed adjacent to the second die (300); and an interconnect structure (206) electrically connected to the first die (200), the second die (300), and the plurality of vias (204).

Description

BACKGROUND

[0001] The semiconductor industry has experienced rapid growth as the integration density of a wide variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) is constantly improving. Improvements in integration density have largely resulted from the iterative reduction of the minimum feature size, allowing more components to be integrated into a given area. As the demand for ever smaller electronic devices has increased, a need has arisen for smaller and more creative packaging techniques for semiconductor die. One example of such packaging systems is package-on-package (PoP) technology. In a PoP device, an upper semiconductor package is stacked on top of a lower semiconductor package to achieve a high level of integration and component density.PoP technology generally enables the production of semiconductor components with extended functionalities and a small footprint on a printed circuit board (PCB). An integrated circuit package and a corresponding process are known from US 2020 / 0 105 635 A1. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Aspects of this disclosure are best understood by reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of various features may be arbitrarily exaggerated or reduced for clarity of illustration. Fig. 1A to 1M illustrate cross-sectional views of intermediate steps in the fabrication of a semiconductor package according to some embodiments. Fig. 2 illustrates a cross-sectional view of a semiconductor package according to some embodiments that serve to explain the invention but are not part of the invention. Fig. 3 illustrates a cross-sectional view of a semiconductor package according to some embodiments that serve to explain the invention but are not part of the invention. Fig. 4A to 4C illustrate cross-sectional views of intermediate steps in the fabrication of a semiconductor package according to some embodiments. Fig. 5 illustrates a cross-sectional view of a semiconductor package according to some embodiments that are illustrative of the invention but are not part of the invention. Fig. 6 illustrates a cross-sectional view of a semiconductor package according to some embodiments that are illustrative of the invention but are not part of the invention. Fig. 7A to 7D illustrate cross-sectional views of intermediate steps in the fabrication of a semiconductor package according to some embodiments. Fig. 8 illustrates a cross-sectional view of a semiconductor package according to some embodiments that are illustrative of the invention but are not part of the invention. Fig. 9 illustrates a cross-sectional view of a semiconductor package according to some embodiments that are illustrative of the invention but are not part of the invention. Fig. 10A to 10C illustrate cross-sectional views of intermediate steps in the fabrication of a semiconductor package according to some embodiments. Fig. 11 illustrates a cross-sectional view of a semiconductor package according to some embodiments that are illustrative of the invention but are not part of the invention. Fig. 12 illustrates a cross-sectional view of a semiconductor package according to some embodiments that are illustrative of the invention but are not part of the invention. DETAILED DESCRIPTION

[0003] The following disclosure provides many different embodiments or examples of implementing various features of the invention. To simplify the present disclosure, specific examples of components and arrangements are described below. For example, the formation of a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, but may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Further, reference numerals may be repeated in the various examples in the present disclosure.This repetition is for the purpose of simplicity and clarity and does not, in itself, prescribe any relationship between the various embodiments and / or configurations discussed herein.

[0004] Furthermore, for convenience, spatially relative terms such as "below," "below," "below," "above," "above," and the like may be used herein to describe the relationship of one element or feature to one or more other elements or features as illustrated in the figures. The spatially relative terms are intended to encompass various orientations of the device in use or operation, in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may also be interpreted accordingly.

[0005] According to some embodiments, stacked dies (e.g., a first die connected to a second die) are encapsulated in an insulating material, and a heat dissipation structure (e.g., a substrate) is connected to a backside of the second die and the insulating material. In some embodiments, the heat dissipation structure is a semiconductor substrate bonded via metal-to-metal bonding, which improves heat dissipation in the completed package and improves adhesion between the heat dissipation structure and the second die. In other embodiments, the heat dissipation structure is bonded using a different bonding configuration (e.g., dielectric-to-dielectric bonding, semiconductor-to-semiconductor bonding, or the like).

[0006] Fig. 1A to 1M are cross-sectional views of intermediate steps of a process for manufacturing a semiconductor package 400 (see Fig. 1M) according to some embodiments.

[0007] With reference to Fig. 1A illustrates a semiconductor die 200. The die 200 may be a bare-chip semiconductor die (e.g., an unpackaged semiconductor die). The die 200 can be, for example, logic dies (e.g., application processors (APs), central processing units, microcontrollers, etc.), memory dies (e.g., DRAM dies, hybrid memory cubes (HBCs), SRAM dies, wide input / output memory dies (wide IO memory dies), MRAM dies, RRAM dies, etc.), power management dies (e.g., power management IC dies (PMIC dies), radio frequency dies (RF dies), sensor dies, MEMS (Micro-Electro-Mechanical-System) dies), signal processing dies (e.g., DSP dies), front-end dies (e.g., analog front-end dies (AFE dies)), biomedical dies, or the like.

[0008] The die 200 can be processed according to the applicable manufacturing methods to form integrated circuits in the die 200. For example, the die 200 can include a semiconductor substrate 202 such as silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 202 can include other semiconductor materials such as germanium, a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide, an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP, or combinations thereof. Other substrates, such as multilayer substrates or gradient substrates, can also be used.

[0009] Devices such as transistors, diodes, capacitors, resistors, etc., may be formed in and / or on the semiconductor substrate 202 and interconnected by an interconnect structure 206, which may include, for example, metallization structures 206A in one or more dielectric layers 206B on the semiconductor substrate 202. The interconnect structures 206 electrically connect the devices on the substrate 202 to form one or more integrated circuits.

[0010] The die 200 further includes further vias 204 that may be electrically connected to the metallization structures in the interconnect structure 206. The vias 204 may include a conductive material (e.g., copper or the like) and extend from the interconnect structure 206 into the substrate 202. Insulating barrier layers 208 may be formed around at least portions of the vias 204 in the substrates 202. The insulating barrier layers 208 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or the like and may be used to physically and electrically isolate the vias 204 from the substrates 202. In subsequent processing steps, the substrate 202 may be thinned to expose the vias 204 (see Fig. 1C). After thinning, the vias 204 form an electrical connection from a backside of the substrate 202 to a frontside of the substrate 202.

[0011] Die 200 further includes contact pads 210 that enable external connections to interconnect structure 206 and the devices on substrate 202. Contact pads 210 may include copper, aluminum (e.g., 28K aluminum), or another conductive material. Contact pads 210 are disposed on a so-called active side or front side 220 of die 200. The active side / front side 220 of die 200 may refer to a side of semiconductor substrate 202 on which the active devices are formed. Back side 222 of die 200 may refer to a side of the semiconductor substrate opposite the active side / front side.

[0012] A passivation film 212 is disposed on the interconnect structure 206, and contact pads 210 are exposed on a top surface of the passivation film 212. The passivation film 212 may include silicon oxide, silicon oxynitride, silicon nitride, or the like. In some embodiments, contact pads 210 may extend above a top surface of the passivation film 212.

[0013] The die 200 may be formed as part of a larger wafer (e.g., bonded to other dies 200). In some embodiments, the dies 200 may be separated from each other (singled) prior to packaging. The singulation process may include mechanical sawing, laser dicing, plasma dicing, combinations thereof, or the like. In other embodiments, the dies 200 are singulated after they are integrated into a semiconductor package. For example, the dies 200 may be packaged while still bonded as part of a wafer.

[0014] In some embodiments, a chip probe (CP) test may be applied to each of the 200 dies (e.g., through the contact pads 210). The CP test verifies the electrical functionality of the 200 dies, and dies that pass the CP tests are referred to as known good dies (KGDs). Die 200 that fail the CP tests are discarded or repaired. In this way, KGDs are provided for packaging, reducing waste and the cost of packaging a faulty die.

[0015] After the CP tests, a passivation layer 214 is formed over the contact pads 210 and the interconnect structure 206 of each KGD. The passivation layer 214 may include silicon oxide, silicon oxynitride, silicon nitride, or the like. The passivation layer 214 may protect the contact pads 210 during subsequent packaging processes as described herein.

[0016] In Fig. 1B, the die 200 is mounted face down on a carrier substrate 102. The carrier substrate 102 may be a glass carrier substrate, a ceramic carrier substrate, or the like. The carrier substrate 102 may be a wafer, so that multiple packages can be formed simultaneously on the carrier substrate 102. Although in Fig. 1B only a single die 200 is shown, multiple dies 200 may be mounted on the carrier substrate 102 for simultaneous processing. The dies 200 may be applied to the carrier substrate 102 after singulation using a chip-on-wafer (CoW) process, or the dies 200 may be applied to the carrier substrate 102 before singulation using a wafer-on-wafer (WoW) process. The dies 200 are arranged face down such that the front sides 220 of the dies 200 face the carrier substrate 102 and the back sides 222 of the dies 200 face away from the carrier substrate 102.

[0017] In some embodiments, the dies 200 are attached to the carrier substrate 102 by a release layer 106, and the passivation layer 214 of the dies 200 may contact the release layer 106. The release layer 106 may be formed from a polymer-based material that may be removed along with the carrier substrate 102 from the dies 200 and other overlying structures formed in subsequent steps. In some embodiments, the release layer 106 is an epoxy-based thermal release material that loses its adhesive properties when heated, such as a light-to-heat conversion (LTHC) release layer. In other embodiments, the release layer 106 may be an ultraviolet (LTV) adhesive that loses its adhesive properties when exposed to LTV light.The release layer 106 may be applied as a liquid and cured, may be a laminate film laminated to the carrier substrate 102, or the like. In other embodiments, the dies 200 may be fusion bonded directly to the carrier 102, e.g., by fusion bonding the passivation layer 214 to the carrier 102. The fusion bonding may form a dielectric-semiconductor bond between the passivation layer 214 and the carrier 102. In such embodiments, the release layer 104 may be omitted.

[0018] In Fig. 1C, a thinning process may be applied to the die 200 to expose the vias 204. The thinning removes portions of the substrate 202 above the vias 204. In some embodiments, the thinning may expose further lateral portions of a barrier layer (e.g., barrier layer 208, see Fig. 1A) on the vias 204 may be removed to expose the vias 204. The thinning process may include chemical mechanical polishing (CMP), grinding, etching back (e.g., wet etching), combinations thereof, or the like. In some embodiments, the thinning process may recess the substrate 202 such that the vias 204 protrude beyond a backside of the substrate 202. This may be achieved, for example, by a selective etching process that selectively etches the substrate 202 without significantly etching the vias 204.

[0019] In Fig. 1D, a dielectric layer 106 is deposited over the substrate 202 and around portions of the vias 204. For example, the dielectric layer 106 may be deposited around portions of the vias 204 that extend above the substrate 202. The dielectric layer 106 may include silicon oxide, silicon nitride, silicon oxynitride, or the like, and the dielectric layer 106 may be deposited by a suitable deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or the like. The dielectric layer 106 may be deposited to initially cover the vias 204. Subsequently, a planarization step may be performed to substantially planarize the surfaces of the vias 204 and the dielectric layer 106.

[0020] In Fig. 1E, dies 300 are bonded to dies 200, for example, in a hybrid bond configuration. Dies 300 may have a similar structure to dies 200, and the details are not repeated herein. The materials and manufacturing processes of the features in dies 300 can be found by referring to the same features in dies 200, where the corresponding features in dies 200 begin with the number "2," and the features in dies 300 have corresponding reference numerals beginning with the number "3." In a particular embodiment, dies 300 are memory dies, but other types of dies may also be used.

[0021] The dies 300 are arranged face down, so that the front sides 320 of the dies 300 face the dies 200 and the back sides 322 of the dies 300 face away from the dies 200. The dies 300 are bonded to the dielectric layer 106 on the back sides of the dies 200 and the vias 204 in the dies 200. For example, a passivation layer of the dies 300 may be bonded directly to the dielectric layer 106, and the contact pads 310 of the dies 300 may be bonded directly to the vias 204. In one embodiment, the bond between the passivation layer 314 may be an oxide-to-oxide bond or the like. The hybrid bonding process further bonds the contact pads 318 of the die 300 directly to the vias 204 of the die 200 by direct metal-to-metal bonding.Thus, the electrical connection between the dies 200 and the die 300 is established by the physical connection of the contact pads 310 to the vias 204.

[0022] For example, the hybrid bonding process begins with aligning dies 200 with dies 300, e.g., by applying a surface treatment to one or more of dielectric layer 106 or passivation layer 314. The surface treatment may include a plasma treatment. The plasma treatment may be performed in a vacuum environment. The surface treatment may further include a post-plasma treatment cleaning process (e.g., a deionized water rinse or the like) that may be applied to one or more of dielectric layer 106 or passivation layer 314. The hybrid bonding process may then continue to align contact pads 310 with vias 204. Once dies 200 and 300 are aligned, contact pads 310 may overlap the respective vias 204.Next, the hybrid bonding includes a pre-bonding step in which each die 200 is brought into contact with an associated die 300. The pre-bonding may be performed at room temperature (e.g., between about 21°C and about 25°C). The hybrid bonding process continues by performing an anneal, e.g., at a temperature between about 150°C and about 400°C for a duration between about 0.5 hour and about 3 hours, so that the metal in the contact pads 310 (e.g., copper) and the metal of the vias 204 (e.g., copper) diffuse into each other, thereby forming direct metal-to-metal bonding. Although only a single die 300 is depicted in connection with the die 200, other embodiments may include multiple dies 300 connected to the die 200. In such embodiments, the plurality of dies 300 may be in a stacked configuration (e.g., with multiple stacked dies 300) and / or in a side-by-side configuration.

[0023] The dies 300 may have a smaller surface area than the dies 200. The dies 200 extend laterally beyond the dies 300, and portions of the dielectric layer 106 are exposed after bonding the dies 200 and 300. Since a portion of the dielectric layer 106 remains exposed, an optional heat dissipation feature 112 may be attached to the dielectric layer 106 to surround the dies 300. The heat dissipation feature 112 may comprise one or more silicon dies (see, for example, the top view of Fig. 1F), a silicon ring (see e.g. the top view of Fig. 1G) or the like, surrounding one or more sides of die 300. Heat dissipation feature 112 may be free of active devices and / or free of passive devices. Thus, heat dissipation feature 112 may be referred to as a dummy feature in some embodiments.

[0024] The heat dissipation feature 112 may be bonded to the dielectric layer 106 by dielectric-to-dielectric bonding, for example, using a native oxide, thermal oxide, or the like formed on the bottom surface of the heat dissipation feature 112. The dielectric-to-dielectric bonding process may include applying a surface treatment to one or more of the dielectric layer 106 or the oxide on the heat dissipation feature 112. The surface treatment may include a plasma treatment. The plasma treatment may be performed in a vacuum environment. The surface treatment may further include a post-plasma treatment cleaning process (e.g., a deionized water rinse or the like) that may be applied to one or more of the dielectric layer 106 or the oxide on the heat dissipation feature 112.The heat dissipation feature 112 may then be aligned with the dielectric layer 106, and the two are pressed against each other to initiate pre-bonding of the heat dissipation feature 112 to the die 200. The pre-bonding may be performed at room temperature (e.g., between about 21°C and about 25°C). After pre-bonding, an annealing process may be performed, e.g., by heating the heat dissipation element 112 at a temperature between about 150°C and about 400°C for a duration between about 0.5 hour and about 3 hours. The annealing processes for bonding the heat dissipation feature 112 to the die 200 and for bonding the dies 300 to the die 200 may be performed simultaneously, eliminating the need to perform separate annealing processes.

[0025] In other embodiments, the heat dissipation feature 112 may be omitted (see, for example, Fig. 2 and Fig. 3). In such embodiments, the surface area of ​​die 300 may be smaller than the surface area of ​​die 200 (see, for example, Fig. 2). Alternatively, the surface of die 300 may be the same as the surface of die 200, and die 300 may be adjacent to die 200 (see, for example, Fig. 3). In some embodiments, for example, dies 300 may be bonded to dies 200 while dies 300 and dies 200 are still integrated into their respective wafers using a wafer-to-wafer (WoW) bonding process. In other embodiments, singulated dies 300 may be bonded to dies 200 while dies 200 are still integrated into a wafer using a chip-to-wafer (CoW) bonding process.

[0026] In Fig. 1H, an insulating material 114 is formed over the die 200, around the die 300, and around the heat dissipation feature 112 (if present). In some embodiments, the insulating material 114 is a molding compound (e.g., an epoxy, a resin, a moldable polymer, or the like), formed or cast using, for example, a mold (not shown), which may have a rim or other feature for retaining the insulating material 114 during use. Such a mold may be used to form the insulating material 114 under pressure around the die 300, to force the insulating material 114 into openings and recesses, and to eliminate air pockets or the like in the insulating material 114.

[0027] In some embodiments, the insulating material 114 is a dielectric including an oxide, nitride, oxynitride, or the like, and is formed over the die 200. In such embodiments, the insulating material 114 may include a silicon nitride, silicon oxide, silicon oxynitride, or other dielectric material and is formed by chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), or another process.

[0028] As in Fig. 1H, the insulating material 114 may be planarized, for example, by grinding, chemical mechanical polishing (CMP), or the like. After planarization, the top surfaces of the encapsulation material 114, the die 300, and the heat dissipation features 112 (if present) are substantially planar. The heat dissipation features 112 provide heat dissipation from the surfaces of the die 200 through the insulating material 114.

[0029] In Fig. 1I, a conductive bonding layer 116 is formed over the die 300, the heat dissipation structure 112 (if present), and the insulating material 114. In some embodiments, the bonding layer 116 comprises one or more conductive layers (e.g., metal layers), such as an optional adhesion layer 116A, an optional diffusion barrier layer 116B, and a conductive layer 116C. Each of the layers in the adhesion layer 116 may be deposited by PVD, CVD, ALD, plating, or the like. The adhesion layer 116A may include titanium, aluminum, tantalum, combinations thereof, or the like. The adhesion layer 116A contributes to the adhesion of the layers 116B and 116C to the die 300, the heat dissipation structure 112 (if present), and the insulating material 114, although the adhesion layer 116A may be omitted in some embodiments. The diffusion barrier layer 116B may include titanium, titanium nitride, tantalum, tantalum nitride, cobalt, combinations thereof, or the like.The diffusion barrier layer 116B may be used to prevent or at least reduce the diffusion of the material of the conductive layer 116C into the underlying features of the package, although the diffusion barrier layer 116B may be omitted in some embodiments. The conductive layer 116C may include copper, aluminum, indium, combinations thereof, or the like. The conductive layer 116C may be used as a bonding interface for a substrate in a subsequent process step. The use of conductive layers as a bonding interface may provide advantages such as improved heat dissipation and improved adhesion in the resulting package structure.

[0030] In Fig. 1J, a substrate 120 is provided. The substrate 120 may be selected to provide heat dissipation after attachment to the dies 200 and 300 (see Fig. 1K). The substrate 120 may be, for example, a silicon substrate, a glass substrate (e.g., a glass substrate with a thermal conductivity in a range of about 1.5 W / mK to about 5 W / mK, or the like). The substrate 120 may be free of active devices and, in some embodiments, also free of passive devices.

[0031] As in Fig. 1J, a conductive bond layer 118 is formed over the substrate 120. In some embodiments, the bond layer 118 consists of one or more conductive layers (e.g., metal layers), such as an optional adhesion layer 118A, an optional diffusion barrier layer 118B, and a conductive layer 118C. Each of the layers in the bond layer 118 can be deposited by PVD, CVD, ALD, plating, or the like. The adhesion layer 118A can include titanium, aluminum, tantalum, combinations thereof, or the like. The adhesion layer 118A contributes to the adhesion of layers 118B and 118C to the substrate 120, although the adhesion layer 118A can be omitted in some embodiments. The diffusion barrier layer 118B can include titanium, titanium nitride, tantalum, tantalum nitride, cobalt, combinations thereof, or the like.The diffusion barrier layer 118B may be used to prevent or at least reduce the diffusion of the material of the conductive layer 118C into the underlying substrate 120, although the diffusion barrier layer 118B may be omitted in some embodiments. The conductive layer 118C may include copper, aluminum, indium, combinations thereof, or the like. The conductive layer 118C may be used as a bonding interface for a substrate in a subsequent process step. The use of conductive layers as a bonding interface may have advantages, such as improved heat dissipation and adhesion in the resulting package structure.

[0032] A material of the conductive layer 118C may be the same as or different from a material of the conductive layer 116C (see Fig. 1I). For example, in some embodiments, conductive layers 116C and 118C may be a copper layer and a gold layer, or the like. In some embodiments, conductive layer 116C is a copper layer and conductive layer 118C is a gold layer; alternatively, conductive layer 116C is a gold layer and conductive layer 118C is a copper layer. In some embodiments, conductive layer 116C is an indium layer and conductive layer 118C is a gold layer; alternatively, conductive layer 116C is a gold layer and conductive layer 118C is an indium layer.

[0033] In Fig. 1K, the substrate 120 is bonded to the dies 200 and 300 by bonding the bond layer 116 directly to the bond layer 118. By directly bonding the bond layers 116 and 118, metal-to-metal bonds (e.g., copper-copper bonds, copper-gold bonds, gold-gold bonds, indium-gold bonds, or the like) may be formed between the conductive layers 116C and 118C. Bonding the substrate 120 may include aligning the bond layers 116 and 118, and pressing the two against each other to initiate pre-bonding of the substrate 120 to the dies 200 and 300. The pre-bonding may be performed at room temperature (e.g., between about 21°C and about 25°C). After pre-bonding, an annealing process may be applied, e.g. by heating to a temperature between about 150°C and about 400°C for a duration between about 0.5 hours and about 3 hours, so that the metal (e.g.Copper, gold, indium and / or the like) in the bonding layers 116 and 118 diffuse into each other and thus the direct metal-metal bond is formed.

[0034] Substrate 120 may provide improved heat dissipation for dies 200 and 300. For example, dies 300, heat dissipation features 112 (if present), and bonding layers 116 and 118 may provide a heat dissipation path from die 200 to substrate 120. Furthermore, substrate 120 may serve as a carrier that physically supports dies 200 and 300. In this way, device reliability and durability may be improved.

[0035] In Fig. 1L, a carrier substrate debonding is performed to separate (debond) the carrier substrate 102 from the dies 200. According to some embodiments, the debonding includes projecting light, such as laser light or UV light, onto the separation layer 104 so that the separation layer 104 disintegrates under the heat of the light and the carrier substrate 102 can be removed. After the carrier substrate 102 is removed, openings are formed through the passivation layer 214 to expose portions of the contact pads 210. The openings can be formed, for example, by laser drilling, etching, or the like.

[0036] Next, Fig. 1M conductive interconnects 122 are formed on the contact pads 210. The conductive interconnects 122 may be BGA interconnects, solder balls, metal pillars, controlled collapse chip connection bumps (C4 bumps), microbumps, ENEPIG-formed bumps (electroless nickel-electroless palladium immersion gold technique), or the like. The conductive interconnects 122 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or a combination thereof. In some embodiments, the conductive interconnects 122 are formed by initially forming a solder layer using commonly used methods such as evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once a solder layer is formed on the structure, reflow can be performed to form the material into the desired bump shapes.In another embodiment, the conductive connectors 122 are metal pillars (such as a copper pillar) formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal pillars may be solderless and have substantially vertical sidewalls. In some embodiments, a metal capping layer (not shown) is formed on top of the metal pillar connectors 122. The metal capping layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, or a combination thereof and may be formed by a plating process.

[0037] In this way, a semiconductor package 400 is formed. The semiconductor package 400 includes a first die 200 and a second die 300 hybrid-bonded to the first die. For example, the first die 200 may be bonded to the second die 300 by a combination of dielectric-to-dielectric bonding and metal-to-metal bonding. In some embodiments, the first die 200 is bonded to the second die 300 without any solder regions formed therebetween. An insulating material 114 is disposed around the second die 300, and one or more heat dissipation features 112 extend from a surface of the first die 200 through the insulating material 114. A substrate 120 is bonded to a side of the second die 300 opposite the first die 200, e.g., by direct metal-to-metal bonding.For example, a conductive bonding layer 116 over the second die 300 and the insulating material 114 may be bonded directly to a conductive bonding layer 118 formed on a silicon substrate. The substrate 120 provides heat dissipation and support within the semiconductor package 400.

[0038] In embodiments where dies 200 are packaged while still part of a wafer, dicing may be used to separate semiconductor package 400 from other semiconductor packages formed at the same time. As a result of dicing, substrate 120, conductive bond layer 116, conductive bond layer 118, insulating material 114, and die 200 may be adjacent to one another.

[0039] Fig. 2 illustrates a cross-sectional view of a semiconductor package 410 according to some alternative embodiments that are not part of the invention but are for illustrative purposes. The semiconductor package 410 may be similar to the semiconductor package 400, with like reference numerals indicating like / similar features formed by like / similar processes. In the semiconductor package 410, the heat dissipation features 112 are omitted. The die 200 may be wider than the die 300 and may extend laterally beyond it.

[0040] Fig. 3 illustrates a cross-sectional view of a semiconductor package 420 according to some alternative embodiments that are not part of the invention but are for illustrative purposes. The semiconductor package 420 may be similar to the semiconductor package 400, with like reference numerals indicating like / similar features formed by like / similar processes. In the semiconductor package 420, the heat dissipation features 112 are omitted. The die 200 may have the same width as and be adjacent to the die 300.

[0041] Fig. 4A to 4C illustrate cross-sectional views of the intermediate stages in the formation of a semiconductor package 500 according to some embodiments. In Fig. 4A is a similar structure as above with reference to Fig. 1I and Fig. 1J, where like reference numerals indicate like / similar features produced by like / similar processes. In Fig. 4A, however, the bonding layer 116 over the dies 200 and 300 is omitted. Furthermore, the bonding layer 118 on the substrate 120 is omitted. In Fig. 4A, the substrate 120 is aligned with the die 300, the insulating material 114, and the heat dissipation features 112 such that an exposed surface of the substrate 120 faces the exposed surfaces of the die 300, the insulating material 114, and the heat dissipation features 112. This is indicated by arrow 150.

[0042] In Fig. 4B, the substrate 120 is bonded directly to the dies 300, the insulating material 114, and the heat dissipation features 112 by direct bonding, without, for example, depositing intervening bonding layers. In some embodiments, the direct bonds are formed between the substrate 120 and the dies 300, and direct bonds may also be formed between the heat dissipation features 112 and the substrate 120.

[0043] As an example of directly bonding the substrate 120, a surface treatment may be performed on the substrate 120. The surface treatment includes forming a native oxide or a thermal oxide on a surface of the substrate 120. The surface treatment may further include a plasma treatment process, and the process gas for generating the plasma may be a hydrogen-containing gas including a first gas containing hydrogen (H2) and argon (Ar), a second gas containing H2 and nitrogen (N2), or a third gas containing H2 and helium (He). The treatment increases the number of OH groups at the surface of the substrate 120, for example, by interacting with the native or thermal oxide present at a surface of the substrate 120. Next, the substrate 120 is pressed against the dies 300 and the insulating material 114 and the heat dissipation features 112 to form weak bonds.An annealing process is then performed to strengthen the weak bonds and form a fusion bond. During the annealing process, the hydrogen from the OH bonds is outgassed, forming Si-O-Si bonds between the substrate 120 and the dies 300, thereby strengthening the bonds.

[0044] The substrate 120 may provide improved heat dissipation for the dies 200 and 300. For example, the dies 300 and the heat dissipation features 112 (if present) may provide a heat dissipation path from the die 200 to the substrate 120. Furthermore, the substrate 120 may serve as a carrier that physically supports the dies 200 and 300. In this way, the reliability and durability of the devices may be improved. Fig. Figure 4C illustrates the resulting package after processing (e.g. as above in Fig. 1L to 1M) to remove the carrier 102 and form the connectors 122.

[0045] Fig. 5 illustrates a cross-sectional view of a semiconductor package 510 according to some alternative embodiments that are not part of the invention but are for illustrative purposes. The semiconductor package 510 may be similar to the semiconductor package 500, with like reference numerals indicating like / similar features formed by like / similar processes. For example, in the semiconductor package 510, the substrate 120 is bonded directly to the die 300 without intervening bond layers. In the semiconductor package 510, the heat dissipation features 112 are omitted, and the die 200 may be wider than the die 300 and extend laterally beyond the die 300.

[0046] Fig. 6 illustrates a cross-sectional view of a semiconductor package 520 according to some alternative embodiments that are not part of the invention but are for illustrative purposes. The semiconductor package 520 may be similar to the semiconductor package 500, with like reference numerals indicating like / similar features formed by like / similar processes. For example, in the semiconductor package 520, the substrate 120 is bonded directly to the die 300 without intervening bond layers. In the semiconductor package 520, the heat dissipation features 112 are omitted, and the die 200 may have the same width as and be adjacent to the die 300.

[0047] Fig. 7A to 7D illustrate cross-sectional views of the intermediate stages in the fabrication of a semiconductor package 600 according to some embodiments. In Fig. 7A will show a similar structure as above with reference to Fig. 1I and Fig. 1J, wherein like reference numerals indicate like / similar features formed by like / similar processes. In Fig. 7A, however, the bonding layer 116 over the dies 200 and 300 is omitted. Furthermore, the bonding layer 118 on the substrate 120 is omitted. In Fig. 7A, a dielectric bonding layer 152 is deposited on the carrier substrate 120. The dielectric bonding layer 152 may include silicon oxide, silicon oxynitride, or the like, and may be deposited by CVD, PVD, ALD, or the like. Alternatively, the dielectric bonding layer 152 may be deposited on the dies 300, the heat dissipation features 112, and the insulating material 114 instead of on the substrate 120 (see Fig. 7B).

[0048] In Fig. 7A and Fig. 7B, the substrate 120 is aligned with the die 300, the insulating material 114, and the heat dissipation features 112 such that an exposed surface of the substrate 120 faces the exposed surfaces of the die 300, the insulating material 114, and the heat dissipation features 112. This is indicated by arrow 154.

[0049] In Fig. 7C, the substrate 120 is bonded to the dies 300, the insulating material 114, and the heat dissipation features 112, using the dielectric bonding layer 152 to form, for example, dielectric-semiconductor bonds. In some embodiments, the dielectric bonding layer 152 is formed between the dielectric bonding layer 152 and the dies 300 and between the heat dissipation features 112 and the substrate 120. In some embodiments, the dielectric bonding layer 152 is formed between the dielectric bonding layer 152 and the substrate 120.

[0050] The substrate 120 may provide improved heat dissipation for the dies 200 and 300. For example, the dies 300 and the heat dissipation features 112 (if present) may provide a heat dissipation path from the die 200 to the substrate 120. Furthermore, the substrate 120 may serve as a carrier that physically supports the dies 200 and 300. In this way, the reliability and durability of the devices may be improved. Fig. Figure 7D illustrates the resulting package after processing (e.g., as described above with reference to Fig. 1L to 1M) to remove the carrier 102 and form the connectors 122. This results in a semiconductor package 600.

[0051] Fig. 8 illustrates a cross-sectional view of a semiconductor package 610 according to some alternative embodiments that are not part of the invention but are for illustrative purposes. The semiconductor package 610 may be similar to the semiconductor package 600, with like reference numerals indicating like / similar features formed by like / similar processes. For example, in the semiconductor package 610, the substrate 120 is bonded to the die 300 with the dielectric bond layer 152. In the semiconductor package 610, the heat dissipation features 112 are omitted, and the die 200 may be wider than the die 300 and may extend laterally beyond the die 300.

[0052] Fig. 9 illustrates a cross-sectional view of a semiconductor package 620 according to some alternative embodiments that are not part of the invention but are for illustrative purposes. The semiconductor package 620 may be similar to the semiconductor package 600, with like reference numerals indicating like / similar features formed by like / similar processes. For example, in the semiconductor package 620, the substrate 120 is bonded to the die 300 with the dielectric bond layer 152. In the semiconductor package 620, the heat dissipation features 112 are omitted, and the die 200 has the same width as and is adjacent to the die 300.

[0053] Fig. 10A to 10C illustrate cross-sectional views of intermediate stages in the fabrication of a semiconductor package 700 according to some embodiments. Fig. 10A, a similar structure as above with reference to Fig. 1I and Fig. 1J, where like reference numerals indicate like / similar features produced by like / similar processes. In Fig. 10A, however, the bonding layer 116 over dies 200 and 300 is omitted. Furthermore, the bonding layer 118 on the substrate 120 is omitted. A first dielectric bonding layer 152A is formed on the substrate 120, and a second dielectric bonding layer 152B is formed on the dies 300, the insulating material 114, and the heat dissipation features 112. The dielectric bonding layers 152A and 152B are substantially similar to the dielectric bonding layer 152 and may be formed by a similar process and from a similar material as described above.

[0054] The substrate 120 is aligned with the die 300, the insulating material 114, and the heat dissipation features 112 such that an exposed surface of the substrate 120 faces the exposed surfaces of the die 300, the insulating material 114, and the heat dissipation features 112. This is indicated by arrow 156.

[0055] In Fig. 10B, the substrate 120 is bonded to the dies 300, the insulating material 114, and the heat dissipation features 112, using dielectric bonding layers 152A and 152B to form, for example, dielectric-to-dielectric bonds. In some embodiments, the dielectric-to-dielectric bonds are formed between the dielectric bonding layer 152A and the dielectric bonding layer 152B.

[0056] As an example of the formation of the dielectric-dielectric bonds, a surface treatment may be performed on the dielectric bonding layer 152A and / or the dielectric bonding layer 152B. The surface treatment may further include a plasma treatment process, and the process gas for generating the plasma may be a hydrogen-containing gas containing a first gas comprising hydrogen (H2) and argon (Ar), a second gas comprising H2 and nitrogen (N2), or a third gas comprising H2 and helium (He). The treatment reduces the number of OH groups on the surface of the dielectric bonding layers 152A and / or 152B. Next, the dielectric bonding layer 152A is pressed against the dielectric bonding layer 152B to form weak bonds. An annealing process is then performed to strengthen the weak bonds and form a fusion bond.During the annealing process, the H of the OH bonds is outgassed, forming Si-O-Si bonds between the dielectric bonding layers 152A and 152B, thereby strengthening the bonds.

[0057] The substrate 120 may provide improved heat dissipation for the dies 200 and 300. For example, the dies 300 and the heat dissipation features 112 (if present) may provide a heat dissipation path from the dies 200 to the substrate 120. Furthermore, the substrate 120 may serve as a carrier that physically supports the dies 200 and 300. This may improve the reliability and durability of the devices. Fig. Figure 10C illustrates the resulting package after processing (e.g., as described above with reference to Fig. 1L to 1M) to remove the carrier 102 and form the connectors 122. Thus, a semiconductor package 700 is formed.

[0058] Fig. 11 illustrates a cross-sectional view of a semiconductor package 710 according to some alternative embodiments that are not part of the invention but are for illustrative purposes. The semiconductor package 710 may be similar to the semiconductor package 700, with like reference numerals indicating like / similar features formed by like / similar processes. For example, in the semiconductor package 710, the substrate 120 is bonded to the die 300 with the dielectric bond layers 152A and 152B. In the semiconductor package 710, the heat dissipation features 112 are omitted, and the die 200 may be wider than the die 300 and may extend laterally beyond the die 300.

[0059] Fig.12 illustrates a cross-sectional view of a semiconductor package 720 according to some alternative embodiments that are not part of the invention but are for illustrative purposes. The semiconductor package 720 may be similar to the semiconductor package 700, with like reference numerals indicating like / similar features formed by like / similar processes. For example, in the semiconductor package 720, the substrate 120 is bonded to the die 300 with the dielectric bond layers 152A and 152B. In the semiconductor package 720, the heat dissipation features 112 are omitted, and the die 200 has the same width as and is adjacent to the die 300.

[0060] According to some embodiments, stacked dies (e.g., a first die bonded to a second die) are encapsulated in an insulating material, and a substrate is bonded to a backside of the second die and the insulating material. The substrate can provide structural support and heat dissipation. In some embodiments, the substrate is connected by metal-to-metal bonding, which improves heat dissipation in the completed package and adhesion between the substrate and the second die. In other embodiments, the substrate is bonded by a different bonding configuration (e.g., with or without intervening dielectric bond layers).

[0061] The invention is defined by the main claim and the subordinate claims. Further embodiments of the invention are recited in the dependent claims.

Claims

[1] Semiconductor package (400, 500, 600, 700) comprising: a first die (200) directly bonded to a second die (300) at an interface, the interface having a conductor-to-conductor bond; an encapsulation material (114) formed over the first die (200) and around the second die (300); a plurality of vias (204) extending through the first die (200); a dielectric layer (106) over the first die (200), wherein the plurality of vias (204) extend through the dielectric layer (106); a plurality of thermal vias (112) extending through the encapsulation material (114), the plurality of thermal vias (112) being bonded to the dielectric layer (106) and disposed adjacent to the second die (300); and an interconnect structure (206) electrically connected to the first die (200), the second die (300), and the plurality of vias (204). [2] The semiconductor package (400, 500, 600, 700) of claim 1, wherein a dielectric layer (314) of the second die (300) is directly connected to the dielectric layer (106) at the interface; and wherein the plurality of vias (204) extend through a semiconductor substrate (202) of the first die (200), wherein a contact pad (310) of the second die (300) is directly bonded to the plurality of vias (204) at the interface. [3] The semiconductor package (400, 500, 600, 700) of claim 2, wherein the plurality of vias (204) extend higher than the semiconductor substrate (202). [4] The semiconductor package (400, 500, 600, 700) of any preceding claim, wherein the plurality of vias (204) electrically connect the second die (300) to the interconnect structure (206). [5] Semiconductor package (400, 500, 600, 700) according to one of the preceding claims, wherein a plurality of contact pads (310) of the second die (300) are directly connected to the plurality of vias (204) of the first die (200) at the interface. [6] A semiconductor package (400, 500, 600, 700) according to any one of the preceding claims, wherein the dielectric layer (106) is formed from a polymer-based material, an epoxy-based thermal barrier material, or an ultraviolet adhesive. [7] Semiconductor package (400, 500, 600, 700) according to one of the preceding claims, wherein the dielectric layer (106) comprises silicon oxide, silicon nitride or silicon oxynitride. [8] Semiconductor package (400, 500, 600, 700) according to any preceding claim, wherein the dielectric layer (106) is deposited by chemical vapor deposition, physical vapor deposition or atomic layer deposition. [9] The semiconductor package (400, 500, 600, 700) of any one of claims 1 to 8, wherein the thermal vias (112) are electrically isolated from all active devices in the first and second die (200; 300). [10] Semiconductor package (400, 500, 600, 700) according to one of the preceding claims, wherein the thermal vias (112) are one or more silicon dies, or a silicon ring surrounding one or more sides of the second die (300). [11] Semiconductor package (400, 500, 600, 700) comprising: a first die (200) bonded to a second die (300), wherein a back side of the first die (200) is bonded directly to a front side of the second die (300); an encapsulation material (114) encapsulating the second die (300); an interconnect structure (206) electrically connected to the first die (200) and the second die (300); a plurality of through-vias (204) extending from the interconnect structure (206) to the surface of the first die (200) opposite the interconnect structure (206); a dielectric layer (106) over the first die (200), wherein the plurality of through vias (204) extend through the dielectric layer (106); a plurality of thermal vias (112) extending from a surface of the second die (300) to the dielectric layer (106). [12] The semiconductor package (400, 500, 600, 700) of claim 11, wherein the package comprises: a dielectric layer (314) of the second die (300) bonded directly to the dielectric layer (106) over the first die (200); and wherein the plurality of through-vias (204) extend through a semiconductor substrate (202) of the first die (200), wherein a plurality of contact pads (310) of the second die (300) are bonded directly to the plurality of through-vias (204). [13] Semiconductor package (400, 500, 600, 700) according to claim 11 or 12, wherein the encapsulation material (114) is directly adjacent to the dielectric layer (106). [14] Semiconductor package (400, 500, 600, 700) according to one of claims 11 to 13, wherein the plurality of contact pads (310) each directly adjoin the dielectric layer (106) in sections. [15] The semiconductor package (400) of any one of claims 11 to 14, wherein a conductive bonding layer (116) is formed on a surface of the second die (300), the surface of the thermal vias (112) and the surface of the encapsulation material (114). [16] Procedure comprising: Depositing a dielectric layer (106) over a substrate (202) and around vias (204) of a first die (200); Hybrid bonding the first die (200) to a second die (300); Applying thermal vias (112) to the dielectric layer (106) and laterally adjacent to the second die (300); Encapsulating the first die (200), the second die (300) and the plurality of thermal vias (112) in an encapsulation material (114); Planarizing the encapsulation material (114) to expose the second die (300) and the plurality of thermal vias (112); and Forming a conductive bonding layer (116) on a side of the second die (300) opposite the first die (200). [17] The method of claim 16, further comprising: prior to hybrid bonding the first die (200) to the second die (300), attaching the first die (200) to a carrier (102); and Performing a thinning process on the substrate (202) of the first die (200) to expose the vias (204) such that the vias (204) protrude beyond the substrate (202). [18] The method of claim 16 or 17, wherein the hybrid bonding of the first die (200) to the second die (300) comprises: directly bonding a passivation layer (314) of the second die (300) to the dielectric layer (106) of the first die (200); and directly bonding contact pads (310) in the passivation layer (314) of the second die (300) to the vias (204) extending through the semiconductor substrate (202) of the first die (200). [19] The method of any one of claims 16 to 18, wherein the thermal vias (112) are bonded to the dielectric layer (106) by dielectric-to-dielectric bonding using a native oxide or thermal oxide formed on the bottom surface of the thermal vias (112). [20] The method of claim 19, wherein the dielectric-to-dielectric bonding process comprises applying a surface treatment to one or more of the dielectric layer (106) or the oxide on the thermal vias (112).

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