Transistor gates and methods for their manufacture

Abstract

Device with: a first nanostructure (52A); a second nanostructure (52B) above the first nanostructure (52A); a first high-k gated dielectric (103) arranged around the first nanostructure (52A); a second high-k gated dielectric (103A) arranged around the second nanostructure (52B); and a gate electrode (102), above the first high-k gate dielectric (103) and the second high-k gate dielectric (103A), wherein a part of the gate electrode (102) between the first nanostructure (52A) and the second nanostructure (52B) has a first part of a p-exit work metal (105), wherein the first part of the p-exit work metal (105) fills an entire region between the first high-k gate dielectric (103) and the second high-k gate dielectric, and wherein the first part of the p-exit work metal (105) consists throughout of the same material, and wherein the first part of the p-exit work metal (105) has a first thickness (T2) and a second part of the p-exit work metal (105) on a side wall of the first nanostructure (52A) has a second thickness (T1), wherein the first thickness (T2) is greater than the second thickness (T1).

Description

background

[0001] Semiconductor devices are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by successively depositing insulating or dielectric material layers, conductive material layers, and semiconductor material layers onto a semiconductor substrate. The different material layers are then structured by lithography to create circuit components and elements on the substrate.

[0002] The semiconductor industry is constantly improving the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the smallest feature size, thus enabling the integration of more components in a given area. However, reducing the smallest feature size introduces further problems that need to be addressed.

[0003] US 9997519 B1 discloses a semiconductor device with a gate stack, wherein the gate stack comprises multiple nanostructures and a barrier layer is arranged around each nanostructure. US 2020 / 0119167 A1 discloses a gate all-round transistor (GAA) with horizontal nanostructures consisting of a multilayer structure with improved etch selectivity. US 2020 / 0083327 A1 discloses a semiconductor device with a first nanostructure and a second nanostructure, each comprising corresponding source / drain structures and contacts, wherein a lower portion of the first contact is lower than a bottom portion of the first nanostructure and a lower portion of the second contact is higher than a top portion of the second nanostructure. Brief description of the drawings

[0004] Aspects of the present invention are best understood with reference to the detailed description below in conjunction with the accompanying drawings. It should be noted that, in accordance with common industry practice, various elements are not drawn to scale. Rather, for the sake of clarity of discussion, the dimensions of the various elements may be arbitrarily enlarged or reduced. Fig. Figure 1 shows an example of a nanostructured field-effect transistor (nano-FET) according to some embodiments in a three-dimensional representation. The Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6A, Fig. 6B, Fig. 7A, Fig. Figures 7B, 8A, 8B, 9A, 9B, 10A, 10B, 11A, 11B, 11C, 12A, 12B, 12C, 12D, 13A, 13B, 13C, 14A, 14B, 15A, 15B, 16A, 16B, 17A, 17B, 18A, 18B, 19A, 19B, 19C, 19D, 22A, 22B, 23A, 23B, 23C, 24A, 24B, 24C, 25A, 25B and 25C are sectional and top views of intermediate stages in the fabrication of nano-FETs according to some embodiments. Fig. Figure 20 is a sectional view of a nano-FET according to some embodiments. Fig. Figure 21 is a sectional view of a nano-FET according to some embodiments. The Fig. 26A, Fig. 26B and Fig. Figures 26C are sectional views of a nano-FET according to some embodiments. Detailed description

[0005] The following description provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present invention. These are, of course, merely examples and are not intended to be limiting. For example, the fabrication of a first element above or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements, such that the first and second elements are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples in the present invention.This repetition serves the purpose of simplicity and clarity and does not in itself prescribe any relationship between the various designs and / or configurations discussed.

[0006] Furthermore, spatially relative terms, such as "located below," "under," "lower," "located above," "upper," and the like, can be used here to simply describe the relationship of an element or structure to one or more other elements or structures depicted in the figures. These spatially relative terms are intended to encompass orientations of the device in use or operation beyond the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in a different orientation), and the spatially relative descriptors used here can be interpreted accordingly.

[0007] In transistor gate stacks, the thickness of one or more exit work metal (WFM) layers influences a threshold voltage (V). TH) of the transistor. However, it has been found that thickness variations due to fused areas of the WFM layers (e.g., between nanowires of a nanoFET) do not significantly affect the electrical properties of the transistor. Furthermore, by omitting a depletion layer around the WFM layer (e.g., to prevent parts of the WFM layer from fusing together), fabrication can be simplified. This is particularly true for modern semiconductor nodes with small feature sizes, as depletion layer materials (e.g., tantalum nitride or the like) are difficult to deposit in small spaces. Thus, by omitting these depletion layers in the gate stacks and allowing the WFM layers to fusing together in certain areas, fabrication can be simplified, and manufacturing defects (e.g.,(caused by poor junction deposition) can be reduced without significantly affecting the electrical performance of the resulting transistor.

[0008] Fig. Figure 1 shows an example of nanoFETs (e.g., nanowire FETs, nanosheet FETs, or the like) according to some embodiments in a three-dimensional representation. The nanoFETs have nanostructures 55 (e.g., nanosheets, nanowires, or the like) over fins 66 on a substrate 50 (e.g., a semiconductor substrate), the nanostructures 55 acting as channel regions for the nanoFETs. The nanostructures 55 can comprise p-nanostructures, n-nanostructures, or a combination thereof. Insulation regions 68 are arranged between adjacent fins 66, which can project beyond the insulation regions 68 and protrude between adjacent insulation regions 68. Although the isolation regions 68 are described / represented as regions that are separated from the substrate 50, the term ‘substrate’ used here can refer to the semiconductor substrate alone or to a combination of the semiconductor substrate and the isolation regions.And although a lower part of the fins 66 is depicted as a single, continuous material with the substrate 50, the lower part of the fins 66 and / or the substrate 50 can consist of only one material or of multiple materials. In this context, the fins 66 refer to the portion that extends between adjacent insulation areas 68.

[0009] Gate dielectrics 100 are arranged over the top surfaces of the fins 66 and along the top, side walls, and bottom surfaces of the nanostructures 55. Gate electrodes 102 are located above the gate dielectrics 100. Epitaxial source / drain regions 92 are arranged on the fins 66 on opposite sides of the gate dielectrics 100 and the gate electrodes 102.

[0010] Fig. Figure 1 also shows reference cross-sections that are used in later figures. A cross-section A - A' runs along a longitudinal axis of a gate electrode 102 and in a direction that is, for example, perpendicular to the direction of current flow between the epitaxial source / drain regions 92 of a nanoFET. A cross-section B - B' is perpendicular to cross-section A - A' and parallel to a longitudinal axis of a fin 66 and runs in a direction of, for example, current flow between the epitaxial source / drain regions 92 of the nanoFET. A cross-section C - C' is parallel to cross-section A - A' and passes through the epitaxial source / drain regions 92 of the nanoFETs. For clarity, subsequent figures refer to these reference cross-sections.

[0011] Some embodiments discussed here relate to nanoFETs fabricated using a gate-last process. Other embodiments may employ a gate-first process. Furthermore, some embodiments consider aspects used in planar devices, such as planar FETs, or in fin field-effect transistors (FinFETs).

[0012] The Fig. Figures 2 to 24C are sectional views of intermediate steps in the fabrication of nano-FETs according to some embodiments. Fig. 2 to 5, 6A, 13A, 14A, 15A, 16A, 17A, 18A, 19A, 20, 21, 22A, 23A, 24A, 25A and 26A show the cross-section A - A', which is in Fig. 1 is shown. Fig. 6B, Fig. 7B, Fig. 8B, Fig. 9B, Fig. 10B, Fig. 11B, Fig. 11C, Fig. 12B, Fig. 12D, Fig. 13B, Fig. 14B, Fig. 15B, Fig. 16B, Fig. 17B, Fig. 18B, Fig. 19B, Fig. 22B, Fig. 23B, Fig. 24B, Fig. 25B and Fig. 26B shows the cross-section B - B', which is in Fig. 1 is shown. Fig. 7A, Fig. 8A, Fig. 9A, Fig. 10A, Fig. 11A, Fig. 12A, Fig. 12C, Fig. 13C, Fig. 22C, Fig. 23C, Fig. 24C, Fig. 25°C and Fig. 26C shows the cross-section C - C', which is in Fig. 1 is shown.

[0013] In Fig. 2. A substrate 50 is provided. The substrate 50 can be a semiconductor substrate, such as a solid semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p- or n-type dopant) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. In general, an SOI substrate comprises a layer of semiconductor material fabricated on an insulating layer. The insulating layer may be, for example, a buried oxide layer (BOX layer), a silicon oxide layer, or the like. The insulating layer is fabricated on a substrate, most often a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used.In some embodiments, the semiconductor material of substrate 50 may comprise: silicon; germanium; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor, such as silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium indium arsenide phosphide; or combinations thereof.

[0014] The substrate 50 has an n-region 50N and a p-region 50P. The n-region 50N can be used to fabricate n-devices, such as NMOS transistors, e.g., n-nanoFETs, and the p-region 50P can be used to fabricate p-devices, such as PMOS transistors, e.g., p-nanoFETs. The n-region 50N can be physically separated from the p-region 50P (as represented by a divider 20), and any number of device structures (e.g., other active devices, doped regions, isolation structures, etc.) can be arranged between the n-region 50N and the p-region 50P. Although only one n-range 50N and one p-range 50P are shown, any number of n-ranges 50N and p-ranges 50P can be provided.

[0015] In Fig. In addition, a multilayer stack 64 is fabricated on the substrate 50. The multilayer stack 64 comprises alternating layers of first semiconductor layers 51A to 51C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A to 53C (collectively referred to as second semiconductor layers 53). For illustrative purposes, and as will be explained in more detail later, the second semiconductor layers 53 are removed, and the first semiconductor layers 51 are patterned to fabricate channel regions of nanoFETs in the p-region 50P. Furthermore, the first semiconductor layers 51 are removed, and the second semiconductor layers 53 are patterned to fabricate channel regions of nanoFETs in the n-region 50N.However, in some embodiments the first semiconductor layers 51 can be removed and the second semiconductor layers 53 can be structured to produce channel regions of nano-FETs in the n-region 50N, and the second semiconductor layers 53 can be removed and the first semiconductor layers 51 can be structured to produce channel regions of nano-FETs in the p-region 50P.

[0016] In further embodiments, the first semiconductor layers 51 can be removed and the second semiconductor layers 53 can be structured to fabricate channel regions of nano-FETs in the n-region 50N and the p-region 50P. In still further embodiments, the second semiconductor layers 53 can be removed and the first semiconductor layers 51 can be structured to fabricate channel regions of nano-FETs in the n-region 50N and the p-region 50P. In these embodiments, the channel regions in the n-region 50N and the p-region 50P can have the same material composition (e.g., silicon or the like) and can be fabricated simultaneously. Fig. 26A, Fig. 26B and Fig. Figure 26C shows a structure resulting from these embodiments, wherein the channel regions in the p-region 50P and the n-region 50N, for example, comprise silicon.

[0017] For illustrative purposes, the multilayer stack 64 is shown as a stack with three layers, each comprising first semiconductor layers 51 and second semiconductor layers 53. In some embodiments, the multilayer stack 64 can comprise any number of first semiconductor layers 51 and second semiconductor layers 53. Each layer of the multilayer stack 64 can be epitaxially grown by a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor-phase epitaxy (VPE), molecular beam epitaxy (MBE), or the like. In various embodiments, the first semiconductor layers 51 can be made from a first semiconductor material suitable for p-nanoFETs, such as silicon germanium or the like, and the second semiconductor layers 53 can be made from a second semiconductor material suitable for n-nanoFETs, such as silicon, silicon-carbon, or the like.For illustrative purposes, the multilayer stack 64 is shown as a stack with a bottom semiconductor layer suitable for p-nano-FETs. In some embodiments, the multilayer stack 64 can be fabricated such that the bottom layer is a semiconductor layer suitable for n-nano-FETs.

[0018] The first and second semiconductor materials can be materials with high etch selectivity for each other. Therefore, the first semiconductor layers 51 can be removed from the first semiconductor material without significantly removing the second semiconductor layers 53 from the second semiconductor material in the n-region 50N, so that the second semiconductor layers 53 can be structured to form channel regions of n-NSFETs (NSFETs: nanostructured field-effect transistors). Similarly, the second semiconductor layers 53 can be removed from the second semiconductor material without significantly removing the first semiconductor layers 51 from the first semiconductor material in the p-region 50P, so that the first semiconductor layers 51 can be structured to form channel regions of p-NSFETs.In other embodiments, the channel regions in the n-region 50N and the p-region 50P can be manufactured simultaneously and can have the same material composition, such as silicon, silicon germanium, or the like. The... Fig. 26A, Fig. 26B and Fig. Figure 26C shows a structure resulting from these embodiments, wherein the channel regions in the p-region 50P and the n-region 50N, for example, comprise silicon.

[0019] Now let's move on to... Fig. 3, in which, in some embodiments, fins 66 are produced in the substrate 50 and nanostructures 55 are produced in the multilayer stack 64. In some embodiments, the nanostructures 55 and the fins 66 in the multilayer stack 64 and the substrate 50, respectively, can be produced by etching trenches in the multilayer stack 64 and the substrate 50. The etching can be carried out using any suitable etching method, such as reactive ion etching (RIE), neutral beam etching (NBE), or the like, or a combination thereof. The etching can be anisotropic. By producing the nanostructures 55 by etching the multilayer stack 64, first nanostructures 52A to 52C (which are collectively referred to as first nanostructures 52) can be defined from the first semiconductor layers 51 and second nanostructures 54A to 54C (which are collectively referred to as second nanostructures 54) can be defined from the second semiconductor layers 53.The first nanostructures 52 and the second nanostructures 54 can in turn be collectively referred to as nanostructures 55.

[0020] The fins 66 and the nanostructures 55 can be structured using any suitable method. For example, the fins 66 and the nanostructures 55 can be structured using one or more photolithographic processes, such as dual or multiple structuring processes. In general, dual or multiple structuring processes combine photolithographic and self-aligning processes, enabling the creation of structures with, for example, grid spacings smaller than those achievable with a single direct photolithographic process. For example, in one embodiment, a sacrificial layer is produced over a substrate and then structured using a photolithographic process. Spacers are produced along the structured sacrificial layer using a self-aligning process.The sacrificial layer is then removed, and the remaining spacers can then be used to structure the fins 66.

[0021] For explanatory purposes, Fig. 3. The fins 66 in the n-region 50N and the p-region 50P are shown as fins having essentially the same widths. In some embodiments, the widths of the fins 66 in the n-region 50N can be larger or smaller than those of the fins 66 in the p-region 50P. Furthermore, while the fins 66 and the nanostructures 55 are shown with a uniform width throughout, in other embodiments the fins 66 and / or the nanostructures 55 can have conical sidewalls, such that the width of each of the fins 66 and / or the nanostructures 55 increases continuously in one direction towards the substrate 50. In these embodiments, the nanostructures 55 can each have a different width and be trapezoidal.

[0022] In Fig. 4. STI regions 68 (STI: shallow trench insulation) are produced adjacent to the fins 66. The STI regions 68 can be produced by depositing an insulating material over the substrate 50, the fins 66, and the nanostructures 55, and between adjacent fins 66. The insulating material can be an oxide, such as silicon dioxide, a nitride, or the like, or a combination thereof, and can be deposited by high-density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD), or the like, or a combination thereof. Other insulating materials deposited by a suitable method can also be used. In the illustrated embodiment, the insulating material is silicon dioxide deposited by an FCVD process. After the insulating material has been deposited, an annealing process can be carried out.In one embodiment, the insulating material is deposited such that excess insulating material covers the nanostructures 55. Although the insulating material is shown as a single layer, several layers can be used in some embodiments. For example, in some embodiments, a coating (not shown separately) can first be produced along a surface of the substrate 50, the fins 66, and the nanostructures 55. Subsequently, a filler material, such as one of those mentioned above, can be deposited over the coating.

[0023] A removal process is then performed on the insulating material to remove excess insulating material covering the nanostructures 55. In some embodiments, a planarization process, such as chemical-mechanical polishing (CMP), a back-etching process, a combination thereof, or the like, can be used. The planarization process exposes the nanostructures 55 so that the top surfaces of the nanostructures 55 and the insulating material are at the same level after completion of the planarization process.

[0024] The insulating material is then recessed to create the STI regions 68. The insulating material is recessed such that the upper portions of the fins 66 protrude between adjacent STI regions 68 in regions 50N and 50P. The upper portions of the fins 68 can have a flat surface as shown, a convex surface, a concave surface (such as "dishing"), or a combination thereof. The top surfaces of the STI regions 68 can be made flat, convex, and / or concave by suitable etching. The STI regions 68 can be recessed using a suitable etching process, such as one that is selective for the insulating material (e.g., one that etches the insulating material at a higher rate than the material of the fins 66 and the nanostructures 55). For example, chemical oxide removal using dilute hydrofluoric acid (dHF acid) can be employed.

[0025] The procedure described above with reference to the Fig. The embodiment described in Sections 2 to 4 is only one example of how the fins 66 and the nanostructures 55 can be fabricated. In some embodiments, the fins 66 and / or the nanostructures 55 can be fabricated using a mask and an epitaxial growth process. For example, a dielectric layer can be fabricated over a top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Epitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the epitaxial structures protrude from the dielectric layer to form the fins 66 and / or the nanostructures 55. The epitaxial structures can comprise the alternating semiconductor materials discussed above, such as the first and second semiconductor materials.In some embodiments where the epitaxial structures are grown epitaxially, the epitaxially grown materials can be doped in situ during growth, thus eliminating the need for prior and subsequent implantations, but in-situ and implantation doping can also be used together.

[0026] Furthermore, the first semiconductor layers 51 (and the resulting first nanostructures 52) and the second semiconductor layers 53 (and the resulting second nanostructures 54) are presented and discussed here as layers / structures that, for illustrative purposes only, have the same materials in the p-region 50P and the n-region 50N. Therefore, in some embodiments, the first semiconductor layers 51 and / or the second semiconductor layers 53 may be made of different materials or be fabricated in different sequences in the p-region 50P and the n-region 50N.

[0027] Furthermore, in Fig. Four suitable wells (not shown individually) are generated in the fins 66, the nanostructures 55, and / or the STI regions 68. In embodiments with different well types, different implantation steps can be performed for the n region 50N and the p region 50P using a photoresist or other masks (not shown individually). For example, a photoresist can be produced over the fins 66 and the STI regions 68 in the n region 50N and the p region 50P. The photoresist is structured to expose the p region 50P. The photoresist can be produced by spin coating and can be structured using suitable photolithographic methods.After the photoresist has been structured, implantation with an n-doper is performed in the p-50P region, and the photoresist can act as a mask to largely prevent implantation of n-dopers in the n-50N region. The n-dopers can be phosphorus, arsenic, antimony, or the like, present in the region at a concentration of approximately 10. 13 atoms / cm² -3 up to about 10 14 atoms / cm² -3 The photoresist is implanted. After implantation, it is removed, for example, using a suitable detachment process.

[0028] Prior to or following the implantation of the p-region 50P, a photoresist or other mask (not shown individually) is fabricated over the fins 66, the nanostructures 55, and the STI regions 68 in the p-region 50P and the n-region 50N. The photoresist is patterned to expose the n-region 50N. The photoresist can be fabricated by spin coating and can be patterned using suitable photolithographic techniques. After the photoresist has been patterned, implantation with a p-doping agent can be performed in the n-region 50N, and the photoresist can act as a mask to largely prevent p-doping agents from being implanted into the p-region 50P. The p-doping agents can be boron, boron fluoride, indium, or the like, present in the region at a concentration of approximately 10 13 atoms / cm² -3 up to about 10 14 atoms / cm² -3The photoresist can be implanted. After implantation, it can be removed, for example, using a suitable detachment process.

[0029] Following implantation of the n-region 50N and the p-region 50P, a tempering process can be performed to repair implantation damage and activate the implanted p- and / or n-doping materials. In some embodiments, the grown materials of the epitaxial fins can be doped in situ during growth, thus eliminating the need for implantation; however, in-situ and implantation doping can also be used together.

[0030] In Fig. In step 5, a dielectric dummy layer 70 is fabricated on the fins 66 and / or the nanostructures 55. The dielectric dummy layer 70 can, for example, comprise silicon oxide, silicon nitride, a combination thereof, or the like, and can be deposited or thermally grown using suitable methods. A dummy gate layer 72 is fabricated over the dielectric dummy layer 70, and a mask layer 74 is fabricated over the dummy gate layer 72. The dummy gate layer 72 can be deposited over the dielectric dummy layer 70 and subsequently planarized, for example, using CMP. The mask layer 74 can be deposited over the dummy gate layer 72. The dummy gate layer 72 can have a conductive or non-conductive material selected from the group consisting of amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides and metals.The dummy gate layer 72 can be deposited by physical vapor deposition (PVD), CVD, sputtering, or other suitable methods for depositing the selected material. The dummy gate layer 72 can also be made of other materials that exhibit high etch selectivity with respect to the etching of insulating regions. The mask layer 74, for example, can be silicon nitride, silicon oxide nitride, or the like. In this example, only one dummy gate layer 72 and only one mask layer 74 are fabricated across the n-region 50N and the p-region 50P. It should be noted that, for illustrative purposes, the dielectric dummy layer 70 is shown as a single layer covering only the fins 66 and the nanostructures 55.In some embodiments, the dielectric dummy layer 70 can be deposited such that it covers the STI areas 68, so that the dielectric dummy layer 70 extends between the dummy gate layer 72 and the STI areas 68.

[0031] The Fig. Sections 6A to 18C show various further steps in the manufacture of the example devices. Fig. 6A, Fig. 7A, Fig. 8A, Fig. 9A, Fig. 10A, Fig. 11A, Fig. 12A, Fig. 12C, Fig. 13A, Fig. 13C, Fig. 14A, Fig. 15A and Fig. 18C show structural elements in the n-regions 50N or the p-regions 50P. In the Fig. 6A and Fig. 6B can be the mask layer 74 (see Fig. 5) are structured using suitable photolithographic and etching processes to produce masks 78. The structure of the masks 78 is then transferred to the dummy gate layer 72 and the dielectric dummy layer 70 to produce dummy gates 76 and dummy gate dielectrics 71, respectively. The dummy gates 76 cover respective channel regions of the fins 66. The structure of the masks 78 can be used to physically separate each of the dummy gates 76 from adjacent dummy gates 76. The dummy gates 76 can also have a longitudinal direction that is substantially perpendicular to the longitudinal direction of the respective fins 66.

[0032] In the Fig. 7A and Fig. 7B, a first spacer layer 80 and a second spacer layer 82 are produced over the structures that are in Fig. Figures 6A and 6B are shown. The first spacer layer 80 and the second spacer layer 82 are subsequently structured to function as spacers for creating self-adjusting source / drain regions. In the Fig. 7A and Fig. In 7B, the first spacer layer 80 is fabricated at the following locations: on the top surfaces of the STI regions 68; on the top and side walls of the fins 66, the nanostructures 55, and the masks 78; and on the side walls of the dummy gates 76 and the dummy gate dielectrics 71. The second spacer layer 82 is deposited over the first spacer layer 80. The first spacer layer 80 can be made of silicon oxide, silicon nitride, silicon oxide nitride, or the like, and can be fabricated by processes such as thermal oxidation or deposited by CVD, ALD, or the like. The second spacer layer 82 can be made of a material having a different etch rate than the material of the first spacer layer 80, such as silicon oxide, silicon nitride, silicon oxide nitride, or the like, and can be deposited by CVD, ALD, or the like.

[0033] After the fabrication of the first spacer layer 80 and before the fabrication of the second spacer layer 82, implantations for lightly doped source / drain regions (LDD regions; not shown individually) can be performed. In embodiments with different device types, similar to the implantations discussed above, a mask, such as a photoresist, can be fabricated over the n-region 50N while the p-region 50P remains exposed, and dopants of a corresponding doping type (e.g., p-conducting) can be implanted into the exposed fins 66 and the nanostructures 55 in the p-region 50P. Subsequently, the mask can be removed. Then, a mask, such as a photoresist, can be fabricated over the p-region 50P while the n-region 50N remains exposed, and dopants of a corresponding doping type (e.g., p-conducting) can be implanted into the exposed fins 66 and the nanostructures 55 in the p-region 50P.n-conducting materials can be implanted into the exposed fins 66 and the nanostructures 55 in the n-region 50N. Subsequently, the mask can be removed. The n-doping materials can be some of the n-doping materials discussed above, and the p-doping materials can be some of the p-doping materials discussed above. The lightly doped source / drain regions can have a doping concentration of approximately 1 × 10⁻⁶. 15 atoms / cm² -3 up to about 1 × 10 19 atoms / cm² -3 have. A tempering process can repair implant damage and activate the implanted dopants.

[0034] In the Fig. 8A and Fig. In step 8B, the first spacer layer 80 and the second spacer layer 82 are etched to produce first spacers 81 and second spacers 83. As will be explained in more detail later, the first spacers 81 and the second spacers 83 function by self-aligning subsequently fabricated source / drain regions and protecting the sidewalls of the fins 66 and / or the nanostructures 55 during subsequent processing. The first spacer layer 80 and the second spacer layer 82 can be etched using a suitable etching process, such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), or the like.In some embodiments, the material of the second spacer layer 82 has a different etch rate than the material of the first spacer layer 80, so that the first spacer layer 80 can act as an etch stop layer during the structuring of the second spacer layer 82, and the second spacer layer 82 can act as a mask during the structuring of the first spacer layer 80. For example, the second spacer layer 82 can be etched using an anisotropic etching process in which the first spacer layer 80 acts as an etch stop layer, with remaining portions of the second spacer layer 82 forming the second spacers 83, as shown in [Figure]. Fig. 8A is shown. Subsequently, the second spacers 83 act as a mask during the etching of exposed parts of the first spacer layer 80, so that the first spacers 81 are formed, as shown in Fig. 8A is shown.

[0035] As in further Fig. As shown in Figure 8A, the first spacers 81 and the second spacers 83 are arranged on the side walls of the fins 66 and / or the nanostructures 55. As shown in Fig. As shown in Figure 8B, in some embodiments the second spacer layer 82 above the first spacer layer 80 adjacent to the masks 78, the dummy gates 76, and the dummy gate dielectrics 71 can be removed, and the first spacers 81 are arranged on the side walls of the masks 78, the dummy gates 76, and the dummy gate dielectrics 71. In other embodiments, a portion of the second spacer layer 82 above the first spacer layer 80 adjacent to the masks 78, the dummy gates 76, and the dummy gate dielectrics 71 can remain.

[0036] It should be noted that the above description is a general method for producing spacers and LDD regions. However, other methods and procedures can also be used. For example, fewer or more spacers can be used, a different sequence of steps can be employed (e.g., the first spacers 81 can be structured before the deposition of the second spacer layer 82), additional spacers can be produced and removed, and / or the like. Furthermore, the n- and p-devices can be produced using different structures and steps.

[0037] In the Fig. 9A and Fig. In step 9B, initial recesses 86 are created in the fins 66, the nanostructures 55, and the substrate 50. Subsequently, epitaxial source / drain regions are produced in the initial recesses 86. The initial recesses 86 can extend through the first nanostructures 52 and the second nanostructures 54 and into the substrate 50. As shown in Fig. As shown in Figure 9A, the top surfaces of the STI regions 68 can be at the same level as the bottom surfaces of the first recesses 86. In various embodiments, the fins 66 can be etched such that the bottom surfaces of the first recesses 86 are located below the top surfaces of the STI regions 68, or the like. The first recesses 86 can be produced by etching the fins 66, the nanostructures 55, and the substrate 50 using anisotropic etching processes such as RIE, NBE, or the like. The first spacers 81, the second spacers 83, and the masks 78 mask parts of the fins 66, the nanostructures 55, and the substrate 50 during the etching processes used to produce the first recesses 86. A single etching process or multiple etching processes can be used to etch each layer of the nanostructures 55 and / or the fins 66.Time-controlled etching processes can be used to stop the etching of the first recesses 86 after reaching a desired depth.

[0038] In the Fig. 10A and Fig. In step 10B, portions of the sidewalls of the layers of the multilayer stack 64, which are made from the first semiconductor materials (e.g., the first nanostructures 52) exposed by the first recesses 86, are etched to create sidewall recesses 88 in the n-region 50N, and portions of the sidewalls of the layers of the multilayer stack 64, which are made from the second semiconductor materials (e.g., the second nanostructures 52) exposed by the first recesses 86, are etched to create sidewall recesses 88 in the p-region 50P. The sidewalls of the first nanostructures 52 and the second nanostructures 54 in the recesses 88 are in Fig. Although 10B is shown as straight sidewalls, they can also be concave or convex. The sidewalls can be etched using isotropic etching processes, such as wet etching or the like. The p-region 50P can be protected by a mask (not shown) while etchants selective for the first semiconductor materials are used to etch the first nanostructures 52, so that the second nanostructures 54 and the substrate 50 remain relatively unetched compared to the first nanostructures 52 in the n-region 50N. Similarly, the n-region 50N can be protected by a mask (not shown) while etchants selective for the second semiconductor materials are used to etch the second nanostructures 54, so that the first nanostructures 52 and the substrate 50 remain relatively unetched compared to the second nanostructures 54 in the p-region 50P. In an embodiment where the first nanostructures 52 are, for example,If the first nanostructures 52 have SiGe and the second nanostructures 54 have e.g. Si or SiC, a dry etching process with tetramethylammonium hydroxide (TMAH), hydrated ammonia (NH4OH) or the like can be used to etch sidewalls of the first nanostructures 52 in the n-region 50N, and a dry etching process with hydrogen fluoride, another fluorine-based gas or the like can be used to etch sidewalls of the second nanostructures 54 in the p-region 50P.

[0039] In the Fig. In sections 11A to 11C, the first internal spacers 90 are produced in the side wall recesses 88. The first internal spacers 90 can be produced by depositing an internal spacer layer (not shown separately) over the structures located in the Fig. 10A and Fig. Figure 10B shows the first internal spacers 90, which act as insulating elements between subsequently fabricated source / drain regions and a gate structure. As will be explained in more detail later, source / drain regions are fabricated in the recesses 86, while the first nanostructures 52 in the n-region 50N and the second nanostructures 54 in the p-region 50P are replaced by corresponding gate structures.

[0040] The spacer layer can be deposited using a conformal deposition method, such as CVD, ALD, or the like. The spacer layer can be made of a material such as silicon nitride or silicon oxide nitride, but any suitable material can be used, such as materials with a low dielectric constant (low-k materials) having a k-value of less than approximately 3.5. The spacer layer can then be anisotropically etched to fabricate the first spacers 90. While it has been shown that the outer sidewalls of the first spacers 90 are flush with the sidewalls of the second nanostructures 54 in the n-region 50N and flush with the sidewalls of the first nanostructures 52 in the p-region 50P, the outer sidewalls of the first spacers 90 can also extend over the sidewalls of the second nanostructures 54 and 52, respectively.extend beyond the first nanostructures 52 or be excluded from them.

[0041] The outer side walls of the first internal spacers 90 are indeed in Fig. 11B is shown straight, but they can also be concave or convex. As an example, it shows Fig. 11C shows an embodiment in which the sidewalls of the first nanostructures 52 are concave, the outer sidewalls of the first inner spacers 90 are concave, and the first inner spacers 90 are recessed from the sidewalls of the second nanostructures 54 in the n-region 50N. Furthermore, embodiments are shown in which the sidewalls of the second nanostructures 54 are concave, the outer sidewalls of the first inner spacers 90 are concave, and the first inner spacers 90 are recessed from the sidewalls of the first nanostructures 52 in the p-region 50P. The inner spacer layer can be etched using an anisotropic etching process, such as RIE, NBE, or the like. The first inner spacers 90 can serve to prevent damage to subsequently fabricated source / drain regions (such as the epitaxial source / drain regions 92, which are subsequently described with reference to the Fig. 12A to 12C will be discussed) to avoid subsequent etching processes, such as etching processes for manufacturing gate structures.

[0042] In the Fig. In 12A to 12C, epitaxial source / drain regions 92 are produced in the first recesses 86. In some embodiments, the source / drain regions 92 can apply a mechanical stress to the second nanostructures 54 in the n region 50N and to the first nanostructures 52 in the p region 50P, thereby improving performance. As shown in Fig. As shown in Figure 12B, the epitaxial source / drain regions 92 are manufactured in the first recesses 86 such that each dummy gate 76 is located between respective adjacent pairs of epitaxial source / drain regions 92. In some embodiments, the first spacers 81 are used to separate the epitaxial source / drain regions 92 from the dummy gates 76, and the first internal spacers 90 are used to separate the epitaxial source / drain regions 92 from the nanostructures 55 by a corresponding lateral distance, so that the epitaxial source / drain regions 92 do not short-circuit subsequently manufactured gates of the resulting nano-FETs.

[0043] The epitaxial source / drain regions 92 in the n-region 50N, e.g., the NMOS region, can be fabricated by masking the p-region 50P, e.g., the PMOS region. The epitaxial source / drain regions 92 are then epitaxially grown in the first recesses 86 in the n-region 50N. The epitaxial source / drain regions 92 can comprise a suitable material for n-nanoFETs. If the second nanostructures 54 are, for example, silicon, then the epitaxial source / drain regions 92 can comprise materials that exert a tensile stress on the second nanostructures 54, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, or the like. The epitaxial source / drain regions 92 can have surfaces that are raised relative to the respective top surfaces of the nanostructures 55, and they can have chamfers.

[0044] The epitaxial source / drain regions 92 in the p-region 50P, e.g., the PMOS region, can be fabricated by masking the n-region 50N, e.g., the NMOS region. The epitaxial source / drain regions 92 are then epitaxially grown in the first recesses 86 in the p-region 50P. The epitaxial source / drain regions 92 can comprise a suitable material for p-nanoFETs. If the first nanostructures 52 are, for example, silicon germanium, then the epitaxial source / drain regions 92 can comprise materials that exert a compressive stress on the first nanostructures 52, such as silicon germanium, boron-doped silicon germanium, germanium, germanium-tin, or the like. The epitaxial source / drain regions 92 may have surfaces that are raised relative to the respective top surfaces of the multilayer stack 64, and they may have chamfers.

[0045] The epitaxial source / drain regions 92, the first nanostructures 52, the second nanostructures 54, and / or the substrate 50 can be implanted with dopants to create source / drain regions, similar to the process discussed above for fabricating lightly doped source / drain regions, and can subsequently be annealed. The source / drain regions can have a doping concentration of approximately 1 × 10 19 atoms / cm² -3 up to about 1 × 10 21 atoms / cm² -3 The n- and / or p-doping agents for the source / drain regions can be those discussed above. In some embodiments, the epitaxial source / drain regions 92 can be doped in situ during growth.

[0046] Through the epitaxial processes used to create the source / drain regions 92 in the n-region 50N and the p-region 50P, the top surfaces of the epitaxial source / drain regions 92 have chamfers that extend laterally outward beyond the side walls of the nanostructures 55. In some embodiments, these chamfers cause adjacent epitaxial source / drain regions 92 of the same NSFET to merge, as shown in Fig. 12A is shown. In other embodiments, adjacent epitaxial source / drain regions 92 remain separated after the completion of the epitaxial process, as shown in Fig. 12C is shown. In the embodiments shown in the Fig. 12A and Fig. As shown in Figure 12C, the first spacers 81 can be fabricated on a top surface of the STI regions 68, thus blocking epitaxial growth. In other embodiments, the first spacers 81 can cover portions of the sidewalls of the nanostructures 55, further blocking epitaxial growth. In still other embodiments, the spacer etching used to fabricate the first spacers 81 can be modified to remove the spacer material, allowing the epitaxially grown region to extend to the surface of the STI region 68.

[0047] The epitaxial source / drain regions 92 can have one or more semiconductor material layers. For example, the epitaxial source / drain regions 92 can have a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. However, any number of semiconductor material layers can be used for the epitaxial source / drain regions 92. The first semiconductor material layer 92A, the second semiconductor material layer 92B, and the third semiconductor material layer 92C can each be made of different semiconductor materials and can be doped to different doping concentrations. In some embodiments, the first semiconductor material layer 92A can have a doping concentration that is lower than that of the second semiconductor material layer 92B and higher than that of the third semiconductor material layer 92C.In embodiments in which the epitaxial source / drain regions 92 have three semiconductor material layers, the first semiconductor material layer 92A can be deposited, the second semiconductor material layer 92B can be deposited over the first semiconductor material layer 92A, and the third semiconductor material layer 92C can be deposited over the second semiconductor material layer 92B.

[0048] Fig. Figure 12D shows an embodiment in which the side walls of the first nanostructures 52 in the n-region 50N and the side walls of the second nanostructures 54 in the p-region 50P are concave, the outer side walls of the first inner spacers 90 are concave, and the first inner spacers 90 are recessed from the side walls of the second nanostructures 54 and the first nanostructures 52, respectively. As shown in Fig. As shown in Figure 12D, the epitaxial source / drain regions 92 can be made in contact with the first internal spacers 90 and can extend beyond the side walls of the second nanostructures 54 in the n region 50N and beyond the side walls of the first nanostructures 52 in the p region 50P.

[0049] In the Fig. In 13A to 13C, a first interlayer dielectric (ILD) 96 is deposited over the structure that is in the Fig. 6A, Fig. 12B or 12A is shown (the processes of the Fig. 7A to 12D change the in Fig. (cross-section shown in Figure 6A not shown). The first ILD 96 can be made of a dielectric material and can be deposited by a suitable process such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Suitable dielectric materials include phosphorus silicate glass (PSG), borosilicate glass (BSG), boron phosphorus silicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials deposited by a suitable process can also be used. In some embodiments, a contact etch stop layer (CESL) 94 is deposited between the first ILD 96 and the epitaxial source / drain regions 92, the masks 78, and the first spacers 81. The CESL 94 can comprise a dielectric material, such as silicon nitride, silicon oxide, silicon oxide nitride, or the like, which has a different etch rate than the material of the overlying first ILD 96.

[0050] In the Fig. In 14A to 14C, a planarization process, such as a CMP, can be performed to bring the top surface of the first ILD 96 to the same level as the top surfaces of the dummy gates 76 or the masks 78. The planarization process can also remove the masks 78 on the dummy gates 76 and portions of the first spacers 81 along the side walls of the masks 78. After the planarization process, the top surfaces of the dummy gates 76, the first spacers 81, and the first ILD 96 are at the same level within process variations. Accordingly, the top surfaces of the dummy gates 76 are exposed by the first ILD 96. In some embodiments, the masks 78 can remain, and in this case, the planarization process brings the top surface of the first ILD 96 to the same level as the top surfaces of the masks 78 and the first spacers 81.

[0051] In the Fig. 15A and Fig. In 15B, the dummy gates 76 and, if present, the masks 78 are removed in one or more etching steps, creating second recesses 98. Parts of the dummy gate dielectrics 71 in the second recesses 98 are also removed. In some embodiments, the dummy gates 76 and the dummy gate dielectrics 71 are removed using an anisotropic dry etching process. The etching process can, for example, be a dry etching process using one or more reactive gases that selectively etch the dummy gates 76 at a higher rate than the first ILD 96 or the first spacers 81. The second recesses 98 expose and / or cover parts of the nanostructures 55, which function as channel regions in subsequently completed nanoFETs. Parts of the nanostructures 55, which function as the channel regions, are arranged between adjacent pairs of epitaxial source / drain regions 92.During removal, the dummy gate dielectrics 71 can be used as etch stop layers when the dummy gates 76 are etched. The dummy gate dielectrics 71 can then be removed after the dummy gates 76 have been removed.

[0052] According to some embodiments, in the Fig. 16A to 21B define nanostructures in the p-region 50P and the n-region 50N, and produce dielectric gate layers and gate electrodes for replacement gates. The dielectric gate layers can be produced simultaneously in the p-region 50P and the n-region 50N, such that the dielectric gate layers in each region consist of the same materials, and the gate electrodes can also be produced simultaneously, so that they consist of the same materials in each region. In some embodiments, the dielectric gate layers in each region can be produced by different methods, such that they may have different materials and / or different numbers of layers, and / or the gate electrodes in each region can be produced by different methods, such that they may have different materials and / or different numbers of layers.Various masking steps can be used to mask and expose corresponding areas when different processes are employed. In the following description, the gate electrodes of the n-region 50N and the p-region 50P are fabricated separately.

[0053] In the Fig. 16A and Fig. 16B The second nanostructures 54 in the p-region 50P can be removed by fabricating a mask (not shown) over the n-region 50N and performing an isotropic etching process, such as wet etching or the like, using etchants that are selective for the materials of the second nanostructures 54, while the first nanostructures 52, the substrate 50, and the STI regions 68 remain relatively unetched compared to the second nanostructures 54. In embodiments where the second nanostructures 54 comprise, for example, SiGe and the first nanostructures 52 comprise, for example, Si or SiC, hydrogen fluoride, another fluorine-based gas, or the like can be used to remove the second nanostructures 54 in the p-region 50P.

[0054] As in Fig. As shown in Figure 16A, the first nanostructures 52 can have a height H1 and a width W1, where the ratio of height H1 to width W1 can be approximately 0.05 to approximately 4. In some embodiments, the ratio is sufficient to prevent interference with an inrush current I during the deposition process. on to prevent the device from malfunctioning, while still maintaining good control over the device. For example, it has been found that if the ratio of height H1 to width W1 is greater than 4, the channel area of ​​the nano-FET may be too thick and the I on which can impair the resulting device. And it has been found that if the ratio of height H1 to width W1 is less than 4, due to a physical limitation of the layer deposition process, the channel area may be too thin to be controlled during deposition.

[0055] In other embodiments, the channel regions in the n-region 50N and the p-region 50P can be produced simultaneously, for example by removing the first nanostructures 52 in the n-region 50N and the p-region 50P or by removing the second nanostructures 54 in the n-region 50N and the p-region 50P. In these embodiments, channel regions of n-NSFETs and p-NSFETs can have the same material composition, such as silicon, silicon germanium, or the like. Fig. 26A, Fig. 26B and Fig. Figure 26C shows a structure resulting from these embodiments, wherein the channel regions in the p-region 50P and the n-region 50N are provided by the second nanostructures 54 and comprise, for example, silicon. In these embodiments, the second nanostructures 54 can have the same dimensions as those described above for the first nanostructures 52. Fig. 16A have been specified.

[0056] The Fig. Figures 17A to 19B show the fabrication of the gate dielectrics 100 and the gate electrodes 102 in the p-region 50P, wherein the n-region 50N can be masked at least during the fabrication of the gate electrodes 102 in the p-region 50P (as shown, for example, below with reference to the Fig. (as set out in sections 18A to 19B).

[0057] In the Fig. 17A and Fig. In 17B, gate dielectrics 100 are conformally deposited in the second recesses 98 in the p-region 50P. The gate dielectrics 100 have one or more dielectric layers, such as an oxide, a metal oxide, or the like, or combinations thereof. In some embodiments, the gate dielectrics 100 can, for example, have a first gate dielectric 101 (comprising, for example, silicon oxide or the like) and a second gate dielectric 103 (comprising, for example, a metal oxide or the like) above the first gate dielectric 101. In some embodiments, the second gate dielectric 103 comprises a high-k dielectric material, and in these embodiments, the second gate dielectric 103 may have a k-value greater than about 7.0 and may comprise a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, or combinations thereof.In some embodiments, the first gate dielectric 101 can be described as an interface layer, and the second gate dielectric 103 can be described as a high-k gate dielectric.

[0058] The structures of the gate dielectrics 100 can be the same or different in the n-region 50N and the p-region 50P. For example, the n-region 50N can be masked or exposed in the p-region 50P during the fabrication of the gate dielectrics. In embodiments where the n-region 50N is exposed, the gate dielectrics 100 can be fabricated simultaneously in the n-region 50N. Molecular beam deposition (MBD), ALD, PECVD, and similar processes can be used as fabrication methods for the gate dielectrics 100.

[0059] In the Fig. 18A and Fig. In embodiment 18B, a conductive material 105 is conformally deposited on the gate dielectrics 100 in the p-region 50P. In some embodiments, the conductive material 105 is a p-WFM layer comprising titanium nitride, tantalum nitride, tungsten nitride, molybdenum nitride, or the like. The conductive material 105 can be deposited by CVD, ALD, PECVD, PVD, or the like. In some embodiments, the conductive material 105 can be deposited on exposed surfaces of the gate dielectrics 100 with sufficient thickness to fuse in regions 50I between adjacent first nanostructures 52 (e.g., first nanostructures 52A, 52B, and 52C).The conductive material 105 can, for example, be deposited on the surfaces of the first nanostructures 52 in regions 50I, and as the thickness of the conductive material 105 increases during deposition, separate parts of the conductive material 105 can touch and fuse together along seams 105S. In particular, the deposition of the conductive material 105 can continue until a first part 105A of the conductive material 105 fuses with a second part 105B of the conductive material 105 in regions 50I.

[0060] As in Fig. As shown in Figure 18A, the conductive material 105 can have a thickness T1 outside the regions 50I (e.g., the unfused regions of the conductive material 105) and a thickness T2 within the regions 50I (e.g., the fused regions of the conductive material 105). For example, the conductive material 105 can have a thickness T1 on sidewalls of the first nanostructures 52 and on a top surface of the first nanostructures 52. The thickness T1 can be large enough to fill a gap between adjacent first nanostructures 52, for example, first nanostructures 52A, 52B, and 52C. For example, the thickness T1 can be at least half the thickness T2, provided that the ratio of thickness T2 to thickness T1 is not more than approximately 2:1.

[0061] In some embodiments, the thickness T1 can be approximately 3 nm to 5 nm (30 Å to approximately 50 Å). It has been found that if the thickness T1 is greater than approximately 5 nm (50 Å), the volume of the conductive material 105 may be unnecessarily large and may restrict the process window for depositing a filler metal for the gate electrode (e.g., a filler metal 117, which will be discussed later). Furthermore, it has been found that if the thickness T1 is less than approximately 3 nm (30 Å), a conductive layer 10 may not adequately fill the space between adjacent first nanostructures 52, which may lead to unstable threshold voltage behavior in the resulting transistor.

[0062] The conductive material 105 has a width W2 at its narrowest point between the first nanostructures 52A. In some embodiments, the width W2 is approximately 10 nm to approximately 180 nm. It has been found that if the width W2 is greater than approximately 180 nm, the process control during the deposition of the conductive material 105 and during the structuring / etching of layers in the regions 50I can be negatively affected (e.g., similar to the effects of a high aspect ratio). It has also been found that if the width W2 is less than approximately 10 nm, the effective channel length can be too short, which can negatively impact the I on which can negatively affect the resulting transistor.

[0063] Furthermore, in some embodiments, the ratio of thickness T2 to width W2 is approximately 0.03 to approximately 1. It has been found that if the ratio of thickness T2 to width W2 is greater than approximately 1, a conductive layer 104 may be too thick, which would impair the I on The resulting transistor is negatively affected. It has also been found that if the ratio of thickness T2 to width W2 is less than approximately 0.03, the process control for depositing the conductive material 105 in the areas 50I can be negatively affected (e.g., similar to the effects of a high aspect ratio).

[0064] The conductive material 105 fills any remaining space between the first nanostructures 52. The regions 50I bridge, for example, a total distance between adjacent first nanostructures 52 (e.g., between first nanostructures 52A and 52B or between first nanostructures 52B and 52C). The regions 50I can be filled with a first part (e.g., first gate dielectric 100A) of the gate dielectric 100, a fused part of the conductive material 105 arranged above and in contact with the first gate dielectric 100A, and a second part (e.g., second gate dielectric 100B) of the gate dielectric 100 arranged above and in contact with the fused part of the conductive material 105. The first gate dielectrics 100A comprise an interface layer 101A and a high-k gate dielectric 103A, and the second gate dielectrics 100B comprise an interface layer 101B and a high-k gate dielectric 103B.This means that the conductive material 105 can extend continuously and can completely fill a region between parts of the gate dielectrics 100 on adjacent first nanostructures 52. It is important to note that there is no barrier layer separating different regions of the conductive material 105 in the regions 50I. For example, the gate electrode cannot have barrier layers in the regions 50I. By omitting a barrier layer in the inner regions 50I, the fabrication process can be simplified. Furthermore, it has been found that the thickness variation of the conductive material 105 (e.g., the difference between thicknesses T1 and T2) does not significantly affect the electrical performance of the resulting transistor. For example, in experiments, transistors with a conductive material 105 of different thicknesses (such as those found in the ) Fig. 18A and Fig. (as shown in Figure 18B) have an effective work function of about 4.89 V. In comparison, transistors with a more uniform WFM layer (made possible, for example, by an intervening depletion layer that prevents the WFM layer from fusing in regions 50I) had an effective work function of about 4.90 V. Therefore, with different embodiments, transistors with a similar effective work function can be more easily manufactured without significantly reducing the electrical performance of the resulting transistors.

[0065] In the Fig. In steps 19A to 19D, the remaining parts of the gate electrodes 102 are deposited such that they fill the remaining portions of the second recesses 98. For example, an adhesive layer 115 and a filler metal 117 can be deposited over the conductive material 105. The resulting gate electrodes 102 are manufactured for replacement gates and can comprise the conductive material 105, the adhesive layer 115, and the filler metal 117. Fig. Figure 19C shows a top-down view along a line X - X' of Fig. 19B (e.g. in areas 50I), while Fig. 19D a top-down view along a line Y - Y' of Fig. 19B shows (e.g. through the first nanostructures 52).

[0066] In some embodiments, the adhesive layer 115 is conformally deposited onto the conductive material 105 in the p-region 50P. In some embodiments, the adhesive layer 115 comprises titanium nitride, tantalum nitride, or the like. The adhesive layer 115 can be deposited by CVD, ALD, PECVD, PVD, or the like. The adhesive layer 115 can alternatively be described as an adhesive layer, and it improves, for example, the adhesion between the conductive material 105 and the filler metal 117 located above it.

[0067] The filler metal 117 can then be deposited over the adhesive layer 115. In some embodiments, the filler metal 117 is cobalt, ruthenium, aluminum, tungsten, a combination thereof, or the like, and it is deposited by CVD, ALD, PECVD, PVD, or the like. In some embodiments, the filler metal 117 can be tungsten deposited by a CVD process. It has been found that CVD allows for a better deposition rate for the filler metal 117. In some embodiments, the CVD process for depositing the filler metal 117 can include introducing a first precursor (e.g., WF6 or the like) and a second precursor (e.g., SiH4 or the like) into a CVD process chamber. In some embodiments, the first and second precursors can be introduced simultaneously during the CVD process for the filler metal 117.

[0068] In the p-area 50P, the gate dielectrics 100, the conductive material 105, the adhesive layer 115, and the filler metal 117 can each be deposited on the top, side, and bottom surfaces of the first nanostructures 52. The gate dielectrics 100, the conductive material 105, the adhesive layer 115, and the filler metal 117 can also be deposited on the top surfaces of the first ILD 96, the CESL 94, the first spacers 81, and the STI areas 68. After filling the second recesses 98, a planarization process, such as CMP, can be performed to remove the excess portions of the gate dielectrics 100, the conductive material 105, the adhesive layer 115, and the filler metal 117 located above the top surface of the first ILD 96. The remaining parts of the material of the gate electrodes 102 and the gate dielectrics 100 thus form replacement gate structures of the resulting nano-FETs.The gate electrodes 102 and the gate dielectrics 100 can be collectively referred to as “gate structures”.

[0069] The Fig. 19A and Fig. Figure 19B shows the gate dielectrics 100 and the gate electrodes 102 with straight side walls and rectangularly clipped corners, but the gate dielectrics and the gate electrodes 102 can also have a different configuration. For example, Figure 19B shows the gate dielectrics 100 and the gate electrodes 102 with straight side walls and rectangularly clipped corners. Fig. Figure 20 shows a sectional view of the gate dielectrics 100 and the gate electrodes 102 according to a further embodiment. Fig. 20 denote similar reference numbers, similar elements as in the Fig. 19A and Fig. 19B, which are produced using similar processes. However, in Fig. 20 because the first nanostructures have 52 rounded corners, the gate dielectrics 100 and the gate electrodes 102 also have rounded corners.

[0070] The Fig. 19A and Fig. Figure 19B shows that the lowest of the first nanostructures 52 touches a fin 66 located below it, but the lowest of the first nanostructures 52 (e.g., the first nanostructure 52A) can also be separated from the fin 66 located below it, as shown in Fig. 21 is shown. Fig. 20 denote similar reference numbers, similar elements as in the Fig. 19A and Fig. 19B, which are manufactured using similar processes. The structure of Fig. 21 can be produced, for example, by placing a second nanostructure 54 between the first nanostructure 52 and the fin 66 and subsequently removing the second nanostructure 54, as described above. This allows parts of the gate dielectrics 100 and the conductive material 105 to be located between the lowest of the first nanostructures 52 and the fin 66.

[0071] The Fig. 22A and Fig. Figure 22B shows a gate stack in the n-region 50N. Fabricating the gate stack in the n-region 50N can initially involve removing the first nanostructures 52 in the n-region 50N. The first nanostructures 52 can be removed by fabricating a mask (not shown) over the p-region 50P and performing an isotropic etching process, such as wet etching or the like, using etchants that are selective for the materials of the first nanostructures 52, while the second nanostructures 54, the substrate 50, and the STI regions 68 remain relatively unetched compared to the first nanostructures 52. In embodiments where the first nanostructures 52A to 52C are, for example, SiGe and the second nanostructures 54A to 54C are, for example, SiGe, the first nanostructures 52 can be removed by fabricating a mask (not shown) over the p-region 50P and performing an isotropic etching process, such as wet etching or the like, using etchants that are selective for the materials of the first nanostructures 52, while the second nanostructures 54, the substrate 50, and the STI regions 68 remain relatively unetched compared to the first nanostructures 52. B. Si or SiC, tetramethylammonium hydroxide (TMAH), hydrated ammonia (NH4OH) or the like can be used to etch the first nanostructures 52 in the n-range 50N.

[0072] The gate stack is then fabricated over and around the second nanostructures 54 in the n-region 50N. The gate stack comprises the gate dielectrics 100 and gate electrodes 127. In some embodiments, the gate dielectrics 100 in the n-region 50N and the p-region 50P can be fabricated simultaneously. Furthermore, at least some parts of the gate electrodes 127 can be fabricated either before or after the fabrication of the gate electrodes 102 (see Fig. 19A and Fig. 19B), and at least some parts of the gate electrodes 127 can be fabricated while the p-region 50P is masked. Therefore, the gate electrodes 127 can have different materials than the gate electrodes 102. For example, the gate electrodes 127 can have a conductive layer 121, a barrier layer 123, and a filler metal 125. The conductive layer 121 can be an n-WFM layer with an n-metal, such as titanium-aluminum, titanium-aluminum carbide, tantalum-aluminum, tantalum carbide, a combination thereof, or the like. The conductive layer 121 can be deposited by CVD, ALD, PECVD, PVD, or the like, and the barrier layer 123 can also function as an adhesive layer. The barrier layer 123 can be deposited by CVD, ALD, PECVD, PVD, or the like.The filler material 125 can be cobalt, ruthenium, aluminum, tungsten, a combination thereof, or the like, and can be deposited by CVD, ALD, PECVD, PVD, or the like. The filler material 125 can have the same material composition as the filler metal 117 and may or may not be deposited simultaneously with it.

[0073] After filling the second recesses 98, a planarization process, such as CMP, can be performed to remove the excess portions of the gate dielectrics 100 and gate electrodes 127 located above the top surface of the first ILD 96. The remaining portions of the gate electrode material 127 and gate dielectric material 100 thus form substitute gate structures of the resulting nanoFETs in the n-region 50N. The CMP processes for removing the excess material from the gate electrodes 102 in the p-region 50P and for removing the excess material from the gate electrodes 127 in the n-region 50N can be performed simultaneously or separately.

[0074] In the Fig. In steps 23A to 23C, the gate structure (comprising the gate dielectrics 100, the gate electrodes 102, and the gate electrodes 127) is recessed, creating a cavity directly above the gate structure and between opposing portions of the first spacers 81. A gate mask 104, comprising one or more layers of dielectric materials such as silicon nitride, silicon oxide nitride, or the like, is filled into the cavity, and subsequently, planarization is performed to remove excess portions of the dielectric material extending over the first ILD 96. Gate contacts manufactured later (such as gate contacts 114, which are described later with reference to the Fig. 24A and Fig. (discussed in 24B) penetrate the gate mask 104 to contact a top side of the recessed gate electrodes 102 and 127.

[0075] As also in the Fig. As shown in Figures 23A to 23C, a second ILD 106 is deposited over the first ILD 96 and the gate mask 104. In some embodiments, the second ILD 106 is a flowable layer produced by FCVD. In other embodiments, the second ILD 106 is made from a dielectric material such as PSG, BSG, BPSG, USG, or the like, and can be deposited by a suitable method such as CVD, PECVD, or the like.

[0076] In the Fig. In steps 24A to 24C, the second ILD 106, the first ILD 96, the CESL 94, and the gate masks 104 are etched to create third recesses 108 that expose the surfaces of the epitaxial source / drain regions 92 and / or the gate structure. The third recesses 108 can be created by etching with an anisotropic etching process such as RIE, NBE, or the like. In some embodiments, the third recesses 108 can be etched through the second ILD 106 and the first ILD 96 in a first etching process, through the gate masks 104 in a second etching process, and then through the CESL 94 in a third etching process. A mask, such as a photoresist, can be produced and structured over the second ILD 106 to protect parts of the second ILD 96 against the first and second etching processes.In some embodiments, the etching process may be over-etching, and therefore the third recesses 108 extend into the epitaxial source / drain regions 92 and / or the gate structure, and an underside of the third recesses 108 may be in the same plane as the epitaxial source / drain regions 92 and / or the gate structure, e.g., at the same level as them or at the same distance from the substrate as they are, or the underside of the third recesses 108 may be lower than the epitaxial source / drain regions 92 and / or the gate structure, e.g., closer to the substrate. Fig. Although Figure 23B shows that the third recesses 108 expose the epitaxial source / drain regions 92 and the gate structure in the same cross-section, in different embodiments the epitaxial source / drain regions 92 and the gate structure can be exposed in different cross-sections, thereby reducing the risk of short-circuiting subsequently manufactured contacts.

[0077] After the third recesses 108 have been created, silicide regions 110 are produced over the epitaxial source / drain regions 92. In some embodiments, the silicide regions 110 are produced as follows. First, a metal (not shown) that can react with the semiconductor materials of the underlying epitaxial source / drain regions 92 (e.g., silicon, silicon germanium, germanium) to form silicide or germanide regions, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, another precious metal, another refractory metal, a rare earth metal, or an alloy thereof, is deposited over the exposed portions of the epitaxial source / drain regions 92. Subsequently, a thermal annealing process is carried out to produce the silicide regions 110. Then, the unreacted portions of the deposited metal are removed, e.g., by an etching process.Although the silicide regions 110 are referred to as silicide regions, they can also be germanide regions or silicon germanide regions (i.e., regions containing both silicide and germanide). In one embodiment, the silicide region 110 contains TiSi and has a thickness of approximately 2 nm to approximately 10 nm.

[0078] Then in the Fig. In embodiments 25A to 25C, contacts 112 and 114 (which can also be referred to as contact pins) are manufactured in the third recesses 108. Contacts 112 and 114 can each have one or more layers, such as barrier layers, diffusion layers, and filler materials. In some embodiments, for example, contacts 112 and 114 each have a barrier layer and a conductive material, and they are each electrically connected to the underlying conductive structural element (e.g., the gate electrodes 102, the gate electrodes 127, and / or the silicide area 110 in the illustrated embodiment). Contacts 114 are electrically connected to the gate electrodes 102 and 127 and can be referred to as gate contacts, and contacts 112 are electrically connected to the silicide areas 110 and can be referred to as source / drain contacts. The barrier layer may contain titanium, titanium nitride, tantalum, titanium nitride or the like.The conductive material can be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as CMP, can be performed to remove excess material from one surface of the second ILD 106.

[0079] The Fig. Figures 26A to 26C show sectional views of a device according to some alternative embodiments. Fig. 26A shows a reference cross-section A - A', which is in Fig. 1 is shown. Fig. 26B shows a reference cross-section B - B', which is in Fig. 1 is shown. Fig. 26C shows a reference cross-section C - C' which is in Fig. 1 is shown. In the Fig. 26A to 26C denote similar reference numbers, similar elements, which are associated with similar processes, such as the structure of the Fig. 25A to 25C are manufactured. In the Fig. However, nanostructures 26A to 26C have channel regions in the n-region 50N and the p-region 50P made of the same material. For example, the second nanostructures 54, which contain silicon, provide channel regions for p-NSFETs in the p-region 50P and for n-NSFETs in the n-region 50N. The structure of Fig. 26A to 26C can be produced, for example, as follows: simultaneous removal of the first nanostructures 52 from the p-region 50P and the n-region 50N; deposition of the gate dielectrics 100 and the gate electrodes 102 around the second nanostructures 54 in the p-region 50P; and deposition of the gate dielectrics 100 and the gate electrodes 102 around the first nanostructures 54 in the n-region 50N.

[0080] In various embodiments, a gate stack of a transistor (e.g., a nanoFET) is provided without a depletion layer between adjacent nanostructures. It has been found that thickness variations due to fused areas of the WFM layers (e.g., between nanowires of a nanoFET) do not significantly affect the electrical properties of the transistor (e.g., relatively similar effective work functions have been observed). Furthermore, by not depositing a depletion layer around the WFM layer (e.g., to prevent fusion of parts of the WFM layer), fabrication can be simplified. This is particularly relevant for modern semiconductor nodes with small feature sizes, since depletion layer materials (e.g., tantalum nitride or the like) are difficult to deposit in small spaces.Thus, by omitting these barrier layers in the gate stacks and by merging the WFM layers in certain areas, manufacturing can be simplified, and manufacturing defects (which arise, for example, from poor barrier layer deposition) can be reduced without significantly affecting the electrical performance of the resulting transistor.

[0081] The invention is defined by the main claim and the dependent claims. Further embodiments of the invention are described by the dependent claims.

Claims

[1] Device with: a first nanostructure (52A); a second nanostructure (52B) above the first nanostructure (52A); a first high-k gated dielectric (103) arranged around the first nanostructure (52A); a second high-k gated dielectric (103A) arranged around the second nanostructure (52B); and a gate electrode (102), above the first high-k gate dielectric (103) and the second high-k gate dielectric (103A), wherein a part of the gate electrode (102) between the first nanostructure (52A) and the second nanostructure (52B) has a first part of a p-exit work metal (105), wherein the first part of the p-exit work metal (105) fills an entire region between the first high-k gate dielectric (103) and the second high-k gate dielectric, and wherein the first part of the p-exit work metal (105) consists throughout of the same material, and wherein the first part of the p-exit work metal (105) has a first thickness (T2) and a second part of the p-exit work metal (105) on a side wall of the first nanostructure (52A) has a second thickness (T1), wherein the first thickness (T2) is greater than the second thickness (T1). [2] Device according to claim 1, wherein the first part of the p-exit work metal (105) has a seam (105S) between the first and the second nanostructure (52A, 52B). [3] Device according to claim 1 or 2, wherein the p-exit work metal (105) comprises titanium niride. [4] Device according to claim 3, wherein the ratio of the first thickness (T2) to the second thickness (T1) is not greater than 2 :

1. [5] Device according to claim 3 or 4, wherein the second thickness (T1) is 3 nm to 5 nm. [6] Device according to one of claims 3 to 5, wherein the ratio of the second thickness (T1) to a minimum width (W2) of the p-exit working metal (105) is 0.03 to 1. [7] Device according to claim 6, wherein the minimum width (W2) of the p-exit working metal (105) is 10 nm to 180 nm. [8] Device according to one of the preceding claims, wherein the part of the gate electrode (102) between the first high-k-gate dielectric (103) and the second high-k-gate dielectric (103A) has no barrier layers. [9] Device according to one of the preceding claims, wherein the gate electrode (102) further comprises an adhesive layer (115) over the p-exit work metal (105), wherein the adhesive layer (115) does not extend between the first nanostructure (52A) and the second nanostructure (52B). [10] Device according to one of the preceding claims, wherein the ratio of a height (H1) of the first nanostructure (52A) to a width (W1) of the first nanostructure (52A) is 0.05 to 4. [11] Transistor with: a first nanostructure (52A) over a semiconductor substrate (50); a second nanostructure (52B) above the first nanostructure (52A); a gate dielectric (103) enclosing the first nanostructure (52A) and the second nanostructure (52B); and a gate electrode (102) above the gate dielectric (103), wherein the gate electrode (102) has the following: a p-type exit work metal (105), wherein the p-type exit work metal (105) extends continuously from a first part of the gate dielectric (103) on the first nanostructure (52A) to a second part of the gate dielectric (103) on the second nanostructure (52B), wherein the p-type exit work metal (105) fills an entire region between the first part of the gate dielectric (103) and the second part of the gate dielectric (103), and the p-type exit work metal (105) is composed of the same material throughout, and wherein the p-type exit work metal (105) has a first thickness (T1) on a top side of the second nanostructure and a second thickness (T2) between the first nanostructure and the second nanostructure, wherein the first thickness (T1) is less than the second thickness (T2); and an adhesive layer (115) over the p-exit work metal (105), and a filler metal (117) above the adhesive layer (115). [12] Transistor according to claim 11, wherein the ratio of the second thickness (T2) to the first thickness (T1) is not greater than 2 :

1. [13] Transistor according to claim 11 or 12, wherein the p-exit work metal (105) has a seam (105S) between the first nanostructure (52A) and the second nanostructure (52B). [14] Transistor according to any one of claims 11 to 13, wherein the p-exit work metal (105) comprises titanium niride. [15] Transistor according to one of claims 11 to 14, further comprising an interface layer (101) below the gate dielectric (103), wherein the interface layer (101) surrounds the first nanostructure (52A) and the second nanostructure (52B) and the gate dielectric (103) comprises a high-k material. [16] Procedure with the following steps: Depositing a gate dielectric (103) around a first nanostructure (52A) and a second nanostructure (52B), wherein the first nanostructure (52A) is arranged above the second nanostructure (52B); and Depositing a p-exit work metal (105) over the gate dielectric (103), wherein the depositing of the p-exit work metal (105) comprises the following: Deposition of a first part of the p-exit work metal (105) on a top side of the second nanostructure (52B) and a second part of the p-exit work metal (105) on a bottom side of the first nanostructure (52A), and Continuing the deposition of the p-type work metal (105) until the first part of the p-type work metal (105) merges with the second part of the p-type work metal (105), the p-type work metal (105) filling an entire region between the gate dielectric (103) around the first nanostructure and the gate dielectric (103) around the second nanostructure, and the p-type work metal being composed of the same material everywhere. wherein the deposition of the p-exit work metal (105) comprises a deposition of the p-exit work metal (105) such that it has a first thickness (T2) between the first nanostructure and the second nanostructure, and has a second thickness (T1) on a side wall of the first nanostructure, where the first thickness (T2) is greater than the second thickness (T1). [17] The method of claim 16, further comprising: Deposition of an adhesive layer (115) over the p-exit work metal (105); and Deposition of a filler metal (117) over the adhesive layer (115). [18] Method according to claim 16 or 17, wherein the p-exit work metal (105) comprises titanium niride. [19] Method according to claim 18, wherein the ratio of the first thickness (T2) to the second thickness (T1) is not greater than 2 :

1. [20] Method according to any one of claims 16 to 19, wherein the deposition of the p-exit work metal (105) comprises forming a seam (105S) between the first part of the p-exit work metal (105) and the second part of the p-exit work metal (105).

Images