Different via configurations for different via interface requirements

Abstract

Device comprising: a first source-drain contact (282A) arranged in a dielectric layer (254), wherein the first source-drain contact (282A) is in physical contact with a first source-drain element; a second source-drain contact (282B) arranged in the dielectric layer (254), wherein the second source-drain contact (282B) is in physical contact with a second source-drain element; a first via (350A) with a first via layer configuration arranged in the dielectric layer (254), wherein the first via (350A) extends into and is in physical contact with the first source-drain contact (282A); and a second via (350B) with a second via layer configuration arranged in the dielectric layer (254).wherein the second via (350B) extends into and is in physical contact with the second source-drain contact (282B), wherein the second via layer configuration differs from the first via layer configuration and a first thickness of the first via (350A) corresponds to a second thickness of the second via (350B), wherein: the first via (350A) and the second via (350B) each have in a first direction a first bottom interface profile with the first and second source-drain contacts (282B) respectively, and in a second direction a second bottom interface profile with the first and second source-drain contacts (282B) respectively, and the first direction differs from the second direction.The first soil boundary profile is defined by a substantially planar surface and the second soil boundary profile by a substantially curved surface.

Description

BACKGROUNDThe semiconductor industry has experienced exponential growth. As materials and integrated circuit (IC) designs have advanced in technology, generations of ICs have evolved in which the circuits have become smaller and more complex from generation to generation. As ICs develop, the functional density (i.e., the number of interconnected IC devices per chip area) has generally increased, while the geometry size (i.e., dimensions and / or size of ICs features and / or distances between these IC features) has decreased. Downsizing has typically been limited only by lithographic definition of ICs features at the ever decreasing geometry dimensions. However, when implementing smaller geometry metrics to achieve higher speed ICs (e.g., by reducing the distances electrical signals must travel), resistance-capacitance (RC) delay has proven to be a significant problem, cancelling some of the advantages achieved by downsizing and further downsizing ICs. An RC delay generally indicates a delay in the speed of electrical signals in an IC that results as a product of resistor (R) (i.e., how a material resists the flow of electrical current) and capacitance (C) (i.e., a material's ability to store electrical charge). Therefore, reducing both resistance and capacitance is desirable to reduce RC delay and optimize performance of scaled ICs. The effects of interconnects of ICs that physically and / or electrically connect IC devices and / or ICs features of the ICs on RC delay are particularly problematic. Thus, there is a need to improve interconnects of ICs and / or methods for fabricating the interconnects.US 2007 / 0 059 931 A1 discloses a contact structure with silicide layers, a semiconductor component which uses the same, and methods for producing the contact structure and the semiconductor component. The contact structure comprises a first conductive region and a second conductive region on a substrate. An insulating layer covers the first and second conductive regions. A first contact hole and a second contact hole are formed through the insulating layer and expose the first and second conductive regions, respectively. A first silicide layer having a first thickness is disposed on the first conductive region exposed by the first contact hole. A second silicide layer having a second thickness different from the first thickness is provided on the second conductive region exposed by the second contact hole. US 2015 / 0118 837 A1 discloses a method for producing a semiconductor integrated circuit (IC). A first conductive feature and a second conductive feature are provided. A first hard mask (HM) is formed on the first conductive feature. A patterned dielectric layer is formed over the first and second conductive features, with first openings for exposing the second conductive features. A first metal plug is formed in the first opening to contact the second conductive features. A second HM is formed on the first metal plug and another patterned dielectric layer is formed over the substrate, with second openings for exposing a subset of the first metal plugs and the first conductive features. A second metal plug is formed in the second openings.BRIEF DESCRIPTION OF THE DRAWINGSThe present disclosure may be best understood when the following detailed description is studied together with the accompanying figures. It should be emphasized that various features of the practice customary in the industry are correspondingly not shown to scale and are used only for illustrative purposes. Rather, the dimensions for the various features may be arbitrarily increased or decreased for purposes of illustration.FIGS. 1A and 1B are a flow diagram of a method for fabricating a portion of a multi-layer interconnect structure, in accordance with various aspects of the present disclosure.FIGS. 2 to 6, 7A to 11A, 7B to 11B, 7C to 11C, and 12 to 16 are schematic partial views of a (part or all of) IC device at various stages of manufacturing a multi-layer interconnect structure, such as the method of manufacturing the multi-layer interconnect structure of the IC device of FIGS. 1A and 1B, in accordance with some embodiments of the present disclosure.FIGS. 17A through 17C are partial schematic views of a (portion or all of) IC device having a multi-layer interconnect structure that may be fabricated with the method of FIGS. 1A and 1B, in accordance with other embodiments of the present disclosure.DETAILED DESCRIPTIONThe present disclosure relates generally to IC devices, and more particularly to multi-layer interconnect structures for IC devices.The following disclosure provides many different embodiments or examples for implementing different features of the invention. Hereinafter, specific examples of components and arrangements will be described for convenience of the present disclosure. In the following description, for forming a first element over or on a second element, for example, embodiments may include where the first and second elements are formed in direct contact, as well as embodiments where additional elements may be formed between the first and second elements such that the first and second elements may not be in direct contact. Spatial reference terms, such as "lower / r", "upper / r", "horizontal", "vertical", "above", "on", "below", "below", "up", "down", "up", "down", "down", etc., as well as derivatives thereof (e.g., "horizontal / r", "down / r", "up / r", etc.) also serve herein to facilitate disclosure of the relationship of one element to another. The terms spatially relative are intended to cover different orientations of the component having the features. Moreover, when a number or range of numbers is described as "about", "about", and the like, the term is intended to cover numbers that are in an appropriate range with respect to deviations that arise during manufacturing due to equipment, as is known to those of ordinary skill in the art. For example, based on known manufacturing tolerances associated with manufacturing an element having a property associated with the number, the number or range of numbers includes an appropriate range including the number described, such as within + / -10% of the number described. For example, a material layer having a thickness of "about 5 nm" may comprise a measurement range of 4.5 nm to 5.5 nm, where it is known to those of ordinary skill in the art that manufacturing tolerances associated with depositing the material layer are + / -10%. In addition, in the present disclosure, reference numerals and / or reference numerals may be repeated in the various examples. This repetition is for convenience and convenience and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.IC technologies continue to encounter the area of sub-20 nm technology nodes so that shrinking critical dimensions on device layers of ICs (e.g., gate lengths, gate spacings, fin spacings, etc.) have resulted in a corresponding shrinking of critical dimensions of the interconnects (e.g., dimensions for vias, dimensions for metal lines, spacings of vias, spacings of metal lines, etc.) that allow the device layers to function. This has led to new problems. Thus, vias to source-drain contacts (associated with source-drain features) and to gate structures typically have the same configuration and are fabricated using the same methods: filling a via opening in a dielectric layer with a metal fill layer disposed over a metal adhesive / barrier layer, the metal adhesive / barrier layer configured to improve adhesion between the vias and the dielectric layer (e.g., the metal adhesive / barrier layer covers sidewalls of the via opening defined by the dielectric layer), reduce contact resistance, and / or prevent components of the via from diffusing into the environment thereof. As critical dimensions of vias shrink, the metal adhesive / barrier layer requires more space in the via opening, thus reducing a residue of the via opening for the metal fill layer. This results in poor filling of the gap with metal because the metal fill layer is unable to fill the remainder of the via opening without gaps (or voids) forming, thereby significantly increasing contact resistance. One solution is to eliminate the metal glue / barrier layer and make barrier-free vias. However, it has been observed that some vias, such as vias to gate structures, require metal glue / barrier layer to optimally reduce contact resistance, while in other vias, such as vias to source-drain contacts, the metal glue / barrier layer must be eliminated to optimally reduce contact resistance.The present disclosure therefore proposes a mixture of via configurations to accommodate different via interface requirements. For example, to optimally reduce contact resistance, the present disclosure proposes fabricating vias on a same level of a multi-level interconnect (MLI) structure (e.g., vias in a bottom-most via layer (Mo)) having different configurations / structures. In some embodiments, vias to gate structures include a metal glue / barrier layer, while vias to source-drain contacts do not include a metal glue / barrier layer. In the vias to the source-drain contacts, the proposed via fabrication methods include forming via openings in a dielectric layer exposing the source-drain contacts, recessing the source-drain contacts to enlarge the via openings, filling the enlarged via openings with a first metal fill material using a bottom-up deposition (bottom-up deposition) process, forming a metal glue / barrier layer over the first metal fill material (e.g., via a conformal deposition process), forming a second metal fill material over the metal glue / barrier layer (e.g., via a blanket deposition process), and performing a planarization process on the second metal fill material, The method may include removing metal glue / barrier layer and / or first metal fill material over a top surface of the dielectric layer. In the vias to the gate structures, the proposed via fabrication methods include forming via openings in a dielectric layer exposing the gate structures, forming a second metal adhesive / barrier layer on sidewalls of the via openings defined by the dielectric layer and a bottom of the via openings defined by the gate structure (e.g., via a conformal deposition process), forming a third metal fill material over the second metal adhesive / barrier layer, and filling a remainder of the via openings (e.g., via a blanket deposition process), and performing a planarization process in which second metal adhesive / barrier layer and / or third metal fill material over the top surface of the dielectric layer is removed. In some embodiments, the vias to the gate structures are formed before the vias to the source-drain contacts are formed. In some embodiments, the vias to the gate structures are formed after the vias to the source-drain contacts are formed.By recessing the source-drain contacts, a contact area between the vias and the source-drain contacts increases. Process variations in the bottom-up deposition process result in a different height of the first metal fill material. For example, the first metal fill material may completely fill a first via opening to a first source-drain contact, while only partially filling a second via opening to a second source-drain contact. In some embodiments, the first metal fill material completely fills the first via opening and extends beyond the top surface of the dielectric layer to form a via rivet head. As a height of the first via rivet head increases (defined between an uppermost surface of the via rivet head and the upper surface of the dielectric layer), the residual stress of the first metal fill material increases, which may result in cracks during continuous growth of the first metal fill material and / or subsequent processing. In some embodiments, the bottom-up deposition process is tuned so that the height of the via rivet head is limited to a predetermined height that may minimize residual stress of the first metal fill material. In some embodiments, the metal adhesive / barrier layer is formed over the first metal fill material prior to forming the second metal fill material (needed to fill a remainder of the via openings partially filled with the first metal fill material) to reduce residual stress in the first metal fill material and prevent cracking in metal fill layers of the vias. In such manufacturing methods, some vias to source-drain contacts with barrier-free interfaces and some vias to source-drain contacts with partial barrier interfaces are produced. Details of the proposed methods for the production of vias and the resulting via structures and / or configurations are described here.FIGS. 1A and 1B are a flow diagram of a method 10 for fabricating a portion of a multi-layer interconnect structure of an IC device, in accordance with various aspects of the present disclosure. The portion of the multi-layer interconnect structure made with method 10 may reduce a / n capacitance and / or resistance associated with the IC device, thereby reducing an RC delay associated therewith. At block 20, the method 10 includes forming first and second source-drain contacts in a dielectric layer. The first source-drain contact is in physical contact with a first source-drain feature. The second source-drain contact is in physical contact with a second source-drain feature. At block 30, the method 10 includes forming first and second via openings in the dielectric layer. The first via opening exposes the first source-drain contact and the second via opening exposes the second source-drain contact. At block 40, the method 10 includes recessing the first source-drain contact to enlarge the first via opening and recessing the second source-drain contact to enlarge the second via opening. At block 50, a bottom-up deposition process is performed to form a first via volume layer in the first via opening and a second via volume layer in the second via opening. In some embodiments, a first thickness of the first via volume layer is different (e.g., greater or less) than a second thickness of the second via volume layer. In some embodiments, a first thickness of the first via volume layer is equal to a second thickness of the second via volume layer. At block 60 and block 70, a first via barrier layer is formed over the first and second via bulk layers and a third via bulk layer is formed over the first via barrier layer, respectively.At block 80, the method 10 includes performing a planarization process to remove third via volume layer, first via barrier layer, second via volume layer, and first via volume layer disposed over a top surface of the dielectric layer, thereby forming a first via having a third thickness and a first via layer configuration and a second via having the third thickness and a second via layer configuration different from the first. At blocks 90, 100, and 110, respectively, a third via opening exposing a gate structure, a second via blocking layer partially filling the third via opening, and a fourth via bulk layer over the second via blocking layer is formed in the dielectric layer. The fourth via volume layer fills a remainder of the third via opening. At block 120, the method 10 includes performing a planarization process to remove fourth via volume layer and second via barrier layer disposed over the top surface of the dielectric layer, thereby forming a third via having a third via layer configuration different from the first and second via layer configurations. In some embodiments, the first, second, and third vias are a portion of a lowermost via layer of the multi-layer interconnect structure. In some embodiments, the fabrication may proceed with forming additional layers of the multi-layer interconnect structure, such as respective lines over the first, second, and third vias that are in physical contact therewith. Additional processing is contemplated by the present disclosure. Additional steps may occur before, during, or after the method 10, and some of the described steps may be re-arranged, replaced, or eliminated for additional embodiments of the method 10. The following discussion relates to interconnects that may be fabricated according to the method 10.FIGS. 2 to 6, 7A to 11A, 7B to 11B, 7C to 11C, and 12 to 16 are schematic partial views of a (part or all of) IC device 200 at various stages of manufacturing a multi-layer interconnect structure of IC device 200 (such as those associated with method 10 of FIG. 1 ), in accordance with various aspects of the present disclosure. FIGS. 2 to 6, 7A to 11A, and 12 to 16 are partial cross-sectional views of the IC device 200 in an XZ plane at different stages of manufacturing in accordance with various aspects of the present disclosure. FIGS. 7B to 11B and 7C to 11C are partial cross-sectional views of portions of the IC device 200 in FIGS. 7A to 11A in a YZ plane along lines at different stages of manufacturing, according to various aspects of the present disclosure. The IC device 200 may be included in a microprocessor, memory, and / or other IC device. In some embodiments, the IC device 200 may be part of an IC chip, a system on a chip (SoC), or a portion thereof, including various passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, p-FET (PFET), n-FET (NFET), metal oxide semiconductor FET (MOSFET), complementary MOS (CMOS) transistors, bipolar junction transistor (BJT), laterally double diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, other suitable components, or combinations thereof. The various transistors may be planar transistors or multi-gate transistors such as FinFETs, depending on the design requirements of the IC device 200. Figures 2 through 6, 7A through 11A, 7B through 11B, 7C through 11C, and 12 through 16 are simplified for clarity so that the inventive concepts of the present disclosure are better understood. Additional features may be added to the IC device 200, and some of the features described below may be replaced, altered, or eliminated in other embodiments of the IC device 200.The IC device 200 in FIG. 2 includes a substrate (wafer) 210. In the depicted embodiment, the substrate 210 includes silicon. The substrate 210 may alternatively or additionally include another elemental semiconductor such as germanium, a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide, an alloy semiconductor such as silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP, or combinations thereof. Alternatively, the substrate 210 is a semiconductor-on-insulator substrate such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. Semiconductor-on-insulator substrates may be fabricated using Separation by Implantation of Oxygen (SIMOX), wafer bonding, and / or other suitable methods. The substrate 210 includes doped regions formed by an ion implant process, a diffusion process, and / or other suitable doping processes. In some embodiments, the substrate 210 includes p-doped regions (e.g., p-wells) doped with p-dopants such as boron, indium, another p-dopant, or combinations thereof. In some embodiments, the substrate 210 includes n-doped regions (e.g., n-wells) doped with n-dopants such as phosphorus, arsenic, another n-dopant, or combinations thereof. In some embodiments, the substrate 210 includes doped regions formed with a combination of p- and n-type dopants. The various doped regions may be formed directly on and / or in the substrate 210 and provide, for example, a p-well, an n-well, a double-well or a raised structure, or combinations thereof.Isolation elements may be formed over and / or in the substrate 210 to isolate various regions such as device regions of the IC device 200. Isolation elements define and electrically isolate active and / or passive device regions from each other. Isolation elements include silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation material (such as silicon, oxygen, nitrogen, carbon, or other suitable isolation component), or combinations thereof. Isolation elements may have different structures, such as shallow trench isolation (STI) structures, deep trench isolation (DTI) structures, and / or local oxidation of silicon (LOCOS) structures. In some embodiments, isolation elements are formed by etching a trench (or trenches) in the substrate 210 and filling the trench with isolation material (e.g., using a chemical vapor deposition (CVD) process or a spin-on-glass process). To remove excess insulating material and / or planarise a top surface of insulating elements, a chemical mechanical polishing (CMP) process may be performed. In some embodiments, isolation elements may be formed by depositing an isolation material over the substrate 210 (in some embodiments, such that the isolation material fills gaps (trenches) between the fin structures) after forming fin structures) and etching back the isolation material. In some embodiments, isolation elements have a multilayer structure that fills trenches, such as a bulk dielectric layer disposed over a liner dielectric layer, where the bulk dielectric layer and the liner dielectric layer include materials depending on design requirements (e.g., a bulk dielectric layer where silicon nitride is disposed over a liner dielectric layer that includes thermal oxide). In some embodiments, isolation elements include a dielectric layer disposed over a doped liner layer (such as borosilicate glass (BSG) or phosphosilicate glass (PSG)).Various gate structures are deposited over the substrate 210, such as a gate structure 230A, a gate structure 230B, and a gate structure 230C. Each of the gate structures 230A- 230C abuts a respective channel region defined between a respective source region and a respective drain region (hereinafter referred to as source-drain regions) such that current may flow between the respective source-drain regions during operation. In some embodiments, gate structures 230A- 230C are formed over a fin structure to each surround a portion of the fin structure and lie between respective source-drain regions of the fin structure. The gate structures 230A- 230C each include a metal gate (MG) stack 232. MG stacks 232 are formed by deposition, lithography, etching, and other suitable processes or combinations thereof. Deposition processes include CVD, physical vapor deposition (PVD), atomic layer deposition (ALD), CVD with high density plasma (HDPCVD), metal organic CVD (MOCVD), remote plasma CVD (RPCVD), plasma enhanced CVD (PECVD), low pressure CVD (LPCVD), atomic layer CVD (ALCVD), atmospheric pressure CVD (APCVD), plasma enhanced ALD (PEALD), plating, other suitable methods, or combinations thereof. Lithography patterning processes include resist coating (e.g., spin coating), soft firing, mask alignment, exposure, post exposure firing, developing the resist, rinsing, drying (e.g., hard firing), other suitable processes, or combinations thereof. Alternatively, the lithographic exposure process is supported, implemented or replaced by other methods such as maskless lithography, electron or ion beam writing. The etching processes include dry, wet, and other etching processes, or combinations thereof. MG stacks 232 are fabricated according to a gate last, a gate first, or a mixed gate last / gate first process. In gate load embodiments, gate structures 230A- 230C include dummy gate stacks that are later fully or partially replaced with MG stack 232. The dummy gate stacks include, for example, an interfacial layer (e.g., a silicon oxide layer) and a dummy gate electrode layer (e.g., a polysilicon layer) disposed over the interfacial layer. In such embodiments, the dummy gate electrode layer is removed, creating openings that are filled with MG stacks 232. In some embodiments, the dummy gate stacks may include a dummy gate dielectric layer disposed between the interface layer and the dummy gate electrode layer and may be removed in the gate replacement process. In some embodiments, the dummy gate dielectric layer and / or the interfacial layer are not removed in the gate replacement process and form a portion of the MG stacks 232.The MG stacks 232 are configured to achieve desired functionality according to design requirements of the IC device 200, such that MG stacks 232 of gate structures 230A- 230C may include the same or different layers and / or materials as compared to one another. In some embodiments, MG stacks 232 include a gate dielectric (e.g., a gate dielectric layer) and a gate electrode (e.g., a work function layer and a bulk conductive layer). MG stacks 232 may include numerous other layers, such as cap layers, interfacial layers, diffusion layers, barrier layers, hard mask layers, or combinations thereof. In some embodiments, the gate dielectric layer is disposed over an interfacial layer (including a dielectric material such as silicon oxide) and the gate electrode is disposed over the gate dielectric layer. The gate dielectric layer includes a dielectric material such as silicon oxide, a high-k dielectric material, another suitable dielectric material, or combinations thereof. Examples of high-k dielectric material include hafnium dioxide (HfO 2), HfSiO, HfSiON, HfTaO, HfTiO, HfNbO, zirconium oxide, aluminum oxide, hafnium dioxide-aluminum oxide alloy (HfO 2- Al 2 O 3- alloy), other suitable high-k dielectric materials, or combinations thereof. Generally, dielectric materials with a high dielectric constant (k value) compared to a dielectric constant of silicon oxide (k≈3.9) are considered high-k dielectric material. High-k dielectric material has, for example, a dielectric constant of greater than about 3.9. In some embodiments, the gate dielectric layer is a high-k dielectric layer. The gate electrode includes a conductive material such as polysilicon, Al, Cu, Ti, Ta, W, Mo, Co, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, other conductive materials, or combinations thereof. In some embodiments, the work function layer is a conductive layer tuned to provide a desired work function (such as an n- or a p-type work function), and the bulk conductive layer is a metal layer formed over the work function layer. In some embodiments, the work function layer includes n-type work function providing material such as Ti, Ag, Mn, Zr, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, other suitable n-type work function providing material, or combinations thereof. In some embodiments, the work function layer includes a p-type work function-providing material such as Ru, Mo, Al, TiN, TaN, WN, ZrSi 2, MoSi 2, TaSi 2, NiSi 2, WN, other suitable p-type work function-providing material, or combinations thereof. The bulk conductive layer (or fill layer) contains a suitable conductive material such as Al, W and / or Cu. The bulk conductive layer may additionally or wholly contain polysilicon, Ti, Ta, metal alloys, other suitable material, or combinations thereof.The gate structures 230A- 230C further include gate spacers 236 disposed adjacent to (e.g., on the sidewalls of) the MG stacks 232. The gate spacers 236 are formed by any suitable process and include a dielectric material. The dielectric material may include silicon, oxygen, nitrogen, other suitable material, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide). For example, in the depicted embodiment, a dielectric layer including silicon and nitrogen, such as a silicon nitride layer, may be deposited over the substrate 210 and then anisotropically etched to form the gate spacers 236. In some embodiments, the gate spacers 236 have a multilayer structure, such as a first dielectric layer including silicon nitride and a second dielectric layer including silicon oxide. In some embodiments, more than one set of spacers are formed adjacent to the MG stacks 232, such as seal spacers, staggered spacers, sacrificial spacers, dummy spacers, and / or main spacers. In such embodiments, the various spacer sets may include material having different etch rates. For example, a first dielectric layer including silicon and oxygen (e.g., silicon oxide) may be deposited over the substrate 210 and etched to form a first set of spacers adjacent to the MG stacks 232, and a second dielectric layer including silicon and nitrogen (e.g., silicon nitride) may be deposited over the substrate 210 and etched to form a second adjacent to the first set of spacers. Implantation, diffusion and / or anneal processes may be performed to form low-doped source and drain (LDD) features and / or heavily doped source and drain (HDD) features in the substrate 210 before and / or after the formation of the gate spacers 236.Epitaxial source and drain elements (referred to as epitaxial source-drain elements) such as an epitaxial source-drain element 240A, an epitaxial source-drain element 240B, an epitaxial source-drain element 240C, and an epitaxial source-drain element 240D are disposed in the source-drain regions of the substrate 210. In the gate structure 230A, the source-drain epitaxial element 240A and the source-drain epitaxial element 240B are arranged to define a channel region therebetween. In the gate structure 230B, the source-drain epitaxial element 240B and the source-drain epitaxial element 240C are arranged to define a channel region therebetween. In the gate structure 230C, the source-drain epitaxial element 240C and the source-drain epitaxial element 240D are arranged to define a channel region therebetween. In some embodiments, the gate structure 230A, the source-drain epitaxial element 240A, and the source-drain epitaxial element 240B form a portion of a first transistor, the gate structure 230B, the source-drain epitaxial element 240B, and the source-drain epitaxial element 240C form a portion of a second transistor, and the gate structure 230C, the source-drain epitaxial element 240C, and the source-drain epitaxial element 240D form a portion of a third transistor.In some embodiments, a semiconductor material is epitaxially grown on the substrate 210 such that epitaxial source-drain elements 240A- 240D are formed over source-drain regions of the substrate 210. In some embodiments, an etching process is performed on source-drain regions of the substrate 210 to form source-drain recesses, wherein epitaxial source-drain elements 240A- 240D are grown to fill the source-drain recesses. In some embodiments, when the substrate 210 is part of a fin structure, epitaxial source-drain elements 240A- 240D surround source-drain regions of the fin structure and / or are disposed in source-drain recesses of the fin structure. An epitaxy process may implement CVD deposition techniques (e.g., vapor-phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), LPCVD, and / or PECVD), molecular beam epitaxy, other suitable SEG processes, or combinations thereof. The epitaxy process may use gaseous and / or liquid precursors interacting with the composition of the substrate 210. The epitaxial source-drain elements 240A- 240D are doped with n- and / or p-dopants. In some embodiments, the epitaxial source-drain elements 240A- 240D are epitaxial layers containing silicon and / or carbon, wherein the silicon-containing epitaxial layers or the silicon-carbon-containing epitaxial layers are doped with phosphorus, another n-type dopant, or combinations thereof. In some embodiments, the epitaxial source-drain elements 240A- 240D are epitaxial layers containing silicon and / or germanium, where the silicon-germanium-containing epitaxial layers are doped with boron, another p-type dopant, or combinations thereof. In some embodiments, the epitaxial source-drain elements 240A- 240D include materials and / or dopants that achieve a desired tensile and / or compressive stress in the channel regions. In some embodiments, the epitaxial source-drain elements 240A- 240D are doped during deposition by adding impurities to a starting material for the epitaxial process. In some embodiments, the epitaxial source-drain elements 240A- 240D are doped after a deposition process in an ion implantation process. In some embodiments, anneal processes are performed to activate dopants in epitaxial source-drain elements 240A- 240D and / or other source-drain elements (e.g., HDD and / or LDD regions).A multilayer interconnect element (MLI element; MLI= Multi Interconnect) 250 is disposed over the substrate 210. The MLI element 250 electrically couples various devices (e.g., transistors, resistors, capacitors, and / or inductors) and / or devices (e.g., the gate structures 230A- 230C and / or the source-drain elements 240A- 240D) of the IC device 200 such that the various devices and / or devices may operate according to the design requirements for the IC device 200. The MLI element 250 includes a combination of dielectric layers and conductive layers (e.g., metal layers) configured to form various interconnects. The conductive layers are configured to form vertical interconnects such as device level contacts and / or vias and / or horizontal interconnects such as lines. Vertical interconnects typically connect horizontal interconnects in different layers (or levels) of the MLI element 250. During operation of the IC device 200, the interconnects pass signals between the devices and / or the devices of the IC device 200 and / or distribute signals (e.g., clock signals, voltage signals, and / or ground signals) to the devices and / or the devices of the IC device 200, except for passing and distributing signals between the devices and / or devices of the IC device 200 with devices and / or devices external to the IC device 200. The MLI element 250 is depicted with a given number of dielectric layers and conductive layers. The present disclosure contemplates that the MLI element 250 has more or fewer dielectric layers and / or conductive layers depending on design requirements.The MLI element 250 includes one or more insulating layers disposed over the substrate 210, such as an interlayer dielectric (ILD) layer 252 (ILD-o), an interlayer dielectric layer 254 (ILD-1), a contact etch stop layer (CESL= Con Etch Stop Layer) 262, and a contact etch stop layer 264. The ILD layer 252 is disposed over the substrate 210 and the ILD layer 254 is disposed over the ILD layer 252. The CESL 262 is disposed between the ILD layer 252 and the substrate 210, the epitaxial source-drain elements 240A- 240C, and / or the gate structures 230A- 230C (particularly, the gate spacers 236). CESL 264 is disposed between ILD layer 252, ILD layer 254, and / or gate structures 230A- 230C. In some embodiments, a thickness of the ILD layer 252 is about 10 nm to about 25 nm, a thickness of the ILD layer 254 is about 10 nm to about 25 nm, a thickness of the CESL 262 is about 1 nm to about 10 nm, and a thickness of the CESL 264 is about 1 nm to about 10 nm. The ILD layers 252, 254 and / or the CESL 262, 264 are formed over the substrate 210 by a deposition process such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, PEALD, other suitable methods, or combinations thereof. In some embodiments, the ILD layer 252 and / or the ILD layer 254 is formed by a high aspect ratio process (HARP=High Aspect Ratio Process) such as HDPCVD, which is generally a deposition process with parameters configured to achieve adequate filling of high aspect ratio structures. In some embodiments, the ILD layer 252 and / or the ILD layer 254 is formed by a flowable CVD (FCVD) process, including, for example, depositing a flowable material (such as a liquid) over the substrate 210 and converting the flowable material to a solid material by a suitable technique, such as by annealing and / or treating the flowable material with ultraviolet radiation. After depositing the ILD layer 252, the ILD layer 254, the CESL 262, and / or the CESL 264, a CMP process and / or another planarization process may be performed such that the ILD layers 252, 254 and / or the CESL 262, 264 have substantially planar surfaces.The ILD layers 252, 254 include a dielectric material such as silicon oxide, carbon doped silicon oxide, silicon nitride, silicon oxynitride, tetraethyl orthosilicate (TEOS), PSG, BSG, boron doped phosphosilicate glass (BPSG), fluorine doped silicate glass (FSG), black Diamond® (Applied Materials of Santa Clara, California, USA), xerogel, aerogel, amorphous fluorinated carbon, parylene, benzocyclobutene (BCB) based dielectric material, SiLK™ (Dow Chemical, Midland, Michigan, USA), polyimide, other suitable dielectric material, or combinations thereof. In some embodiments, the ILD layers 252, 254 include a low-k dielectric material, which is generally a low-k dielectric material with a low dielectric constant with respect to the dielectric constant of silicon oxide (k≈3.9). Low-k dielectric material has, for example, a dielectric constant of less than about 3.9. In some embodiments, the low-k dielectric material has a dielectric constant less than about 2.5, which may be referred to as an extremely low-k (ELK) dielectric material. In the depicted embodiment, the ILD layers 252, 254 include an ELK dielectric material such as silicon dioxide (SiO 2) ( for example, porous silicon dioxide), silicon carbide (SiC), and / or carbon doped oxide (for example, a SiCOH-based material (for example, Si-CH 3- bonds)) that is each tuned / configured to have a dielectric constant less than about 2.5 (and may thus be referred to as an ELK dielectric layer). The CESL 262, 264 include a different material than the ILD layers 252, 254, such as a dielectric material different than the dielectric material of the ILD layers 252, 254. For example, if the ILD layers 252, 254 contain silicon and oxygen (e.g., SiCOH, SiO x or other silicon and oxygen-containing material having a dielectric constant of less than about 2.5), then the CESL 262, 264 may contain silicon and nitrogen and / or carbon (e.g., SiN, SiCN, SiCON, SiON, SiC, and / or SiCO) (and thus may be referred to as a silicon nitride layer). In some embodiments, the CESL 262, 264 include a metal oxide and / or a metal nitride layer. The ILD layers 252, 254 and / or the CESL 262, 264 may have a multilayer structure with multiple dielectric materials.In FIG. 3, a patterning process forms one or more interconnect openings in a dielectric layer, such as an interconnect opening 270A and an interconnect opening 270B. The interconnect opening 270A and the interconnect opening 270B pass vertically through the ILD layer 254, the CESL 264, ILD layer 252, and the CESL 262, thus exposing the source-drain epitaxial element 240B and the source-drain epitaxial element 240C, respectively. The interconnect openings 270A, 270B may thus be referred to as source-drain contact openings (plug openings). The interconnect opening 270A includes a sidewall 272A (defined by the ILD layer 254, the CESL 264, ILD layer 252, and the CESL 262), a sidewall 274A (defined by the ILD layer 254, the CESL 264, ILD layer 252, and the CESL 262), and a bottom 276A (defined by a source-drain epitaxial element 240B) that extends between the sidewall 272A and the sidewall 274A. The interconnect opening 270B includes a sidewall 272B (defined by the ILD layer 254, the CESL 264, ILD layer 252, and the CESL 262), a sidewall 274B (defined by the ILD layer 254, the CESL 264, ILD layer 252, and the CESL 262), and a bottom 276B (defined by a source-drain epitaxial element 240C) that extends between the sidewall 272B and the sidewall 274B. In FIG. 3, each of the interconnect openings 270A, 270 205B has a trapezoidal shape, however, the present disclosure contemplates interconnect openings 270A, 270B of a different shape, such as rectangular shape. The sidewalls 272A, 274A taper such that a lower width of the interconnect opening 270A exposing the epitaxial source-drain element 240B is less than an upper width of the interconnect opening 270A at an upper surface of the ILD layer 254. A width of the interconnect opening 270A thus decreases in the z-direction from the upper width to the lower width of the interconnect opening 270A. The sidewalls 272B, 274B taper such that a lower width of the interconnect opening 270B exposing the epitaxial source-drain element 240C is less than an upper width of the interconnect opening 270B at an upper surface of the ILD layer 254. A width of the interconnect opening 270B thus decreases in the z-direction from the upper width to the lower width of the interconnect opening 270B.In some embodiments, the patterning process includes performing a lithography process to form a patterned mask layer 278 having an opening 279A (substantially aligned with the source-drain epitaxial element 240B) and an opening 279B (substantially aligned with the source-drain epitaxial element 240C) therein over the ILD layer 254, and performing an etching process to transfer a pattern defined in the patterned mask layer 278 to an underlying dielectric layer (here, the ILD layer 254, the CESL 264, the ILD layer 252, and the CESL 262). The lithography process may include forming a resist layer on the ILD layer 254 (e.g., by spin coating), performing a pre-exposure firing process, an exposure process using a mask, a post-exposure firing process, and a development process. In the exposure process, the resist layer is exposed to radiation energy (such as ultraviolet light (UV light), deep UV light (DUV light) or extreme UV light (EUV light), wherein the mask blocks, transmits and / or reflects radiation falling on the resist layer depending on its mask structure and / or a mask type (for example binary mask, phase shift mask or EUV mask), such that an image corresponding to the mask structure is projected onto the resist layer. Since the resist layer is sensitive to radiant energy, exposed portions of the resist layer change chemically, and exposed (or unexposed) portions of the resist layer dissolve in the course of the development process depending on properties of the resist layer and a developing solution used in the development process. After development, the patterned resist layer has a resist pattern corresponding to the mask. Alternatively, the exposure process may be implemented or replaced by other methods such as maskless lithography, electron and / or ion beam writing.In some embodiments, the patterned resist layer is the patterned resist layer 278. In such embodiments, the patterned resist layer is used as an etch mask to remove portions of the underlying dielectric layer (here, ILD layer 254, CESL 264, ILD layer 252, and / or CESL 262) exposed by the openings 279A, 279B. In some embodiments, the patterned resist layer is formed over a mask layer formed over the underlying dielectric layer prior to forming the resist layer, and the patterned resist layer is used as an etch mask for removing portions of the mask layer formed over the underlying dielectric layer, thereby forming the patterned mask layer 278. In such embodiments, the patterned mask layer is used as an etch mask to remove portions of the ILD layer 254, the CESL 264, the ILD layer 252, and the CESL 262 that are exposed by the openings 279A, 279B. The etching process may include a dry etching process (e.g., a reactive ion etching (RIE) process), a wet etching process, another suitable etching process, or combinations thereof. Various selective etching processes may be performed to form the interconnect openings 270A, 270B. The etching process may include, for example, a first etch in which the ILD layer 254 is selectively etched with respect to the patterned mask layer 278 and the CESL 264 such that the first etch stops when it reaches the CESL 264, a second etch in which the CESL 264 is selectively etched with respect to the ILD layers 254, 252 such that the second etch stops when it reaches the ILD layer 252, a third etch in which the ILD layer 252 is selectively etched with respect to the CESL 262, 264 such that the third etch stops when it reaches the CESL 262, and a fourth etch, wherein the CESL 262 is selectively etched with respect to the ILD layers 252, 254 and the epitaxial source-drain elements 240B, 240C such that the fourth etch stops when it reaches the epitaxial source-drain elements 240B, 240C. In some embodiments, the first, second, third, and fourth etchings may be configured to overetch slightly. For example, the first etch may partially etch the CESL 264, the second etch may partially etch the ILD layer 252, the third etch may partially etch the CESL 262, and / or the fourth etch may partially etch the epitaxial source-drain elements 240B, 240C. In some embodiments, the first, second, third, and fourth etchings are similar to etching processes described herein for etching ILD and CESL. In some embodiments, the etching process may include multiple steps for etching the CESL 262, 264. In some embodiments, the etching process implements an etchant with low etch selectivity between the ILD layers 254, 252 and the CESL 262, 264 such that the interconnect openings 270A, 270B are formed by a single etching step based on time, for example. In some embodiments, after the etching process, the patterned mask layer 278 is removed (in some embodiments, by a resist stripping process) from the ILD layer 254. In some embodiments, the patterned mask layer 278 is removed during etching of the ILD layer 254, the CESL 264, the ILD layer 252, and / or the CESL 262.In FIG. 4, silicide layers 280 are formed on the epitaxial source-drain elements 240B, 240C. Silicide layers 280 pass through CESL 262. In the depicted embodiment, upper surfaces of silicide layers 280 are disposed further upward than an upper surface of CESL 262 with respect to an upper surface of substrate 210. In some embodiments, the top surfaces of silicide layers 280 are disposed further down relative to the top surface of substrate 210 than or substantially planar with the top surface of CESL 262. In some embodiments, the top surfaces of silicide layers 280 are disposed further below than the top surface of substrate 210. The silicide layers 280 may be formed by depositing a metal layer over the epitaxial source-drain elements 240B, 240C and heating the IC device 200 (e.g., performing an anneal process on the IC device 200), thereby reacting constituents of the epitaxial source-drain elements 240B, 240C (e.g., silicon and / or germanium) with metal constituents of the metal layer. The metal layer includes any metal component suitable for promoting silicide formation, such as nickel, platinum, palladium, vanadium, titanium, cobalt, tantalum, ytterbium, zirconium, another suitable metal, or combinations thereof. The silicide layers 280 thus include a metal component and a component of the epitaxial source-drain elements 240B, 240C, such as silicon and / or germanium. In some embodiments, the silicide layers 280 include nickel silicide, titanium silicide, or cobalt silicide. Unreacted metal, such as remaining portions of the metal layer, may be selectively removed by, for example, an etching process with respect to the silicide layers 280 and / or a dielectric material.Then, a source-drain contact 282A and a source-drain contact 282B are formed in the interconnect opening 270A and the interconnect opening 270B, respectively. The source-drain contacts 282A, 282B each pass through the ILD layer 254, the CESL 264, and the ILD layer 252 to the silicide layers 280, such that the source-drain contacts 282A, 282B are respectively disposed on silicide layers 280 on the epitaxial source-drain elements 240B, 240C. In some embodiments, the source-drain contacts 282A, 282B may extend partially or completely through the CESL 262 depending on the configuration of the silicide layers 280. The source-drain contacts 282A, 282B each include a contact barrier layer 284 and a contact bulk layer 286 disposed over the contact barrier layer 284. The contact barrier layer 284 is disposed on the sidewalls 272A, 272B, the sidewalls 274A, 274B, and the bottom 276A, 276B of the interconnect openings 270A, 270B, respectively. For example, the contact barrier layer 284 is in physical contact with the sidewalls 272A, 272B, the sidewalls 274A, 274B, and the bottom 276A, 276B of the interconnect openings 270A, 270B, respectively. In some embodiments, the source-drain contacts 282A, 282B are formed by performing a first deposition process to form a contact blocking material over the ILD layer 254 that partially fills the interconnect openings 270A, 270B and a second deposition process to form a contact bulk material over the contact blocking material, the contact bulk material filling a remainder of the interconnect openings 270A, 270B. In such embodiments, the contact blocking material and the contact bulk material are disposed in the interconnect openings 270A, 270B and over the top surface of the ILD layer 254. The first and second deposition processes may include CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, PEALD, electrodeposition, electroless plating, other suitable deposition methods, or combinations thereof. In some embodiments, the contact barrier layer 284 has a substantially uniform thickness at the sidewalls 272A, 272B, the sidewalls 274A, 274B, and the bottom 276A, 276B, respectively, of the interconnect openings 270A, 270B. The contact barrier layer 284 may thus be formed by a conformal deposition process. To remove excess contact bulk material and contact blocking material, for example, over the top surface of the ILD layer 254, a CMP process and / or other planarization process is performed, thereby creating the source-drain contacts 282A, 282B (in other words, the contact blocking layer 284 and the contact bulk layer 286 fill the interconnect openings 270A, 270B). In the CMP process, a top surface of the source-drain contacts 282A, 282B is planarized such that the top surface of the ILD layer 254 and top surfaces of the source-drain contacts 282A, 282B form a substantially planar surface in some embodiments.The contact barrier layer 284 includes a material that enhances adhesion between an surrounding dielectric material (here, the ILD layer 254, the CESL 264, and / or the ILD layer 252), and the contact bulk layer 286. The material of the contact blocking layer 284 may further prevent diffusion of metal constituents (e.g., metal atoms / ions) from the source-drain contacts 282A, 282B into the surrounding dielectric material. In some embodiments, the contact barrier layer 284 includes titanium, titanium alloy, tantalum, tantalum alloy, cobalt, cobalt alloy, ruthenium, ruthenium alloy, molybdenum, molybdenum alloy, palladium, palladium alloy, or other suitable component configured to improve and / or increase adhesion between a metal material and a dielectric material and / or prevent diffusion of metal components from the metal material into the dielectric material. The contact barrier layer 284 includes tantalum, tantalum nitride, tantalum aluminum nitride, tantalum silicon nitride, tantalum carbide, titanium, titanium nitride, titanium silicon nitride, titanium aluminum nitride, titanium carbide, tungsten, tungsten nitride, tungsten carbide, molybdenum nitride, cobalt, cobalt nitride, ruthenium, palladium, or combinations thereof. In some embodiments, the contact barrier layer 284 includes multiple layers. For example, the contact blocking layer 284 may include a first sublayer including titanium and a second sublayer including titanium nitride. In another example, the contact blocking layer 284 may include a first sub-layer including tantalum and a second sub-layer including tantalum nitride. The contact volume layer 286 includes tungsten, ruthenium, cobalt, copper, aluminum, iridium, palladium, platinum, nickel, a low resistivity metal component, alloys thereof, or combinations thereof. In the depicted embodiment, the contact volume layer 286 includes tungsten, ruthenium, and / or cobalt. In some embodiments, the source-drain contacts 282A, 282B do not include a contact blocking layer 284 (e.g., the source-drain contacts 282A, 282B are barrier-free contacts) such that the contact bulk layer 286 is in physical contact with the ILD layer 254, the CESL 264, the ILD layer 252, the silicide layer 280, and / or the epitaxial source-drain elements 240B, 240C. In some embodiments, the source-drain contacts 282A, 282B are partially barrier-free, with the contact blocking layer 284 disposed between a dielectric layer of the MLI element 250 and a portion of the contact volume layer 286. In some embodiments, the contact volume layer 286 includes multiple layers.In FIG. 5, the processing is continued with the formation of another dielectric layer of the MLI element 250. For example, an ILD layer 292 is formed over the ILD layer 254 and the source-drain contacts 282A, 282B. The ILD layer 292 may be similar to the ILD layer 254. The ILD layer 292 is formed, for example, by a deposition process such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, PEALD, FCVD, other suitable deposition methods, or combinations thereof. The ILD layer 292 includes a dielectric material such as silicon oxide, carbon doped silicon oxide, silicon nitride, silicon oxynitride, TEOS, PSG, BSG, BPSG, FSG, Black Diamond® (Applied Materials of Santa Clara, California, USA), xerogel, aerogel, amorphous fluorinated carbon, parylene, BCB-based dielectric material, SiLK™ (Dow Chemical, Midland, Michigan, USA), polyimide, other suitable dielectric material, or combinations thereof. In some embodiments, the ILD layer 292 includes a low-k dielectric material. In the depicted embodiment, the ILD layer 292 includes, for example, an ELK dielectric material such as silicon dioxide (SiO 2) ( for example, porous silicon dioxide), silicon carbide (SiC), and / or carbon-doped oxide (for example, a SiCOH-based material (for example, Si-CH 3- bonds) that is each tuned / configured to have a dielectric constant of less than about 2.5. In some embodiments, the ILD layer 292 may have a multilayer structure including multiple dielectric materials. In some embodiments, the ILD layer 292 has a thickness t 1 of about 10 nm to about 120 nm. After depositing the ILD layer 292, a CMP process and / or another planarization process may be performed such that the ILD layer 292 has a substantially planar surface.In some embodiments, prior to forming the ILD layer 292, a CESL 294 is formed over the ILD layer 254 and the source-drain contacts 282A, 282B such that the CESL 294 is disposed between the ILD layer 292 and the ILD layer 254 and the source-drain contacts 282A, 282B. CESL 294 is similar to CESL 264. For example, the CESL 294 includes a different material than the ILD layer 292, such as a dielectric material different from the dielectric material of the ILD layer 292, to achieve etch selectivity in subsequent etching processes, such as those used to form the interconnect openings exposing the source-drain contacts 282A, 282B. In other words, the CESL 294 and the layers surrounding them contain material of pronounced etch sensitivity to a given etchant. For example, the CESL 294 includes a material having an etch rate in an etchant that is less than an etch rate of a material of the ILD layer 292 in the etchant, such that the material of the CESL 294 acts as an etch stop in etching the overlying ILD layer 292. The material of the CESL 294 may also be configured to improve adhesion between the CESL 294 and the ILD layer 292. In some embodiments, the CESL 294 includes silicon and nitrogen and / or carbon (e.g., SiN, SiCN, SiCON, SiON, SiC, and / or SiCO). In some embodiments, the CESL 294 includes a metal oxide and / or a metal nitride layer. The metal may include aluminum, hafnium, titanium, copper, manganese, vanadium, another suitable metal, or combinations thereof. In some embodiments, the CESL 294 includes multiple layers. The CESL 294 is formed by CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, PEALD, FCVD, other suitable deposition methods, or combinations thereof. In some embodiments, the CESL 294 has a thickness t 2 of about 1 nm to about 30 nm. After depositing the CESL 294, a CMP process and / or another planarization process may be performed such that the CESL 294 substantially has a planar surface.In FIG. 6, one or more interconnect openings such as an interconnect opening 300A and an interconnect opening 300B are formed in a dielectric layer (e.g., the ILD layer 292 and the CESL 294) by a patterning process. The interconnect opening 300A extends vertically through the ILD layer 292 and the CESL 294 and exposes the source-drain contact 282A. The interconnect opening 300B extends vertically through the ILD layer 292 and the CESL 294 and exposes the source-drain contact 282B. The interconnect openings 300A, 300B may thus be referred to as via openings. The interconnect opening 300A includes a sidewall 302A (defined by the ILD layer 292 and the CESL 294), a sidewall 304A (defined by the ILD layer 292 and the CESL 294), and a bottom 306A (defined by a source-drain contact 282A) extending between the sidewall 302A and the sidewall 304A. The interconnect opening 300B includes a sidewall 302B (defined by the ILD layer 292 and the CESL 294), a sidewall 304B (defined by the ILD layer 292 and the CESL 294), and a bottom 306B (defined by a source-drain contact 282B) extending between the sidewall 302B and the sidewall 304B. The interconnect openings 300A, 300B have a width x1 defined between the sidewalls 302A, 302B and the sidewalls 304A, 304B, respectively, and a depth d1 defined between a top surface of the ILD layer 292 and the source-drain contacts 282A, 282B, respectively. In some embodiments, the width x 1 is about 10 nm to about 30 nm and the depth d 1 is about 10 nm to about 150 nm (e.g., about 20 nm to about 80 nm). As CDs of interconnect openings 300A, 300B shrink in modern IC technology nodes, a metal glue / barrier layer formed thereafter requires more space in the interconnect openings 300A, 300B, thus reducing a remainder of the interconnect openings 300A, 300B for a metal fill layer formed thereafter. This may result in poor filling of the gap with metal, as the metal fill layer is unable to fill a remainder of the interconnect openings 300A, 300B without gaps (or voids) forming, thereby significantly increasing contact resistance. In some embodiments, an aspect ratio (e.g., d1 / x1) of the interconnect openings 300A, 300B is at least about 3. In some embodiments, the aspect ratio is about 5 to about 15. As aspect ratios of at least about 3 may result in gap fill problems, the present disclosure reduces the aspect ratio of the interconnect openings 300A, 300B (e.g., to an aspect ratio of less than about 3) before forming the metal adhesive / barrier layer, preventing or minimizing the formation of gaps in interconnects formed in the interconnect openings 300A, 300B. In FIG. 6, each of the interconnect openings 300A, 300B has a trapezoidal shape, however, the present disclosure contemplates interconnect openings 300A, 300B of a different shape, such as rectangular shape. The sidewalls 302A, 304A taper such that a lower width of the interconnect opening 300A exposing the source-drain contact 282A is less than an upper width of the interconnect opening 300A at an upper surface of the ILD layer 292. The width x 1 of the interconnect opening 300A thus decreases in the z-direction from the upper width to the lower width of the interconnect opening 300A. The sidewalls 302B, 304B taper such that a lower width of the interconnect opening 300B exposing the source-drain contact 282B is less than an upper width of the interconnect opening 300B at an upper surface of the ILD layer 292. The width x 1 of the interconnect opening 300B thus decreases in the z-direction from the upper width to the lower width of the interconnect opening 300B. In the depicted embodiment, the interconnect openings 300A, 300B have a bottom width that is greater than the width of the source-drain contacts 282A, 282B, such that the interconnect openings 300A, 300B also expose portions of the ILD layer 292. In some embodiments, the bottom width is less than or substantially equal to the width of the source-drain contacts 282A, 282B.In some embodiments, the patterning process includes performing a lithography process to form a patterned mask layer 308 having an opening 309A (substantially aligned with the source-drain contacts 282A) and an opening 309B (substantially aligned with the source-drain contacts 282B) therein over the ILD layer 292 and performing an etching process to transfer a pattern defined in the patterned mask layer 308 to the ILD layer 292 and the CESL 294. The lithography process may include forming a resist layer on the ILD layer 292 (e.g., by spin coating), performing a pre-exposure firing process, an exposure process using a mask, a post-exposure firing process, and a development process. During the exposure process, the resist layer is exposed to radiation energy (such as UV light, DUV light or EUV light, wherein the mask blocks, transmits and / or reflects radiation falling onto the resist layer depending on its mask structure and / or a mask type (for example binary mask, phase shift mask or EUV mask), such that an image corresponding to the mask structure is projected onto the resist layer. Since the resist layer is sensitive to radiant energy, exposed portions of the resist layer change chemically, and exposed (or unexposed) portions of the resist layer dissolve in the course of the development process depending on properties of the resist layer and a developing solution used in the development process. After development, the patterned resist layer has a resist pattern corresponding to the mask. Alternatively, the exposure process may be implemented or replaced by other methods such as maskless lithography, electron and / or ion beam writing. In some embodiments, the patterned resist layer is the patterned resist layer 308. In such embodiments, the patterned resist layer is used as an etch mask for removing portions of the ILD layer 292 and the CESL 294 exposed by the openings 309A, 309B. In some embodiments, the patterned resist layer is formed over a mask layer formed over the ILD layer 292 prior to forming the resist layer, and the patterned resist layer is used as an etch mask to remove portions of the mask layer formed over the ILD layer 292, thereby forming the patterned mask layer 308. In such embodiments, the patterned mask layer is used as an etch mask for removing portions of the ILD layer 292 and the CESL 294 exposed by the openings 309A, 309B. In some embodiments, after the etching process, the patterned mask layer 308 is removed (in some embodiments, by a resist stripping process) from the ILD layer 292. In some embodiments, the patterned mask layer 308 is removed during etching of the ILD layer 292 and / or the CESL 294.The etching process may include a dry etching process, a wet etching process, another suitable etching process, or combinations thereof. The etching process is, for example, a dry etching process such as an RIE process in which a fluorine-containing etching gas removes the material of the ILD layer 292 (e.g., silicon and oxygen-containing material) and the material of the CESL 294 (e.g., silicon and nitrogen-containing material) at a higher rate than the material of the patterned mask layer 308 and / or the source-drain contacts 282A, 282B (e.g., metal-containing material) (i.e., the etchant has a higher etch selectivity with respect to the ILD layer 292 and the CESL 294). In some embodiments, the dry etching process is configured to generate a fluorine-containing plasma from the fluorine-containing gas, such that in the dry etching process using plasma-excited fluorine-containing species, the ILD layer 292 and the CESL 294 are removed. The fluorine-containing etching gas includes fluorine (F 2), fluoromethane (CH 3 F), difluoromethane (CH 2 F 2), trifluoromethane (CHF 3), tetrafluoromethane (CF 4), hexafluoromethane (C 2 F 6), sulfur hexafluoride (SF 6), nitrogen trifluoride (NF 3), another fluorine-containing etchant, or combinations thereof. In dry etching, alternatively or additionally, a hydrogen-containing etching gas (e.g., H 2 and / or CH 4), a nitrogen-containing etching gas (e.g., N 2 and / or NH 3), a chlorine-containing etching gas (e.g., Cl 2, CHCl 3, CCl 4 and / or BCl 3), an oxygen-containing etching gas (e.g., O 2), a bromine-containing etching gas (e.g., HBr and / or CHBr 3), an iodine-containing etching gas, another suitable etching gas, or combinations thereof may be used. The dry etching may be configured to generate a plasma from one of the etching gases disclosed herein, such that plasma excited species are used in the dry etching to remove the ILD layer 292 and the CESL 294. In some embodiments, a carrier gas is used to supply the fluorine-containing etching gas and / or other etching gas. The carrier gas may be an inert gas such as an argon-containing gas, a helium-containing gas, a xenon-containing gas, another suitable inert gas, or combinations thereof.In some embodiments, dry etching employs an etching gas including CF 4 to selectively etch the ILD layer 292 and the CESL 294. In some embodiments, dry etching uses an etching gas with CF 4 in combination with O 2, N 2 and / or H 2. A flow rate of CF 4, a flow rate of O 2, a flow rate of N 2, a ratio of CF 4 to O 2, N 2 and / or H 2, an etch duration, an etch temperature, an etch pressure and / or an RF power may be tuned to achieve the desired etch selectivity. In some embodiments, a flow rate of CF 4 is about 10 sccm to about 1000 sccm. In some embodiments, a dry etch duration is about 5 seconds to about 50 seconds. In some embodiments, an RF power of about 100 W to about 1000 W is used to generate a fluorine-containing plasma. In some embodiments, a pressure maintained during dry etching in a process chamber is about 10 mTorr to about 1000 mTorr (1 Torr = 133 Pa). In some embodiments, a temperature maintained in the process chamber during dry etching is about 18° C. to about 100° C. In some embodiments, the etching process is a multistage (multi-phase) etching process having a first etching step where the ILD layer 292 is selectively etched and a second etching step where the CESL 294 is selectively etched. For example, the first etching step is configured to remove the ILD layer 292, but not or hardly remove the CESL 294, such that the first etching stops when it reaches the CESL 294, while the second etching step is configured to remove the CESL 294, but not or hardly remove the ILD 292 and the source-drain contacts 282A, 282B, such that the second etching stops when it reaches the source-drain contacts 282A, 282B. Various etch parameters may be tuned to achieve selective etching of the ILD layer 292 and the CESL 294. For example, for the first etching step, an etchant is selected for the first etching process that etches the material of the ILD layer 292 at a higher rate than the material of the CESL 294 (i.e., the etchant has a high etch selectivity with respect to the material of the ILD layer 292). For the second etching step, an etchant is selected that etches the material of the CESL 294 at a higher rate than the material of the ILD layer 292 (i.e., the etchant has a high etch selectivity with respect to the material of the CESL 294). In some embodiments, the same etchant may be used in the first and second etch steps, but with different flow rate and / or concentration of constituents of the etchant. In some embodiments, the first and / or second etch steps may be configured to overetch a little. In such embodiments, the first etch step may partially etch the CESL 294 and / or the second etch step may partially etch the source-drain contacts 282A, 282B. In some embodiments, the second etching step may include multiple steps for selectively etching each layer of the CESL 294, each step configured to etch a respective one of the layers of the CESL 294.Referring to FIGS. 7A through 7C, an etching process is performed to recess the source-drain contacts 282A, 282B. Such a process may be referred to as contact etchback, contact well, and / or plug well (or etchback). The etching process is a dry etching process, a wet etching process, another suitable etching process, or combinations thereof. In the depicted embodiment, contact etchback is a wet etch that uses a wet etchant solution to remove the material of the source-drain contacts 282A, 282B (e.g., metal material) at a higher rate than the material of the ILD layer 292 (e.g., dielectric material such as silicon and oxygen containing material) and the material of the CESL 294 (e.g., dielectric material such as silicon and nitrogen containing material) (i.e., the etchant has high etch selectivity with respect to the source-drain contacts 282A, 282B). In the depicted embodiment, the wet etchant solution removes the material of the contact volume layer 286 at a higher rate than the material of the contact blocking layer 284 (i.e., the etchant has high etch selectivity with respect to the contact volume layer 286), such that, while the contact volume layer 286 is removed during contact etchback, the contact blocking layer 284 is not, or hardly, removed. The wet etching process implements, for example, a wet etchant solution containing hydrofluoric acid (HF), nitric acid (HNO 3), hydrochloric acid (HCl), ammonia water (NH 4 OH), hydrogen peroxide (H 2 O 2), water (H 2 O), other suitable constituents of a wet etchant solution, or combinations thereof. In some embodiments, a pH of the wet etchant solution, an etch temperature, and / or an etch duration may be tuned to selectively achieve a desired etch. In some embodiments, the wet etchant solution has a pH of about 5.5 to about 8.5. In some embodiments, a temperature of the wet etchant solution is about 18° C. to about 100° C. In some embodiments, a duration of the wet etching is about 10 seconds to about 200 seconds. As will be described further below, contact etchback increases a contact area between the source-drain contacts 282A, 282B and vias formed later, which may increase the performance of the IC device 200 or improve the structural integrity of the vias and / or interconnect structures including the vias. In some embodiments, contact etch back partially removes the contact barrier layer 284 such that a thickness of the contact barrier layer 284 varies along the ILD layer 254. In some embodiments, the entire contact barrier layer 284 is removed by the contact etchback.After contact etchback, the interconnect opening 300A has an upper portion 310A and a lower portion 311A, and the interconnect opening 300B has an upper portion 310B and a lower portion 311B. The upper portions 310A, 310B are configured substantially the same in the XZ plane and the YZ plane. For example, in the XZ plane, the upper portions 310A, 310B are respectively defined between sidewalls 302A, 302B and sidewalls 304A, 304B and have a width w 1 and a depth d 1 as described above. In the YZ plane, the upper portions 310A, 310B have a width y 1 defined between sidewalls 312A, 312B and sidewalls 313A, 313B, respectively, and a depth d 1 defined between an upper surface of the ILD layer 292 and a lower surface of the CESL 294. The sidewalls 312A, 312B, and 313A, 313B are defined by the ILD layer 292 and the CESL 294. In some embodiments, the width y1is substantially equal to the width x1(e.g., about 10 nm to about 30 nm). In some embodiments, width y1is greater than or equal to width x1. The upper portions 310A, 310B also have a trapezoidal shape in the YZ plane, however, the present disclosure contemplates having a different shape, such as a rectangular shape. The side walls 312A, 312B and 313A, 313B taper such that the lower width of the upper portions 310A, 310B is less than the upper width of the upper portions 310A, 310B. The width y2 therefore decreases in the z-direction from the upper width to the lower width of the upper parts 310A, 310B. The present disclosure contemplates embodiments in which the upper portions 310A, 310B are configured differently in the XZ plane and the YZ plane.The lower parts 311A, 311B are configured differently in the XZ plane and the YZ plane. For example, the lower parts 311A, 311B have a trapezoidal shape in the XZ plane (FIG. 7A ) and a semi-circular shape in the YZ plane (FIGS. 7B and 7C ), but the present disclosure contemplates that the lower parts 311A, 311B have a different shape in the XZ plane. The bottom portion 311A in FIG. 7A is defined by a sidewall 314A (defined by the contact barrier layer 284), a sidewall 315A (defined by the contact barrier layer 284), and a bottom 316A (defined by the contact bulk layer 286) that extends between the sidewall 314A and the sidewall 315A, and the bottom portion 311B is defined by a sidewall 314B (defined by the contact barrier layer 284), a sidewall 315B (defined by the contact barrier layer 284), and a bottom 316B (defined by the contact bulk layer 286) that extends between the sidewall 314B and the sidewall 315B. A width x2is defined between the side walls 314A, 314B and the side walls 315A, 315B. In the depicted embodiment, width x2is less than width x1because contact bulk layer 286 is selectively removed with respect to contact blocking layer 284 during contact etchback. In some embodiments, the width x2is about 8 nm to about 30 nm. In some embodiments, width x2is greater than or equal to width x1. The side walls 314A, 314B and 315A, 315B taper such that the lower width of the lower portions 311A, 311B is less than the upper width of the lower portions 311A, 311B. The width x 2 thus decreases in the z direction from the upper width to the lower width of the lower parts 311A, 311B. A depth d2is defined between a top surface of the ILD layer 254 and the bottom 316A, 316B, respectively. In some embodiments, depth d 2 is less than depth d 1. In some embodiments, the depth d 2 is less than or equal to about 30 nm.The lower portions 311A, 311B in FIGS. 7B and 7C further include curved walls 318A and 318B (defined by the contact volume layer 286), respectively. The depth d 2 is further defined between the top surface of the ILD layer 254 and the curved sidewalls 318A, 318B, respectively, in the YZ plane. Accordingly, in the depicted embodiment, the depth d 2 is substantially equal in the x-direction, but varies in the y-direction. The curved side walls 318A, 318B also define a width y2, respectively. In the depicted embodiment, the upper widths of the lower portions 311A, 311B are greater than the lower widths of the upper portions 310A, 310B because the contact etch back is isotropic in nature (in other words, in the contact etch back, portions of the contact volume layer 286 are laterally (e.g., in the x and y directions) and vertically (e.g., in the z direction)). The width y 2 is larger than the width y 1, for example. In some embodiments, the width y2is about 10 nm to about 50 nm. In some embodiments, the width y2is about 10 nm to about 20 nm greater than the width y1. In some embodiments, the contact etch back exposes a portion of a bottom surface of the CESL 294, such as the CESL surfaces 320A and 320B. In some embodiments, a width y 3 of the exposed CESL surfaces 320A, 320B is less than or equal to about 10 nm. Due to the curved side walls 318A, 318B, the lower parts 311A, 311B have a tapering width in the YZ plane, so that the width y2 decreases in the z-direction from top to bottom at the lower parts 311A, 311B.In FIGS. 8A through 8C, a via bulk material 330 is formed in the interconnect openings 300A, 300B by a bottom-to-top deposition process. The via bulk material 330 includes tungsten, tungsten alloy, ruthenium, ruthenium alloy, cobalt, cobalt alloy, copper, copper alloy, aluminum, aluminum alloy, iridium, iridium alloy, palladium, palladium alloy, platinum, platinum alloy, nickel, nickel alloy, other low resistivity metal components and / or alloys thereof, or combinations thereof. The bottom-up deposition process generally refers to a deposition process in which an opening is filled from bottom-up (which may also be referred to as bottom-up filling or bottom-to-top filling of an opening). In some embodiments, the bottom-up deposition process is selective CVD, wherein various parameters of the selective CVD are tuned to selectively grow tungsten, ruthenium, cobalt, or alloys thereof on the contact bulk layer 286 and / or the contact barrier layer 284 while restricting (or preventing) growth of tungsten, ruthenium, cobalt, or alloys thereof on the ILD layer 292 and / or the CESL 294. The various parameters include deposition precursors (e.g., metal precursors and / or reactants), flow rates of deposition precursors, deposition temperature, deposition time, deposition pressure, other suitable deposition parameters, or combinations thereof. In the depicted embodiment, various parameters of selective CVD are tuned so that polycrystalline tungsten is selectively grown on the contact volume layer 286 in a reduction reaction. In such embodiments, selective CVD includes introducing a tungsten-containing precursor (e.g., WF x( where x indicates a number of F atoms and x≥1), WCl y( where y indicates a number of Cl atoms and y≥1), another suitable tungsten-containing gas, or combinations thereof) and a reaction precursor (e.g., H 2, another suitable reaction gas, or combinations thereof) into a process chamber for depositing via bulk material 330 on the contact bulk layer 286 in the interconnect openings 300A, 300B. In some embodiments, a carrier gas is used to supply the tungsten-containing precursor gas and / or the reaction gas into the process chamber. The carrier gas may be an inert gas such as an argon-containing gas, a helium-containing gas, a xenon-containing gas, another suitable inert gas, or combinations thereof. In some embodiments where the tungsten-containing precursor is tungsten hexafluoride (e.g., WF 6) this may be reduced according to the following example reduction reaction with H 2In some embodiments where the tungsten-containing precursor is tungsten pentachloride (e.g. WCl 5) this may be reduced according to the following exemplary reduction reaction with H 2 :In some embodiments, the tungsten-containing precursor is mixed with the reaction gas (e.g., H 2) and a proportion of the tungsten-containing precursor in the reaction gas is about 0.1% to about 1.5%. In some embodiments, a pressure maintained in the process chamber during the selective CVD is about 1 mTorr to about 50 mTorr (1 Torr = 133 Pa). In some embodiments, a temperature of the IC device 200 (e.g., the substrate 210) in the targeted CVD is about 200° C. to about 400° C. In some embodiments, the various parameters of the bottom-up deposition process are tuned to minimize variations in via bulk material 330 in interconnect openings of the IC device 200 as described above and herein. In some embodiments, the bottom-up deposition process is an ALD, where various parameters of the ALD are tuned to selectively grow tungsten, ruthenium, cobalt, or alloys thereof on the contact bulk layer 286 and / or the contact barrier layer 284 while restricting (or preventing) growth of tungsten, ruthenium, cobalt, or alloys thereof on the ILD layer 292 and / or the CESL 294. In some embodiments, multiple ALD cycles are performed to form via bulk material 330. In some embodiments, the bottom-up deposition process is a plurality of cycles of deposition / etch steps, including, for example, depositing a via bulk material over the IC device 200 and then etching back the via bulk material.As depicted in FIGS. 8A through 8C, via bulk material 330 may not be uniformly deposited in interconnect openings such as interconnect opening 300A and interconnect opening 300B on IC device 200 during the bottom-up deposition process. For example, via bulk material 330 partially fills interconnect opening 300A while completely filling interconnect opening 300B. In the depicted embodiment, via bulk material 330 fills bottom portions 311A, 311B completely, top portion 310A partially, and top portion 310B completely. The via bulk material 330 filling the interconnect opening 300A has a height (or thickness) h1 defined between the source-drain contact 282A (particularly the top surface of the contact bulk layer 286) and a top surface 332A of the via bulk material 330, and the via bulk material 330 filling the interconnect opening 300B has a height (or thickness) h2 defined between the source-drain contact 282B (particularly the top surface of the contact bulk layer 286) and a top surface 332B of the via bulk material 330. In some embodiments, height h 1 is about 20 nm to about 50 nm and height h 2 is about 40 nm to about 130 nm. In some embodiments, the ratio of height h 1 to height h 2 is about 1:2 to about 1:7. In some embodiments, a variation Δh in height (growth) between via bulk material 330 deposited (grown) in interconnect openings of IC device 200 such as interconnect openings 300A, 300B is about 20 nm to about 80 nm. In the depicted embodiment, the top surface 332A and the top surface 332B have a different surface profile. For example, the top surface 332A is a substantially planar surface and the top surface 332B is a substantially curved surface, however, the present disclosure recognizes that both the planar and curved surfaces may have irregularities and / or roughness that may occur due to the bottom-up deposition process (i.e., the planar and curved surfaces may not be as smooth as depicted). In some embodiments, the top surface 332A and the top surface 332B are substantially planar or substantially curved surfaces. In some embodiments, the top surface 332A is a substantially curved surface while the top surface 332B is a substantially planar surface. A remaining (unfilled) portion of the interconnect opening 300A has a depth d1' defined between a top surface of the ILD layer 292 and the top surface 332A of the via bulk material 330. In some embodiments, the depth d1' is less than about 30 nm. The depth d1' is less than the depth d1, thereby reducing an aspect ratio of the interconnect openings 300A, 300B. In some embodiments, an aspect ratio (e.g., d1' / x1) of the interconnect openings 300A, 300B after the bottom-up deposition process is less than about 5, and in some embodiments less than about 3. In the depicted embodiment, via bulk material 330 overfills interconnect opening 300B and extends over and on the top surface of ILD layer 292. For example, a portion of the via bulk material 330 forms a via rivet head having a height (or thickness) h 3 defined between the top surface of the ILD layer 292 and the top surface 332B of the via bulk material 330. In some embodiments, the height h3is about 5 nm to about 20 nm. The via rivet head has a width that is greater than the width y 1. In the depicted embodiment, via bulk material 330 of the via rivet head extends over the top surface of ILD layer 292. In such embodiments, a width y 4 of a portion of the top surface of the ILD layer 292 covered with the via bulk material 330 is about 5 nm to about 15 nm. In some embodiments, as depicted, width y 4 is greater than width y 3. In some embodiments, the width y4is substantially less than or equal to the width y3. As the height h 3 of the via rivet head increases, the residual stress within the via bulk material 330 increases, which may result in cracks during continuous growth of the via bulk material 330 and / or during subsequent processing. In some embodiments, the bottom-up deposition process is tuned accordingly such that height h 3 is limited to a predetermined height that may minimize the residual stress of via bulk material 330, while simultaneously ensuring that height h 1 is sufficient to reduce an aspect ratio of interconnect openings 300A, 300B to a range where filling of the gap with metal improves. For example, in some embodiments, the bottom-up deposition process is tuned to ensure that height h3is less than or equal to 20 nm to minimize the residual stress of via bulk material 330, while height h1is within a desired height range that achieves a depth d1' of less than about 30 nm, thus providing gaps for interconnect openings 300A, 300B with aspect ratios with better metal fill characteristics. In such an example, if the height h3is greater than 20 nm, the via bulk material 330 may have a degree of residual stress that results in cracks in the via bulk material 330 that affect the performance of the IC device 200.In FIGS. 9A through 9C, a via barrier layer 335 (also referred to as a via liner layer) is formed over the via bulk material 330. Via barrier layer 335 is formed over the top surface of ILD layer 292, top surfaces 332A, 332B of via bulk material 330, and sidewalls 302A, 304A defining a remainder of top portion 310A. Via blocking layer 335 is formed in and partially fills interconnect opening 300A. The deposited via barrier layer 335 floats over the source-drain contact 282A in the interconnect opening 300A and is not in physical contact therewith. In the depicted embodiment, via barrier layer 335 has a thickness t 3 over the top surface of ILD layer 292 and top surfaces 332A, 332B of via bulk material 330 and a thickness t 4 over sidewalls 302A, 304A defining a remainder of top portion 310A. In the depicted embodiment, thickness t 3 is greater than thickness t 4. For example, thickness t 3 is about 4 nm to about 8 nm and thickness t 4 is about 1 nm to about 3 nm. With a thickness t4of more than 3 nm, there may not be enough space for a subsequently deposited via bulk material, which may lead to gap filling problems (e.g., voids in the vias). In some embodiments, via barrier layer 335 is conformally deposited over IC device 200 such that thickness t 3 substantially corresponds to thickness t 4. In some embodiments, depending on process conditions, thickness t 3 is less than thickness t 4. In some embodiments, via barrier layer 335 is formed over via bulk material 330 to reduce residual stress and prevent cracks in via bulk material 330. In some embodiments, via bulk material 330 may completely fill both interconnect openings 300A, 300B (and in some embodiments, all interconnect openings on a wafer). In such embodiments, via barrier layer 335 (and via bulk material formed as described below) may still be formed to reduce residual stress and prevent cracks in via bulk material 330, for example, during a planarization process. Via blocking layer 335 includes a material that improves adhesion between a dielectric material (here, ILD layer 292) and a subsequently formed metal material for filling a remainder of interconnect opening 300A. Via barrier layer 335 includes, for example, titanium, titanium alloy, tantalum, tantalum alloy, cobalt, cobalt alloy, ruthenium, ruthenium alloy, molybdenum, molybdenum alloy, tungsten, tungsten alloy, or other suitable component configured to improve and / or increase adhesion between a metal material and a dielectric material, or combinations thereof. In the depicted embodiment, via barrier layer 335 includes tantalum and nitrogen (e.g., tantalum nitride), titanium and nitrogen (e.g., titanium nitride), tungsten and nitrogen (e.g., tungsten nitride), or tungsten. In some embodiments, via barrier layer 335 includes multiple layers. Via barrier layer 335 includes, for example, a first sublayer including titanium and a second sublayer including titanium nitride disposed over the first sublayer. In another example, via barrier layer 335 may include a first sub-layer including tantalum and a second sub-layer including tantalum nitride.Via barrier layer 335 is deposited by PVD, CVD, ALD, electroplating, electroless plating, other suitable deposition process, or combinations thereof. In some embodiments, via barrier layer 335 is a titanium nitride layer formed by performing PVD to deposit a titanium layer over IC device 200 and subsequently performing a nitrogen plasma treatment of the titanium layer. In some embodiments, a pressure maintained during PVD in a process chamber is about 10 mTorr to about 1 mTorr (1 Torr = 133 Pa). In some embodiments, a temperature maintained in the process chamber during PVD is about 300° C. to about 450° C. In some embodiments, the PVD is a radio frequency (RF) sputtering process. In such embodiments, the RF sputtering process may implement an RF power of about 1 kilowatts (kW) to about 2 kW. In some embodiments, the nitrogen plasma treatment includes treating the titanium layer with a nitrogen-containing plasma (i.e., the titanium layer is blasted with plasma-excited nitrogen-containing species to drive the nitrogen into the titanium layer). In some embodiments, via barrier layer 335 includes a titanium nitride layer disposed over a titanium layer, the titanium layer formed by performing PVD and the titanium nitride layer formed by performing CVD. In some embodiments, a pressure maintained during PVD in a process chamber is about 10 mTorr to about 150 mTorr. In some embodiments, a temperature maintained during PVD in the process chamber is about 400° C. to about 500° C. In embodiments where PVD is an RF sputtering process, PVD may implement an RF power of about 3 kW to about 5 kW. In some embodiments, the CVD implements a titanium-containing precursor such as tetrakis(dimethylamino)titanium (TDMAT). In some embodiments, a pressure maintained in a process chamber during CVD is about 1 mTorr to about 5 mTorr. In some embodiments, a temperature maintained in the process chamber during CVD is about 100° C. to about 500° C. In some embodiments, the via barrier layer 335 includes a tungsten-containing layer formed by CVD, wherein the CVD implements a tungsten-containing precursor such as tungsten hexacarbonyl (W(CO) 6). In some embodiments, the CVD process implements a mixture of the tungsten-containing precursor with hydrogen (H 2), silane (SiH 4) and / or borane (for example diborane (B 2 H 6)).In FIGS. 10A through 10C, via bulk material 340 is formed over via barrier layer 335. Via bulk material 340 is formed in and fills a remainder of top portion 310A of interconnect opening 300A. In the depicted embodiment, via bulk material 340 is disposed over and covers the top surface of ILD layer 292 and top surface 332B of via bulk material 330. In some embodiments, depending on its thickness, the via bulk material 340 does not or only partially cover the top surface 332B. The via bulk material 340 includes tungsten, tungsten alloy, ruthenium, ruthenium alloy, cobalt, cobalt alloy, copper, copper alloy, aluminum, aluminum alloy, iridium, iridium alloy, palladium, palladium alloy, platinum, platinum alloy, nickel, nickel alloy, other low resistivity metal components and / or alloys thereof, or combinations thereof. In the depicted embodiment, via bulk material 340 and via bulk material 330 include the same material. Thus, via bulk material 340 and via bulk material 330 may include tungsten. In some embodiments, via bulk material 340 and via bulk material 330 include different metals. In the depicted embodiment, via bulk material 340 and via bulk material 330 are formed by different processes. For example, to deposit via bulk material 340 over via barrier layer 335, a blanket deposition process such as blanket CVD is performed. In the blanket deposition process, via bulk material 340 is deposited over all exposed surfaces of IC device 200. In some embodiments, blanket CVD includes introducing a tungsten-containing precursor (e.g., WF 6 or WCl 5 and a reaction precursor (e.g., H 2, another suitable reaction gas, or combinations thereof)) into a process chamber. In some embodiments, a carrier gas is used to supply the tungsten-containing precursor gas and / or the reaction gas into the process chamber. The carrier gas may be an inert gas such as an argon-containing gas, a helium-containing gas, a xenon-containing gas, another suitable inert gas, or combinations thereof. In some embodiments, a pressure maintained in a process chamber during blanket CVD is about 1 mTorr to about 500 mTorr. In some embodiments, a temperature maintained in the process chamber during blanket CVD is about 200° C. to about 400° C. In some embodiments, the blanket deposition process is PVD, ALD, electroplating, electroless plating, another suitable deposition process, or combinations thereof.In FIGS. 11A-11C, a CMP process and / or another planarization process is performed to remove excess via bulk material 340, excess via barrier layer 335, and excess via bulk material 330 (such as that disposed over the top surface of ILD layer 292), thereby forming via 350A and via 350B of MLI element 250. Via 350A electrically and / or physically couples source-drain contact 282A to a conductive feature of MLI element 250, such as a first line of a metal layer of MLI element 250 (e.g., a metal 1 layer (M1 layer)), and via 350B electrically and / or physically couples source-drain contact 282B to a conductive feature of MLI element 250, such as a second line of a metal layer of MLI element 250 (e.g., the M1 layer). Vias 350A, 350B may therefore be referred to as vias to contacts. In the CMP process, top surfaces of vias 350A, 350B may be planarized such that the top surface of ILD layer 292 and the top surfaces of vias 350A, 350B are substantially planar surfaces. Vias 350A, 350B include via bulk material 340, via blocking layer 335, and / or via bulk material 330 remaining in interconnect openings 300A, 300B after the planarization process, each referred to as via bulk material 340', via blocking layer 335', and / or via bulk material 330'. Via 350A includes a lower via portion AL and an upper via portion AU, and via 350B includes a lower via portion BL and an upper via portion BU. The lower via portions AL, BL extend into the source-drain contacts 282A, 282B, respectively. More specifically, the lower via portions Al, BL each extend from the top surface of the ILD layer 254 to the top surface of the contact blocking layer 284 of the source-drain contacts 282A, 282B. The lower via portions AL, BL have a width x2in the x direction, a width y2in the y direction and a thickness t5in the z direction. In the depicted embodiment, thickness t 5 is approximately equal to depth d 2 (thickness t 5 is less than or equal to about 10 nm, for example). The upper via portions AU, BU extend through the ILD layer 292 and the CESL 294, for example, from the upper surface of the ILD layer 292 to the upper surface of the ILD layer 254. The upper via portions AU, BU have a width x1 in the x direction, a width y1 in the y direction and a thickness t6 in the z direction. In the depicted embodiment, the thickness t 6 is approximately equal to the depth d 1 (the thickness t 6 is, for example, about 20 nm to about 80 nm). In the depicted embodiment, a width of the lower via portions AL, BL in the XZ plane is less than a width of the upper via portions AU, BU (i.e., the width x 2 is less than the width x 1) and a width of the lower via portions AL, BL in the YZ plane is greater than a width of the upper via portions AU, BU (i.e., the width y 2 is greater than the width y 1). In some embodiments, the width of the lower via portions AL, BL in the XZ plane is equal to or greater than the width of the upper via portions AU, BU. In some embodiments, the width of the lower via portions AL, BL in the YZ plane is less than or approximately equal to the width of the upper via portions AU, BU.The lower via part AL and the lower via part BL are substantially the same as each other. Each of the bottom via portions AL, BL includes, for example, a bottom portion of the via volume layer 330' that is in physical contact with the contact barrier layer 284 and the contact volume layer 286, respectively, of the source-drain contacts 282A, 282B. In the XZ plane, the bottom portions of the via volume layer 330' have tapered, substantially planar side surfaces that are respectively connected to the contact blocking layer 284 of the source-drain contacts 282A, 282B and substantially planar bottom surfaces that are respectively connected to the contact volume layer 286 of the source-drain contacts 282A, 282B. The contact barrier layer 284 separates the tapered, substantially planar side surfaces of the lower portions of the via volume layer 330' from the ILD layer 254. In the YZ plane, the bottom portions of the via volume layer 330' have substantially curved surfaces that are respectively connected to the contact volume layer 286 of the source-drain contacts 282A, 282B. The contact volume layer 286 and the contact barrier layer 284 separate the substantially curved surfaces of the bottom portions of the via volume layer 330' from the ILD layer 254. The lower via portions AL, BL increase a contact area between the vias 350A, 350B and the source-drain contacts 282A, 282B, so that a resistance between the vias 350A, 350B and the source-drain contacts 282A, 282B is reduced, thereby improving overall performance of the IC device 200. For example, instead of vias 350A, 350B each having a single interface between bottom surfaces of vias 350A, 350B and top surfaces of source-drain contacts 282A, 282B, bottom via portions AL, BL are respectively surrounded by source-drain contacts 282A, 282B and each have multiple interfaces (e.g., bottom interfaces and side interfaces) to source-drain contacts 282A, 282B. The larger contact area provided by the lower via parts AL, BL also improves the mechanical strength and thus the structural stability of the vias 350A, 350B. Moreover, in the YZ plane, portions of the via volume layer 330' that extend below and abut the CESL surfaces 320A, 320B, respectively, attach the vias 350A, 350B to the source-drain contacts 282A, 282B, thereby further improving the mechanical strength and, thus, the structural stability of the vias 350A, 350B.Because the growth (and thus height) of the via bulk material 330 in interconnect openings of the IC device 200 is subject to variations, the via bulk layer 335' is irregularly placed in vias of the IC device 200 to form vias on the device 200 to the source-drain contacts of different configurations. For example, in Figures 11A-11C, since via bulk material 330 partially fills interconnect opening 300A and completely fills interconnect opening 300B, upper via portion AU of via 350A includes via bulk layer 330', via blocking layer 335' and via bulk layer 340', while upper via portion BU of via 350B includes only via bulk layer 330'. The upper via part AU may be divided into an upper via part AU- 1 and an upper via part AU- 2. The upper via part AU- 1 is similar to the upper via part BU, except a thickness of the upper via part AU- 1 is less than a thickness of the upper via part BU. Each of the upper via portions AU-1, BU includes, for example, an upper portion of the via volume layer 330'. The upper portion of via volume layer 330' has a thickness t6in via 350B, while the upper portion of via volume layer 330' has a thickness t7in via 350A that is less than thickness t6. In the XZ and YZ planes, the upper portions of the via volume layer 330' have conically extending, substantially planar side surfaces that are in physical contact with and connected to the ILD layer 292 and the CESL 294. Thus, there is no barrier layer (or liner layer) between the upper via portions AU- 1, BU and a dielectric layer of the MLI element 250 (e.g., CESL 294 and ILD layer 292). In the depicted embodiment, via 350B may be referred to as a barrier-free via, because no barrier layer is disposed between via bulk layer 330' and ILD layer 292 or CESL 294. In contrast, since the upper via portion AU-1 does not have a barrier layer between the via volume layer 330' and the ILD layer 292 or the CESL 294, but the upper via portion AU-2 has a via barrier layer 335' disposed between the via volume layer 340 and the ILD 292, the via 350A may be referred to as a partially barrier-free via. In Figures 11A-11C, via barrier layer 335' is further disposed between via bulk layer 340' and via bulk layer 330' so as to float in via 350A and not be in physical contact with source-drain contact 282A. The upper via portion AU- 2 has a thickness t 8 in the z direction. In the depicted embodiment, thickness t8is approximately equal to depth d1' (thickness t8, for example, is about 1 nm to about 50 nm). In some embodiments, a ratio of the thickness t 8 to the width x 1 (e.g., t 8 / x 1) of the upper via portion AU- 2 is less than about 5, and in some embodiments less than about 3. the thickness t 8 may be greater than or equal to the thickness t 7, depending on the growth of the via bulk material 330.In another example, such as that depicted in FIGS. 17A through 17C, because the growth (and thus height) of the via bulk material 330 in the interconnect openings of the IC device 200 varies, rather than partially filling the interconnect opening 300A and completely filling the interconnect opening 300B, the via bulk material 330 partially fills both the interconnect opening 300A and the interconnect opening 300B, but with different thicknesses. In such embodiments, the upper via portion AU of via 350A and the upper via portion BU of via 350B each include via volume layer 330', via barrier layer 335', and via volume layer 340'. The upper via part AU may be divided into an upper via part AU- 1 and an upper via part AU- 2, and the upper via part BU may be divided into an upper via part BU- 1 and an upper via part BU- 2. The upper via portion AU- 1 is similar to the upper via portion BU- 1, except a thickness of the upper via portion AU- 1 is less than a thickness of the upper via portion BU- 1. For example, each of the upper via portions AU- 1, BU- 1 includes an upper portion of the via volume layer 330', however, the upper portion of the via volume layer 330' in the via 350B has a thickness t9 and the upper portion of the via volume layer 330' has a thickness t7 that is less than the thickness t9. Both the thickness t 7 and the thickness t 9 are less than the thickness t 6 of the upper via parts AU, BU. In the XZ and YZ planes, the upper portions of the via volume layer 330' have conically extending, substantially planar side surfaces that are in physical contact with and connected to the ILD layer 292 and the CESL 294. Thus, there is no barrier layer (or liner layer) between the upper via portions AU- 1, BU- 1 and a dielectric layer of the MLI element 250 (e.g., CESL 294 and ILD layer 292). Because the upper via portions AU- 1, BU- 1 do not have a barrier layer between the via bulk layer 330' and the ILD layer 292 or the CESL 294 in the depicted embodiment, but the upper via portions AU- 2, BU- 2 have a via barrier layer 335' disposed between the via bulk layer 340 and the ILD 292, the vias 350A, 350B may be referred to as a partially barrier-free via. In Figures 17A-17C, via barrier layer 335' is further disposed between via bulk layer 340' and via bulk layer 330' so as to float in via 350A and via 350B and not in physical contact with source-drain contacts 282A, 282B. The upper via portion BU- 2 has a thickness t10 that is less than the thickness t8 of the upper via portion AU- 2 such that the via blocking layer 335' is placed differently in the via 350A than in the via 350B. In the depicted embodiment, a distance between an upper surface of substrate 210 and via barrier layer 335' of via 350A (particularly a lower surface of via barrier layer 335') is less than a distance between the upper surface of substrate 210 and via barrier layer 335' of via 350B (particularly a lower surface of via barrier layer 335'). In some embodiments, a ratio of thickness t 8 to width x 1 (e.g., t 8 / x 1) of top via portion AU- 2 and a ratio of thickness t 10 to width x 1 (e.g., t 10 / x 1) of top via portion BU- 2 in FIGS. 17A-17C are each less than about 5, and in some embodiments less than about 3.In FIGS. 12-15, a via is formed to one or more gate structures of IC device 200, such as gate structure 230B. In FIG. 12, an interconnect opening 360 is formed in a dielectric layer via a patterning process such as those described herein. The interconnect opening 360 extends vertically through the ILD layer 292, the CESL 294, the ILD layer 254, and the CESL 264 to the metal gate stack 232 of the gate structure 230B. The interconnect opening 360 may be referred to as a gate contact opening (plug opening). The interconnect opening 360 includes a sidewall 362 (defined by the ILD layer 292, the CESL 294, the ILD layer 254, and the CESL 264), a sidewall 364 (defined by the ILD layer 292, the CESL 294, the ILD layer 254, and the CESL 264), and a bottom 366 (defined by a metal gate stack 232) that extends between the sidewall 362 and the sidewall 364. The interconnect opening 360 in FIG. 12 has a trapezoidal shape, however, the present disclosure contemplates an interconnect opening 360 of another shape, such as rectangular shape. The sidewalls 362, 364 taper such that a lower width of the interconnect opening 360 exposing the metal gate stack 232 of the gate structure 230B is less than an upper width of the interconnect opening 360 at an upper surface of the ILD layer 292. A width of the interconnect opening 360 thus decreases along the z-direction from top to bottom. In some embodiments, the width of the interconnect opening 360 increases in the z-direction. In some embodiments, the width of the interconnect opening 360 increases in the z-direction.In some embodiments, the patterning process includes performing a lithography process to form a patterned mask layer 365 having an opening 367 (substantially aligned with metal gate stacks 232 of the gate structure 232B), and performing an etching process to transfer a pattern defined in the patterned mask layer 365 to an underlying dielectric layer (here, the ILD layer 292, the CESL 294, the ILD layer 254, and the CESL 264). The patterning process for forming the patterned mask layer 365 and the interconnect opening 360 may be similar to the patterning process described above for forming the patterned mask layer 278 and the interconnect openings 300A, 300B. In some embodiments, the patterned mask layer 365 is a patterned resist layer. In such embodiments, the patterned resist layer is used as an etch mask for removing portions of the underlying dielectric layer exposed by the opening 367. In some embodiments, the patterned resist layer is formed over a mask layer formed over the underlying dielectric layer prior to forming the resist layer, and the patterned resist layer is used as an etch mask for removing portions of the mask layer formed over the underlying dielectric layer, thereby forming the patterned mask layer 365. In such embodiments, the patterned mask layer is used as an etch mask for removing portions of the underlying dielectric layer exposed by the opening 367. Various selective etching processes may be performed to form the interconnect opening 360. The etching process may include, for example, a first etch in which the ILD layer 292 is selectively etched with respect to the patterned mask layer 365 and the CESL 294 such that the first etch stops when it reaches the CESL 294, a second etch in which the CESL 294 is selectively etched with respect to the ILD layers 294, 254 such that the second etch stops when it reaches the ILD layer 254, a third etch in which the ILD layer 254 is selectively etched with respect to the CESL 294, 264 such that the third etch stops when it reaches the CESL 264, and a fourth etch, wherein the CESL 264 is selectively etched with respect to the ILD layers 292, 254 and the metal gate stack 232 of the gate structure 230B such that the fourth etch stops when it reaches the metal gate stack 232. In some embodiments, the first, second, third, and fourth etchings may be configured to overetch slightly as described herein. In some embodiments, the etching process may include multiple steps for etching the CESL 294, 264. In some embodiments, the etching process implements an etchant with low etch selectivity between the ILD layers 292, 254 and the CESL 294, 264 such that the interconnect opening 360 is formed by a single etching step based on time, for example. In some embodiments, after the etching process, the patterned mask layer 365 is removed (in some embodiments, by a resist stripping process) from the ILD layer 292. In some embodiments, the patterned resist layer 365 is removed during etching of the ILD layer 292, the CESL 294, the ILD layer 254, and / or the CESL 264.In FIG. 13, a via barrier layer 370 (also referred to as a via liner layer) is formed over the IC device 200. Via blocking layer 370 is formed over, for example, the top surface of ILD layer 292, the top surfaces of vias 350A, 350B, sidewalls 362, 364 of interconnect opening 360A, and bottom 366 of interconnect opening 360. Via blocking layer 370 is formed in and partially fills interconnect opening 360. In the depicted embodiment, via barrier layer 370 has a thickness t 9 over the top surface of ILD layer 292 and the top surfaces of vias 350A, 350B, and a thickness t 10 over sidewalls 362, 364 of interconnect opening 360. In the depicted embodiment, thickness t 9 is greater than thickness t 10. For example, thickness t 9 is about 4 nm to about 8 nm and thickness t 10 is about 1 nm to about 3 nm. In some embodiments, via barrier layer 370 is conformally deposited over IC device 200 such that thickness t 9 substantially corresponds to thickness t 10. In some embodiments, depending on process conditions, thickness t 9 is less than thickness t 10. Via barrier layer 370 includes a material that improves adhesion between a dielectric material (here, ILD layer 292, CESL 294, ILD layer 254, and CESL 264) and a subsequently formed metal material to fill a remainder of interconnect opening 360. Via barrier layer 370 includes, for example, titanium, titanium alloy, tantalum, tantalum alloy, cobalt, cobalt alloy, ruthenium, ruthenium alloy, molybdenum, molybdenum alloy, tungsten, tungsten alloy, or other suitable component configured to improve and / or increase adhesion between a metal material and a dielectric material, or combinations thereof. In the depicted embodiment, via barrier layer 370 includes tantalum and nitrogen (e.g., tantalum nitride), titanium and nitrogen (e.g., titanium nitride), tungsten and nitrogen (e.g., tungsten nitride), or tungsten. In some embodiments, the via barrier layer 370 includes multiple layers. Via barrier layer 370 includes, for example, a first sub-layer including titanium and a second sub-layer including titanium nitride disposed over the first sub-layer. In another example, the via blocking layer 370 may include a first sub-layer including tantalum and a second sub-layer including tantalum nitride. The via barrier layer 370 is deposited by PVD, CVD, ALD, electroplating, electroless plating, other suitable deposition process, or combinations thereof. In some embodiments, via barrier layer 370 is similar to via barrier layer 335 and is formed using processes similar to those described above for forming via barrier layer 335.In FIG. 14, via bulk material 375 is formed over via barrier layer 370. Via volume layer 375 is formed in and fills a remainder of interconnect opening 360. In the depicted embodiment, via volume layer 375 is disposed over and covers the top surface of ILD layer 292 and top surfaces of vias 350A, 350B. The via volume layer 375 includes tungsten, tungsten alloy, ruthenium, ruthenium alloy, cobalt, cobalt alloy, copper, copper alloy, aluminum, aluminum alloy, iridium, iridium alloy, palladium, palladium alloy, platinum, platinum alloy, nickel, nickel alloy, other low resistivity metal components and / or alloys thereof, or combinations thereof. In the depicted embodiment, via volume layer 375 includes tungsten. Via bulk layer 375 is deposited by PVD, CVD, ALD, electroplating, electroless plating, other suitable deposition process, or combinations thereof. In some embodiments, via volume layer 375 is similar to via volume material 340 and is formed using processes similar to those described above for forming via volume material 340. For example, to deposit via bulk material 375 over via barrier layer 370, a blanket deposition process such as blanket CVD is performed.In FIG. 15, to remove excess via bulk layer 375 and excess via barrier layer 370 (such as that disposed over the top surface of ILD layer 292 and the top surfaces of vias 350A, 350B), A CMP process and / or other planarization process is performed, thereby forming a via 380 of MLI element 250. Via 380 includes via bulk material 375 and via barrier layer 370 remaining in interconnect opening 360 after the planarization process, referred to as via bulk layer 375' and via barrier layer 370', respectively. Via 380 electrically and / or physically couples metal gate stack 232 of gate structure 230B to a conductive feature of MLI element 250, such as a third line of a metal layer of MLI element 250 (e.g., the M1 layer). The via 380 may therefore be referred to as a via to the gate. Via 380 extends through ILD layer 292, CESL 294, ILD layer 254, and CESL 264. The through-via 380 has a width x 4 in the x direction and a thickness t 11 in the z direction. In the depicted embodiment, thickness t 11 is greater than thickness t 6 of vias 350A, 350B and thickness x 4 is less than thickness x 1 of vias 350A, 350B. In the CMP process, top surfaces of via 380 may be planarized such that the top surface of ILD layer 292, the top surfaces of vias 350A, 350B, and the top surface of via 380 are substantially planar surfaces.In FIG. 16, the fabrication of the MLI element 250 may be continued, for example, by forming additional dielectric layers and metal layers of the MLI element 250. For example, a CESL 390 (similar to CESL 262, 264, 294) is formed over ILD layer 292, vias 350A, 350B, and via 380, an ILD layer 392 (similar to ILD layers 252, 254, 292) is formed over CESL 390, and one or more lines (e.g., line 394A, line 394B, and line 394C) are formed in ILD layer 392 and CESL 390. The leads 394A- 394C include tungsten, ruthenium, cobalt, copper, aluminum, iridium, palladium, platinum, nickel, a low resistivity metal component, alloys thereof, or combinations thereof. In some embodiments, forming the lines 394A- 394C includes performing a lithography and etching process to form three interconnect openings in the ILD layer 392 and the CESL 390 (here, exposing the via 350A, the via 350B, and the via 380), filling the interconnect openings with a conductive material, and performing a planarization process in which excess conductive material is removed such that the conductive material and the ILD layer 392 have a substantially planar surface. The interconnect openings have sidewalls defined by the ILD layer 392 (along with the CESL 390) and a bottom defined by a corresponding via. The conductive material is formed by a deposition process (e.g., PVD, CVD, ALD, and / or other suitable deposition process) and / or an annealing process. In some embodiments, the leads 394A- 394C include a bulk layer (also referred to as conductive plugs). In some embodiments, the lines 394A- 394C include a barrier layer, an adhesion layer, and / or another suitable layer disposed between the bulk layer and the ILD layer 392 (along with the CESL 390). In such embodiments, the barrier layer and / or the adhesion layer conform to the interconnect openings such that the barrier layer and / or the adhesion layer is disposed on the ILD layer 392 (along with the CESL 390) and the bulk layer is disposed on the barrier layer and / or the adhesion layer. In some embodiments, the barrier layer, adhesion layer, and / or other suitable layer includes titanium, titanium alloy (e.g., TiN), tantalum, tantalum alloy (e.g., TaN), other suitable constituent, or combinations thereof. In the depicted embodiment, the leads 394A- 394C have a rectangular cross-section. For example, the conduit 394A- 394C has a substantially planar bottom surface, a substantially planar top surface, and substantially planar sidewalls. In some embodiments, the sidewalls of the leads 394A- 394C taper such that a thickness of the leads 394A- 394C decreases from a top surface of the ILD layer 390 toward the top surface of the ILD layer 292. In the depicted embodiment, line 394A is further physically in contact with via 350A, line 394B is physically in contact with via 380, and line 394C is physically in contact with via 350B. In some embodiments, line 394A and line 394B respectively couple epitaxial source-drain elements 240B, 240C to a first voltage and line 394C couples metal gate 232 to a second voltage.The MLI element 250 in FIG. 16 includes a metal o-layer (Mo layer) (including source-drain contacts 282A, 282B), a metal 1 layer (M1 layer) (including lines 394A- 394C), and a via o-layer (Vo layer) (including vias 350A, 350B and via 380) that physically and electrically connects the Mo layer to the M1 layer. The Mo layer is a deepest lowermost contact / metal layer of the MLI element 250 that is in physical contact with substrate level device features (e.g., source-drain elements and / or gate structures), the Vo layer is a deepest lowermost via layer of the MLI element 250, and the M1 layer is a second deepest lowermost contact / metal layer of the MLI element 250. The Mo layer may also be referred to as a contact layer, local interconnect layer, or device level contact layer. In the depicted embodiment, via 380 is in direct and physical contact with gate structure 230B. In some embodiments, the Mo layer further includes a gate contact disposed between the via 380 and the gate structure 230B, where the via 380 is physically in contact with the gate contact and the gate contact is physically in contact with the gate structure 230B. In such embodiments, the gate contact may be configured similar to the source-drain contacts 282A, 282B. The gate contact may include, for example, a contact volume layer, such as contact volume layer 286, disposed over a contact blocking layer, such as contact blocking layer 284. In such embodiments, the contact volume layer of the gate contact is not recessed when forming the via 280, unlike the contact volume layer 286 of the source-drain contacts 282A, 282B, such that a contact blocking layer of the gate contact is not disposed at a portion of the sidewalls of the via 280. In some embodiments, the present disclosure contemplates recessing the contact volume layer of the gate contact prior to forming the via 280 such that the via 280 extends into the gate contact similar to the vias 350A, 350B. However, although not shown, it should be appreciated that the MLI element 250 may include additional metal layers and / or via layers formed over the M1 layer, such as a via 2 (V2) layer disposed over the M1 layer, a metal 2 (M2) layer formed over the V2 layer, and so forth, and that provide the desired electrical connection for the IC device 200. During production, the production of the MLI element 250 can then be continued. For example, additional levels of the MLI element 250 may be formed over the M1 layer, such as an M2 through to a Mn layer, where n represents a number of metal layers in the MLI element 250 and each of the M2 through to the Mn layers may include lines similar to lines 394A through 394C disposed in a dielectric material. Vias similar to vias 350A, 350B may be fabricated that connect metal layers directly adjacent to one another, such as the M2 layer to the M3 layer. In some embodiments, vias may connect metal layers that are not adjacent to one another.From the above description, it can be seen that vias described in the present disclosure provide advantages over conventional vias. It should be understood, however, that other embodiments may provide additional advantages and not necessarily all advantages are disclosed herein and that no particular advantage is provided in all embodiments. An advantage is that, to optimize the reduction of contact resistance, vias to contacts and vias to gates are provided with different configurations (in particular different interface configurations). For example, vias to contacts are at least partially barrier free to increase via to contact openings dimensions, thereby improving via to contact opening filling with metal (in some embodiments, imperfections in the vias to contacts are reduced or eliminated) and reducing via to contact resistance, while vias to gates have a via barrier layer to ensure minimum via to gate resistance. The present disclosure indicates that when via barriers are implemented in both contact vias and gate vias, contact-to-contact interfaces (e.g., between via barriers and source-drain contacts) cannot achieve the same resistance reduction as contact-to-gate interfaces (e.g., between via barriers and metal gates), and that a reduction in resistance through the via barriers in contact vias does not substantially account for the risk of voids forming in contact vias when the via barriers are incorporated therein. Thus, removing the via barriers from the vias to contacts reduces the risk of voids forming and thus minimizes the resistance for vias to contacts as well as (if not more than) for vias to contacts with via barriers. For example, vias to contacts with via barriers may contain voids, which results in the resistance of vias to contacts increasing more than by decreasing the resistance by integrating the via barriers. In another example, the via bulk via-to-contact material formed in a bottom-to-top deposition process described herein has low resistance characteristics. In yet another example, by forming a via barrier layer and an additional via volume layer after the bottom-to-top deposition process, full via-to-contact opening filling (considering growth variations arising from the bottom-to-top deposition process) is ensured and / or residual stress of the via volume layer is minimized and, thus, crack formation in the via volume layer is reduced or eliminated during planarization and / or other subsequent processing. The disclosed via fabrication methods thus address various via interface requirements and / or considerations.The present disclosure enables many different embodiments. An example interconnect structure includes first and second source-drain contacts disposed in a dielectric layer. The first source-drain contact is in physical contact with a first source-drain element and the second source-drain contact is in physical contact with a second source-drain element. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first and second vias extend into the first and second source-drain contacts, respectively, and are in physical contact therewith. A first thickness of the first via corresponds to a second thickness of the second via. The third via is in physical contact with a gate structure disposed between the first and second source-drain contacts. In some embodiments, the first via has a first upper portion disposed over a first lower portion and the second via has a second upper portion disposed over a second lower portion. In such embodiments, the dielectric layer is in physical contact with sidewalls of the first upper portion and the source-drain contact is in physical contact with sidewalls of the first lower portion, and the dielectric layer is in physical contact with sidewalls of the second upper portion and the second source-drain contact is in physical contact with sidewalls of the second lower portion. In some embodiments, the first and second vias each have a first cross-sectional profile in a first direction and a second cross-sectional profile in a second direction. The first direction is different from the second, and the first cross-sectional profile is different from the second. In some embodiments, the first and second vias each have a first bottom interface profile with the first and second source-drain contacts, respectively, in a first direction and a second bottom interface profile with the first and second source-drain contacts, respectively, in a second direction. The first direction is different from the second direction, the first ground interface profile is defined by a substantially planar surface, and the second ground interface profile is defined by a substantially curved surface.In some embodiments, the dielectric layer includes a first inter-level dielectric layer, a second inter-level dielectric layer disposed over the first inter-level dielectric layer, and a contact etch stop layer disposed between the first and second inter-level dielectric layers. The first and second source-drain contacts are disposed in and pass through the first inter-level dielectric layer. The first and second vias are disposed in and pass through the second inter-level dielectric layer and the contact etch stop layer. In such embodiments, a first portion of the first via extending into the first source-drain contact and a second portion of the second via extending into the second source-drain contact are in physical contact with a bottom surface of the contact etch stop layer.In some embodiments, the first via having the first via layer configuration includes a first via volume layer, a second via volume layer disposed over the first via volume layer, and a via barrier layer disposed between the first and second via volume layers. The first via volume layer is in physical contact with the dielectric layer, and the via barrier layer is further disposed between the second via volume layer and the dielectric layer. In such embodiments, the second via having the second via layer configuration further includes a third via volume layer in physical contact with the dielectric layer. The first and third via volume layers include a same material, the third via volume layer has the second thickness, and the first via volume layer has a third thickness less than the first thickness. In some embodiments, the first source-drain contact includes a first contact blocking layer and a first contact bulk layer, and the second source-drain contact includes a second contact blocking layer and a second contact bulk layer. In some embodiments, a first portion of the first contact blocking layer is disposed between the first contact bulk layer and the dielectric layer and a second portion of the first contact blocking layer is disposed between the first via bulk layer and the dielectric layer. In some embodiments, a first portion of the second contact blocking layer is disposed between the second contact bulk layer and the dielectric layer and a second portion of the second contact blocking layer is disposed between the third via bulk layer and the dielectric layer.In some embodiments, the first via having the first via layer configuration includes a first via volume layer, a second via volume layer disposed over the first via volume layer, and a via barrier layer disposed between the first and second via volume layers. The first via volume layer is in physical contact with the dielectric layer, and the first via barrier layer is further disposed between the second via volume layer and the dielectric layer. In such embodiments, the second via having the second via layer configuration further includes a third via volume layer, a fourth via volume layer disposed over the third via volume layer, and a second via barrier layer disposed between the third and fourth via volume layers. The third via volume layer is in physical contact with the dielectric layer, and the second via barrier layer is further disposed between the fourth via volume layer and the dielectric layer. In some embodiments, the first and third via volume layers include a first material, the second and fourth via volume layers include a second material, and the first and second via barrier layers include a third material. In some embodiments, a first distance between the first via barrier layer and a substrate is different than a second distance between the second via barrier layer and the substrate. In some embodiments, the first source-drain contact includes a first contact blocking layer and a first contact bulk layer, and the second source-drain contact includes a second contact blocking layer and a second contact bulk layer. A first portion of the first contact blocking layer is disposed between the first contact volume layer and the dielectric layer and a second portion of the first contact blocking layer is disposed between the first via volume layer and the dielectric layer. A first portion of the second contact blocking layer is disposed between the second contact volume layer and the dielectric layer and a second portion of the second contact blocking layer is disposed between the third via volume layer and the dielectric layer.An example device includes a gate structure disposed over a substrate. The gate structure is arranged between a first and a second source-drain element. The device further includes first and second source-drain contacts disposed in a dielectric layer. The first source-drain contact is in physical contact with the first source-drain element and the second source-drain contact is in physical contact with the second source-drain element. The device further includes first, second, and third vias disposed in the dielectric layer. The first via is in physical contact with the first source-drain contact, the second via is in physical contact with the second source-drain contact, and the third via is in physical contact with the gate structure. The first via includes a first metal fill layer having first sidewalls in physical contact with the dielectric layer. The second via includes a second metal fill layer having second sidewalls in physical contact with the dielectric layer. The third via includes a third metal fill layer disposed over a metal barrier layer. The metal barrier layer is disposed between the third metal fill layer and the dielectric layer such that third sidewalls of the third metal fill layer are not in physical contact with the dielectric layer. In some embodiments, the first and second vias have a first cross-sectional profile in a first direction and a second cross-sectional profile in a second direction. The first direction is different from the second. A first bottom of the first via and a second bottom of the second via have a substantially planar surface in the first cross-sectional profile and a substantially curved surface in the second cross-sectional profile.In some embodiments, the metal barrier layer is a first metal barrier layer. In such embodiments, the first via includes a first portion including the first metal fill layer and a second portion disposed over the first portion. The second portion includes a fourth metal fill layer disposed over a second metal barrier layer disposed between the fourth metal fill layer and the dielectric layer such that fourth sidewalls of the fourth metal fill layer are not in physical contact with the dielectric layer, and the second metal barrier layer is disposed between the first and fourth metal fill layers. In some embodiments, the first and second vias have a first thickness, the first metal fill layer has a second thickness less than the first thickness, and the second metal fill layer has a third thickness corresponding to the first thickness. In some embodiments, the second via includes a third portion including the second metal fill layer and a fourth portion disposed over the third portion. The fourth portion includes a fifth metal fill layer disposed over a third metal barrier layer disposed between the fifth metal fill layer and the dielectric layer such that fifth sidewalls of the fifth metal fill layer are not in physical contact with the dielectric layer, and the third metal barrier layer is disposed between the second and fifth metal fill layers. In some embodiments, the first and second vias have a first thickness, the first metal fill layer has a second thickness less than the first thickness, and the second metal fill layer has a third thickness less than the first thickness, and the third thickness is different than the second thickness.In some embodiments, the first source-drain contact includes a first contact volume layer disposed over a first contact blocking layer and the second source-drain contact includes a second contact volume layer disposed over a second contact blocking layer. A first portion of the first sidewalls of the first metal fill layer is in physical contact with the dielectric layer and a second portion of the first sidewalls of the first metal fill layer is in physical contact with the first contact barrier layer such that the first contact barrier layer is disposed between the second portion of the first sidewalls of the first metal fill layer and the dielectric layer. A third portion of the second sidewalls of the second metal fill layer is in physical contact with the dielectric layer and a fourth portion of the second sidewalls of the second metal fill layer is in physical contact with the second contact barrier layer such that the second contact barrier layer is disposed between the fourth portion of the second sidewalls of the second metal fill layer and the dielectric layer.An example method includes forming first and second source-drain contacts in a dielectric layer. The first source-drain contact is in physical contact with a first source-drain element and the second source-drain contact is in physical contact with a second source-drain element. The method further includes forming first and second via openings in the dielectric layer. The first via opening exposes the first source-drain contact and the second via opening exposes the second source-drain contact. The method further includes recessing the first source-drain contact to enlarge the first via opening and the second source-drain contact to enlarge the second via opening, and performing a bottom-up deposition process to form a first via volume layer in the first via opening and a second via volume layer in the second via opening. A first thickness of the first via volume layer is different than a second thickness of the second via volume layer. The method further includes forming a first via barrier layer over the first and second via bulk layers, forming a third via bulk layer over the first via barrier layer, and performing a planarization process to remove third via bulk layer, first via barrier layer, second via bulk layer, and first via bulk layer disposed over an upper surface of the dielectric layer, thereby forming a first via having a third thickness and a first via layer configuration and a second via having the third thickness and a second via layer configuration different from the first via layer configuration. The method further includes forming a third via opening in the dielectric layer exposing a gate structure, a second via blocking layer partially filling the third via opening, and a fourth via bulk layer over the second via blocking layer. The fourth via volume layer fills the remainder of the third via opening. The method further includes performing a planarization process to remove fourth via bulk layer and second via barrier layer disposed over the top surface of the dielectric layer, thereby forming a third via having a third via layer configuration different from the first and second via layer configurations. In some embodiments, forming the first and second via openings in the dielectric layer includes performing a dry etching process, and recessing the first and second source-drain contacts includes performing a wet etching process. In some embodiments, the first and second source-drain contacts each include a contact volume layer disposed over a contact barrier layer, and recessing the first and second source-drain contacts includes etching the contact volume layer without substantially etching the contact barrier layer. In some embodiments, forming the third via volume layer and forming the fourth via volume layer each includes performing a blanket deposition process.Another example method includes forming a source-drain contact to a source-drain element in a first dielectric layer, forming a first via to the source-drain contact, and forming a second via to a gate structure. Forming the first via includes forming a second dielectric layer over the first dielectric layer and forming a first via opening in the second dielectric layer. The first via opening exposes the source-drain contact. Forming the first via further includes recessing the source-drain contact to enlarge the first via opening, performing a bottom-up deposition process to fill the enlarged first via opening with a first metal layer, forming a second metal layer over the first metal layer and the second dielectric layer, forming a third metal layer over the second metal layer, and performing a planarization process to remove first, second, and third metal layers disposed over an upper surface of the second dielectric layer. Forming the second via includes forming a second via opening in the second and first dielectric layers. The second via opening exposes the gate structure. Forming the second via opening further includes forming a fourth metal layer to partially fill the second via opening and forming a fifth metal layer over the fourth metal layer to fill a remainder of the second via opening. In some embodiments, forming the first metal layer includes forming a first tungsten-containing layer and forming the third metal layer includes forming a second tungsten-containing layer. In some embodiments, forming the second metal layer includes forming a titanium-containing layer.In some embodiments, the enlarged first via opening has a first cross-sectional profile in a first direction and a second cross-sectional profile in a second direction. The first direction is different from the second. In such embodiments, a bottom of the enlarged first via opening is defined by a substantially planar surface in the first cross-sectional profile and a substantially curved surface in the second cross-sectional profile. In some embodiments, forming the second metal layer includes depositing a first adhesive layer and depositing a second adhesive layer over the first adhesive layer. In such embodiments, the first adhesive layer may include titanium and the second adhesive layer may include titanium and nitrogen. In some embodiments, the first metal layer completely fills the first via opening, such that the first via includes the first metal layer. In some embodiments, forming the first metal layer includes filling a bottom portion of the first via opening with the first metal layer such that after forming the first metal layer, a top portion of the first via opening remains. In such embodiments, forming the second metal layer includes partially filling the top portion of the first via with the second metal layer and forming the third metal layer includes filling the remainder of the top portion of the first via with the third metal layer.In some embodiments, forming the first via opening includes performing a dry etching process, and recessing the source-drain contact includes performing a wet etching process. In some embodiments, the source-drain contact includes a metal fill layer disposed over a metal adhesive layer, and recessing the source-drain contact includes etching the metal fill layer without substantially etching the metal adhesive layer. In some embodiments, the gate structure has a first dimension in a first direction and a second dimension in a second direction substantially perpendicular to the first direction. In such embodiments, when recessing the source-drain contact to increase the first via opening, the first via opening under the second dielectric layer is increased in the second direction without increasing the first via opening under the second dielectric layer in the first direction. In some embodiments, the first dimension is a gate length and the second dimension is a gate width.In some embodiments, the source-drain contact is a first source-drain contact and the source-drain element is a first source-drain element. In such embodiments, the method may further include forming a second source-drain contact to a second source-drain element in the first dielectric layer. The gate structure is arranged between the first and the second source-drain elements. In such embodiments, the method may further include, in forming the first via to the first source-drain contact, forming a third via in the second dielectric layer to the second source-drain contact. Forming the third via includes forming a third via opening in the second dielectric layer. The third via opening exposes the second source-drain contact. Forming the third via further includes recessing the second source-drain contact to enlarge the third via opening, performing the bottom-up deposition process to fill the enlarged third via opening with the first metal layer, forming the second metal layer over the first metal layer and the second dielectric layer, forming the third metal layer over the second metal layer, and performing the planarization process to remove first, second, and third metal layers disposed over the top surface of the second dielectric layer. In some embodiments, the first metal layer partially fills the first via opening and completely fills the third via opening and extends over the second dielectric layer, thereby forming a first portion of the first metal layer disposed in the first via opening and a second portion of the first metal layer disposed in the third via opening. In some embodiments, the second metal layer partially fills the first via opening and is disposed over the first portion of the first metal layer disposed in the first via opening and over the second portion of the first metal layer disposed in the third via opening. In some embodiments, the third metal layer partially fills a remainder of the first via opening and is disposed over the second metal layer.Another example device includes a gate structure disposed over a substrate. The gate structure is arranged between a first and a second source-drain element. The device further includes first and second source-drain contacts disposed in a dielectric layer. The first source-drain contact is in physical contact with the first source-drain element and the second source-drain contact is in physical contact with the second source-drain element. The device further includes first, second, and third vias disposed in the dielectric layer. The first via is in physical contact with the first source-drain contact, the second via is in physical contact with the second source-drain contact, and the third via is in physical contact with the gate structure. The first and second vias each include a first metal fill layer in physical contact with the dielectric layer. The third via includes a second metal fill layer and a metal adhesive layer. The metal adhesive layer is disposed between the second metal fill layer and the dielectric layer. In some embodiments, the metal adhesive layer is a first metal adhesive layer, the first via includes a first portion where the first metal fill layer is in physical contact with the dielectric layer, and the first via includes a second portion where a second metal adhesive layer is disposed between the first metal fill layer and the dielectric layer. In some embodiments, the first and second source-drain contacts each include a third metal adhesive layer disposed between a third metal fill layer and the dielectric layer. In such embodiments, the first via further includes a third portion in which the third metal fill layer is disposed between the first metal fill layer and the dielectric layer, and the second via includes a portion in which the third metal adhesive layer is disposed between the first metal fill layer and the dielectric layer. In some embodiments, the first and second vias have a first cross-sectional profile in a first direction and a second cross-sectional profile in a second direction. The first direction is different from the second. In such embodiments, a first bottom of the first via and a second bottom of the second via are defined by a substantially planar surface in the first cross-sectional profile and a substantially curved surface in the second cross-sectional profile.

Claims

An apparatus comprising: a first source-drain contact (282A) disposed in a dielectric layer (254), the first source-drain contact (282A) being in physical contact with a first source-drain element; a second source-drain contact (282B) disposed in the dielectric layer (254), the second source-drain contact (282B) being in physical contact with a second source-drain element; a first via (350A) having a first via layer configuration disposed in the dielectric layer (254), wherein the first via (350A) extends into and is in physical contact with the first source-drain contact (282A), and a second via (350B) having a second via layer configuration disposed in the dielectric layer (254), the second via (350B) extending into and being in physical contact with the second source-drain contact (282B), the second via layer configuration being different from the first via layer configuration and a first thickness of the first via (350A) corresponding to a second thickness of the second via (350B), wherein: the first via (350A) and the second via (350B) each have a first footprint profile with the first and second source-drain contacts (282B), respectively, in a first direction and a second footprint profile with the first and second source-drain contacts (282B), respectively, in a second direction, and the first direction is different from the second direction, the first footprint profile is defined by a substantially planar surface, and the second footprint profile is defined by a substantially curved surface.The device of claim 1, wherein: the first via (350A) has a first upper portion disposed over a first lower portion, the dielectric layer (254) being in physical contact with sidewalls of the first upper portion and the first source-drain contact (282A) being in physical contact with sidewalls of the first lower portion, and the second via (350B) has a second upper portion disposed over a second lower portion, the dielectric layer (254) being in physical contact with sidewalls of the second upper portion and the second source-drain contact (282B) being in physical contact with sidewalls of the second lower portion, wherein: the dielectric layer (254) has a first inter-level dielectric layer, a second inter-level dielectric layer disposed over the first inter-level dielectric layer and an etch stop layer (264) disposed between the first and second inter-level dielectric layers, the first and second source-drain contacts (282B) are disposed in and pass through the first inter-level dielectric layer, and the first and second vias (350B) are disposed in and pass through the second inter-level dielectric layer and the etch stop layer (264), wherein a first portion of the first via (350A) extending into the first source-drain contact (282A) and a second portion of the second via (350B) extending into the second source-drain contact (282B) extend, in physical contact with a bottom surface of the contact etch stop layer (264).The device of claim 1 or 2, wherein the first via (350A) and the second via (350B) each have a first cross-sectional profile in a first direction and a second cross-sectional profile in a second direction, wherein the first direction is different from the second direction and the first cross-sectional profile is different from the second cross-sectional profile.The device of any preceding claim, wherein: the first via (350A) having the first via layer configuration comprises: a first via volume layer (330'), a second via volume layer (340') disposed over the first via volume layer (330'), and a via barrier layer (335, 370) disposed between the first and second via volume layers (340'), wherein the first via volume layer (330') is in physical contact with the dielectric layer (254), and the first via barrier layer is further disposed between the second via volume layer (340') and the dielectric layer (254), and the second via (350B) having the second via layer configuration comprises: a third via volume layer, which is in physical contact with the dielectric layer (254), wherein the first and third via volume layers comprise a same material, the third via volume layer has the second thickness, and the first via volume layer (330') has a third thickness that is less than the first thickness.The device of claim 4, wherein: the first source-drain contact (282A) comprises a first contact blocking layer and a first contact volume layer, wherein a first portion of the first contact blocking layer is disposed between the first contact volume layer and the dielectric layer (254), and a second portion of the first contact blocking layer is disposed between the first via volume layer (330') and the dielectric layer (254), and the second source-drain contact (282B) comprises a second contact blocking layer and a second contact volume layer, wherein a first portion of the second contact blocking layer is disposed between the second contact volume layer and the dielectric layer (254), and a second portion of the second contact blocking layer is disposed between the third via volume layer and the dielectric layer (254).The device of any of claims 1 to 3, wherein: the first via (350A) having the first via layer configuration comprises: a first via volume layer (330'), a second via volume layer (340') disposed over the first via volume layer (330'), and a first via barrier layer disposed between the first and second via volume layers (340'), wherein the first via volume layer (330') is in physical contact with the dielectric layer (254), and the first via barrier layer is further disposed between the second via volume layer (340') and the dielectric layer (254), the second via (350B) having the second via layer configuration comprises: a third via volume layer, a fourth via volume layer disposed over the third via volume layer and a second via barrier layer disposed between the third and fourth via volume layers, wherein the third via volume layer is in physical contact with the dielectric layer (254), and the second via barrier layer is further disposed between the fourth via volume layer and the dielectric layer (254), wherein the first and third via volume layers include a first material, the second and fourth via volume layers include a second material, and the first and second via barrier layers include a third material; and wherein a first distance between the first via barrier layer and a substrate (210) is different than a second distance between the second via barrier layer and the substrate (210).The device of claim 6, wherein: the first source-drain contact (282A) comprises a first contact blocking layer and a first contact volume layer, wherein a first portion of the first contact blocking layer is disposed between the first contact volume layer and the dielectric layer (254), and a second portion of the first contact blocking layer is disposed between the first via volume layer (330') and the dielectric layer (254), and the second source-drain contact (282B) comprises a second contact blocking layer and a second contact volume layer, wherein a first portion of the second contact blocking layer is disposed between the second contact volume layer and the dielectric layer (254), and a second portion of the second contact blocking layer is disposed between the third via volume layer and the dielectric layer (254).An apparatus comprising: a gate structure (230A-C, 232B) disposed over a substrate (210), the gate structure (230A-C, 232B) disposed between first and second source-drain elements; first and second source-drain contacts (282B) disposed in a dielectric layer (254), the first source-drain contact (282A) being in physical contact with the first source-drain element and the second source-drain contact (282B) being in physical contact with the second source-drain element; and first, second, and third vias disposed in the dielectric layer (254), wherein: the first via (350A) is in physical contact with the first source-drain contact (282A), the second via (350B) is in physical contact with the second source-drain contact (282B), and the third via is in physical contact with the gate structure (230A-C, 232B), the first via (350A) comprises a first metal fill layer having first sidewalls that are in physical contact with the dielectric layer (254), the second via (350B) comprises a second metal fill layer having second sidewalls that are in physical contact with the dielectric layer (254), and the third via comprises a third metal fill layer disposed over a metal barrier layer, wherein the metal barrier layer is disposed between the third metal fill layer and the dielectric layer (254) such that third sidewalls of the third metal fill layer are not in physical contact with the dielectric layer (254).The apparatus of claim 8, wherein: the metal barrier layer is a first metal barrier layer; and the first via (350A) has a first portion comprising the first metal fill layer and a second portion disposed over the first portion, the second portion comprising a fourth metal fill layer disposed over a second metal barrier layer, the second metal barrier layer is disposed between the fourth metal fill layer and the dielectric layer (254) such that fourth sidewalls of the fourth metal fill layer are not in physical contact with the dielectric layer (254), and the second metal barrier layer is disposed between the first and fourth metal fill layers.The device of claim 8 or 9, wherein the first and second vias (350B) have a first thickness, the first metal fill layer has a second thickness less than the first thickness, and the second metal fill layer has a third thickness corresponding to the first thickness.The apparatus of claim 8 or 9, wherein: the second via (350B) has a third portion comprising the second metal fill layer and a fourth portion disposed over the third portion, the fourth portion comprising a fifth metal fill layer disposed over a third metal barrier layer, the third metal barrier layer disposed between the fifth metal fill layer and the dielectric layer (254) such that fifth sidewalls of the fifth metal fill layer are not in physical contact with the dielectric layer (254), and the third metal barrier layer is disposed between the second and fifth metal fill layers.The device of claim 11, wherein the first and second vias (350B) have a first thickness, the first metal fill layer has a second thickness less than the first thickness, the second metal fill layer has a third thickness less than the first thickness, and the third thickness is different than the second thickness.The apparatus of any of claims 8 to 12, wherein: the first and second vias (350B) have a first cross-sectional profile in a first direction and a second cross-sectional profile in a second direction, the first direction being different from the second direction, and a first bottom of the first via (350A) and a second bottom of the second via (350B) have a substantially planar surface in the first cross-sectional profile and a substantially curved surface in the second cross-sectional profile.The apparatus of any of claims 8 to 13, wherein: the first source-drain contact (282A) comprises a first contact volume layer disposed over a first contact blocking layer, and the second source-drain contact (282B) comprises a second contact volume layer disposed over a second contact blocking layer, a first portion of the first sidewalls of the first metal fill layer is in physical contact with the dielectric layer (254), and a second portion of the first sidewalls of the first metal fill layer is in physical contact with the first contact blocking layer, such that the first contact blocking layer is disposed between the second portion of the first sidewalls of the first metal fill layer and the dielectric layer (254), and a third portion of the second sidewalls of the second metal fill layer is in physical contact with the dielectric layer (254) and a fourth portion of the second sidewalls of the second metal fill layer is in physical contact with the second contact barrier layer such that the second contact barrier layer is disposed between the fourth portion of the second sidewalls of the second metal fill layer and the dielectric layer (254).A method comprising: forming first and second source-drain contacts (282B) in a dielectric layer (254), wherein the first source-drain contact (282A) is in physical contact with a first source-drain element and the second source-drain contact (282B) is in physical contact with a second source-drain element; forming first and second via openings in the dielectric layer (254), wherein the first via opening exposes the first source-drain contact (282A) and the second via opening exposes the second source-drain contact (282B), Recessing the first source-drain contact (282A) to enlarge the first via opening and recessing the second source-drain contact (282B) to enlarge the second via opening, performing a bottom-up deposition process to form a first via volume layer (330') in the first via opening and a second via volume layer (340') in the second via opening, wherein a first thickness of the first via volume layer (330') is different from a second thickness of the second via volume layer (340'), forming a first via barrier layer over the first and second via volume layers (340'), forming a third via volume layer over the first via barrier layer, Performing a planarization process to remove third via volume layer, first via barrier layer (335, 370), second via volume layer (340'), and first via volume layer (330') disposed over an upper surface of the dielectric layer (254), thereby forming a first via (350A) having a third thickness and a first via layer configuration and a second via (350B) having the third thickness and a second via layer configuration different from the first via layer configuration, forming a third via opening in the dielectric layer (254) exposing a gate structure (230A-C, 232B), forming a second via barrier layer partially filling the third via opening, forming a fourth via volume layer over the second via blocking layer, the fourth via volume layer filling a remainder of the third via opening, and performing a planarization process to remove fourth via volume layer and second via blocking layer (335, 370) disposed over the top surface of the dielectric layer (254), thereby forming a third via having a third via layer configuration different from the first and second via layer configurations.The method of claim 15, wherein: forming the first and second via openings in the dielectric layer (254) comprises performing a dry etching process; and recessing the first and second source-drain contacts (282B) comprises performing a wet etching process.The method of claim 15 or 16, wherein: the first and second source-drain contacts (282B) each comprise a contact volume layer (286) disposed over a contact barrier layer (284), and recessing the first and second source-drain contacts (282B) comprises etching the contact volume layer (286) without substantially etching the contact barrier layer (284).The method of any of claims 15 to 17, wherein forming the third via volume layer and forming the fourth via volume layer each comprises performing a blanket deposition process.

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