SEMICONDUCTOR DEVICE AND METHOD

Abstract

A device comprising: a first fin (52) and a second fin (52) extending from a substrate (50), the first fin (52) having a first recess (77) and the second fin (52) having a second recess (77), an isolation region (56) surrounding the first fin (52) and the second fin (52), a gate stack above the first fin (52) and the second fin (52), and a source / drain region (82) in the first recess (77) and the second recess (77), the source / drain region (82) being adjacent to the gate stack, the source / drain region (82) having a bottom surface extending from the first fin (52) to the second fin (52), a first portion of the bottom surface that is below a first height above the isolation region (56) having a first inclination, and wherein a second portion of the lower surface located above the first height has a second inclination,which is greater than the first inclination, the second inclination being between 54.7° and 90°.,

Description

PRIORITY CLAIM AND CROSS-REFERENCE

[0001] This application claims priority over preliminary US application No. 62 / 928,197, which was filed on October 30, 2019, and which is incorporated herein in its entirety by cross-reference. STATE OF THE ART

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers onto a semiconductor substrate, and by lithography to structure the various material layers and form circuit components and elements.

[0003] The semiconductor industry is constantly improving the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, thus enabling more components to be integrated into a given area. However, reducing the smallest feature sizes brings additional problems to light that must be addressed. List of characters

[0004] Aspects of this disclosure are best understood from the detailed description below, when read together with the accompanying figures. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 shows an example of a FinFET device in a three-dimensional view according to some embodiments. Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8A, Fig. 8B, Fig. 9A, Fig. 9B, Fig. 10A, Fig. 10B and Fig. Figure 10C shows cross-sectional views of intermediate stages in the manufacture of a FinFET device according to some embodiments. Fig. 11, Fig. 12, Fig. 13A and Fig. Figure 13B shows cross-sectional views of intermediate stages in the fabrication of an epitaxial source / drain region of a FinFET device according to some embodiments. Fig. 14A and Fig. Figure 14B shows a diagram of inclination angle relative to sidewall position for an epitaxial source / drain region of a FinFET device and a diagram of profiles of an epitaxial source / drain region of a FinFET device according to some embodiments. Fig. Figure 15 shows a diagram of union heights versus fin pitch for an epitaxial source / drain region of a FinFET device according to some embodiments. Fig. Figure 16 shows a cross-sectional view of an intermediate stage in the fabrication of an epitaxial source / drain region of a FinFET device according to some embodiments. Fig. 17A, Fig. 17B, Fig. 18A, Fig. 18B, Fig. 19A, Fig. 19B, Fig. 20A, Fig. 20B, Fig. 20C, Fig. 21A, Fig. 21B, Fig. 22A and Fig. Figure 22B shows cross-sectional views of intermediate stages in the manufacture of a FinFET device according to some embodiments. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments, or examples, for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, forming a first feature over or on top of a second feature in the description below may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features can be formed between the first and second features, so that the first and second features may not be in direct contact. Furthermore, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition is done for the sake of simplicity and clarity and does not in itself prescribe any relationship between the various designs and / or configurations discussed.

[0006] Furthermore, terms relating to spatial relativity, such as "below," "under," "lower," "above," "upper," and the like, may be used herein for the convenience of discussion to describe the relationship of one element or feature to another element or feature (or other elements or features), as illustrated in the figures. The terms relating to spatial relativity are intended to encompass various orientations of the apparatus used or operated in addition to the orientation illustrated in the figures. The apparatus may be oriented in a different way (rotated by 90 degrees or otherwise), and the terms relating to spatial relativity used herein may likewise be interpreted accordingly.

[0007] Various embodiments provide processes for forming source / drain regions with reduced volume and cross-sectional area. These regions can be formed by epitaxially growing a first epitaxial layer in a recess formed in a semiconductor fin, performing a back-etching process, and subsequently epitaxially growing a second epitaxial layer over the first. Using the techniques described here, adjacent source / drain regions can be formed that merge at a greater distance above the substrate, thus reducing the cross-sectional area of ​​the merged region.Semiconductor devices manufactured according to embodiments of the present application and having source / drain regions may exhibit reduced gate-drain capacitance (Cgd), reduced RC delay, faster turn-on / turn-off, and improved device speed.

[0008] Fig. Figure 1 shows an example of a FinFET in a three-dimensional view according to some embodiments. The FinFET has a fin. 52 on a substrate 50 (e.g., a semiconductor substrate). Isolation areas 56 are in the substrate 50 arranged, and the fin 52 It is above neighboring isolation areas 56 and from the space between them. Although the isolation zones 56 are described / represented in such a way that they are independent of the substrate 50While the components are separate, the term "substrate" can be used, as here, to refer exclusively to the semiconductor substrate or a semiconductor substrate including its isolation regions. Although the fin 52 as a single continuous material such as the substrate 50 As shown, the fin can also be used. 52 and / or the substrate 50 a single material or multiple materials. In this context, the fin refers to 52 on the section that lies between the adjacent isolation areas 56 extends.

[0009] A gate dielectric layer 92 It is located along the side walls and above an upper surface of the fin. 52 , and a gate electrode 94 is located above the gate dielectric layer 92 Source / drainage areas 82 are on opposite sides of the fin 52 with regard to the gate dielectric layer92 and the gate electrode 94 arranged. Fig. Figure 1 further shows reference cross-sections that are used in later figures. Cross-section AA runs along a longitudinal axis of the gate electrode. 94 and, for example, in a direction perpendicular to the direction of current flow between the source / drain areas 82 of the FinFET. The cross-section BB is perpendicular to the cross-section AA and runs along a longitudinal axis of the fin. 52 and, for example, in one direction of current flow between the source / drain areas 82 of the FinFET. Cross-section CC is parallel to cross-section AA and extends through a source / drain region of the FinFET. For clarity, subsequent figures refer to these reference cross-sections.

[0010] Some embodiments discussed here are in the context of FinFETs designed using a gate-last process. In other embodiments, a gate-first process can be used. Furthermore, some embodiments consider aspects used in planar devices, such as planar FETs.

[0011] Fig. 2 to Fig. 13B and Fig. 16 to Fig. Figure 22B shows cross-sectional views of intermediate stages in the fabrication of FinFETs according to some embodiments. Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8A, Fig. 9A, Fig. 10A, Fig. 17A, Fig. 18A, Fig. 19A, Fig. 20A, Fig. 21A and Fig. 22A are along the in Fig. 1 shown reference cross-section AA, and Fig. 8B, Fig. 9B, Fig. 10B, Fig. 17B, Fig. 18B, Fig. 19B, Fig. 20B, Fig. 20C, Fig. 21B and Fig. 22B are along the in Fig. 1 similar cross-section BB shown. Fig. 10C, Fig. 11, Fig. 12, Fig. 13A, Fig. 13B and Fig. 16 are along the in Fig. 1 shown reference cross-section CC.

[0012] In Fig. 2. A substrate will be used. 50 provided. The substrate 50 The substrate can be a semiconductor substrate, such as a bulk semiconductor, an SOI substrate (semiconductor on an insulator), or the like, which can be doped (e.g., with a p- or n-type dopant) or undoped. 50The substrate can be a wafer, such as a silicon wafer. Generally, a SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide layer (BOX layer), a silicon oxide layer, or the like. The insulating layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multilayer or gradient substrate, can also be used. In some embodiments, the semiconductor material of the substrate can be... 50comprising: silicon; germanium; a compound semiconductor comprising silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor comprising silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide, or combinations thereof.

[0013] The substrate 50 an area 50N and an area 50P up. The area 50N It can be used to form n-devices, such as NMOS transistors, e.g., n-FinFETs. The area 50P It can be used to form p-type devices, such as PMOS transistors, e.g., p-FinFETs. The area 50N can from the area 50P be physically separated (as by a separation) 51(shown), and any number of device features (e.g., other active devices, doped areas, isolation structures, etc.) can be placed between the area 50N and the area 50P be ordered.

[0014] In Fig. 3 will be Finns 52 in the substrate 50 trained. The Finns 52 are semiconductor bridges. In some embodiments, the fins can 52 in the substrate 50 by etching trenches in the substrate 50 The etching can be any suitable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), the like, or a combination thereof. The etching can be anisotropic. In some embodiments, the fins can be 52 They are designed to have a width WF of between approximately 5 nm and approximately 30 nm. In some embodiments, the fins can 52are designed to have a pitch PF of approximately 10 nm to approximately 40 nm.

[0015] The Finns 52 can be structured using any suitable method. For example, the Finns 52The fins are structured using one or more photolithographic processes, including dual or multiple structuring processes. Generally, dual or multiple structuring processes combine photolithographic and self-aligning processes, enabling the creation of structures with, for example, smaller pitches than would otherwise be achievable using a single direct photolithographic process. For example, in one embodiment, a sacrificial layer is formed over a substrate and structured using a photolithographic process. Spacers are formed along the structured sacrificial layer using a self-aligning process. The sacrificial layer is then removed, and the remaining spacers can be used to structure the fins. In some embodiments, the mask (or another layer) can be applied to the fins.52 remain.

[0016] In Fig. 4. An insulating material will be used. 54 above the substrate 50 and between neighboring Finns 52 trained. The insulation material 54 The insulating material can be an oxide, such as silicon dioxide, a nitride, the like, or a combination thereof, and can be formed by chemical vapor deposition using high-density plasma (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system followed by curing to transform it into another material, such as an oxide), the like, or a combination thereof. Other insulating materials formed by any suitable process can be used. In the illustrated embodiment, the insulating material is... 54Silicon oxide formed using an FCVD process. An annealing process can be carried out after the insulating material has formed. In one embodiment, the insulating material 54 designed in such a way that excess insulation material 54 the Finns 52 covers. Although the insulation material 54 While depicted as a single layer, some embodiments can use multiple layers. For example, in some embodiments, a liner (not shown) can first be applied along a surface of the substrate. 50 and the Finns 52 The liner can be formed. Afterwards, a filler material, such as those discussed above, can be applied over the liner.

[0017] In Fig. 5. A removal process will be applied to the insulation material. 54 applied to remove excess insulation material 54 about the Finn 52to remove. In some embodiments, a planarization process, such as chemical-mechanical polishing (CMP), a re-etching process, combinations thereof, or the like, may be used. The planarization process lays the fins flat. 52 free, so that the upper surfaces of the fins 52 and the insulation material 54 are at the same level after the planarization process is complete. In embodiments where a mask is placed on the fins 52 If the remaining material is removed, the planarization process can expose or remove the mask, so that the upper surfaces of the mask or the fins are visible. 52 and the insulation material 54 are at the same level after the leveling process has been completed.

[0018] In Fig. 6. The insulation material will be 54 omitted to avoid STI areas (Shallow Trench Isolation) 56to train. The insulation material 54 is left out in such a way that the upper sections of the fins 52 in the area 50N and in the area 50P from the area between adjacent STI areas 56 They protrude. Furthermore, the upper surfaces of the STI areas can 56 They may have a flat surface, as shown, a convex surface, a concave surface (such as a curve), or a combination thereof. The upper surfaces of the STI areas 56 STI areas can be formed flat, convex and / or concave using a suitable etching process. 56 can be achieved using a suitable etching process, such as one that is resistant to the insulating material. 54 is selective (e.g., the material of the insulation material). 54 etches at a faster rate than the material used by the Finns 52), can be omitted. For example, an oxide remover that uses, for example, diluted hydrofluoric acid (dHF) can be used.

[0019] The one in relation to Fig. 2 to Fig. The process described in point 6 is merely one example of how the Finns 52 fins can be formed. In some embodiments, the fins can be formed using an epitaxial growth process. For example, a dielectric layer can be grown over a top surface of the substrate. 50 can be formed, and trenches can be etched through the dielectric layer to expose the underlying substrate. 50to expose. Homoepitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the homoepitaxial structures protrude from the dielectric layer to form fins. Furthermore, in some embodiments, heteroepitaxial structures can be used for the fins. 52 can be used. For example, the Finns can 52 in Fig. 5 will be left out, and one from the Finns 52 Various materials can be epitaxially inserted over the recessed fin. 52 are grown up. In such embodiments, the Finns exhibit 52 The recessed material and the epitaxially grown material arranged above the recessed material are shown. In a further embodiment, a dielectric layer can be formed over an upper surface of the substrate. 50They can be formed, and trenches can be etched through the dielectric layer. Heteroepitaxial structures can then be created in the trenches using a substrate-specific material. 50 Different materials can be grown epitaxially, and the dielectric layer can be recessed in such a way that the heteroepitaxial structures protrude from the dielectric layer to form the fins. 52 to develop. In some embodiments where homoepitaxy or heteroepitaxy structures are grown epitaxially, the epitaxially grown materials can be doped in situ during growth, which can avoid prior and subsequent implantations, although in situ and implantation doping can be used together.

[0020] Furthermore, it can be advantageous to have a material in the area 50N (e.g., in an NMOS area) to grow epitaxially, which is derived from the material in the area 50P(e.g., a PMOS region) differs. In various embodiments, upper sections of the fins can be 52 made from silicon germanium (Si x Ge 1-x , where x can be in the range of 0 to 1), silicon carbide, pure or essentially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. For example, the available materials for forming a III-V compound semiconductor include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, and the like.

[0021] Furthermore, in Fig. 6 suitable tubs (not shown) in the Finns 52 and / or the substrate 50 be formed. In some embodiments, a P-tub can be formed in the area 50Nbe trained, and an N-tub can be used in the area 50P are formed. In some embodiments, a P-tub or an N-tub is used in both areas. 50N as well as in the area 50P trained.

[0022] In the embodiments with different tub types, the various implantation steps for the area can be performed. 50N and the area 50P This can be achieved using a photoresist or other masks (not shown). For example, a photoresist can be applied over the fin. 52 and the STI areas 56 in the area 50N to be trained. The photoresist is structured to protect the area. 50P of the substrate 50, such as a PMOS region, to expose the photoresist. The photoresist can be formed using a rotary coating technique and can be structured using suitable photolithographic techniques. After the photoresist has been structured, an n-contamination is implanted in the region. 50P carried out, and the photoresist can act as a mask to essentially prevent n-contaminants from entering the area 50N , such as an NMOS region, are implanted. The n-impurities can be phosphorus, arsenic, antimony, or the like, introduced into the region to a concentration less than or equal to 10 18 cm -3 is, for example, between approximately 10 16 cm -3 and approximately 10 18 cm -3 , are implanted. After implantation, the photoresist is removed, e.g. using a suitable ashing process.

[0023] After implantation in the area 50PA photoresist coating is applied over the fins. 52 and the STI areas 56 in the area 50P trained. The photoresist is structured to protect the area. 50N of the substrate 50 , such as the NMOS region, to expose the photoresist. The photoresist can be formed using a rotary coating technique and can be structured using suitable photolithographic techniques. After the photoresist has been structured, a α-contamination can be implanted in the region. 50N the process can be carried out, and the photoresist can act as a mask to essentially prevent p-contamination from entering the area. 50P , such as the PMOS region. The p-impurities can be boron, boron fluoride, indium, or the like, which are introduced into the region to a concentration less than or equal to 10 18 cm -3 is, for example, between approximately 10 16 cm -3 and approximately 10 18 cm-3 , are implanted. After implantation, the photoresist can be removed, e.g. using a suitable ashing process.

[0024] After the implantations of the area 50N and the area 50P Tempering can be performed to repair implantation damage and activate the implanted p- and / or n-impurities. In some embodiments, the grown materials can be doped in situ by epitaxial fins during growth, which can avoid implantation altogether, although in situ and implantation doping can be used together.

[0025] In Fig. 7 becomes a dielectric dummy layer 60 on the Finns 52 trained. The dummy dielectric layer 60It can be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and can be deposited or thermally grown using suitable techniques. A dummy gate layer 62 is applied above the dummy dielectric layer 60 trained and a mask layer 64 is above the dummy gate layer 62 trained. The dummy gate layer 62 can be above the dummy dielectric layer 60 separated and then planarized, for example using a CMP. The mask layer 64 can be above the dummy gate layer 62 be separated. The dummy gate layer 62 It can be a conductive or non-conductive material and can be selected from a group that includes amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, and metals. The dummy gate layer62 It can be deposited using physical vapor deposition (PVD), CVD, sputtering, or other techniques known in the prior art and used to deposit the selected material. The dummy gate layer 62 It can be made from other materials that exhibit high etch selectivity for etching isolation areas. The mask layer 64 It can, for example, contain silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer is used. 62 and a single layer of masks 64 over the area 50N and the area 50P trained. It should be noted that the dummy dielectric layer 60 shown for illustrative purposes only, in such a way that they merely represent the Finns 52 covers. In some embodiments, the dummy dielectric layer can 60are deposited in such a way that the dummy dielectric layer 60 the STI areas 56 covers itself by positioning itself between the dummy gate layer 62 and the STI areas 56 extends.

[0026] Fig. 8A to Fig. 13B and Fig. 16 to Fig. Figure 22B shows various additional steps in the manufacture of devices of the embodiments. These figures show features either in the area 50N or the area 50P For example, the structures depicted in these figures can refer to the area 50N as well as the area 50P applicable. Differences (if any) in the structures of the area. 50N and the area 50P are described in the text that accompanies each character.

[0027] In Fig. 8A and Fig. 8B can be the mask layer 64 (see Fig. 7) be structured using suitable photolithographic and etching techniques to create masks 74 to train. The structure of the masks 74 can then access the dummy gate layer 62 can be transferred. In some embodiments (not shown), the structure of the masks can be 74 also on the dummy dielectric layer 60 They can be transferred using a suitable etching technique to create dummy gates. 72 to train. The dummy gates 72 cover respective canal areas 58 the Finns 52 off. The structure of the masks 74 can be used to test each of the dummy gates 72 to physically separate them from adjacent dummy gates. The dummy gates 72 may also have a longitudinal direction that corresponds to the longitudinal direction of the respective epitaxial fins. 52 is essentially perpendicular.

[0028] Furthermore, in Fig. 8A and Fig. 8B Gate sealing spacer 80 on exposed areas of the dummy gates 72 , the masks 74 and / or the Finns 52 They can be formed. Thermal oxidation or deposition followed by anisotropic etching can be used to form the gate sealing spacers. 80 train. The gate sealing spacers 80 can be formed from silicon oxide, silicon nitride, silicon oxynitride or the like.

[0029] After forming the gate sealing spacers 80 Implantations can be performed for poorly doped source / drain regions (LDDs) (not explicitly shown). In embodiments with different device types, similar to the above, Fig. For the 6 discussed implantations, a mask, such as a photoresist, is placed over the area. 50N be trained while the area 50Pis exposed, and impurities of a suitable type (e.g. p-type) can enter the exposed fins. 52 in the area 50P The mask can then be implanted. Afterwards, a mask, such as photoresist, can be applied over the area. 50P be trained while the area 50N is exposed, and contaminants of a suitable type (e.g. n-type) can enter the exposed fins. 52 in the area 50N to be implanted. The mask can then be removed. The n-impurities can be any of the n-impurities discussed above, and the p-impurities can be any of the p-impurities discussed above. The lightly doped source / drain regions can have an impurity concentration of approximately 10 15 cm -3 up to about 10 19 cm -3exhibit. Tempering can be used to repair implant damage and to activate the implanted impurities.

[0030] In Fig. 9A and Fig. 9B will be gatespacers 86 on the gate sealing spacers 80 along the side walls of the dummy gates 72 and the masks 74 trained. The Gatespacers 86 They can be formed by conformal deposition of an insulating material and subsequent anisotropic etching of the insulating material. The insulating material of the gatespacer 86 It can be silicon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride, a combination thereof, or the like. The gatespacer 86 , the gate sealing spacers 80 , the dummy gates 72 and the masks 74 These can be collectively referred to as "dummy gate structures".

[0031] It should be noted that the preceding disclosure generally describes a process for forming spacers and LDD regions. Other processes and sequences can be used. For example, fewer or additional spacers can be used, and other sequences of steps can be employed (e.g., the gate sealing spacers are...). 80 possibly before training the gatespacers 86 (not etched, resulting in "L-shaped" gate sealing spacers), spacers can be formed and removed, and / or the like. Furthermore, n- and p-devices can be formed using various structures and steps. For example, LDD areas for n-devices can be created prior to forming the gate sealing spacers. 80 are formed, while the LDD areas for p-devices are formed after the gate sealing spacers have been formed. 80 can be trained.

[0032] Fig. 10A to Fig. Figure 13B shows different steps in the formation of epitaxial source / drain regions. 82 in the Finns 52 according to some embodiments. Fig. 10C, Fig. 11, Fig. 12 and Fig. 13A-B are along the in Fig. The reference cross-section CC shown in section 1 is depicted. For clarity, some dimensions or proportions of the features shown in Fig. 10C to Fig. The epitaxial source / drain regions shown in Figure 13B may differ from those depicted in other figures. 82 in the area 50N e.g. the NMOS area, can be masked by masking the area 50P , e.g. of the PMOS area, and etching in the area 50N , to create recesses 77 in the Finns 52 to train, to be trained. Then the epitaxial source / drain regions are 82 in the area 50N in the recesses 77Epitaxially grown. The epitaxial source / drainage areas 82 in the area 50P , e.g. the PMOS area, can be masked by masking the area 50N , e.g., the NMOS area, and etching in the area 50P , to create recesses 77 in the Finns 52 to train, to be trained. Then the epitaxial source / drain regions are 82 in the area 50P in the recesses 77 Epitaxially grown. The epitaxial source / drainage areas 82 can be formed using multiple deposition and etching processes, which are described in more detail below.

[0033] Fig. 10A, Fig. 10B and Fig. 10C shows the etching of the source / drain regions of the fins. 52 , to the recesses 77 to train. The recesses 77Gatespacers can be formed by etching using any suitable etching process, such as a dry etching process (e.g., RIE, NBE, or the like) or a wet etching process (e.g., tetramethylammonium hydroxide (TMAH), ammonia water (NH4OH), or the like), or a combination thereof. The etching processes can be anisotropic. In some embodiments, the gatespacer material remains. 86 and / or the gate sealing spacer 80 in the STI areas 56 between the neighboring Finns 52 (not shown in the figures). In some embodiments, the recesses extend 77 into the Finns 52 below an upper surface of the STI areas 56 In other embodiments, a section of the fins is 52 from the STI areas 56 after forming the recesses 77 The STI areas stand out. 56 between neighboring Finns 52They can be flat, as shown, or they can have a convex or a concave surface. Fig. 10C to Fig. 13B is the location of the canal areas 58 the Finns 52 under the dummy gate structure (e.g. the canal areas) 58 , which are not etched to create the recesses 77 (to train) shown as a reference.

[0034] With reference to Fig. 11. A first deposition process is carried out to establish an epitaxial area. 81 in the recesses 77 to be designed according to some embodiments. The epitaxial area 81The material can be epitaxially grown using a suitable process, such as CVD, metal-organic CVD (MOCVD), molecular beam epitaxy (MBE), liquid-phase epitaxy (LPE), gas-phase epitaxy (VPE), selective epitaxial growth (SEG), or a combination thereof. For example, the initial deposition process may involve a process carried out at a pressure between approximately 5 Torr and approximately 300 Torr, or at a temperature between approximately 500 °C and approximately 800 °C. In some embodiments, the initial deposition process may involve gases and / or precursors such as SiH4, DCS, Si2H6, GeH4, PH3, AsH3, B2H6, HCl, or combinations thereof. The gases and / or precursors may be fed into a process chamber at a rate between approximately 10 sccm and approximately 2000 sccm.The initial deposition process can be carried out for a duration of approximately 50 seconds to approximately 3000 seconds. Other deposition processes or process parameters can be used.

[0035] The epitaxial area 81 It can be made of any suitable material, such as that suitable for n-FinFETs or p-FinFETs. For example, if the fin 52 Silicon is, the epitaxial area 81 in the area 50N materials exhibit tensile stress in the canal area 58 exert, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, or the like. If the fin 52 Silicon is, the epitaxial area 81 in the area 50P materials exhibiting compressive stress in the canal area 58exert, such as silicon germanium, boron-doped silicon germanium, germanium, germanium-tin, or the like. The epitaxial region 81 can have areas that are defined by the respective areas of the fins 52 are raised, and can have facets.

[0036] As in Fig. As shown in 11, this can be seen in the neighboring Finns. 52 Combine trained epitaxial material to form a continuous epitaxial area 81 to form air gaps 79 can be formed between the material formed on adjacent fins and beneath them. In some embodiments, where the epitaxial area 81 When united, the air gaps can 79 a “union height” HM1 above the STI areas 56exhibiting dimensions between approximately 5 nm and approximately 50 nm. During the initial deposition process, surfaces of the epitaxial material can exhibit facets of different crystal orientations. For example, surfaces near the top of the channel regions may 58 and areas near the lower side of the canal area 58Other surfaces may have {111} facets. Other surfaces may have other facets, such as {110} facets, or they may have a combination of facets, such as a combination of {111} and {110} facets, or other facets. In some embodiments, a higher flow rate of HCl during the deposition process may cause surfaces with {100} facets, surfaces with {100} facets, and / or surfaces with {111} facets to have more similar growth rates. Therefore, increasing the flow rate of HCl during the deposition process may promote the growth of surfaces that have a combination of {100} facets, {110} facets, and / or {111} facets.

[0037] In some cases, the epitaxial area grows during the first deposition process. 81 to the side of each fin 52, whereby the limits of growth are essentially determined by the formation of the {111} facets. In other words, the shape of the epitaxial region is 81 essentially determined by the {111} facets, and the maximum size (e.g. volume or cross-sectional area) of the epitaxial area 81 is essentially determined by the {111} facets. As an illustrative example, the {111} facets, which define the growth boundaries of the epitaxial area, are 81 essentially determine, in Fig. 11 is indicated by the dashed outline marked “{111}”. Due to the growth of facets, the shape and size of the epitaxial area 81 essentially confined within this dashed outline. Therefore, the growth of the epitaxial area can 81 be "facet-limited".

[0038] During the first deposition process, the epitaxial material can initially deposit on lower {111} facets near the lower side of the canal regions. 58 and upper {111} facets near the top of the canal regions 58 form. As the first deposition process progresses, the epitaxial material grows along these upper and lower {111} facets, with the lateral growth rate being strongly limited outside the intersection of the upper and lower {111} facets. In this way, the maximum lateral growth of the epitaxial material can be approximately defined by the upper and lower {111} facets. Fig. 11 is a point where the {111} facets define the boundary of the lateral growth of the epitaxial area. 81 The point is approximately defined and displayed as "LP". The LP point can be located at a height HL above the STI areas. 56exhibiting wavelengths between approximately 20 nm and approximately 50 nm, depending on the depth of the recesses. 77 or the height of the exposed sections of the fins 52 may depend on it. In some cases, the growth rate of the epitaxial area may 81 are greatly reduced after the growth of the epitaxial area 81 has reached the LP point defined by the {111} facets. In some cases, the height HL can be approximately half the height of the recesses. 77 It may be approximately half the height HF of the epitaxial area. 82 amount (see Fig. 13B). The maximum lateral width of the epitaxial material can be approximately determined by the distance between opposing LP points, which in some embodiments may range from approximately 40 nm to approximately 100 nm. In cases where the adjacent fins 52are sufficiently close (e.g., have a sufficiently small pitch PF) so that the effect on the adjacent fins 51 If the epitaxial material {111} has overlapping facets, the epitaxial material can combine to form a continuous epitaxial area. 81 The undersides of the epitaxial material, which are {111} facets, unite at a height HMo above the STI regions that is approximately defined by the intersection of the {111} facets and may depend on the pitch PF. In some embodiments, the height HMo can range from approximately 10 nm to approximately 60 nm.

[0039] In some embodiments, the first deposition process is stopped before the lateral growth of the epitaxial area begins. 81 The point LP has been reached. In this way, the epitaxial area can be 81with regions that exhibit surfaces with different crystal orientations. For example, as in Fig. 11 shown, lower areas 83A near the underside of the canal areas 58 and upper regions 83B near the upper reaches of the canal areas 58 have surfaces that have {111} facets. This is also true in Fig. 11 shown by the lower areas 83A and the upper areas 83B Areas along the dashed outline “{111}” that indicate the growth-limiting {111} facets. Areas between the lower regions 83A and the upper areas 83B , such as the areas of medium-sized regions 83C , which in Fig. The facets shown in Figure 11 may have other facets, such as {110} facets, or may have a combination of facets, such as a combination of {111} and {110} facets, or other facets. The epitaxial material on each fin 52 can be separate or can form a continuous epitaxial area 81 be united, as in Fig. 11. Furthermore, by such a halt to the first deposition process, the epitaxial area can be 81It can be designed to have a smaller cross-sectional area, which can reduce the parasitic capacitance (e.g., Cgd) of the FinFET device, as described in more detail below. In some embodiments, the first deposition process is stopped before facets growing along the undersides of the epitaxial material merge (e.g., at height HMo). In these embodiments, the epitaxial material can merge at a height HM1 that is greater than the height HMo.

[0040] In Fig. 12 According to some embodiments, a back-etching process is carried out on the epitaxial area. 81The etching process can, for example, be an anisotropic dry etching process. The etching process can involve multiple gases and / or precursors, such as HCl, GeH4, SiH4, the like, or combinations thereof. The process gases can flow into a process chamber at a rate between approximately 20 sccm and approximately 3000 sccm. The etching process can have a process temperature in the range of approximately 600 °C to approximately 800 °C and a process pressure in the range of approximately 3 Torr to approximately 300 Torr. The etching process can be carried out for a duration between approximately 1 second and approximately 300 seconds, such as approximately 50 seconds.

[0041] In some embodiments, the characteristics of the etching process are controlled such that surfaces exhibiting {110} facets are etched at a higher rate than surfaces exhibiting {111} facets. The etching process may, for example, involve gases and / or precursors such as HCl, Cl₂, H₂, N₂, the like, or combinations thereof. The etching process may have a process pressure between 5 Torr and approximately 300 Torr or a process temperature between approximately 600 °C and approximately 800 °C. In some embodiments, the ratio of the etching rate of {111} facets to the etching rate of {110} facets can be controlled by controlling the process temperature of the etching process. In some cases, {111} facets and {110} facets may have different activation energies for the etch reactions of the back-etch process, and controlling the process temperature may increase or decrease the etch rate ratio due to the differences in activation energies.In some embodiments, the back-etching process etches {110} facets at a rate that is at least approximately 4 times greater than that of {111} facets. Therefore, the back-etching process can etch the central regions. 83C The lower areas are more corroded than by the back-etching process. 83A or the upper areas 83B It etches, and therefore it can etch mostly in lateral directions. In this way, the central areas can be affected. 83C exhibit a flatter profile (e.g., less rounded or more vertical profile) after the re-etching process. In some cases, the lower areas show 83A and the upper areas 83B essentially {111}faceted surfaces on and the central areas 83C exhibit surfaces that have {111} and {110} facets after the re-etching process. In some cases, the lower regions 83A less etched than the upper areas 83B , as in Fig. 12 shown.

[0042] In some embodiments, the epitaxial material is applied to the fins. 52 The epitaxial material is separated again by the etching process. In other embodiments, the epitaxial material remains as an epitaxial region after the etching process. 81 united, as in Fig. 12 shown. In some embodiments, the union height HM1 of the air gaps may be affected by the etching process. 79 Increase. For example, after the etching process, the air gaps can increase. 79 a union height HM2 above the STI areas 56 exhibiting a range between approximately 10 nm and approximately 60 nm, which may be higher than the height HM1 of the air gaps 79 before the etching process. In this way, the etching process can cover the entire cross-sectional area of ​​the epitaxial region. 81 decrease, which is an increase in the union height of the united epitaxial material of the epitaxial area. 81This can include [various areas]. In some cases, the presence of epitaxial material with a small or incompletely united area can allow gaseous etchants to more easily reach the underside (e.g., adjacent to air gaps). 79 ) of the epitaxial area 81 to reach, and increased etching of the underside of the epitaxial area 81 This enables. Furthermore, the use of an anisotropic back-etching process, as described above, can result in increased etching of the underside of the epitaxial area. 81 This is possible because the non-prestressed gaseous etchants are able to more easily reach the underside of the epitaxial area. 81 to get there.

[0043] In Fig. 13A and Fig. 13B, according to some embodiments, a second deposition process is carried out to deposit epitaxial material on the epitaxial area. 81 to separate in order to create an epitaxial area82 to train. Fig. 13A and Fig. Figure 13B shows the same cross-sectional view with features that are labelled separately on each figure for clarity. The epitaxial material of the epitaxial area 82 can be epitaxially grown using a suitable process such as CVD, MOCVD, MBE, LPE, VPE, SEG, or a combination thereof. The epitaxial area 81The epitaxially deposited material may consist of materials similar to those deposited during the first deposition process, as described above. For example, the second deposition process may involve a process carried out at a pressure between approximately 5 Torr and approximately 300 Torr, or at a process temperature between approximately 500 °C and approximately 800 °C. In some embodiments, the second deposition process may involve gases and / or precursors such as SiH4, DCS, Si2H6, GeH4, PH3, AsH3, B2H6, HCl, the like, or combinations thereof. The gases and / or precursors may be fed into a process chamber at a rate between approximately 10 sccm and approximately 2000 sccm. The second deposition process may be carried out for a duration between approximately 50 seconds and approximately 3000 seconds. Other deposition processes or process parameters may be used.The epitaxial material deposited by the second deposition process can be similar to that deposited by the first deposition process, or it can be different, for example, having a different semiconductor composition or doping. The epitaxial regions... 82 can have areas that are defined by the respective areas of the fins 52 are raised and may have facets.

[0044] As in Fig. As shown in 13A-B, the epitaxial material is located over the epitaxial area. 81 and between the Finns 52 isolated, so that the epitaxial area 82 a continuous area. In some cases, the growth rate of the epitaxial material between the fins can vary. 52be greater than the growth rate of epitaxial material on other surfaces, especially when the epitaxial material is aggregated. The epitaxial area 82 It can have a substantially flat upper surface, or the upper surface can be concave, convex, or wavy. In some embodiments, the epitaxial material deposited by the second deposition process can exhibit facets of different crystal orientations. For example, lower regions can 85A of the epitaxial area 82 having surfaces that essentially have {111} facets. In some embodiments, the lower regions may be 85A extend to a height HSA that is between approximately 5 nm and approximately 60 nm. In some embodiments, the upper regions can 85B of the epitaxial area 82having surfaces that essentially have {111} facets. In some embodiments, the upper regions may be 85 extend at a HSB height between approximately 0 nm and approximately 30 nm. In some cases, the presence of an epitaxial region may be observed. 81 with a small or not fully united area, it makes it easier for precursors to be attached to the underside (e.g., adjacent to the air gaps). 79 ) of the epitaxial area 81 and can therefore allow epitaxial material to reach the underside of the epitaxial area. 81 is deposited. In some cases, epitaxial material may be found near the lower surface of the lower regions. 85A be separated.

[0045] In some embodiments, the central areas 85C of the epitaxial area 82 , which are located between the lower areas 85Aand the upper areas 85B The areas are located on surfaces that have {110} facets. The central areas 85C They can also have a combination of {110} facets and {111} facets, or other facets. The surfaces of the lower regions 85A deviation of {111} facets at the boundary between the lower regions 85A and the central areas 85C from, which may be located, for example, at or near elevation HSA. An example of a boundary point between the lower areas 85A and the central areas 85C is in Fig. 13A is shown as the "inflection point" STP. In some embodiments, the central regions can 85C exhibit a sidewall slope that is greater than the sidewall slope of the lower areas 85A and / or the slope of the upper walls 85B The position of STP (e.g., the height of HSA) on the epitaxial field 82can be controlled by controlling the parameters of the first deposition process, the etching process, and / or the second deposition process. In some embodiments, the length of the {111} facets in lower regions can be controlled. 85A The result depends on the amount of {111}-faceted material deposited by the first deposition process and / or the amount of {111}-faceted material deposited by the second deposition process. For example, performing the first deposition process and / or the second deposition process for longer durations may result in more {111}-faceted material in the lower regions. 85A to grow and therefore increase the height HSA of STP. As another example, performing the etching process for a longer duration can remove more material from the lower regions. 83A (see Fig. 12) etching, and therefore the height of HSA can decrease from STP.

[0046] In some cases, after the epitaxial area has formed 82 essentially combined the growth rate of the epitaxial material on the underside of the epitaxial area. 82 can be greatly reduced. In this way, the position of STP can be determined by unifying the epitaxial area. 82 can be determined approximately. In some cases, if the growth rate of {111} facets is slower than the growth rate of {110} facets, the limit of the epitaxial material 81The growth of STP is largely determined by surfaces with {111} facets. In this situation, a relatively slower growth rate of {111} facets can result in the position of STP being closer to the union point MP (described in more detail below), and therefore the HSA being relatively high. In some cases, a growth rate of {111} facets that is closer to that of {110} facets can result in the position of STP being farther from the union point MP, and therefore the HSA being relatively low. In this way, the position of STP and the height of HSA can be controlled by adjusting the relative growth rates (e.g., the ratio of the growth rates) of {111} and {110} facets. These are examples, and the position of STP or the height of HSA can be controlled by adjusting other parameters or other combinations of parameters.

[0047] The techniques described here can cover the entire cross-sectional area of ​​the epitaxial region. 82 reduce. By reducing the total cross-sectional area of ​​the epitaxial regions. 82 The gate-drain capacitance (Cdg) of a FinFET device can be reduced, which can improve the device's performance. For example, the RC delay of the FinFET device can be reduced, and its response speed can be improved. In some embodiments, the cross-sectional area of ​​the epitaxial region can be reduced. 82 to between approximately 5% and approximately 60% of the maximum facet-limited cross-sectional area shown by the dashed outline labeled “{111}”. In some embodiments, the maximum facet-limited cross-sectional area can be reduced to between approximately 1000 nm. 2 and approximately 6000 nm 2amount to, and the cross-sectional area of ​​the epitaxial region 82 can range between approximately 500 nm 2 and approximately 5000 nm 2 other cross-sectional areas of the epitaxial region 82 are possible.

[0048] In some embodiments, the cross-sectional area of ​​the epitaxial regions can be controlled by controlling the first deposition process, the etching process, and the second deposition process. 82 can be reduced by increasing the lateral width of the epitaxial area. 82 is reduced. For example, the lateral width of the epitaxial area can be reduced. 82 The lateral width of the epitaxial area can be reduced to between approximately 5% and approximately 70% of the maximum facet-limited lateral width (e.g., between opposing LP points). In some embodiments, the lateral width of the epitaxial area can be further reduced. 82The lateral widths range from approximately 40 nm to approximately 80 nm, although other widths can be achieved. Furthermore, the cross-sectional area of ​​the epitaxial regions can vary. 82 can be reduced by increasing the height of the air gaps 79 is increased. For example, after the second deposition process, the air gaps can be reduced. 79 a union height HMP above the STI areas 56 exhibiting a height between approximately 15 nm and approximately 60 nm. Increasing the height of the HMP increases the cross-sectional area of ​​the epitaxial region. 82 reduced, and the capacity Cdg can be reduced accordingly. In some cases, the height of the air gap may change. 79 vertically closer to an upper surface of the epitaxial areas 82 are located as the STI areas 56 In some embodiments, the second deposition process deposits epitaxial material on sections of the underside of the epitaxial area. 81from, so that the height HMP is less than the height HM2 (see Fig. 12) In other embodiments, the second deposition process does not deposit epitaxial material on sections of the underside of the epitaxial area. 81 from, so that the height HMP is approximately the same as the height HM2 (see Fig. 12). In some embodiments, the height HMP can be greater than the height HM1 (see Fig. 11) In some embodiments, the union height HMP can be greater than the facet-limited union height HMo. For example, the height HMP can be between approximately 3 nm and approximately 15 nm greater than the height HMo. In some embodiments, the height HMP can be greater than the height HL, although in other embodiments the height HMP can be approximately equal to or less than the height HL. Other dimensions, heights, or relative heights are possible.

[0049] With reference to Fig. 13B are reference points on the side wall of the air gap. 79 Marked. Point Po indicates a lower point of the epitaxial area. 82 Point STP indicates the "inflection point" as described above, and point MP indicates the "union point" on the top of the air gap. 79 Furthermore, point Mo indicates the "union point" of the facet-limited cross-sectional area (shown by the dashed outline labeled "{111}"). As in Fig. As shown in Figure 13B, Mo and MP are positioned laterally approximately in the middle between the adjacent fins. 52 arranged. In some embodiments, a first vertical distance from an upper surface of the epitaxial areas is 82 MP less than half a second vertical distance from the upper surface of the epitaxial areas 82 to the STI areas 56 .

[0050] Due to the different facet formation between the lower areas 85A and the central areas 85C The lateral wall inclination of the epitaxial area changes. 82 at or near the "inflection point" (STP). As an illustrative example, Fig. 14A a diagram of inclination angle vs. sidewall section for points Po, STP, MP and Mo, which are in Fig. Figure 13B shows the side wall of the epitaxial region. 82 from Po to STP in a lower area 85A exhibits an inclination angle Ao of approximately 54.7°, which corresponds to the crystal plane of a {111} facet. From STP to MP in a central region. 85C The side wall has an angle of inclination. A1The angle can be between approximately 54.7° and approximately 90°, such as approximately 78°. The sidewall from STP to MP can have more than one angle of inclination or can have a varying angle of inclination, and the transition between angles of inclination near STP can be abrupt or gradual. Fig. Figure 14B shows a diagram of profiles of epitaxial areas. 82 , which corresponds to a section of the cross-sectional view from Po to union at ½PF, as in Fig. Figure 13 shows the profile of the epitaxial area. 82 From Po to STP, the crystal plane corresponds to a {111} facet. If the profile between Po and ½PF also existed along the {111} plane, it would follow the line from STP to Mo and have a corresponding inclination angle of approximately 54.7°. However, due to the change in inclination near STP, the profile exhibits a greater inclination between STP and the union point MP. Fig. Figure 14B shows an abrupt change in profile slope at STP, but the profile change can be gradual or curved. Four possible union points MP1, MP2, MP3, and MP4 are shown as illustrative examples in Figure 14B. Fig. Figure 14B shows each of which has an increasingly greater profile slope from STP. The techniques described here allow the profile slope between STP and the union point (e.g., MP1, MP2, MP3, or MP4) to be greater than a slope corresponding to a {111} facet, and can therefore form a higher union point. For example, the profile slope from STP to MP3 is greater than the profile slope from STP to MP1, and therefore the union point MP3 is higher than the union point MP1, and both are higher than the union point Mo. In this way, the shape and slopes of an epitaxial region can be controlled to increase the union height of that epitaxial region. As in Fig. 13B and Fig. As shown in 14A-B, the central areas 85C a greater angle of inclination than the lower areas 85A , and therefore MP is higher than Mo.

[0051] By controlling the parameters of the first deposition process, the second deposition process, and the etching process to adjust the tilt angle A1 To control the sidewall position of the tilt inflection point STP, the height HMP of the union point MP can be controlled. For example, as described above, the first deposition process and / or the second deposition process can be controlled to reduce the formation of facets in the upper and lower regions, and the back-etching process can be controlled to adjust the tilt angle. A1to increase by etching {110} facets at a higher rate than {111} facets. Other examples are possible. Furthermore, as described above, controlling the temperature during the deposition of the epitaxial material can control the relative growth rates of {111} and {110} facets, which affects the position of STP, the position of MP, or the ratio of facets that determine the inclination angle. A1 The position of MP can be determined and controlled. The position of MP can also be determined by controlling the position of STP and controlling the tilt angle. A1 or by choosing a specific fin pitch PE. As an illustrative example, it shows Fig. 15 the range of possible union heights HMP of an epitaxial area 82 For a given fin pitch, PE. For facet-limited growth, the union height HMP is applied to the heights within zone. 151The epitaxial area is limited to the height of union HMP equal to the height HMo, and the maximum union height HMP is the height HL. Using the techniques described here, the formation of the epitaxial area can be achieved. 82 be controlled in such a way that there is any union height HMP within the zone 153 exhibits heights within the zone 151 This includes, as shown, the techniques described here allow for greater design flexibility for the epitaxial regions. 82 , including a reduction in cross-sectional area.

[0052] In some embodiments, an epitaxial area can 82 are formed from a united epitaxial material that is divided into more than two fins 52 is grown up. An example of a multi-fin design is in Fig. 16 shown, although an epitaxial area 82 about more or less Finns62 It can be trained as shown. The techniques described here can be used to increase the cross-sectional area of ​​the epitaxial region. 82 in this and other embodiments with multiple fins to reduce. It should be noted that other techniques for controlling a tilt inflection point (STP) and / or increasing the union height (HMP) to reduce the cross-sectional area of ​​an epitaxial region are available. 82 to reduce, can be used which include, but are not limited to, carrying out additional deposition or etching processes.

[0053] In some embodiments, the spacer pattern used to form the gatespacer can 86 is used, adapted to remove the spacer material to allow the epitaxially grown material to extend to the area of ​​the STI region. 56 extends, as in Fig. 13A-B is shown. In other embodiments, the gatespacers 86 designed in such a way that they form a section of the side walls of the fins 52 cover the areas above the STI areas 56 extends, thereby blocking epitaxial growth in those sections. Into the epitaxial source / drain regions 82 and / or the Finns 52 Dopants can be implanted to form source / drain regions, similar to the previously discussed process for forming lightly doped source / drain regions followed by annealing. The source / drain regions can contain impurities with a concentration of approximately 10 19 cm -3 and approximately 10 21 cm -3 exhibit. The n- and p-impurities for source / drain regions can be any of the impurities discussed above. In some embodiments, the epitaxial source / drain regions can 82doped in situ during growth.

[0054] In Fig. 17A and Fig. 17B will be a first dielectric intermediate layer (ILD) 88 isolated above the structure. The first ILD 88 It can be formed from a dielectric material and can be deposited using any suitable process, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Dielectric materials can be phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials formed using any suitable process can be used. In some embodiments, a contact etch stop layer (CESL) is used. 87 between the first ILD 8 and the epitaxial source / drain areas 82 , the masks 74 and the gate spacers86 arranged. The CESL 87 may contain a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, which has a different etch rate than the material of the overlying first ILD. 88 In some embodiments, the air gap remains. 79 empty (e.g., free of the first ILD) 88 or the CESL 87 In other embodiments, the first ILD can 88 or the CESL 87 within the air gap 79 be separated.

[0055] In Fig. 18A and Fig. 18B A planarization process, such as a CMP, can be performed to flatten the upper surface of the first ILD. 88 with the upper surfaces of the dummy gates 72 or the masks 74 to level the ground. The leveling process can also remove the masks. 74 on the dummy gates 72 and sections of the gate sealing spacers 80and the gatespacer 86 along the side walls of the masks 74 remove. After the planarization process, the upper surfaces of the dummy gates are located 72 , the gate sealing spacer 80 , the gatespacer 86 and the first ILD 88 on the same level. Accordingly, the upper surfaces of the dummy gates 72 through the first ILD 88 exposed. In some embodiments, the masks can 74 remain, whereby in this case the planarization process affects the upper surface of the first ILD 88 with the upper surfaces of the upper surface of the masks 74 paves the way.

[0056] In Fig. 19A and Fig. 19B will be the dummy gates 72 and the masks 74 , if present, removed in one etching step(s), so that recesses 90 to be formed. Sections of the dummy dielectric layer 60 in the recesses 90They can also be removed. In some embodiments, only the dummy gates are removed. 72 removed and the dummy dielectric layer 60 remains and is formed by the recesses 90 exposed. In some embodiments, the dummy dielectric layer is 60 from the recesses 90 in a first region of a die (e.g., a core logic region), and remains in the recesses. 90 in a second area of ​​the die (e.g., an input / output area). In some embodiments, the dummy gates 72 removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process that uses a reactive gas that removes the dummy gates. 72 selectively etches (etches), without affecting the ILD 88 or the gatespacers 86 to etch. Each recess 90 A canal area is laid out for each fin. 52free and / or lies above this. Every canal area 58 is between adjacent pairs of epitaxial source / drain regions 82 arranged. During removal, the dummy dielectric layer can be removed. 60 can be used as an etch stop layer when the dummy gates 72 to be etched. The dummy dielectric layer 60 This can then optionally be done after removing the dummy gates. 72 be removed.

[0057] In Fig. 20A and Fig. 20B gate dielectric layers 92 and gate electrodes 94 trained to be a replacement gate operator. Fig. Figure 20C shows a detailed view of the area. 89 from Fig. 20B. The gate dielectric layers 92 fit snugly into the recesses 90 , such as on the upper surfaces and side walls of the fins 52and deposited on the side walls of the gate sealing spacers 80 / 86. The gate dielectric layers 92 can also occur on the upper surface of the first ILD 88 are formed. According to some embodiments, the gate dielectric layers have 92 silicon oxide, silicon nitride, or multiple layers thereof. In some embodiments, the gate dielectric layers have 92 a high-k dielectric material on and in these embodiments the gate dielectric layers can 92 They exhibit a k-value greater than approximately 7.0 and can be a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The methods for forming the gate dielectric layers 92These may include molecular beam deposition (MBD), ALD, PECVD, and the like. In embodiments where sections of the dummy dielectric layer 60 in the recesses 90 The remaining gate dielectric layers exhibit 92 a material of the dummy dielectric layer 60 (e.g. SiO2).

[0058] The gate electrodes 94 are each located above the gate dielectric layers 92 isolated and they fill the remaining sections of the recesses. 90 The gate electrodes 94 They can contain a metal-based material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. Although a single-layer gate electrode 94 in Fig. As shown in 20B, the gate electrode 94 for example, any number of liner layers 94A, any number of exit work hiring shifts 94B and a filling material 94C exhibit, as demonstrated by Fig. 20C is shown. After filling the recesses. 90 A planarization process, such as CMP, can be performed to remove the excess sections of the gate dielectric layers. 92 and the material of the gate electrodes 94 to remove the excess sections above the upper surface of the ILD. 88 The remaining sections of material from the gate electrodes are located there. 94 and the gate dielectric layers 92 They therefore form replacement gates for the resulting FinFETs. The gate electrodes 94 and the gate dielectric layers 92 These can be collectively referred to as a "gate stack". The gate and the gate stacks can extend along the side walls of a canal area. 58 the Finns 52 extend.

[0059] The formation of the gate dielectric layers 92 in the area 50N and the area 50P can occur simultaneously, so that the gate dielectric layers 92 in each area are formed from the same materials, and the formation of the gate electrodes 94 can occur simultaneously, so that the gate electrodes 94 Each area is formed from the same materials. In some embodiments, the gate dielectric layers can be 92 in each area they are formed using various processes, so that the gate dielectric layers 92 They can be made of different materials, and / or the gate electrodes 94 Different processes can be used to form gate electrodes in each area. 94They can be made of different materials. Different masking steps can be used to mask and expose suitable areas when different processes are used.

[0060] In Fig. 21A and Fig. 21B will be a second ILD 108 above the first ILD 88 isolated. In some embodiments, the second ILD is 108 a flowable film formed using a flowable CVD process. In some embodiments, the second ILD 108 It is formed from a dielectric material, such as PSG, BSG, BPSG, USG, or the like, and can be deposited using any suitable method, such as CVD and PECVD. According to some embodiments, before forming the second ILD... 108 the gate stack (which is a gate dielectric layer) 92 and a corresponding gate electrode above it 94(has) recessed, so that a recess is directly above the gate stack and between opposing sections of the gate spacer 86 is trained, as in Fig. 21A and Fig. 21B is shown. A gate mask 96 A component, which has one or more layers of a dielectric material, such as silicon nitride, silicon oxynitride, or the like, is filled into the cavity, followed by a planarization process to remove excess sections of the dielectric material that extend beyond the first ILD. 88 extend. The gate contacts subsequently formed 110 (see Fig. 22A-B) penetrate the gate mask 96 , to the upper surface of the recessed gate electrode 94 to contact.

[0061] In Fig. 22A and Fig. According to some embodiments, 22B gate contacts are used. 110 and source / drain contacts 112 through the second ILD108 and the first ILD 88 trained. Openings for the source / drain contacts. 112 are through the first and second ILD 88 and 108 trained, and openings for the gate contacts 110 are through the second ILD 108 and the gate mask 96 The openings can be formed using suitable photolithographic and etching techniques. A liner, such as a diffusion barrier, bonding layer, or the like, and a conductive material are formed within the openings. The liner can be titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material can be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as CMP, can be performed to remove excess material from an area of ​​the first ILD. 108to remove. The remaining liner and the conductive material form the source / drain contacts. 112 and the gate contacts 110 in the openings. A tempering process can be carried out to apply a silicide to the interface between the epitaxial source / drain areas. 82 and the source / drain contacts 108 to train. The source / drain contacts 112 are associated with the epitaxial source / drain areas 82 physically and electrically coupled, and the gate contacts 110 are connected to the gate electrodes 106 physically and electrically coupled. The source / drain contacts 112 and the gate contacts 110 They can be formed in different processes or they can be formed in the same process. Although depicted as being formed in the same cross-sections, it is understood that each of the source / drain contacts 112 and the gate contacts 110It can be designed in different cross-sections, which can prevent short-circuiting of the contacts.

[0062] The described embodiments can provide advantages. For example, the techniques described here can allow adjacent epitaxial source / drain regions of a FinFET device to merge further away from the substrate, which can reduce the overall cross-sectional area of ​​the merged epitaxial source / drain region. Furthermore, a merged epitaxial source / drain region can be formed with fewer facets, reducing the cross-sectional area compared to a merged source / drain region with larger facets or one that is facet-limited. Such a reduction in the area of ​​the merged epitaxial source / drain region can reduce the parasitic capacitance between the gate stack and the epitaxial source / drain region (e.g., Cgd), resulting in improved device speed (e.g.,This enables faster turn-on / turn-off speeds in a ring oscillator device or the like, reduced RC delay effects, or a reduction in other performance problems arising from parasitic capacitances. In some embodiments, the epitaxial source / drain regions are formed by first growing an initial epitaxial layer, then performing a back-etching process to increase the union height, and then growing a second epitaxial layer.

[0063] According to some embodiments of the present disclosure, a device comprises: a first fin and a second fin extending from a substrate, wherein the first fin has a first recess and the second fin has a second recess, an isolation region surrounding the first fin and the second fin, a gate stack above the first fin and the second fin, and a source / drain region in the first recess and the second recess, wherein the source / drain region is adjacent to the gate stack, wherein the source / drain region has a lower surface extending from the first fin to the second fin, wherein a first section of the lower surface, located below a first height above the isolation region, has a first slope, and wherein a second section of the lower surface, located above the first height, has a second slope greater than the first slope.In one embodiment, the first section of the lower surface has a {111} crystal plane. In one embodiment, the second inclination is between 54.7° and 90°. In one embodiment, a first vertical distance from an upper surface of the source / drain region to the lower surface is less than half of a second vertical distance from the upper surface of the source / drain region to the lower side of the first recess. In one embodiment, an upper surface of the source / drain region extends over the first fin, and the second fin is flat. In one embodiment, the second section of the lower surface has facets of at least two different crystal planes. In one embodiment, the source / drain region further has opposing side walls, wherein, below the first height, the side walls are facets of a {111} crystal plane.In one embodiment, upper sidewalls of the source / drain region, extending from a second height above the isolation region to an upper surface of the source / drain region, are facets of a {111} crystal plane, the second height being located above the first height. In another embodiment, between the first height and the second height, the sidewalls have surfaces exhibiting a third slope greater than the first slope.

[0064] According to some embodiments of the present disclosure, a structure comprises: a first fin above a semiconductor substrate, a second fin above the semiconductor substrate, the second fin being adjacent to the first fin, an isolation region surrounding the first fin and the second fin, a gate structure along side walls and over top surfaces of the first fin and the second fin, and a source / drain region on the first fin and the second fin adjacent to the gate structure, the source / drain region having a bottom surface between the first fin and the second fin, the bottom surface having a lower surface and an upper surface, the lower surface being a facet of a first crystal plane extending from the bottom surface of the bottom surface to a facet of a second crystal plane located a first height above the isolation region.wherein the upper surface extends from the first height to the uppermost section of the underside, the upper surface having facets of the first crystal plane and the second crystal plane. In one embodiment, the structure has an air gap between the first fin and the second fin, which is bounded by the underside. In one embodiment, the uppermost section of the underside is vertically closer to an upper surface of the source / drain region than to the isolation region. In one embodiment, the upper surface has a greater sidewall inclination than the lower surface. In one embodiment, the source / drain region has a sidewall surface opposite the first fin extending from the second fin, wherein a first section of the sidewall surface extending from a lower surface of the source / drain region is a facet of the first crystal plane. In one embodiment, a second section of the sidewall surface,extending from an upper surface of the source / drain region, a facet of the first crystal plane. In one embodiment, a third section of the sidewall surface between the first section and the second section has facets of the first crystal plane and facets of the second crystal plane.

[0065] According to some embodiments of the present disclosure, a method comprises: forming fins projecting from a semiconductor substrate, forming an isolation region surrounding the fins, forming a gate structure over the fins, and forming an epitaxial source / drain region adjacent to the gate structure extending over the fins, comprising: performing a first deposition process to deposit a first epitaxial material onto the fins, wherein lower surfaces of the first epitaxial material on adjacent fins unite at a first height above the isolation region, performing an etching process on the first epitaxial material, wherein the etching process etches lower surfaces of the first epitaxial material, and after performing the etching process, performing a second deposition process to deposit a second epitaxial material onto the first epitaxial material.wherein the epitaxial source / drain region comprises the first epitaxial material and the second epitaxial material, wherein, after the second deposition process, lower surfaces of the epitaxial source / drain region between adjacent fins extend a second height above the isolation region that is greater than the first height. In one embodiment, the etching process etches {110} surfaces at a higher rate than {111} surfaces. In another embodiment, after the second deposition process, surfaces of the epitaxial source / drain region extending from the isolation region to a third height are {111} facets, wherein the third height is lower than the first height. In another embodiment, the etching process reduces a lateral width of the first epitaxial material.

[0066] The foregoing outlines features of several embodiments so that a person skilled in the art can better understand the aspects of the present disclosure. A person skilled in the art should recognize that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to accomplish the same tasks and / or achieve the same advantages as the embodiments presented herein. A person skilled in the art should also understand that such equivalent embodiments do not deviate from the inventive concept and scope of the present disclosure, and that they can make various changes, substitutions, and modifications here without deviating from the inventive concept and scope of the present disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 62 / 928197

[0001]

Claims

[1] Device comprising: a first fin and a second fin extending from a substrate, the first fin having a first recess and the second fin having a second recess, an isolation area surrounding the first fin and surrounding the second fin, a gate stack above the first fin and the second fin, and a source / drain region in the first recess and the second recess, the source / drain region being adjacent to the gate stack, the source / drain region having a bottom surface extending from the first fin to the second fin, a first portion of the bottom surface being below a first height above the isolation region having a first slope, and a second portion of the bottom surface being above the first height, has a second slope that is greater than the first slope. [2] The device of claim 1, wherein the first portion of the lower surface comprises a {111} crystal plane. [3] Device according to claim 1 or 2, wherein the second inclination is between 54.7° and 90°. [4] The device of any preceding claim, wherein a first vertical distance from a top surface of the source / drain region to the bottom surface is less than half of a second vertical distance from the top surface of the source / drain region to the bottom side of the first recess. [5] A device according to any preceding claim, wherein an upper surface of the source / drain region extends above the first fin and the second fin is flat. [6] A device according to any preceding claim, wherein the second portion of the lower surface comprises a plurality of facets of at least two different crystal planes. [7] The device of any preceding claim, wherein the source / drain region further comprises opposing sidewalls, wherein below the first height the sidewalls are facets of a {111} crystal plane. [8] The device of claim 7, wherein upper sidewalls of the source / drain region extending from a second height above the isolation region to a top surface of the source / drain region are facets of a {111} crystal plane, the second height being above the first height. [9] The device of claim 8, wherein, between the first height and the second height, the side walls have surfaces having a third slope that is greater than the first slope. [10] Structure comprising: a first fin over a semiconductor substrate, a second fin above the semiconductor substrate, the second fin being adjacent to the first fin, an isolation area surrounding the first fin and the second fin, a gate structure along sidewalls and over upper surfaces of the first fin and the second fin, and a source / drain region on the first fin and the second fin adjacent to the gate structure, the source / drain region having a bottom surface between the first fin and the second fin, the bottom surface having a bottom surface and a top surface, the bottom surface being a facet of a first crystal plane extending from the bottom side of the bottom surface to a facet of a second crystal plane located a first height above the isolation region, the top surface extending from the first height to the topmost portion of the bottom surface, wherein the upper surface has facets of the first crystal plane and the second crystal plane. [11] The structure of claim 10, comprising an air gap between the first fin and the second fin defined by the bottom surface. [12] The structure of claim 10 or 11, wherein the uppermost portion of the bottom surface is vertically closer to a top surface of the source / drain region than to the isolation region. [13] A structure according to any one of the preceding claims 10 to 12, wherein the upper surface has a greater sidewall slope than the lower surface. [14] The structure of any one of the preceding claims 10 to 13, wherein the source / drain region has a sidewall surface opposite the first fin from the second fin, wherein a first portion of the sidewall surface extending from a bottom surface of the source / drain region is a facet of the first crystal plane. [15] The structure of claim 14, wherein a second portion of the sidewall surface extending from a top surface of the source / drain region is a facet of the first crystal plane. [16] The structure of claim 15, wherein a third portion of the sidewall surface between the first portion and the second portion comprises facets of the first crystal plane and facets of the second crystal plane. [17] Method comprising: Forming a plurality of fins protruding from a semiconductor substrate, Forming an isolation area surrounding the several Finns, Forming a gate structure over the plurality of fins, and Forming an epitaxial source / drain region adjacent to the gate structure and extending over the plurality of fins, comprising: Performing a first deposition process to deposit a first epitaxial material on the plurality of fins, wherein lower surfaces of the first epitaxial material on adjacent fins merge at a first height above the isolation region, Performing an etching process on the first epitaxial material, wherein the etching process etches lower surfaces of the first epitaxial material, and after performing the etching process, performing a second deposition process to deposit a second epitaxial material on the first epitaxial material, wherein the epitaxial source / drain region comprises the first epitaxial material and the second epitaxial material, wherein after performing the second deposition process, lower surfaces of the epitaxial source / drain region between adjacent fins extend a second height above the isolation region that is greater than the first height. [18] The method of claim 17, wherein the etching process etches {110} surfaces at a greater rate than {111} surfaces. [19] The method of claim 17 or 18, wherein, after performing the second deposition process, surfaces of the epitaxial source / drain region extending from the isolation region to a third height are {111} facets, wherein the third height is less than the first height. [20] The method of any one of the preceding claims 17 to 19, wherein the etching process reduces a lateral width of the first epitaxial material.

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