Semiconductor device and method for its manufacture

Abstract

Device comprising: a nanostructure (56); a gate structure (100) surrounding the nanostructure; an epitaxial source / drain region (92) adjacent to the gate structure; a first dielectric layer (96) over an upper section of the epitaxial source / drain region (92); a second dielectric layer (114) under a lower section of the epitaxial source / drain region; a busbar via (148) extending through the first dielectric layer (96) and the second dielectric layer (114), wherein the busbar via (148) is physically and electrically coupled to the upper and lower sections of the epitaxial source / drain region, and wherein the busbar via (148) extends along a side wall of the epitaxial source / drain region (92).

Description

BACKGROUND

[0001] Semiconductor devices are used in a wide variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by the sequential deposition of insulating or dielectric layers, conductive layers, and semiconductor layers of material over a semiconductor substrate, and by structuring the various material layers using lithography to create circuit components and elements.

[0002] The semiconductor industry continuously improves the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum component size, thus enabling more components to be integrated into a given area. However, decreasing minimum component sizes give rise to further problems that will be addressed.

[0003] Document US 2019 / 0288004A1 relates to a semiconductor device comprising a plurality of first source / drain (S / D) contacts and a plurality of first sources / drains, wherein each of the plurality of first S / D contacts is formed over a respective first source / drain and has a bar shape with a top section, a bottom section and side sections such that the bottom section covers the respective first source / drain.

[0004] Publication US 2019 / 0157310A1 concerns techniques for reducing back-side contact resistance for semiconductor devices with metallization on both sides by using deep vias and back-side contacts to connect front-end and back-end circuits.

[0005] Document US 2019 / 0164882A1 relates to a semiconductor device and a manufacturing process for integrating a backside power grid comprising conductive rails along fin structures and through-connections across the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 illustrates an example of simplified nanostructured field-effect transistors (nano-FETs) according to some embodiments. Fig. 2 to 14B are different views of intermediate stages in the fabrication of nano-FETs according to some embodiments. Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19, Fig. 20, Fig. 21 to Fig. Figure 22 shows different views of intermediate stages in the manufacture of semiconductor devices according to some embodiments. Fig. Items 23A to 31 are different views of intermediate stages in the manufacture of semiconductor devices according to some other embodiments. Fig. 32A to 40 are different views of intermediate stages in the manufacture of semiconductor devices according to some other embodiments. DETAILED DESCRIPTION

[0007] The subject matter of the invention is defined by the features specified in the independent claims. Other features shown in the description or figures are not part of the invention unless they fall within the scope of the claims. The dependent claims relate to corresponding embodiments. The following disclosure provides many different embodiments or examples of the implementation of various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not to be understood as limiting.For example, the formation of a first element or a second element in the following description may include embodiments in which the first and second elements are formed in direct contact, and it may also include embodiments in which further elements can be formed between the first and second elements, so that the first and second elements need not be in direct contact. Furthermore, this disclosure may repeat reference numbers and / or letters of the various examples. This repetition is for the sake of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations described.

[0008] Furthermore, spatially relative terms such as "below," "underneath," "lower," "above," "upper," and the like may be used herein for a simpler description of the relationship of one element or feature to one or more other elements or features, as illustrated in the figures. These spatially relative terms are intended to encompass various orientations of the device in use or operation, in addition to the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in another orientation), and the spatially relative terms used herein may be interpreted accordingly.

[0009] In various embodiments, a semiconductor device is formed comprising a device layer sandwiched between two interconnect structures. The device layer includes transistors, such as nanostructured field-effect transistors (nanoFETs). One interconnect structure is located on the front side of the device layer and includes conductive elements that connect the transistors to form functional circuits. The other interconnect structure is located on the back side of the device layer and includes conductive elements used to provide power circuitry for the device layer. Specifically, the backside interconnect structure includes its own power rails to provide a reference voltage, supply voltage, or the like to the functional circuitry.Conductive vias are formed by the device layer and connect the conductive elements of the backside interconnect structure to the conductive elements of the frontside interconnect structure. The formation of such conductive vias allows the interconnect structures to be connected by conductive elements instead of semiconductor elements, which can improve the performance of the resulting semiconductor devices.

[0010] Fig. Figure 1 illustrates an example of simplified nano-FETs according to some embodiments. Fig. Figure 1 is a three-dimensional sectional view in which some elements of the nano-FETs have been omitted for clarity of illustration. The nano-FETs can be nanosheet field-effect transistors (NSFETs), nanowire field-effect transistors (NWFETs), gate-all-around field-effect transistors (GAAFETs), or the like.

[0011] The nano-FETs comprise nanostructures 56 over a substrate 50, such as fins 54 extending from the substrate 50. The nanostructures 56 are a semiconductor layer that serves as channel regions for the nano-FETs. Insulating regions 60, such as shallow trench insulating regions (STI regions), are arranged over the substrate 50 and between adjacent fins 54, which may protrude over and between adjacent insulating regions 60. Although the insulating regions 60 are described / illustrated as separate from the substrate 50, the term "substrate" can refer to the substrate 50 alone or to a combination of the substrate 50 and the insulating regions 60. Furthermore, although the fins 54 are illustrated as individual, continuous materials forming the substrate 50, the fins 54 and / or the substrate 50 may comprise a single material or multiple materials.In this context, the Finns 54 refer to the section that extends over and between the adjacent isolated regions 60.

[0012] Gate structures 100 are wound around the nanostructures 56. The gate structures 100 comprise gate dielectrics 102 and gate electrodes 104. The gate dielectrics 102 are located along the upper surfaces, sidewalls, and lower surfaces of the nanostructures 56 and can extend along sidewalls and / or over the upper surfaces of the fins 54. The gate electrodes 104 are located over the gate dielectrics 102. The epitaxial source / drain regions 92 are arranged on opposite sides of the gate structures 100. In embodiments in which multiple transistors are formed, the epitaxial source / drain regions 92 can be shared between different transistors.For example, adjacent epitaxial source / drain regions 92 can be electrically coupled by epitaxial growth or by coupling of the epitaxial source / drain regions 92 with the same source / drain contact, such as by fusion of the epitaxial source / drain regions 92. One or more interlayer dielectric layer(s) (ILD layers) (explained in more detail below) are located over the epitaxial source / drain regions 92 and / or gate structures 100, through which contacts (explained in more detail below) to the epitaxial source / drain regions 92 and gate electrodes 104 are formed.

[0013] Some embodiments discussed herein are related to nanoFETs that employ a gate-last process. In other embodiments, a gate-first process may be used. Furthermore, some embodiments consider aspects used in planar devices, such as planar FETs or fin field-effect transistors (FinFETs).

[0014] Fig. Figure 1 further illustrates a cross-section used in subsequent figures. Cross-section AA runs along a longitudinal axis of a nanostructure 56 and in the direction of, for example, a current flow between the epitaxial source / drain regions 92 of a nano-FET. For clarity, subsequent figures refer to this reference cross-section.

[0015] Fig. 2 to 14B are different views of intermediate stages in the fabrication of nano-FETs according to some embodiments. Fig. 2, Fig. 3, Fig. 4, Fig. 5A, Fig. 6A, Fig. 7A, Fig. 8A, Fig. 9A, Fig. 10A, Fig. 11A, Fig. 12A, Fig. 13A and Fig. 14B are three-dimensional views that provide a similar three-dimensional view to Fig. Figure 1 shows a gate structure and two fins. Fig. 5B, Fig. 6B, Fig. 7B, Fig. 8B, Fig. 9B, Fig. 10B, Fig. 11B, Fig. 12B, Fig. 13B and Fig. 14B are cross-sectional views taken along reference cross-section AA in Fig. 1 are illustrated. Fig. 5A, Fig. 6A, Fig. 7A, Fig. 8A, Fig. 9A, Fig. 10A, Fig. 11A, Fig. 12A, Fig. 13A and Fig. 14B are simplified three-dimensional views and do not show all elements of the corresponding Fig. 5B, Fig. 6B, Fig. 7B, Fig. 8B, Fig. 9B, Fig. 10B, Fig. 11B, Fig. 12B, Fig. 13B and Fig. 14B.

[0016] In Fig. 2. A substrate 50 is provided for the fabrication of nanoFETs. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, an insulator substrate (SOI substrate), or the like, which may be doped (e.g., with a p- or n-type dopant) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. In general, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide layer (BOX layer), a silicon oxide layer, or the like. The insulating layer is provided on a substrate, usually silicon or a glass substrate. Other substrates, such as a multilayer or gradient substrate, may also be used.In some embodiments, the semiconductor material of the substrate 50 may comprise silicon; germanium; a composite semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium indium arsenide phosphide; or combinations thereof.

[0017] The substrate 50 has an n-region 50N and a p-region 50P. The n-region 50N can be used to form n-devices such as NMOS transistors, e.g., n-nanoFETs, and the p-region 50P can be used to form p-devices such as PMOS transistors, e.g., p-nanoFETs. The n-region 50N can be physically separated from the region 50P (not shown separately), and any number of device elements (e.g., other active devices, doped regions, insulating structures, etc.) can be placed between the n-region 50N and the p-region 50P.

[0018] Substrate 50 can be readily doped with a p- or n-type impurity. Anti-punch-through (APT) implantation can therefore be performed on an upper portion of substrate 50 to form an APT region. During APT implantation, dopants can be implanted in the n-type region 50N and the p-type region 50P. The dopants can have a conductivity type that opposes the conductivity type of source / drain regions subsequently formed in the n-type region 50N and the p-type region 50P. The APT region can extend beneath subsequently formed source / drain regions in the nanoFETs created in downstream processes. The APT region can be used to reduce leakage from the source / drain regions into substrate 50. In some embodiments, the doping concentration in the APT region can be in the range of approximately 10 18 cm -3 up to about 10 19 cm -3 lay.

[0019] A multilayer stack 52 is formed on top of the substrate 50. The multilayer stack 52 comprises alternating first semiconductor layers 52A and second semiconductor layers 52B. The first semiconductor layers 52A are formed from a first semiconductor material, and the second semiconductor layers 52B are formed from a second semiconductor material. The semiconductor materials can each be selected from the candidate semiconductor materials of the substrate 50. In the illustrated embodiment, the multilayer stack 52 comprises four layers of each of the first semiconductor layers 52A and the second semiconductor layers 52B. It should be noted that the multilayer stack 52 can comprise any number of first semiconductor layers 52A and second semiconductor layers 52B.

[0020] In the illustrated embodiment, the second semiconductor layers 52B are used to form channel regions for nanoFETs in the n-region 50N and the p-region 50P. The first semiconductor layers 52A are sacrificial (or dummy) layers that are removed in subsequent processing to expose the top and bottom faces of the second semiconductor layers 52B in both regions. The second semiconductor material of the second semiconductor layers 52B is a material suitable for n- and p-nanoFETs, such as silicon, and the first semiconductor material of the first semiconductor layers 52A is a material exhibiting high etch selectivity from the second semiconductor material, such as silicon-germanium.

[0021] In another embodiment, the first semiconductor layers 52A are used to form channel regions for the nanoFETs in one region (e.g., the p-region 50P), and the second semiconductor layers 52B are used to form channel regions for the nanoFETs in another region (e.g., the n-region 50N). The first semiconductor material of the first semiconductor layers 52A can be suitable for p-nanoFETs, such as silicon germanium (e.g., Si3). x Ge 1-x, where x can be in the range of 0 to 1), pure or essentially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like, and the second semiconductor material of the second semiconductor layer 52B can be suitable for n-nanoFETs, such as silicon, silicon carbide, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. The first semiconductor material and the second semiconductor material can exhibit high etch selectivity for mutual etching, such that the first semiconductor layer 52A can be removed without removing the second semiconductor layer 52B in the n-region 50N, and the second semiconductor layer 52B can be removed without removing the first semiconductor layer 52A in the p-region 50P.

[0022] Each of the layers of the multilayer stack 52 can be formed using a process such as vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like. Each of the layers can be formed with a small thickness, such as a thickness in the range of approximately 5 nm to approximately 30 nm. In some embodiments, one group of layers (e.g., the second semiconductor layers 52B) is formed to be thinner than the other groups of layers (e.g., the first semiconductor layers 52A). For example, in embodiments in which the second semiconductor layers 52B are used to form channel regions, and the first semiconductor layers 52A are sacrificial (or dummy) layers, the first semiconductor layers 52A can be formed with a first thickness T1, and the second semiconductor layers 52B can be formed with a second thickness T2, the second thickness T2 being approximatelyThe thickness is 30% to approximately 60% less than the first layer T1. Forming the second semiconductor layer 52B with a smaller thickness allows the formation of channel regions with a higher density.

[0023] In Fig. In step 3, grooves are etched into the substrate 50 and the multilayer stack 52 to form fins 54 and nanostructures 56. The fins 54 are semiconductor strips structured within the substrate 50. The nanostructures 56 comprise the remaining portions of the multilayer stack 52 adjacent to the fins 54. Specifically, the nanostructures 56 comprise alternating first nanostructures 56A and second nanostructures 56B. The first nanostructures 56A and the second nanostructures 56B are formed from remaining portions of the first semiconductor layers 52A and the second semiconductor layers 52B, respectively. After formation, the second nanostructures 56B are arranged in the intermediate layers of the structure, each between two of the first nanostructures 56A.The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), the like, or a combination thereof, and can be performed with masks 58 having a fin structure 54 and nanostructures 56. The etching can be anisotropic.

[0024] The fins 54 and the nanostructures 56 can be structured using any suitable method. For example, the fins 54 and the nanostructures 56 can be structured using one or more photolithography processes, including dual-structuring or multiple-structuring processes. In general, dual-structuring or multiple-structuring processes combine photolithography and self-aligning processes, which allows the creation of structures that, for example, have spacings that are smaller than would otherwise be possible using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and structured using a photolithography process. Spacers are formed along the structured sacrificial layer using a self-aligning process.The sacrificial layer is then removed, and the remaining spacers can then be used as masks 58 to structure the fins 54 and the nanostructures 56. In some embodiments, the masks 58 (or other layer) can remain on the nanostructures 56.

[0025] The fins 54 and the nanostructures 56 can have widths ranging from approximately 8 nm to approximately 40 nm. For illustrative purposes, the fins 54 and the nanostructures 56 in the n-region 50N and the p-region 50P are shown to have substantially the same widths. In some embodiments, the fins 54 and the nanostructures 56 in one region (e.g., the n-region 50N) can be wider or narrower than the fins 54 and the nanostructures 56 of the other region (e.g., the p-region 50P).

[0026] STI regions 60 are then formed adjacent to the fins 54. The STI regions 60 can be formed by depositing an insulating material over the substrate 50 and the nanostructures 56 and between adjacent fins 54. The insulating material can be an oxide such as silicon oxide, a nitride such as silicon nitride, the like, or a combination thereof, and can be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), the like, or a combination thereof. Other insulating materials formed by an acceptable process can be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. An annealing process can be performed once the insulating material has formed. In one embodiment, the insulating material is formed such that excess insulating material covers masks 58 (if present) or the nanostructures 56.Although the insulating material is illustrated as a single layer, embodiments can use multiple layers. For example, in some embodiments, a lining can first be formed along surfaces of the substrate 50, the fins 54, and the nanostructures 56. A filler material, such as the one discussed above, can then be formed over the lining.

[0027] A removal process is then applied to the insulating material to remove excess insulating material above the masks 58 (if present) or the nanostructures 56. In some embodiments, a planarization process, such as chemical-mechanical polishing (CMP), a back-etching process, combinations thereof, or the like, may be used. The planarization process exposes the masks 58 (if present) or the nanostructures 56, such that the top surfaces of the masks 58 (if present) or the nanostructures 56 and the insulating material are coplanar after completion of the planarization process (within the process variations).

[0028] The insulating material is then cut out to form the STI regions 60. The insulating material is cut out such that at least one section of the nanostructures 56 projects between adjacent STI regions 60. In the illustrated embodiment, the upper surfaces of the STI regions 60 (within the process variations) are coplanar with the upper surfaces of the fins 54. In some embodiments, the upper surfaces of the STI regions 60 are above or below the upper surfaces of the fins 54. Furthermore, the upper surfaces of the STI regions 60 can have a flat surface as illustrated, a convex surface, a concave surface (such as dishing), or a combination thereof. The upper surfaces of the STI regions 60 can be formed flat, convex, and / or concave by suitable etching. The STI regions 60 can be excised using an acceptable etching process, such as one that is selective for the insulating material (e.g.The insulating material of the STI regions 60 corrodes faster than the materials of the fins 54 and the nanostructures 56). For example, oxide removal can be carried out using dilute hydrofluoric acid (dHF).

[0029] The masks 58 (or other layer) can be removed before, during, or after the formation of the STI regions 60. For example, the masks 58 can be removed by the etching processes used to pattern the fins 54 and the nanostructures 56, or by the etching processes used to excise the STI regions 60. In another embodiment, the masks 58 are removed by a different etching process after the STI regions 60 have been excised.

[0030] The process described above is just one example of how the fins 54 and the nanostructures 56 can be formed. In some embodiments, the fins 54 and the nanostructures 56 can be formed by an epitaxial growth process. For example, a dielectric layer can be formed over a top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Epitaxial structures can be built up epitaxially in the trenches, and the dielectric layer can be cut away such that the epitaxial structures protrude from the dielectric layer to form the fins 54 and the nanostructures 56. The epitaxial structures can include the alternating semiconductor materials explained above, such as the first semiconductor material and the second semiconductor material.In embodiments where epitaxial structures are built up epitaxially, the epitaxially built materials may be doped in situ during growth, which may obscure previous and / or subsequent implantations, although in-situ and implantation doping may be used together.

[0031] Furthermore, suitable wells can be formed in the substrate 50, the fins 54, and / or the nanostructure 56. In some embodiments, a p-well can be formed in region 50N and an n-well can be formed in region 50P. In another embodiment, p-wells or n-wells can be formed in the n-region 50N and the p-region 50P, respectively.

[0032] In embodiments with different well types, the various implantation steps for the n-region 50N and the p-region 50P can be achieved using a photoresist or other masks. For example, a photoresist can be formed over the fins 54, the nanostructures 56, and the STI regions 60 in the n-region 50N. The photoresist is structured to expose the p-region 50P. The photoresist can be formed using a spin-on technique and can be produced using acceptable photolithography techniques. If the photoresist is structured, n-impurity implantation occurs in the p-region 50P, and the photoresist can act as a mask to essentially prevent n-impurities from being implanted into the n-region 50N. The n-impurities can be phosphorus, arsenic, antimony, or the like, which are introduced into the region at a concentration in the range of approximately 10 13 cm -3 up to about 10 14 cm-3 They are implanted. After implantation, the photoresist is removed, for example through an acceptable ash removal process.

[0033] Following the implantation of the p-region 50P, a photoresist is formed over the fins 54, the nanostructures 56, and the STI regions 60 within the p-region 50P. The photoresist is structured to expose the p-region 50P. It can be formed using a spin-on technique and can be produced using acceptable photolithography techniques. With the photoresist structured, p-impurity implantation can be performed in the n-region 50N, and the photoresist can act as a mask to essentially prevent the implantation of p-impurities into the p-region 50P. The n-impurities can be boron, boron fluoride, indium, or similar substances, introduced into the region at a concentration in the range of approximately 10⁻⁵. 13 cm -3 up to about 10 14 cm -3It can be implanted. After implantation, the photoresist can be removed, for example through an acceptable ash removal process.

[0034] Following the implantation of the n-region 50N and the p-region 50P, annealing can be performed to repair implantation damage and activate the implanted p- and / or n-impurities. In some embodiments, the built-up materials or epitaxial fins can be doped in place during growth, which can eliminate the need for implantation doping; however, in-place and implantation doping can be used concurrently.

[0035] In Fig. 4. A dummy dielectric layer 62 is formed on the fins 54 and the nanostructures 56. The dummy dielectric layer 62 can be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and can be deposited or thermally built up using acceptable techniques. A dummy gate layer 64 is formed over the dummy dielectric layer 62, and a mask layer 66 is formed over the dummy gate layer 64. The dummy gate layer 64 can be deposited over the dummy dielectric layer 62 and then planarized, for example, by CMP. The mask layer 66 can be deposited over the dummy gate layer 64. The dummy gate layer 64 can consist of conductive or non-conductive material and can be selected from a group that includes amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, and metals.The dummy gate layer 64 can be deposited by physical vapor deposition (PVD), CVD, sputtering, or other techniques to deposit the selected material. The dummy gate layer 64 can consist of one or more materials exhibiting high etch selectivity from insulating materials, such as the materials of the STI regions 60 and / or the dummy dielectric layer 62. The mask layer 66 can comprise one or more layers of, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 64 and a single mask layer 66 are formed over the n-region 50N and the p-region 50P. Although the dummy dielectric layer 62 is shown covering the STI regions 60, it should be noted that the dummy dielectric layer 62 can be formed in other ways.In some embodiments, such as when the dummy dielectric layer 62 is thermally built up, the dummy dielectric layer 62 is formed to cover only the fins 54 and the nanostructures 56.

[0036] Fig. 5A to 14B illustrate further intermediate steps in the fabrication of nano-FETs. Fig. 5B, Fig. 6B, Fig. 7B, Fig. 8B, Fig. 9B, Fig. 10B, Fig. 11B, Fig. 12B, Fig. 13B and Fig. 14B can apply to the n-region 50N and the p-region 50P. Differences (if any) between the structures of the n-region 50N and the p-region 50P are described in the text accompanying each figure.

[0037] In the Fig. 5A and Fig. In step 5B, the mask layer 66 is structured using acceptable photolithography and etching techniques to form masks 76. The structure of the masks 76 is then transferred to the dummy gate layer 64 using an acceptable etching technique to form dummy gates 74. The structure of the masks 76 can optionally be further transferred to the dummy dielectric layer 62 using an acceptable etching technique to form dummy dielectrics 72. The dummy gates 74 cover portions of the nanostructures 56 that are exposed in subsequent processing to form channel regions. Specifically, the dummy gates 74 extend along the portions of the nanostructures 56 that are used to form channel regions 68. The structure of the masks 76 can be used to physically separate each of the adjacent dummy gates 74. The dummy gates 74 can also have longitudinal directions that are essentially perpendicular (within the process boundaries) to the longitudinal directions of the fins 54.The masks 76 can optionally be removed after structuring, for example by an acceptable etching technique.

[0038] In Fig. 6A and Fig. In 6B, gate spacers 80 are formed over the nanostructures 56 and the fins 54 on exposed sidewalls of the masks 76, the dummy gates 74, and the dummy dielectrics 72. The gate spacers 80 can be formed by conformal forming of an insulating material and subsequent etching of the insulating material. The insulating material of the gate spacers 80 can be silicon nitride, silicon carbonitride, silicon oxycarbonitride, combinations thereof, or the like, and can be formed by thermal oxidation, deposition, a combination thereof, or the like. The gate spacers 80 can be formed from a single layer of insulating material or from multiple layers of insulating materials. In some embodiments, the gate spacers 80 each comprise multiple layers of silicon oxycarbonitride, each layer having a different silicon oxycarbonitride composition.In some embodiments, the gate spacers 80 each comprise a layer of silicon oxide sandwiched between two layers of silicon nitride. Other spacer structures are possible. The etching of the insulating material can be anisotropic. For example, the etching process can be dry etching, such as RIE, NBE, or the like. After etching, the gate spacer 80 can have straight or curved sidewalls.

[0039] Prior to the formation of the gate spacer 80, implantations for lightly doped source / drain regions (LDD regions) can be performed. In embodiments with different device types, similar to the implantations described above, a mask, such as a photoresist, can be formed over an n-region 50N while the p-region 50P is exposed, and suitable impurities (e.g., type p) can be implanted into the nanostructures 56 and the fins 54 exposed in the p-region 50P. The mask can then be removed. Subsequently, a mask, such as a photoresist, can be formed over the p-region 50P while the n-region 50N is exposed, and impurities of a suitable type (e.g., type n) can be implanted into the nanostructures 56 and the fins 54 exposed in the n-region 50N. The mask can then be removed.The n-impurities can be any of the previously discussed n-impurities, and the p-impurities can be any of the previously discussed p-impurities. The lightly doped source / drain regions can have an impurity concentration in the range of approximately 10. 15 cm -3 up to about 10 19 cm -3 Tempering can be used to repair implantation damage and activate the implanted impurities. During implantation, canal regions 68 remain covered by the dummy gates 74, so canal regions 68 remain essentially free of the impurity implanted in the LDD regions.

[0040] It is noted that the above revelation generally describes a process of forming spacers and LDD regions. Other processes and sequences can be used. For example, fewer or more spacers can be used, different step sequences can be employed (e.g., additional spacers can be formed and removed, etc.), and / or the like. Furthermore, the n- and p-devices can be formed using different structures and steps.

[0041] After the gate spacers 80 are formed, source / drain cutouts 82 are then formed in the nanostructures 56. In the illustrated embodiment, the source / drain cutouts 82 extend through the nanostructures 56 to expose the fins 54. The source / drain cutouts 82 can also extend into the substrate 50 and / or the fins 54. In other words, the source / drain cutouts 82 can be formed only in the nanostructures 56, as shown by Fig. 6A shown, or may also be formed extending into the fins 54, as in Fig. Figure 6B shows that in various embodiments, the source / drain cutouts 82 can extend from an upper surface of the substrate 50 without etching the substrate 50; the substrate 50 can be etched such that lower surfaces of the source / drain cutouts 82 are located beneath the upper surfaces of the STI regions 60; or the like. The source / drain cutouts 82 can be formed by etching the nanostructures 56 using anisotropic etching processes such as a RIE, an NBE, or the like. The gate spacers 80 and the masks 76 collectively mask sections of the nanostructures 56, the fins 54, and the substrate 50 during the etching processes used to form the source / drain cutouts 82. A single etching process can be used to etch each of the nanostructures 56. In other embodiments, several etching processes can be used to etch the nanostructures 56.Time-controlled etching processes can be used to stop the etching of the source / drain cutouts 82 after the source / drain cutouts 82 reach a desired depth D1. The depth D1 can be in the range of approximately 40 nm to approximately 140 nm.

[0042] Internal spacers 84 are optionally formed on the sidewalls of the remaining sections of the first nanostructures 56A, e.g., the sidewalls exposed by the source / drain cutouts 82. As explained in more detail below, source / drain regions are subsequently formed in the source / drain cutouts 82, and the first nanostructures 56A are subsequently replaced by corresponding gate structures. The internal spacers 84 act as insulating elements between the subsequently formed source / drain regions and the subsequently formed gate structures. Furthermore, the internal spacers 84 can be used to prevent damage to the subsequently formed source / drain regions from subsequent etching processes, such as those used to subsequently form the gate structures.

[0043] As an example of forming the inner spacers 84, the source / drain cutouts 82 can be extended. Specifically, sections of the sidewalls of the first nanostructures 56A, exposed by the source / drain cutouts 82, can be cut out. Although the sidewalls of the first nanostructures 56A are illustrated as straight, they can be concave or convex. The sidewalls can be cut out by an acceptable etching process, such as one that is selective for the material of the first nanostructures 56A (e.g., selectively etching the material of the first nanostructures 56A faster than the material(s) of the second nanostructures 56B and the fins 54). The etching can be anisotropic.For example, if the fins 54 and the second nanostructures 56B are formed from silicon and the first nanostructures 56A from silicon germanium, the etching process can be a wet etching using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like. In another embodiment, the etching process can be a dry etching using a fluorine-based gas such as hydrogen fluoride gas (HF gas). In some embodiments, the same etching process can be performed continuously to form both the source / drain cutouts 82 and the sidewalls of the first nanostructures 56A. The inner spacers 84 can then be formed by conformal forming of an insulating material and subsequent etching of the insulating material.The insulating material can be a material such as silicon nitride or silicon oxynitride, although any suitable material, such as materials with a lower dielectric constant (low k-value) with a k-value below approximately 3.5, can be used. The insulating material can be deposited by a conformal deposition process, such as ALD, CVD, or the like. The etching of the insulating material can be anisotropic. For example, the etching process can be dry etching, such as RIE, NBE, or the like. Although the original outer sidewalls of the inner spacer 84 are illustrated as being flush with the sidewalls of the gate spacer 80, the outer sidewalls of the inner spacers 84 can extend over or be cut out of the sidewalls of the gate spacers 80. In other words, the inner spacers 84 can partially fill, completely fill, or overfill the sidewall cutouts.Furthermore, although the side walls of the inner spacers 84 are illustrated as straight, the side walls of the inner spacers 84 can also be concave or convex.

[0044] In Fig. 7A and Fig. Epitaxial source / drain regions 92 are formed in the source / drain cutouts 82. The epitaxial source / drain regions 92 are formed in the source / drain cutouts 82 such that each of the dummy gates 74 is positioned between adjacent pairs of epitaxial source / drain regions 92. In some embodiments, gate spacers 80 are used to separate the epitaxial source / drain regions 92 from the dummy gates 74 and the first nanostructures 56A by a suitable lateral distance, preventing the epitaxial source / drain regions 92 from short-circuiting with subsequently formed gates of the nano-FETs. The epitaxial source / drain regions 92 may be formed in contact with the inner spacers 84 (if present) and may extend past the side walls of the second nanostructures 56B.The epitaxial source / drain regions 92 can load the second nanostructures 56B and thus improve performance.

[0045] The epitaxial source / drain regions 92 in the n-region 50N can be formed by masking the p-region 50P. The epitaxial source / drain regions 92 are then built epitaxially within the source / drain cutouts 82 in the n-region 50N. The epitaxial source / drain regions 92 can comprise any acceptable material suitable for n-nanoFETs. For example, the epitaxial source / drain regions 92 in the n-region 50N can comprise materials that exert a tensile force in the channel regions 68, such as silicon, silicon carbide, phosphor-doped silicon carbide, silicon phosphide, or the like. The epitaxial source / drain regions 92 in the n-region 50N can have surfaces that are raised by the respective faces of the second nanostructures 56B and the fins 54 and can have facets.

[0046] The epitaxial source / drain regions 92 in the p-region 50P can be formed by masking the n-region 50N. The epitaxial source / drain regions 92 are then epitaxially constructed within the source / drain cutouts 82 in the p-region 50P. The epitaxial source / drain regions 92 can comprise any acceptable material suitable for p-nanoFETs. For example, the epitaxial source / drain regions 92 in the p-region 50P can comprise materials that exert a pressure load on the channel regions 68, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, or the like. The epitaxial source / drain regions 92 in the p-region 50P may have surfaces raised from respective surfaces of the second nanostructures 56B and the fins 54, and may have facets.

[0047] The epitaxial source / drain regions 92, the second nanostructures 56B, and / or the fins 54 can be implanted with dopants to form source / drain regions, similar to the process previously used to form lightly doped source / drain regions followed by annealing. The source / drain regions can contain an impurity concentration in the range of approximately 10 19 cm -3 up to about 10 21 cm -3 exhibiting n and / or p impurities. The n and / or p impurities for source / drain regions can be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 92 can be locally doped during growth.

[0048] As a result of the epitaxial process used to form the epitaxial source / drain regions 92, the upper surfaces of the epitaxial source / drain regions 92 exhibit facets that extend laterally outward beyond the surfaces of the second nanostructures 56B and the fins 54. Thus, the epitaxial source / drain regions 92 have a height H1 that is greater than the depth D1 of the source / drain cutouts 82. For example, the height H1 can range from approximately 30 nm to approximately 120 nm. In some embodiments, adjacent epitaxial source / drain regions 92 remain separated in the p-region 50P after the epitaxial process is complete, as shown in Fig. 7A is illustrated. In other embodiments, these facets cause adjacent epitaxial source / drain regions 92 of the same nano-FET to merge. In the embodiments shown in Fig. 7A and Fig. As illustrated in Figure 7B, the spacer etching used to form the gate spacers 80 is modified to remove the spacer material so that the epitaxial source / drain regions 92 can extend onto the upper surfaces of the STI regions 60. In another embodiment, the gate spacers 80 are formed to cover sections of the sidewalls of the nanostructures 56 that extend over the STI regions 60, thereby blocking epitaxial growth on the upper surfaces of the STI regions 60.

[0049] The epitaxial source / drain regions 92 can comprise one or more semiconductor material layers. For example, the epitaxial source / drain regions 92 can comprise first semiconductor material layers, second semiconductor material layers, and third semiconductor material layers. Any number of semiconductor material layers can be used for the epitaxial source / drain regions 92. Each of the first semiconductor material layers, the second semiconductor material layers, and the third semiconductor material layers can be formed from different semiconductor materials and / or can be doped to different dopant concentrations. In some embodiments, the first semiconductor material layers can have a dopant concentration that is lower than that of the second semiconductor material layers and higher than that of the third semiconductor material layers.In embodiments in which the epitaxial source / drain regions 92 comprise three semiconductor material layers, the first semiconductor material layers can be composed of the fins 54, the second semiconductor material layers can be composed of the first semiconductor material layers, and the third semiconductor material layers can be composed of the second semiconductor material layers.

[0050] In Fig. 8A and Fig. 8B is a first ILD 96 formed over the epitaxial source / drain regions 92 and the STI regions 60. The first ILD 96 may be formed from a dielectric. Dielectrics may include oxides such as silicon dioxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like; nitrides such as silicon nitride or the like. Other insulating materials may be used.

[0051] The first ILD 96 can be formed by depositing a dielectric over the epitaxial source / drain regions 92, the gate spacers 80, the masks 76 (if present), or the dummy gates 74 and the STI regions 60, and subsequently planarizing the dielectric. Deposition can be performed by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Other acceptable processes may be used to form the dielectric. Planarization can be performed by any suitable method, such as CMP, a back-etching process, combinations thereof, or the like. The planarization process flattens the top surface of the first ILD 96 with the top surfaces of the masks 76 or the dummy gates 74. The planarization process can also remove the masks 76 at the dummy gates 74 and sections of the gate spacer 80 along the sidewalls of the masks 76.After the planarization process, the upper surfaces of the first ILD 96, the gate spacer 80, and the masks 76 (if present) or dummy gates 74 are coplanar (within the process variations). Accordingly, the upper surfaces of the masks 76 (if present) or dummy gates 74 are exposed by the first ILD 96. In the illustrated embodiment, the masks 76 remain, and the planarization process aligns the upper surface of the first ILD 96 with the upper surfaces of the masks 76.

[0052] In some embodiments, a contact etch stop layer (CESL) 94 is arranged between the first ILD 96 and the epitaxial source / drain regions 92, the gate spacer 80, and the STI regions 60. The CESL 94 can comprise a dielectric such as silicon nitride, silicon oxide, silicon oxynitride, or the like, which exhibits high etch selectivity by etching the first ILD 96.

[0053] In Fig. 9A and Fig. In the second nanostructures 56B, the masks 76 (if present) and the dummy gates 74 are removed in an etching process, forming cutouts 98. Sections of the dummy dielectrics 72 in the cutouts 98 can also be removed. In some embodiments, the dummy gates 74 are removed by an anisotropic dry etching process. For example, the etching process can include a dry etching process that uses one or more reactive gases that selectively etch the dummy gates 74 at a faster rate than the first ILD 96 or the gate spacers 80. During removal, the dummy dielectrics 72 can be used as etch stop layers when the dummy gates 74 are etched. The dummy dielectrics 72 can then be removed after the dummy gate 74 has been removed. Each cutout 98 exposes and / or overlays sections of the channel regions 68 in the second nanostructures 56B.Sections of the second nanostructures 56B, which serve as the channel regions 68, are arranged between adjacent pairs of the epitaxial source / drain regions 92.

[0054] The remaining sections of the first nanostructures 56A are then removed to eliminate the cutouts 98. The remaining sections of the first nanostructures 56A can be removed by an acceptable etching process that selectively etches the material of the first nanostructures 56A faster than the materials of the second nanostructures 56B, the fins 54, and the STI regions 60. The etching can be anisotropic. For example, if the fins 54 and the second nanostructures 56B are formed from silicon and the first nanostructures 56A from silicon germanium, the etching process can be a wet etching using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like.

[0055] The exposed sections of the second nanostructures 56B and the fins 54 are optionally trimmed back. This trimming reduces the thickness of the exposed sections of the second nanostructures 56B from the second thickness T2 (above with reference to Fig. (2 explained) to a third thickness T3, wherein the third thickness T3 is in a range of approximately 3 nm to approximately 8 nm and the third thickness T3 is between approximately 40% and approximately 70% less than the second thickness T2. The trimming can be performed simultaneously with the formation of the cutouts 98 or after the formation of the cutouts 98. For example, the exposed sections of the second nanostructures 56B and the fins 54 can be trimmed by an acceptable etching process that selectively etches the material(s) of the second nanostructures 56B and the fins 54 at a faster rate than the materials of the first nanostructures 56A, the inner spacers 84, and the gate spacers 80. The etching can be anisotropic.For example, if the fins 54 and the second nanostructures 56B are formed from silicon and the first nanostructures 56A are formed from silicon germanium, the etching process can be a wet etching using a dilute ammonium hydroxide hydrogen peroxide mixture (APM), a sulfurous acid hydrogen peroxide mixture (SPM), or the like.

[0056] In Fig. Gate dielectrics 102 and gate electrodes 104 for replacement gates are formed at 10A to 10B. The gate dielectrics 102 are conformally deposited in the cutouts 98, such as on the upper surfaces and sidewalls of the fins 54 and on the upper surfaces, sidewalls, and lower surfaces of the second nanostructures 56B. The gate dielectrics 102 can also be deposited on the upper surfaces of the first ILD 96, the gate spacers 80, and the STI regions 60. The gate dielectrics 102 comprise one or more dielectric layers, such as an oxide, a metal oxide, a metal silicate, the like, or combinations thereof. In some embodiments, the gate dielectrics 102 comprise silicon oxide, silicon nitride, or multiple layers thereof. In some embodiments, the gate dielectrics 102 comprise a dielectric with a high k-value, and in these embodiments the gate dielectrics 102 may have a higher k-value than approximately7.0 and a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The gate dielectrics 102 can be multilayered. For example, in some embodiments, the gate dielectrics 102 can each comprise an interface layer of silicon oxide formed by thermal and chemical oxidation and a metal oxide layer over the interface layer. The formation methods of the gate dielectrics 102 can include molecular beam deposition (MBD), ALD, PECVD, and the like.

[0057] The gate electrodes 104 are each arranged over the gate dielectrics 102 and fill the remaining portions of the cutouts 98. The gate electrodes 104 can comprise a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. For example, although single-layer gate electrodes 104 are illustrated, the gate electrodes 104 can comprise any number of lining layers, any number of work function matching layers, and a filler material. Any combination of the layers representing the gate electrodes 104 can be deposited in the regions between each of the second nanostructures 56B and between the fins 54 and the second nanostructures 56B. The formation methods for the gate electrodes 104 can include ALD, PECVD, and the like.After filling the cutouts 98, a planarization process such as a CMP can be performed to remove excess sections of the materials of the gate dielectrics 102 and the gate electrodes 104, with these excess sections located above the top surfaces of the first ILD 96 and the gate spacers 80. The remaining sections of the materials of the gate dielectrics 102 and the gate electrodes 104 thus form substitute gates of the resulting nano-FETs. The gate dielectrics 102 and the gate electrodes 104 can be collectively referred to as gate structures 100 or “gate stacks”.

[0058] The formation of the gate dielectrics 102 in region 50N and region 50P can occur simultaneously, so that the gate dielectrics 102 in each region are formed from the same materials, and the formation of the gate electrodes 104 can also occur simultaneously, so that the gate electrodes 104 in each region are formed from the same materials. In some embodiments, the gate dielectrics 102 in each region can be formed by separate processes, so that the gate dielectrics 102 can consist of different materials, and / or the gate electrodes 104 in each region can be formed by separate processes, so that the gate electrodes 104 can consist of different materials. Various masking steps can be used to mask and expose suitable regions when using separate processes.

[0059] In Fig. 11A and Fig. Source / drain contact openings 106 are formed by the first ILD 96 and the CESL 94. The source / drain contact openings 106 can initially be formed in the first ILD 96 using acceptable photolithography and etching techniques, such as an etching process that is selective for the first ILD 96 (e.g., the material of the first ILD 96 etches faster than the material of the CESL 94). For example, the source / drain contact openings 106 can initially be formed by dry etching through the first ILD 96 using ammonia (NH3) and hydrogen fluoride gas (HF gas). The source / drain contact openings 106 are then extended by the CESL 94 using acceptable photolithography and etching techniques, such as an etching process that is selective for CESL 94 (e.g., the material of the CESL 94 etches faster than the material of the epitaxial source / drain regions 92).For example, the source / drain contact openings 106 can be extended through the CESL 94 by dry etching using a fluorine-based gas (e.g., C4F6) and hydrogen (H2) or oxygen (O2) gas. The source / drain contact openings 106 are then partially extended into the epitaxial source / drain regions 92, such as the upper portions of the epitaxial source / drain regions 92. For example, the source / drain contact openings 106 can be extended into the upper portions of the epitaxial source / drain regions 92 by dry etching using chlorine gas (Cl2 gas), hydrogen bromide gas (HBr gas), and oxygen gas (O2 gas).

[0060] After formation, the source / drain contact openings 106 extend by a distance D2 into the upper sections of the epitaxial source / drain regions 92. In some embodiments, the distance D2 is approximately half the height H1 of the epitaxial source / drain regions 92. Time-controlled etching processes can be used to extend the etching of the source / drain contact openings 106, after the extension of the source / drain contact openings 106 into the upper sections of the epitaxial source / drain regions 92, by a desired distance D2. For example, if the etchants described above are used to etch the epitaxial source / drain regions 92, the etching can be carried out for a duration in the range of approximately 50 seconds to approximately 200 seconds, which can cause the source / drain contact openings 136 to extend by a distance D2 in the range of approximately 15 nm to approximately 60 nm into the upper sections of the epitaxial source / drain regions 92.

[0061] Metal-semiconductor alloy regions 108 are formed in the source / drain contact openings 106, such as at sections of the epitaxial source / drain regions 92 exposed by the source / drain contact openings 106. The metal-semiconductor alloy regions 108 can be silicide regions formed from a metal silicide (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), germanide regions formed from a metal germanide (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.), silicon germanide regions formed from both a metal silicide and a metal germanide, or the like. The metal-semiconductor alloy regions 108 can be formed by depositing a metal in the source / drain contact openings 106 and then performing a heat tempering process. The metal can be any metal that is able to interact with the semiconductor materials (e.g. silicon, silicon germanium, germanium, etc.).) of the epitaxial source / drain regions 92 to form a low-resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, or other precious metals, other high-melting-point metals, rare earth metals, or their alloys. A metal can be deposited by a deposition process such as ALD, CVD, PVD, or the like. In one embodiment, the metal-semiconductor alloy regions 108 are silicide regions formed from titanium silicon. After the thermal annealing process, a cleaning process, such as wet cleaning, can be performed to remove residual metal from the source / drain contact openings 106, such as from the upper surfaces of the first ILD 96.

[0062] In the illustrated embodiment, the source / drain contact openings 106 are formed in a self-aligned structuring process such that all of the first ILD 96 in the cross-section of Fig. 11B are removed. In another embodiment, other structuring methods can be used, so that some of the first ILD 96 in the cross-section are removed. Fig. Remain 11B.

[0063] In Fig. 12A and Fig. 12B are first source / drain contacts 112A formed in the source / drain contact openings 106. A lining, such as a diffusion barrier layer, an adhesive layer, or the like, and a conductive material are formed in the source / drain contact openings 106. The lining may comprise titanium, titanium nitride, tantalum, tantalum nitride, or the like. The lining may be deposited by a conformal deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like. In some embodiments, the lining may comprise an adhesive layer, and at least one portion of the adhesive layer may be treated to form a diffusion barrier layer. The conductive material may be tungsten, cobalt, ruthenium, aluminum, nickel, copper, a copper alloy, silver, gold, or the like. The conductive material may be deposited by ALD, CVD, PVD, or other methods.A planarization process, such as CMP, can be performed to remove excess material from the top surfaces of the first ILD 96. The remaining lining and conductive material in the source / drain contact openings 106 form the first source / drain contacts 112A. The first source / drain contacts 112A are physically and electrically coupled to the metal-semiconductor alloy regions 108. The top surfaces of the first source / drain contacts 112A, the gate electrodes 104, and the gate spacers 80 are coplanar (within the process variations).

[0064] After forming, the first source / drain contacts 112A have similar dimensions to the source / drain contact openings 106. The first source / drain contacts 112A extend by the distance D2 (see Fig. 11B) into the upper sections of the epitaxial source / drain regions 92 and have a height H2. The height H2 can be in the range of approximately 30 nm to approximately 90 nm. In embodiments in which the distance D2 is approximately half the height H1 (see Fig. 7B), the height H2 is more than about half the height H1.

[0065] In Fig. 13A and Fig. In embodiment 13B, a second ILD 114 is deposited over the first ILD 96, the gate electrodes 104, and the first source / drain contacts 112A. The second ILD 114 may be formed from a material selected from the same group of candidate materials as the first ILD 96 and may be deposited using a method selected from the same group of candidate methods used to deposit the first ILD 96. The first ILD 96 and the second ILD 114 may be formed from the same material or comprise different materials. After formation, the second ILD 114 may be planarized, for example, by a CMP. In some embodiments, an etch stop layer is formed between the first ILD 96 and the second ILD 114. The etch stop layer may comprise a dielectric, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, which has a different etch rate than the material of the overlying second ILD 114.

[0066] Contact openings 116 are then formed in the second ILD 114. A first subset of contact openings 116A exposes the first source / drain contacts 112A, and a second subset of contact openings 116B exposes the gate electrodes 104. The contact openings 116 can be formed using acceptable photolithography and etching techniques.

[0067] In Fig. 14A and Fig. Second source / drain contacts 112B and gate contacts 118 are formed at the contact openings 116, extending through the second ILD 114. A lining, such as a diffusion barrier layer, an adhesive layer, or the like, and a conductive material are formed in the contact openings 116. The lining may comprise titanium, titanium nitride, tantalum, tantalum nitride, or the like. The lining may be deposited by a conformal deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like. In some embodiments, the lining may comprise an adhesive layer, and at least one portion of the adhesive layer may be treated to form a diffusion barrier layer. The conductive material may be tungsten, cobalt, ruthenium, aluminum, nickel, copper, a copper alloy, silver, gold, or the like. The conductive material may be deposited by ALD, CVD, PVD, or other methods.A planarization process, such as CMP, can be performed to remove excess material from an upper surface of the second ILD 114. The remaining lining and conductive material in the contact openings 116A form the second source / drain contacts 112B. The remaining lining and conductive material in the contact openings 116B form the gate contacts 118. The second source / drain contacts 112B are physically and electrically coupled to the first source / drain contacts 112A, and the gate contacts 118 are physically and electrically coupled to the gate electrodes 104.

[0068] The second source / drain contacts 112B and the gate contacts 118 can be formed in different processes or in the same process. Furthermore, the second source / drain contacts 112B and the gate contacts 118 can be formed in the same cross-sections, defined by Fig. 13B and Fig. 14B are shown, or may be formed in other cross-sections, as shown by Fig. 13A and Fig. 14A is shown, which can prevent short circuits of the contacts.

[0069] As explained in more detail below, a first interconnection structure (e.g., a front interconnection structure) is formed over the substrate 50. The substrate 50 is then removed and replaced with a second interconnection structure (e.g., a back interconnection structure). This creates a device layer 120 of active devices between a front interconnection structure and a back interconnection structure. The front and back interconnection structures each comprise conductive elements that are electrically connected to the nanoFETs of the device layer 120. The conductive elements (e.g.,Metallization structures (also referred to as interconnects) of the front interconnect structure are electrically connected to the front faces of one or more of the epitaxial source / drain regions 92 and the gate electrodes 104 to form functional circuits, such as logic circuits, memory circuits, image sensor circuits, or the like. The conductive elements (e.g., busbars) of the rear interconnect structure are electrically connected to the back faces of one or more of the epitaxial source / drain regions 92 to provide a reference voltage, supply voltage, or the like to the functional circuits. Furthermore, conductive vias are formed through the device layer 120, connecting some of the conductive elements of the front interconnect structure to some of the conductive elements of the rear interconnect structure. Specifically, a conductive element (e.g.,a busbar) of the rear interconnection structure is connected to a conductive element (e.g., metallization structures) of the front interconnection structure and also to one or more of the epitaxial source / drain regions 92 of the device layer 120. Although the device layer 120 is described as having nanoFETs, other embodiments may have a device layer 120 that has a different type of transistor (e.g., planar FETs, FinFETs, TFTs, or the like).

[0070] Even if Fig. As Figure 14B illustrates a second source / drain contact 112B extending to each of the epitaxial source / drain regions 92, the second source / drain contacts 112B can be omitted for certain epitaxial source / drain regions 92. For example, as explained in more detail below, a subset of the epitaxial source / drain regions 92P is connected to conductive elements (e.g., a busbar) of the rear intermediate structure. In the illustrated embodiment for these particular epitaxial source / drain regions 92P, the second source / drain contacts 112B are also configured such that the busbars can be connected to overlying conductive elements of the front intermediate structure.In other embodiments, the second source / drain contacts 112B can be omitted for these particular epitaxial source / drain regions 92P, or they can be dummy contacts that are not electrically connected to overlying conductive elements of the front-side intermediate connection structure.

[0071] Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19, Fig. 20, Fig. 21 to Fig. Figure 22 shows various views of intermediate stages in the fabrication of semiconductor devices according to several embodiments. Specifically, the fabrication of front- and back-side interconnect structures for nano-FETs is illustrated. Fig. 15, Fig. 16, Fig. 17, Fig. 18B, Fig. 19B, Fig. 20, Fig. 21 and Fig. 22 are cross-sectional views, which are arranged along reference cross-section AA in Fig. 1 are illustrated. Fig. 18A and Fig. 19B are three-dimensional views that provide a similar three-dimensional view to Fig. Figure 1 shows a gate structure and two fins. Fig. 18A and Fig. 19A are simplified three-dimensional views and do not show all properties of the corresponding Fig. 18B and Fig. 19B. Fig. 15, Fig. 16, Fig. 17, Fig. 18B, Fig. 19B, Fig. 20, Fig. 21 and Fig. Figure 22 can apply to the n-region 50N and the p-region 50P. Differences (if any) between the structures of the n-region 50N and the p-region 50P are described in the text accompanying each figure.

[0072] In Fig. 15 An intermediate connection structure 122 is formed on the device layer 120, e.g., on the second ILD 114. The intermediate connection structure 122 can also be referred to as a front-side intermediate connection structure, since it is formed on a front side of the substrate 50 / the device layer 120 (e.g., a side of the substrate 50 on which the device layer 120 is formed).

[0073] The interconnect structure 122 can comprise one or more layers of conductive elements 124 formed within one or more stacked dielectric layers 126. Each of the dielectric layers 126 can comprise a dielectric, such as a low k-value dielectric, an extra-low k-value dielectric (ELK dielectric), or the like. The dielectric layers 126 can be deposited using a suitable process such as CVD, ALD, PVD, PECVD, or the like.

[0074] The conductive elements 124 can comprise conductive conductors and conductive vias that connect the conductive conductor layers. The conductive vias can extend through each of the dielectric layers 126 to provide vertical connections between conductive conductor layers. The conductive elements 124 can be formed by any acceptable process. For example, the conductive elements 124 can be formed by a damascening process, such as a single-damascening process, a double-damascening process, or the like. In a damascening process, each dielectric layer 126 is structured using a combination of photolithography and etching techniques to form grooves that correspond to the desired structure of the conductive elements 124.An optional diffusion barrier and / or adhesive layer can be deposited, and the trenches can then be filled with a conductive material. Suitable materials for the barrier layer include titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, tantalum oxide, or other alternatives, and suitable materials for the conductive material include copper, silver, gold, tungsten, aluminum, combinations thereof, or the like. In one embodiment, the conductive elements 124 can be formed by depositing a seed layer of copper or a copper alloy and filling the trenches with electroplating. A chemical-mechanical planarization (CMP) process or the like can be used to remove excess conductive material from an area of ​​the respective dielectric layer 126 and subsequently planarize the area for further processing.

[0075] The illustrated example shows five layers of conductive elements 124 and dielectric layers 126. However, it should be noted that the interconnection structure 122 can comprise any number of conductive elements arranged on any number of dielectric layers. The conductive elements 124 of the interconnection structure 122 are electrically connected to the gate contacts 118 and the second source / drain contacts 112B to form functional circuits. In some embodiments, the functional circuits formed by the interconnection structure 122 may include logic circuits, memory circuits, image sensor circuits, or the like. The second ILD 114, the second source / drain contacts 112B, and the gate contacts 118 can also be considered part of the interconnection structure 122, such as part of a first layer of conductive elements of the interconnection structure 122.

[0076] In Fig. In the 16 form, a support substrate 130 is connected to an upper surface of the intermediate interconnect structure 122 by interconnect layers 132A, 132B (collectively referred to as interconnect layers 132). The support substrate 130 can be a glass support substrate, a ceramic support substrate, a semiconductor substrate (e.g., a silicon substrate), a wafer (e.g., a silicon wafer), or the like. The support substrate 130 can provide structural support during subsequent processing steps and in the completed device. The support substrate 130 is essentially free of any active or passive devices.

[0077] In various embodiments, the support substrate 130 can be bonded to the intermediate structure 122 using a suitable technique such as dielectric-dielectric bonding or the like. Dielectric-dielectric bonding can include the deposition of the bonding layers 132A, 132B on the intermediate structure 122 and the support substrate 130, respectively. In some embodiments, the bonding layer 132A comprises silicon oxide (e.g., a high-density plasma oxide (HDP) or the like) deposited by CVD, ALD, PVD, or the like. The bonding layer 132B can also be an oxide layer formed prior to bonding using, for example, CVD, ALD, PVD, thermal oxidation, or the like. Other suitable materials can also be used for the bonding layers 132A, 132B.

[0078] The dielectric-dielectric bonding process can further include applying a surface treatment to one or more of the bonding layers 132. The surface treatment can include plasma treatment. The plasma treatment can be performed in a vacuum environment. After the plasma treatment, the surface treatment can further include a cleaning process (e.g., rinsing with deionized water or the like) that can be applied to one or more of the bonding layers 132. The support substrate 130 is then aligned with the intermediate bonding structure 122, and the two are pressed together to initiate the pre-bonding of the support substrate 130 to the intermediate bonding structure 122. The pre-bonding can be performed at room temperature (e.g., in a range of approximately 20 °C to approximately 25 °C).After pre-compounding, a tempering process can be applied, for example by heating the intermediate compound structure 122 and the support substrate 130 to a temperature of approximately 170 °C.

[0079] In Fig. In 17, the intermediate structure is inverted so that the back side of the substrate 50 faces upwards. The back side of the substrate 50 refers to the side opposite the front side of the substrate 50 where the device layer 120 is formed. The substrate 50 is then thinned to remove back-side sections of the substrate 50. The thinning process may include a planarization process (e.g., mechanical grinding, chemical-mechanical polishing (CMP), or the like), a back-etching process, combinations thereof, or the like. The thinning process exposes the STI regions 60 and fin faces 54 on the back side of the device layer 120.

[0080] A dielectric layer 128 is arranged over the back surface of the device layer 120, such as over the fins 54 and the STI regions 60. The dielectric layer 128 is part of an intermediate interconnect structure formed at the device layer 120. The dielectric layer 128 can physically contact surfaces of the remaining portions of the fins 54 and the STI regions 60. The dielectric layer 128 can be formed from a material selected from the same group of candidate materials as the first ILD 96 and can be deposited using a method selected from the same group of candidate methods for depositing the first ILD 96. The first ILD 96 and the dielectric layer 128 can be formed from the same material or comprise different materials.

[0081] In Fig. 18A and Fig. In 18B, a mask 134 is formed over the dielectric layer 128. The mask 134 can be formed from a photoresist, such as a single-layer, two-layer, three-layer, or the like. In some embodiments, the mask 134 is a three-layer mask comprising a bottom layer (e.g., a bottom antireflective coating layer (BARC layer)), a middle layer (e.g., a nitride, an oxide, an oxynitride, or the like), and a top layer (e.g., a photoresist). The type of mask used (e.g., single-layer, two-layer, three-layer, etc.) may depend on the photolithography process used to subsequently pattern the mask 134. For example, in extreme ultraviolet lithography (EUV) processes, the mask 134 may be a single-layer or a two-layer mask.The mask 134 can be formed by spin coating, a deposition process such as CVD, combinations thereof, or the like. The mask 134 can be structured using acceptable photolithography techniques to form the openings that exhibit a structure of subsequently formed source / drain contacts.

[0082] Source / drain contact openings 136 are formed by the dielectric layer 128, the fins 54, the epitaxial source / drain regions 92P, and the metal-semiconductor alloy regions 108. The source / drain contact openings 136 can initially be formed in the dielectric layer 128 using acceptable photolithography and etching techniques, such as an etching process that is selective for the dielectric layer 128 (e.g., the material of the dielectric layer 128 etches faster than the material of the fins 54), using the mask 134 as the etching mask. For example, the source / drain contact openings 136 can initially be formed by dry etching through the dielectric layer 128 using ammonia (NH3) and hydrogen fluoride gas (HF gas).The source / drain contact openings 136 are then extended through the fins 54 using acceptable photolithography and etching techniques, such as an etching process that is selective for the fins 54 (e.g., the material of the fins 54 etches faster than the material of the fins 92). For example, the source / drain contact openings 136 can be extended through the fins 54 by dry etching using a fluorine-based gas such as hydrogen fluoride gas (HF gas). The source / drain contact openings 136 are then extended through the epitaxial source / drain regions 92P and the metal-semiconductor alloy regions 108, such that the source / drain contact openings 136 extend into the lower portions of the epitaxial source / drain regions 92P and expose the first source / drain contacts 112A.For example, the source / drain contact openings 136 can be extended through the epitaxial source / drain regions 92P and the metal-semiconductor alloy regions 108 by dry etching using chlorine gas (Cl₂ gas), hydrogen bromide gas (HBr gas), and oxygen gas (O₂ gas). In the illustrated embodiment, essentially no etching of the first source / drain contacts 112A occurs when the source / drain contact openings 136 are patterned. In another embodiment, the source / drain contact openings 136 can also extend into the first source / drain contacts 112A.

[0083] The mask 134 can be removed during or after the structuring of the source / drain contact openings 136. For example, the mask 134 can be removed by the etching processes used to structure the dielectric layer 128, the fins 54, the epitaxial source / drain regions 92P, or the metal-semiconductor alloy regions 108. In another embodiment, the mask 134 is removed after the structuring of the source / drain contact openings 136, such as by an acceptable ash etching process.

[0084] After formation, the source / drain contact openings 136 extend a distance D3 into the lower sections of the epitaxial source / drain regions 92P. In some embodiments, the distance D3 is approximately half the height H1 (see Fig. 7B) of the epitaxial source / drain regions 92P. The sum of the distances D2 (see Fig. 11B) and D3 corresponds to the height H1. In other words, the distances D2 and D3 can be equal. In another embodiment, the distances D2 and D3 are different; for example, the distance D2 can be greater or less than the distance D3. Time-dependent etching processes can be used to extend the etching of the source / drain contact openings 136, after the source / drain contact openings 136 have been extended to the lower sections of the epitaxial source / drain regions 92P, by a desired distance D3. For example, if the etchants described above are used to etch the epitaxial source / drain regions 92P, the etching can be carried out for a duration in the range of approximately 50 seconds to approximately 200 seconds, which can cause the source / drain contact openings 136 to extend by a distance D3 in the range of approximately 15 nm to approximately 60 nm into the lower sections of the epitaxial source / drain regions 92P.

[0085] In Fig. 19A and Fig. 19B are metal-semiconductor alloy regions 138 formed in the source / drain contact openings 136, such as at sections of the epitaxial source / drain regions 92P exposed by the source / drain contact openings 136. The metal-semiconductor alloy regions 138 can be silicide regions formed from a metal silicide (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), germanide regions formed from a metal germanide (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.), silicon germanide regions formed from both a metal silicide and a metal germanide, or the like. The metal-semiconductor alloy regions 138 can be formed by depositing a metal in the source / drain contact openings 136 and then performing a heat tempering process. The metal can be any metal that is able to interact with the semiconductor materials (e.g. silicon, silicon germanium, germanium, etc.).The epitaxial source / drain regions 92P react to form a low-resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, or other precious metals, other high-melting-point metals, rare earth metals, or their alloys. A metal can be deposited by a deposition process such as ALD, CVD, PVD, or the like. In one embodiment, the metal-semiconductor alloy regions 138 are silicide regions formed from titanium silicon. After the thermal annealing process, a cleaning process, such as wet cleaning, can be performed to remove residual metal from the source / drain contact openings 136, such as from surfaces of the first source / drain contacts 112A and the STI regions 60.Although the metal semiconductor alloy regions 108, 138 are shown as separate regions, it should be noted that in some embodiments the metal semiconductor alloy regions 108, 138 merge during formation, so that there is no distinguishable interface between them.

[0086] Third source / drain contacts 112C are formed in the source / drain contact openings 136. A lining, such as a diffusion barrier layer, an adhesive layer, or the like, and a conductive material are formed in the source / drain contact openings 136. The lining may comprise titanium, titanium nitride, tantalum, tantalum nitride, or the like. The lining may be deposited by a conformal deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like. In some embodiments, the lining may comprise an adhesive layer, and at least one portion of the adhesive layer may be treated to form a diffusion barrier layer. The conductive material may be tungsten, cobalt, ruthenium, aluminum, nickel, copper, a copper alloy, silver, gold, or the like. The conductive material may be deposited by ALD, CVD, PVD, or other methods.A planarization process, such as CMP, can be performed to remove excess material from the top surface of the dielectric layer 128. The remaining lining and conductive material in the source / drain contact openings 136 form the third source / drain contacts 112C. The third source / drain contacts 112C are physically and electrically coupled to the first source / drain contacts 112A. The top surfaces of the third source / drain contacts 112C and the dielectric layer 128 are coplanar (within the process variations).

[0087] After forming, the third source / drain contacts 112C have similar dimensions to the source / drain contact openings 136. The third source / drain contacts 112C extend by the distance D3 (see Fig. 18B) into the lower sections of the epitaxial source / drain regions 92 and have a height H3. The height H3 can be in the range of approximately 25 nm to approximately 70 nm. In embodiments in which the distance D3 is approximately half the height H1 (see Fig. 7B), the height H3 is more than about half the height H1.

[0088] In Fig. 20 A dielectric layer 142 and conductive elements 144 are formed over the dielectric layer 128 and the third source / drain contacts 112C. The dielectric layer 142 and the conductive elements 144 are also part of an intermediate interconnect structure formed on the device layer 120. The dielectric layer 142 can be formed from a material selected from the same group of candidate materials as the first ILD 96 and can be deposited using a method selected from the same group of candidate methods as the first ILD 96. The first ILD 96 and the dielectric layer 142 can be formed from the same material or comprise different materials.

[0089] The conductive elements 144 are formed in the dielectric layer 142 and can be conductive conductors. Forming the conductive elements 144 can, for example, involve structuring cutouts in the dielectric layer 142 using a combination of photolithography and etching processes. A structure of the cutouts in the dielectric layer 142 can correspond to a structure of the conductive elements 144. The conductive elements 144 are then formed by depositing a conductive material in the cutouts. In some embodiments, the conductive elements 144 comprise a metal layer, which can be a single layer or a composite layer comprising several sublayers formed from different materials. In some embodiments, the conductive elements 144 comprise copper, aluminum, cobalt, tungsten, titanium, tantalum, ruthenium, or the like.An optional diffusion barrier and / or adhesive layer can be applied prior to filling the cutouts with a conductive material. Suitable materials for the barrier / adhesive layer include titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, titanium oxide, or the like. The conductive elements 144 can be formed using, for example, CVD, ALD, PVD, plating, or the like. The conductive elements 144 are electrically connected to the epitaxial source / drain regions 92P via the third source / drain contacts 112C and the metal-semiconductor alloy regions 138. A planarization process (e.g., CMP, looping, back-etching, or the like) can be performed to remove excess portions of the conductive elements 144 formed above the dielectric layer 142.

[0090] Some or all of the conductive elements 144 are busbars 144P, which are conductive lines that electrically connect the epitaxial source / drain regions 92P to a reference voltage, supply voltage, or the like. Advantages can be achieved by placing the busbars 144P on a back side of the device layer 120 instead of on a front side. For example, the gate density of the nanoFETs and / or the interconnect density of the interconnect structure 122 can be increased. Furthermore, the back side of the device layer 120 can accommodate wider busbars, reducing resistance and increasing the efficiency of current delivery to the nanoFETs. For example, the width of the conductive elements 144 can be at least twice the width of a first-level conductive line (e.g., conductive line 124A in Fig. 15) exhibit the intermediate connection structure 122.

[0091] The first source / drain contacts 112A and the third source / drain contacts 112C form conductive vias 148, which can be referred to as busbar vias. Each busbar via comprises a first source / drain contact 112A and a third source / drain contact 112C. The total height of the conductive vias 148 corresponds to the sum of the heights H2 (see Fig. 12B) and H3 (see Fig. 19B). The conductive vias 148 extend through the device layer 120 and connect the conductive elements of the interconnect structure 122 (e.g., metallization structures) to the conductive elements of the interconnect structure 150 (e.g., busbars 144P). The reference voltage, supply voltage, etc., can thus be electrically connected to both the epitaxial source / drain regions 92P and the interconnect structure 122 via the conductive vias 148. Connecting the busbars 144P to the interconnect structure 122 via conductive elements (e.g., the conductive vias 148) instead of semiconductor elements (e.g., the epitaxial source / drain regions 92P) can offer advantages.For example, conductive elements exhibit lower resistance than semiconductor elements, which allows for improved performance of a local interconnect between the interconnect structures 122, 150. Furthermore, the conductive vias 148 are also physically and electrically coupled to the epitaxial source / drain regions 92P where a busbar connection is desired. In this embodiment, the metal-semiconductor alloy regions 108, 138 surround and are coupled to the portions of the conductive vias 148 that extend through the epitaxial source / drain region 92P. Since the conductive vias 148 extend through the epitaxial source / drain regions 92P, voltage drops across the epitaxial material of the epitaxial source / drain regions 92P can be avoided during operation, thereby reducing the parasitic capacitance of the nanoFETs.Finally, the same conductive elements can be used to connect the epitaxial source / drain regions 92P to the busbars 144P and to create local intermediate connections between the intermediate connection structures 122, 150, which reduces the amount of conductive elements in the intermediate connection structure 150.

[0092] In Fig. 21 Remaining sections of an interconnection structure 150 are formed on a back side of the device layer 120, such as above the dielectric layer 142 and the conductive elements 144. The interconnection structure 150 can also be referred to as a back-side interconnection structure because it is formed on a back side of the device layer 120. The remaining sections of the interconnection structure 150 can be similar to the interconnection structure 122. For example, the interconnection structure 150 can comprise similar materials and be formed using similar processes as the interconnection structure 122. In particular, the interconnection structure 150 can comprise stacked layers of conductive elements 154 formed in stacked dielectric layers 152. The conductive elements 154 can be routing lines (e.g.,for routing to and from subsequently formed contact pads and external connectors). The conductive elements 154 may further include conductive vias extending into the dielectric layers 152 to provide a vertical connection between stacked layers of the conductive conductors. The interconnection structure 150 thus comprises the dielectric layers 128, 142, 152 and the conductive elements 144, 154.

[0093] In some embodiments, the conductive elements of the interconnection structure 150 can further be structured to include one or more embedded passive devices, such as resistors, capacitors, inductors, or the like, within the interconnection structure 150. The embedded passive devices can be integrated with the conductive elements 144, 154 (e.g., the busbars 144P) to provide circuits (e.g., power circuits) on the rear side of the device layer 120.

[0094] In Fig. 22 A passivation layer 160, UBMs 162, and external connectors 164 are formed over the intermediate interconnect structure 150. The passivation layer 160 can comprise polymers such as PBO, polyimide, BCB, or the like. Alternatively, the passivation layer 160 can comprise inorganic dielectrics such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or the like. The passivation layer 160 can be deposited, for example, by CVD, PVD, ALD, or the like.

[0095] The UBMs 162 are formed by the passivation layer 160 on the conductive elements 154 of the intermediate interconnect structure 150, and the external connectors 164 are formed on the UBMs 162. The UBMs 162 can comprise one or more layers of copper, nickel, gold, or the like, formed by a plating process or the like. The external connectors 164 (e.g., solder balls) are formed on the UBMs 162. Forming the external connectors 164 can involve placing solder balls on the exposed sections of the UBMs 162 and then melting the solder balls. In alternative embodiments, forming the external connectors 164 involves performing a plating step to form solder regions over the uppermost conductive element 154 and then melting the solder regions. In another embodiment, the external connectors are 164 metal connectors with substantially vertical sidewalls such as microbumps.The UBMs 162 and the external connectors 164 can be used to provide input / output connections to other electrical components, such as other device matrices, redistribution structures, printed circuit boards (PCBs), mainboards, or the like. The UBMs 162 and the external connectors 164 can also be referred to as backside input / output pads that can provide a signal, reference voltage, supply voltage, and / or ground connections to the nanoFETs of the device layer 120.

[0096] Fig. Figures 23A to 31 show different views of intermediate stages in the fabrication of semiconductor devices according to some other embodiments. In particular, the fabrication of front- and back-side interconnect structures for nano-FETs is illustrated. Fig. 23A, Fig. 24A, Fig. 25A, Fig. 26A, Fig. 27A, Fig. 28A, Fig. 29A and Fig. 30A are three-dimensional views that provide a similar three-dimensional view to Fig. Figure 1 shows two gate structures and two fins. Fig. 23B, Fig. 24B, Fig. 25B, Fig. 26B, Fig. 27B, Fig. 28B, Fig. 29B, Fig. 30B and Fig. Figure 31 are cross-sectional views taken along the reference cross-section AA in Fig. 1. Illustrate. Fig. 23A, Fig. 24A, Fig. 25A, Fig. 26A, Fig. 27A, Fig. 28A, Fig. 29A and Fig. 30A are simplified three-dimensional views and do not show all elements of the corresponding Fig. 23B, Fig. 24B, Fig. 25B, Fig. 26B, Fig. 27B, Fig. 28B, Fig. 29B and Fig. 30B. Fig. 23B, Fig. 24B, Fig. 25B, Fig. 26B, Fig. 27B, Fig. 28B, Fig. 29B, Fig. 30B and Fig. Figure 31 can apply to both n-region 50N and p-region 50P. Differences (if any) between the structures of n-region 50N and p-region 50P are described in the text accompanying each figure.

[0097] In the Fig. 23A and Fig. 23B will have a structure similar to the one referenced in Fig. 10A and Fig. 10B described.

[0098] In Fig. 24A and Fig. In 24B, one or more gate structures 100 are removed and replaced by dielectric elements 172. In some embodiments, the replaced gate structures 100 are those at the end of a memory cell, such as the gate structures 100 at the ends of the fins 54. The replaced gate structures 100 and adjacent epitaxial source / drain regions 92P are connected to busbars. The desired gate structures 100 can be removed using acceptable photolithography and etching techniques to create openings. The dielectric elements 172 are then formed in the openings. The dielectric elements 172 can be made of a dielectric such as silicon oxide, silicon nitride, or the like.The dielectric elements 172 can be formed by depositing the dielectric over the remaining gate structures 100 and subsequently planarizing the dielectric such that the upper surfaces of the dielectric elements 172 and the remaining gate structures 100 are coplanar (within the process variations). The dielectric elements 172 thus surround the nanostructures 56B that were previously surrounded by the replaced gate structures 100.

[0099] In Fig. 25A and Fig. In this embodiment, source / drain contact openings 106 are formed by the first ILD 96 and the CESL 94. In this embodiment, a first subset of source / drain contact openings 106P (e.g., those used to form busbar vias) is also formed by the dielectric elements 172, the inner spacer 84, the gate spacer 80, and the second nanostructures 56B to expose sidewalls of the epitaxial source / drain regions 92P. A second subset of source / drain contact openings 106R (e.g., those not used to form busbar vias) does not extend through the dielectric elements 172, the inner spacer 84, the gate spacer 80, or the second nanostructures 56B.

[0100] The source / drain contact orifices 106R, 106P can be formed by multiple photolithography and etching techniques. The source / drain contact orifices 106R, 106P can initially be formed in the first ILD 96 using acceptable photolithography and etching techniques, such as an etching process that is selective for the first ILD 96 (e.g., the material of the first ILD 96 etches faster than the material of CESL 94). For example, the source / drain contact orifices 106R, 106P can initially be formed by dry etching through the first ILD 96 using ammonia (NH3) and hydrogen fluoride gas (HF gas). The source / drain contact openings 106R, 106P are then extended by the CESL 94 using acceptable photolithography and etching techniques, such as an etching process that is selective for CESL 94 (e.g., the material of the CESL 94 etches faster than the material of the epitaxial source / drain regions 92).For example, the source / drain contact openings 106R, 106P can be extended through the CESL 94 by dry etching using a fluorine-based gas (e.g., C4F6) and hydrogen (H2) or oxygen (O2) gas. The source / drain contact openings 106R are then masked, for example, by forming a photoresist over them. The source / drain contact openings 106P are then extended through the dielectric elements 172, the inner spacers 84, the gate spacers 80, and the second nanostructures 56B using acceptable photolithography and etching techniques, such as an etching process that is selective for the dielectric elements 172, the inner spacers 84, the gate spacers 80, and the second nanostructures 56B (e.g.,The materials of the dielectric elements 172, the inner spacers 84, the gate spacers 80, and the second nanostructures 56B are etched faster than the material of the epitaxial source / drain regions 92. For example, the source / drain contact openings 106P can be extended through the dielectric elements 172, the inner spacers 84, the gate spacers 80, and the second nanostructures 56B by dry etching using a fluorine-based gas (e.g., C4F6) and hydrogen gas (H2 gas) or oxygen gas (O2 gas). The source / drain contact openings 106P may not extend into the fins 54, as shown by... Fig. 25A shown, or may also be formed to extend into the fins 54, as shown by Fig. 25B shown.

[0101] After formation, the source / drain contact openings 106R, 106P extend a distance D4 partially into the epitaxial source / drain regions 92, such as into the upper sections of the epitaxial source / drain regions 92. In some embodiments, the distance D4 is less than approximately half the height H1 (see Fig. 7B) of the epitaxial source / drain regions 92. Time-controlled etching processes can be used to extend the etching of the source / drain contact openings 106R, 106P, after the expansion of the source / drain contact openings 106R, 106P, to the upper portions of the epitaxial source / drain regions 92 by a desired distance D4. For example, if the etchants described above are used to etch the epitaxial source / drain regions 92, the etching can be performed for a duration in the range of approximately 10 seconds to approximately 40 seconds, which can cause the source / drain contact openings 136 to extend by a distance D4 in the range of approximately 2 nm to approximately 10 nm into the upper portions of the epitaxial source / drain regions 92P. The source / drain contact openings 106R can be formed with a width W1 that can be in the range of approximately 10 nm to approximately 30 nm.

[0102] After expansion, the source / drain contact openings 106P extend a distance D5 into the intermediate structure. In some embodiments, the distance D5 is greater than the height H1 of the epitaxial source / drain regions 92. Time-controlled etching processes can be used to etch the source / drain contact openings 106P after expansion by a desired distance D5 into the intermediate structure. For example, if the etchants described above are used to etch the dielectric elements 172, the inner spacers 84, the gate spacers 80, and the second nanostructures 56B, the etching can be carried out for a duration in the range of approximately 140 seconds to approximately 400 seconds, which can cause the source / drain contact openings 136P to extend into the intermediate structure by a distance D5 in the range of approximately 40 nm to approximately 120 nm. The upper section of the source / drain contact openings 106R (e.g.,The sections above the epitaxial source / drain regions 92P can also be extended to a width W2, which can range from approximately 10 nm to approximately 50 nm and is greater than the width W1. The lower section of the source / drain contact openings 106R (e.g., the sections adjacent to the epitaxial source / drain regions 92P) can also be formed to a width W3, which can range from approximately 10 nm to approximately 30 nm and is smaller than the width W2.

[0103] Metal-semiconductor alloy regions 108 are then formed in the source / drain contact openings 106, such as on sections of the epitaxial source / drain regions 92 that are exposed by the source / drain contact openings 106. In this embodiment, the metal-semiconductor alloy regions 108 extend along the exposed sidewalls of the epitaxial source / drain regions 92P. The metal-semiconductor alloy regions 108 can be formed in a similar manner as described with reference to Fig. 11A and Fig. 11B described.

[0104] In Fig. 26A and Fig. 26B, the first source / drain contacts 112A are formed in the source / drain contact openings 106. The first source / drain contacts 112A can be formed in a similar manner to those referred to in Fig. 12A and Fig. 12B described. In this embodiment, a substructure of the first source / drain contacts 112A extends P, such as those formed in the source / drain contact openings 106P, along the side walls and upper surfaces of the epitaxial source / drain regions 92P and are in contact with them.

[0105] After forming, the first source / drain contacts 112A have similar dimensions to the source / drain contact openings 106. The first source / drain contacts 112A extend by the distance D4 (see Fig. 25B) into the upper sections of the epitaxial source / drain regions 92 and sections of the first source / drain contacts 112A above the epitaxial source / drain regions 92 have a height in the range of approximately 2 nm to approximately 10 nm.

[0106] In Fig. 27A and Fig. 27B shows a second ILD 114 deposited above the first ILD 96, the gate electrodes 104, and the first source / drain contacts 112A. Contact openings 116 are then formed in the second ILD 114. The second ILD 114 and the contact openings 116 can be formed in a similar manner to those described with reference to Fig. 13A and Fig. 13B described.

[0107] In Fig. 28A and Fig. 28B are formed by second source / drain contacts 112B and gate contacts 118, which extend through the second ILD 114. The second source / drain contacts 112B and the gate contacts 118 can be formed in a similar manner to those relating to Fig. 14A and Fig. 14B described. As noted above, the second source / drain contacts 112B and the gate contacts 118 can be formed in the same cross-sections, which are defined by Fig. 27B and Fig. 28B are shown, or may be formed in other cross-sections, as shown by Fig. 27A and Fig. 28A shown.

[0108] In Fig. 29A and Fig. 29B, the intermediate structure can be processed in a similar way to that referred to Fig. 15, Fig. 16 to Fig. 17 described. For example, an intermediate connection structure 122 can be formed, the structure can be inverted, and the substrate 50 can be replaced with a dielectric layer 128. Source / drain contact openings 136 are then formed by the dielectric layer 128 and the fins 54. The source / drain contact openings 136 can also extend into the lower sections of the epitaxial source / drain regions 92P. The source / drain contact openings 136 can be formed in a similar manner to those described with respect to Fig. 18A and Fig. 18B described, e.g., by using a mask 134 as an etching mask. In this embodiment, the source / drain contact openings 136 are not formed by the epitaxial source / drain regions 92P, but extend only partially into the lower sections of the epitaxial source / drain regions 92P. Time-dependent etching processes can be used to extend the etching of the source / drain contact openings 136 by the desired distance D6 after the source / drain contact openings 136 have been extended to the lower sections of the epitaxial source / drain regions 92P. For example, if the etching process described in reference to Fig. 18A and Fig. Using the etching agent described in Section 18B to etch the source / drain contact openings 136, the etching can be carried out for a duration in the range of approximately 90 seconds to approximately 240 seconds, which can cause the source / drain contact openings 136 to extend by a distance D6 in the range of approximately 2 nm to approximately 10 nm into the lower portions of the epitaxial source / drain regions 92P. The source / drain contact openings 136 can be formed with a width W3, which can be in the range of approximately 10 nm to approximately 50 nm.

[0109] In Fig. 30A and Fig. 30B, metal-semiconductor alloy regions 138 are formed in the source / drain contact openings 136, such as at sections of the epitaxial source / drain regions 92P exposed by the source / drain contact openings 136. The metal-semiconductor alloy regions 138 can be formed in a similar manner as described with reference to Fig. 19A and Fig. 19B described. In one embodiment, the metal-semiconductor alloy regions 138 are curved layers that are physically coupled to the portions of the metal-semiconductor alloy regions 108 that extend along the sidewalls of the epitaxial source / drain regions 92P. Although the metal-semiconductor alloy regions 108, 138 are shown as separate regions, it should be noted that in some embodiments the metal-semiconductor alloy regions 108, 138 merge during formation, so that there is no distinguishable interface between them.

[0110] Third source / drain contacts 112C are then formed in the source / drain contact openings 136. The third source / drain contacts 112C can be formed in a similar manner to those described with reference to Fig. 19A and Fig. 19B described. In this embodiment, the third source / drain contacts 112C have sections at the first source / drain contacts 112A. P and sections extending into the lower sections of the epitaxial source / drain regions 92P. The third source / drain contacts 112C thus extend along the lower surfaces of the epitaxial source / drain regions 92P and contact them. After formation, the third source / drain contacts 112C have similar dimensions to the source / drain contact openings 136. The first source / drain contacts 112A Pand the third source / drain contacts 112C form conductive vias 148, which can be referred to as busbar vias. In this embodiment, the metal-semiconductor alloy regions 108, 138 are arranged between each conductive via 148 and each of the two surfaces, the side wall and the bottom surface, of the respective epitaxial source / drain region 92P.

[0111] In Fig. 31 Remaining sections of an intermediate connection structure 150 are formed on a rear side of the device layer 120. The remaining sections of the intermediate connection structure 150 can be formed in a similar manner to those described with reference to Fig. 20 and Fig. 21 described. The intermediate connection structure 150 comprises busbars 144P which are connected to the conductive vias 148.

[0112] A passivation layer 160, UBMs 162, and external connectors 164 are then formed above the intermediate connection structure 150. The passivation layer 160, the UBMs 162, and the external connectors 164 can be formed in a similar manner as described above. Fig. 22 described.

[0113] Fig. Figures 32A to 40 show different views of intermediate stages in the fabrication of semiconductor devices according to some other embodiments. Specifically, the fabrication of front- and back-side interconnect structures for nano-FETs is illustrated. Fig. 32A, Fig. 33A, Fig. 34A, Fig. 35A, Fig. 36A, Fig. 37A, Fig. 38A and Fig. 39A are three-dimensional views that provide a similar three-dimensional view to Fig. Figure 1 shows two gate structures and two fins. Fig. 32B, Fig. 33B, Fig. 34B, Fig. 35B, Fig. 36B, Fig. 37B, Fig. 38B, Fig. 39B and Fig. 40 are cross-sectional views taken along the reference cross-section AA in Fig. 1. Illustrate. Fig. 32A, Fig. 33A, Fig. 34A, Fig. 35A, Fig. 36A, Fig. 37A, Fig. 38A and Fig. 39A are simplified three-dimensional views and do not show all elements of the corresponding Fig. 32B, Fig. 33B, Fig. 34B, Fig. 35B, Fig. 36B, Fig. 37B, Fig. 38B and Fig. 39B. Fig. 32B, Fig. 33B, Fig. 34B, Fig. 35B, Fig. 36B, Fig. 37B, Fig. 38B, Fig. 39B and Fig. The following 40 values ​​can apply to the n-region 50N and the p-region 50P. Differences (if any) between the structures of the n-region 50N and the p-region 50P are described in the text accompanying each figure.

[0114] In the Fig. 32A and Fig. 32B will have a structure similar to the one referenced in Fig. 24A and Fig. The source / drain contact openings 106 described in Section 24B are then formed by the first ILD 96 and the CESL 94. The source / drain contact openings 106 can initially be formed in the first ILD 96 using acceptable photolithography and etching techniques, such as an etching process that is selective for the first ILD 96 (e.g., the material of the first ILD 96 etches faster than the material of the CESL 94). For example, the source / drain contact openings 106 can initially be formed by dry etching through the first ILD 96 using ammonia (NH3) and hydrogen fluoride gas (HF gas). The source / drain contact openings 106 are then extended by the CESL 94 using acceptable photolithography and etching techniques, such as an etching process that is selective for CESL 94 (e.g., the material of the CESL 94 etches faster than the material of the epitaxial source / drain regions 92).For example, the source / drain contact openings 106 can be extended through the CESL 94 by dry etching using a fluorine-based gas (e.g. C4F6) and hydrogen (H2) or oxygen (O2) gas.

[0115] Busbar openings 174 are then formed by the dielectric elements 172 and the second nanostructures 56B. The busbar via openings 174 can be formed using acceptable photolithography and etching techniques, such as an etching process that is selective for the dielectric elements 172 and the second nanostructures 56B (e.g., the materials of the dielectric elements 172 and the second nanostructures 56B etch faster than the material of the epitaxial source / drain regions 92). For example, the busbar via openings 174 can be extended through the dielectric elements 172 and the second nanostructures 56B by dry etching using a fluorine-based gas (e.g., C4F6) and hydrogen gas (H2 gas) or oxygen gas (O2 gas). The busbar contact openings 174 may not extend into the fins 54, as shown by Fig. 32A shown, or may also be formed to extend into the fins 54, as shown by Fig. 32B shown.

[0116] After forming, the busbar via openings 174 extend a distance D7 into the intermediate structure. In some embodiments, the distance D7 is greater than the height H1 (see Fig. 7B) of the epitaxial source / drain regions 92. Time-controlled etching processes can be used to etch the busbar vias 174 after the busbar vias 174 have been extended by a desired distance D7 into the intermediate structure. For example, if the etchants described above are used to etch the dielectric elements 172 and the second nanostructures 56B, the etching can be performed for a duration in the range of approximately 140 seconds to approximately 400 seconds, which can cause the source / drain vias 136 to extend by a distance D7 in the range of approximately 40 nm to approximately 120 nm into the intermediate structure. The busbar vias 174 can be formed with a width W4, which can be in the range of approximately 10 nm to approximately 30 nm.

[0117] In Fig. 33A and Fig. 33B, the first source / drain contacts 112A are formed in the source / drain contact openings 106. The first source / drain contacts 112A can be formed in a similar manner to those referred to in Fig. 12A and Fig. 12B described. Furthermore, busbar contacts 176 are formed in the busbar via openings 174. The busbar contacts 176 can be formed in a similar manner to the first source / drain contacts 112A. The first source / drain contacts 112A and the busbar contacts 176 can be formed in the same process or in different processes. The busbar contacts 176 extend along, but are not physically separated from, the sidewalls of the epitaxial source / drain regions 92P. The busbar contacts 176 extend through the dielectric elements 172 and the second nanostructures 56B.

[0118] In Fig. 34A and Fig. 34B shows a second ILD 114 deposited above the first ILD 96, the gate electrodes 104, the first source / drain contacts 112A, and the busbar contacts 176. Contact openings 116 are then formed in the second ILD 114. The second ILD 114 and the contact openings 116 can be formed in a similar manner to those described with reference to Fig. 13A and Fig. 13B described. In this embodiment, a third substructure of the contact openings 116C exposes the busbar contacts 176 and the respective adjacent first source / drain contacts 112A.

[0119] In Fig. 35A and Fig. 35B are formed by second source / drain contacts 112B, gate contacts 118, and split contacts 178, extending through the second ILD 114. The second source / drain contacts 112B and the gate contacts 118 can be formed in a similar manner to those relating to Fig. 14A and Fig. 14B described. The split contacts 178 can be formed in a similar manner to the second source / drain contacts 112B and the gate contacts 118. The split contacts 178 are each connected to a busbar contact 176 and a respective adjacent first source / drain contact 112A.

[0120] In Fig. 36A and Fig. 36B, the split contacts 178 are cut out, forming openings 180 over the split contacts 178. The remaining sections of the split contacts 178 can be considered conductive traces. The split contacts 178 can be cut out using acceptable photolithography and etching techniques, such as a back-etching process that is selective for the split contacts 178 (e.g., the material of the split contacts 178 etches faster than the material of the second ILD 114).

[0121] In Fig. 37A and Fig. 37B Dielectric plugs 182 are formed in the openings 180. The dielectric plugs 182 can be formed from a material belonging to the same group of candidate materials as the dielectric elements 172 and can be deposited using a method selected from the same group of candidate methods for depositing the dielectric elements 172. The dielectric elements 172 and the dielectric plugs 182 can be formed from the same material or comprise different materials. Forming the dielectric plugs 182 allows for the electrical insulation of the split contacts 178 and their protection during subsequent machining.

[0122] In Fig. 38A and Fig. 38B, the intermediate structure can be processed in a similar way to that with reference to Fig. 15, Fig. 16 to Fig. 17 described. For example, an intermediate connection structure 122 can be formed, the structure can be inverted, and the substrate 50 can be replaced with a dielectric layer 128. Source / drain contact openings 136 are then formed by the dielectric layer 128 and the fins 54. The source / drain contact openings 136 can also extend into the lower sections of the epitaxial source / drain regions 92P. The source / drain contact openings 136 can be formed in a similar manner to those described with respect to Fig. 18A and Fig. 18B described, e.g., by using a mask 134 as an etching mask. In this embodiment, the source / drain contact openings 136 are not formed by the epitaxial source / drain regions 92P, but extend only partially into the lower sections of the epitaxial source / drain regions 92P. Time-dependent etching processes can be used to extend the etching of the source / drain contact openings 136 by the desired distance D8 after the source / drain contact openings 136 have been extended to the lower sections of the epitaxial source / drain regions 92P. For example, if the etching process described in reference to Fig. 18A and Fig. Using the etching agent described in Section 18B to etch the source / drain contact openings 136, the etching can be carried out for a duration in the range of approximately 90 seconds to approximately 240 seconds, which can cause the source / drain contact openings 136 to extend by a distance D8 in the range of approximately 2 nm to approximately 10 nm into the lower portions of the epitaxial source / drain regions 92P. The source / drain contact openings 136 can be formed with a width W5, which can be in the range of approximately 10 nm to approximately 50 nm.

[0123] In Fig. 39A and Fig. 39B Metal-semiconductor alloy regions 138 are formed in the source / drain contact openings 136, such as at sections of the epitaxial source / drain regions 92P exposed by the source / drain contact openings 136. The metal-semiconductor alloy regions 138 can be formed in a similar manner as described with reference to Fig. 19A and Fig. 19B described. In one embodiment, the metal-semiconductor alloy regions 138 are curved layers. Although the metal-semiconductor alloy regions 108, 138 are shown as separate regions, it should be noted that in some embodiments the metal-semiconductor alloy regions 108, 138 merge during formation, so that there is no distinguishable interface between them.

[0124] Third source / drain contacts 112C are then formed in the source / drain contact openings 136. The third source / drain contacts 112C can be formed in a similar manner to those described with reference to Fig. 19A and Fig. as described in Figure 19B. In this embodiment, the third source / drain contacts 112C have sections at the busbar contacts 176 and sections extending into the lower sections of the epitaxial source / drain regions 92P. The third source / drain contacts 112C thus extend along the lower surfaces of the epitaxial source / drain regions 92P and contact them. After forming, the third source / drain contacts 112C have similar dimensions to the source / drain contact openings 136. The first source / drain contacts 112A and the busbar contacts 176 form conductive vias 148, which can be referred to as busbar vias.

[0125] In Fig. 40 Remaining sections of an intermediate connection structure 150 are formed on a rear side of the device layer 120. The remaining sections of the intermediate connection structure 150 can be formed in a similar manner to those described with reference to Fig. 20 and Fig. 21 described. The intermediate connection structure 150 comprises busbars 144P which are connected to the conductive vias 148.

[0126] A passivation layer 160, UBMs 162, and external connectors 164 are then formed above the intermediate connection structure 150. The passivation layer 160, the UBMs 162, and the external connectors 164 can be formed in a similar manner as described above. Fig. 22 described.

[0127] Embodiments can offer advantages. Placing the busbars 144P on the back side of the device layer 120 instead of on the front side can allow for an increase in the gate density and / or interconnect density of the resulting semiconductor devices. Furthermore, the back side of the device layer 120 can accommodate wider busbars, reduce resistance, and increase the efficiency of current delivery to the semiconductor devices. Connecting the busbars 144P to the interconnect structure 122 by conductive elements (e.g., the conductive vias 148) instead of semiconductor elements (e.g., the epitaxial source / drain regions 92P) can also offer advantages. In particular, the performance of the local interconnect between the interconnect structures 122 and 150 can be improved. Finally, the same conductive elements (e.g.,the conductive vias 148) are used to connect the epitaxial source / drain regions 92P to the busbars 144P and to create local intermediate connections between the intermediate connection structures 122, 150, which reduces the amount of conductive elements in the intermediate connection structure 150.

[0128] In one embodiment, a device comprises: a nanostructure; a gate structure surrounding the nanostructure; an epitaxial source / drain region adjacent to the gate structure; a first dielectric layer over an upper section of the epitaxial source / drain region; a second dielectric layer beneath a lower section of the epitaxial source / drain region; and a busbar via extending through the first dielectric layer and the second dielectric layer, wherein the busbar via is physically and electrically coupled to the upper and lower sections of the epitaxial source / drain region.

[0129] In some embodiments of the device, the busbar via extends through the epitaxial source / drain region. In some embodiments of the device, the busbar via comprises: a first source / drain contact extending through the first dielectric layer and into an upper portion of the epitaxial source / drain region; and a second source / drain contact extending through the second dielectric layer and into a lower portion of the epitaxial source / drain region, the second source / drain contact being physically and electrically coupled to the first source / drain contact. In some embodiments, the device further comprises: a metal-semiconductor alloy region surrounding portions of the busbar via extending through the epitaxial source / drain region.In some embodiments of the device, the busbar via extends along a side wall of the epitaxial source / drain region. In some embodiments of the device, the device comprises: a first source / drain contact extending through the first dielectric layer, wherein the first source / drain contact extends along the side wall and an upper surface of the epitaxial source / drain region; and a second source / drain contact extending through the second dielectric layer, wherein the second source / drain contact extends along a lower surface of the epitaxial source / drain region. In some embodiments, the device further comprises: a metal-semiconductor alloy region arranged between the busbar via and each of the upper surface, the side wall, and the lower surface of the epitaxial source / drain region.

[0130] In one embodiment, a device comprises: a first interconnection structure comprising metallization structures; a second interconnection structure comprising a busbar; a device layer between the first interconnection structure and the second interconnection structure, wherein the device layer comprises a first transistor, and the first transistor comprises an epitaxial source / drain region; and a conductive via extending through the device layer, wherein the conductive via connects the busbar to the metallization structures and contacts the epitaxial source / drain region.

[0131] In some embodiments of the device, the conductive via extends through the epitaxial source / drain region. In some embodiments of the device, the conductive via extends along and contacts a side wall, a top face, and a bottom face of the epitaxial source / drain region. In some embodiments of the device, the conductive via extends along and contacts a bottom face of the epitaxial source / drain region, and extends along and is physically separated from a side wall of the epitaxial source / drain region.

[0132] In one embodiment, a method comprises: forming a nanostructure over a fin; forming a gate structure around the nanostructure; building an epitaxial source / drain region adjacent to the gate structure; depositing a first dielectric layer on the epitaxial source / drain region; forming a first contact through the first dielectric layer to contact the epitaxial source / drain region; and forming a second contact through the fin to contact the epitaxial source / drain region and the first contact.

[0133] In some embodiments of the method, forming the first contact comprises: forming a first opening extending through the first dielectric layer and into an upper portion of the epitaxial source / drain region; and forming the first contact in the first opening. In some embodiments of the method, forming the second contact comprises: forming a second opening extending through the fin and into a lower portion of the epitaxial source / drain region, the second opening exposing the first contact; and forming the second contact in the second opening. In some embodiments of the method, forming the first opening comprises: etching the first dielectric layer using a dry etching process with ammonia and hydrogen fluoride gas; and etching the epitaxial source / drain region using a dry etching process with chlorine gas, hydrogen bromide gas, and oxygen gas.In some embodiments of the method, the first opening extends a first distance into the upper portion of the epitaxial source / drain region, and the second opening extends a second distance into the lower portion of the epitaxial source / drain region, the first and second distances each being in the range of 15 nm to 60 nm. In some embodiments, the method further comprises: replacing the gate structure with a second dielectric layer; forming a first opening extending through the first and second dielectric layers, the first opening exposing a sidewall of the epitaxial source / drain region; and forming the first contact in the first opening.In some embodiments of the method, forming the second contact comprises: forming a second opening extending through the fin, the second opening exposing the first contact and the epitaxial source / drain region; and forming the second contact within the second opening. In some embodiments of the method, forming the first opening comprises: etching the first dielectric layer using a dry etch with ammonia and hydrogen fluoride gas; and etching the second dielectric layer using a dry etch with a fluorine-based gas and hydrogen or oxygen gas. In some embodiments of the method, the depth of the first opening is in the range of 40 nm to 120 nm.

Claims

[1] Device comprising: a nanostructure (56); a gate structure (100) surrounding the nanostructure; an epitaxial source / drain region (92) adjacent to the gate structure; a first dielectric layer (96) over an upper section of the epitaxial source / drain region (92); a second dielectric layer (114) under a lower section of the epitaxial source / drain region; a busbar via (148) extending through the first dielectric layer (96) and the second dielectric layer (114), wherein the busbar via (148) is physically and electrically coupled to the upper and lower sections of the epitaxial source / drain region, and wherein the busbar via (148) extends along a side wall of the epitaxial source / drain region (92). [2] Device according to claim 1, wherein the busbar via (148) comprises: a first source / drain contact (112C) extending through the first dielectric layer, wherein the first source / drain contact extends along the side wall and an upper surface of the epitaxial source / drain region; and a second source / drain contact (176) extending through the second dielectric layer, wherein the second source / drain contact extends along a lower surface of the epitaxial source / drain region. [3] Device according to claim 2, further comprising: a metal semiconductor alloy region (108) located between the busbar via (148) and each of the top surface, side wall and bottom surface of the epitaxial source / drain region (92). [4] Device comprising: a first intermediate compound structure (150), comprising metallization structures (124); a second intermediate connection structure (122), comprising a power rail (144); a device layer (120) between the first interconnection structure and the second interconnection structure, wherein the device layer (120) comprises a first transistor, and the first transistor comprises an epitaxial source / drain region (92); a conductive via (148) extending through the device layer (120), wherein the conductive via (148) connects the busbar (144) to the metallization structures (124) and the conductive via (148) contacts the epitaxial source / drain region (92), and wherein the conductive through-hole (148) extends along and contacts a lower surface of the epitaxial source / drain region (92), and extends along a side wall of the epitaxial source / drain region (92) and is physically separated from it. [5] Device according to claim 4, wherein the conductive via (148) extends along and contacts a lower surface of the epitaxial source / drain region (92), and extends along a side wall of the epitaxial source / drain region (92) and is physically separated from it. [6] Procedure, comprehensive: Forming a nanostructure (56) over a fin (54); Forming a gate structure (100) around the nanostructure; Establish an epitaxial source / drain region (92) adjacent to the gate structure; Deposition of a first dielectric layer (96) at the epitaxial source / drain region (92); Forming an initial contact through the first dielectric layer (112A) to contact the epitaxial source / drain region (92); Forming a second contact (112C) through the fin (54) to contact the epitaxial source / drain region (92) and the first contact (112A), further comprising: Replacing the gate structure (100) with a second dielectric layer (114); Forming a first opening (106) extending through the first dielectric layer (96) and the second dielectric layer (114), the first opening exposing a side wall of the epitaxial source / drain region (92); Formation of first contact (112A) in the first opening; and Forming a second opening (136) extending through the fin (54), the second opening exposing the first contact (112A) and the epitaxial source / drain region (92); and Formation of the second contact (112C) in the second opening. [7] Method of claim 6, comprising forming the first opening (106) Etching of the first dielectric layer (96) using a dry etching process with ammonia and hydrogen fluoride gas; and Etching of the second dielectric layer (114) by dry etching using a fluorine-based gas and hydrogen or oxygen gas. [8] Method according to claim 6, wherein a depth (H2) of the first opening (106) is in a range of 40 nm to 120 nm.

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