Semiconductor packages with electrical redistribution layers of different thicknesses and methods for their production

Abstract

Semiconductor package, comprehensive: a non-power chip (2) comprising a first electrical contact (4) located at a first main surface of the non-power chip (2); a power chip (8) comprising a second electrical contact (10) located at a second main surface of the power chip (8); a first electrical redistribution layer (14), wherein the first electrical redistribution layer (14) is configured to provide electrical coupling between the first electrical contact (4) and a first external electrical contact (16) of the semiconductor package; and a second electrical redistribution layer (18), wherein the second electrical redistribution layer (18) is designed to provide electrical coupling between the second electrical contact (10) and a second external electrical contact (20) of the semiconductor package, wherein the second electrical redistribution layer (18) comprises a connecting conductor (50) of a conductor frame (48), a base (54) of a structured metal sheet (52), a conductive column (70), wherein, when measured in a first direction perpendicular to at least one of the first principal surfaces or the second principal surface, a maximum thickness of at least one section of the first electrical redistribution layer (14) is less than a maximum thickness of the second electrical redistribution layer (18), and wherein the second main surface faces the second external electrical contact (20).

Description

Technical area

[0001] This disclosure relates to semiconductor packages with electrical redistribution layers of different thicknesses. Furthermore, this disclosure relates to methods for manufacturing such semiconductor packages. background

[0002] Semiconductor packages can contain various types of semiconductor chips, such as logic chips and power chips. Techniques for integrating different types of semiconductor chips into a single package may need to consider the specific characteristics of each chip type. For example, logic chips may require small contacts, short connections, and low currents, while power chips may require thick metals for high currents and a small number of connections. Semiconductor package manufacturers are constantly striving to improve their products and manufacturing processes. It may be desirable to develop semiconductor packages that address the aforementioned chip requirements, thereby providing improved electrical and thermal performance compared to standard semiconductor packages. Furthermore, it may be desirable to provide efficient manufacturing processes for such semiconductor packages.

[0003] Document US 2018 / 0130732A1 relates to an electronic package with a multi-thickness conductive layer and a method for its fabrication. Document US 2002 / 0027276A1 relates to a circuit arrangement and a method for its fabrication. Document US 2018 / 0130783A1 relates to an electronic package with a multi-layer conductive layer and an associated fabrication method. Brief description

[0004] One aspect of the present disclosure relates to a semiconductor package. The semiconductor package comprises a non-power chip, which includes a first electrical contact located at a first major surface of the non-power chip. The semiconductor package further comprises a power chip, which includes a second electrical contact located at a second major surface of the power chip. The semiconductor package further comprises a first electrical redistribution layer, wherein the first electrical redistribution layer is configured to provide electrical coupling between the first electrical contact and a first external electrical contact of the semiconductor package.The semiconductor package further comprises a second electrical redistribution layer, the second electrical redistribution layer being designed to provide electrical coupling between the second electrical contact and a second external electrical contact of the semiconductor package. The second electrical redistribution layer comprises a terminal conductor of a conductor frame, a base of a structured metal sheet, or a conductive column. When measured in a first direction perpendicular to at least one of the first principal surfaces or the second principal surface, the maximum thickness of at least one section of the first electrical redistribution layer is less than the maximum thickness of the second electrical redistribution layer. The second principal surface faces the second external electrical contact.

[0005] One aspect of the present disclosure relates to a method for fabricating a semiconductor package. The method comprises providing a non-power chip comprising a first electrical contact located at a first major surface of the non-power chip. The method further comprises providing a power chip comprising a second electrical contact located at a second major surface of the power chip. The method further comprises forming a first electrical redistribution layer, wherein the first electrical redistribution layer is configured to provide electrical coupling between the first electrical contact and a first external electrical contact of the semiconductor package.The method further comprises forming a second electrical redistribution layer, wherein the second electrical redistribution layer is configured to provide electrical coupling between the second electrical contact and a second external electrical contact of the semiconductor package. When measured in a first direction perpendicular to at least one of the first principal surfaces or the second principal surface, the maximum thickness of at least one section of the first electrical redistribution layer is less than the maximum thickness of the second electrical redistribution layer.Provisioning the non-power chip and provisioning the power chip includes: providing a support, arranging the non-power chip and the power chip over the support, encapsulating the non-power chip and the power chip in an encapsulation material, and removing the support, wherein the first major surface, the second major surface and a major surface of the encapsulation material form a common planar surface.

[0006] One aspect of the present disclosure relates to a method for fabricating a semiconductor package. The method comprises providing a non-power chip comprising a first electrical contact located at a first major surface of the non-power chip. The method further comprises providing a power chip comprising a second electrical contact located at a second major surface of the power chip. The method further comprises forming a first electrical redistribution layer, wherein the first electrical redistribution layer is configured to provide electrical coupling between the first electrical contact and a first external electrical contact of the semiconductor package.The method further comprises forming a second electrical redistribution layer, wherein the second electrical redistribution layer is configured to provide electrical coupling between the second electrical contact and a second external electrical contact of the semiconductor package. When measured in a first direction perpendicular to at least one of the first principal surfaces or the second principal surface, the maximum thickness of at least one section of the first electrical redistribution layer is less than the maximum thickness of the second electrical redistribution layer. The method further comprises providing a metal sheet with a first principal surface and a second principal surface opposite the first principal surface, wherein forming the second electrical redistribution layer includes subtractive structuring of the first principal surface of the metal sheet.

[0007] One aspect of the present disclosure relates to a method for fabricating a semiconductor package. The method comprises providing a non-power chip comprising a first electrical contact located at a first major surface of the non-power chip. The method further comprises providing a power chip comprising a second electrical contact located at a second major surface of the power chip. The method further comprises forming a first electrical redistribution layer, wherein the first electrical redistribution layer is configured to provide electrical coupling between the first electrical contact and a first external electrical contact of the semiconductor package.The method further comprises forming a second electrical redistribution layer, wherein the second electrical redistribution layer is configured to provide electrical coupling between the second electrical contact and a second external electrical contact of the semiconductor package. When measured in a first direction perpendicular to at least one of the first main surfaces or the second main surfaces, the maximum thickness of at least one section of the first electrical redistribution layer is less than the maximum thickness of the second electrical redistribution layer. The method further comprises providing a support comprising a metal coating, wherein the formation of the first electrical redistribution layer and the second electrical redistribution layer includes subtractive structuring of the metal coating.Forming the second electrical redistribution layer involves arranging electrically conductive columns above the subtractively structured metal coating. Brief description of the drawings

[0008] The accompanying drawings serve to further understand aspects. The drawings illustrate aspects and, together with the description, serve to explain the principles of aspects. Other aspects and many of the intended benefits of aspects are easily recognized when they are better understood by referring to the following detailed description. The elements of the drawings are not necessarily to scale with each other. Identical reference symbols may denote corresponding similar parts. Fig. Figure 1 schematically illustrates a cross-sectional side view of a semiconductor package 100 according to the disclosure. Fig. Figure 2 illustrates a flowchart of a process for manufacturing a semiconductor package according to the disclosure. Fig. 3 includes the Fig. Figures 3A to 3J, which schematically illustrate a cross-sectional side view of a method for manufacturing a semiconductor package 300 according to the disclosure. Fig. 4 includes the Fig. Figures 4A to 4E, which schematically illustrate a cross-sectional side view of a method for manufacturing a semiconductor package 400 according to the disclosure. Fig. 5 includes the Fig. Figures 5A to 5E, which schematically illustrate a cross-sectional side view of a method for manufacturing a semiconductor package 500 according to the disclosure. Fig. 6 includes the Fig. Figures 6A to 6F schematically illustrate a cross-sectional side view of a method for manufacturing a semiconductor package 600 according to the disclosure. Detailed description

[0009] The following detailed description refers to the accompanying drawings, which illustrate certain aspects in which the disclosure can be realized. In this context, directional terminology such as "above," "below," "front," "back," etc., may be used with reference to the orientation of the described figures. Since components of the described devices can be positioned in a number of different orientations, the directional terminology serves only for illustration and is in no way restrictive. Other aspects may be used, and structural or logical modifications may be made, without departing from the concept of the present disclosure.

[0010] The semiconductor package 100 of Fig. Section 1 is presented in a general manner to qualitatively describe aspects of the disclosure. Semiconductor package 100 may have further aspects which are not shown for the sake of simplicity. For example, semiconductor package 100 may be extended to include any of the aspects described in connection with other semiconductor packages and methods according to the disclosure.

[0011] The semiconductor package 100 can include a non-power chip 2 with a first electrical contact 4 located at a first primary surface 6 of the non-power chip 2, and a power chip 8 with a second electrical contact 10 located at a second primary surface 12 of the power chip 8. The semiconductor package 100 can further include a first electrical redistribution layer 14 designed to provide electrical coupling between the first electrical contact 4 of the non-power chip 2 and a first external electrical contact 16 of the semiconductor package 100, and a second electrical redistribution layer 18 designed to provide electrical coupling between the second electrical contact 10 of the power chip 8 and a second external electrical contact 20 of the semiconductor package 100.When considered in a first direction perpendicular to at least one of the first main surface 6 or the second main surface 12 (e.g. in the z-direction), a maximum thickness t1 of at least one section of the first electrical redistribution layer 14 can be smaller than a maximum thickness t2 of the second electrical redistribution layer 18.

[0012] It is noted that in this description the terms "chip", "semiconductor chip", "die", and "semiconductor die" may be used interchangeably. In general, the semiconductor chips described herein may be made from an elemental semiconductor material (e.g., Si), a wide-bandgap semiconductor material, or a compound semiconductor material (e.g., SiC, GaN, SiGe, GaAs).

[0013] The power chip 8 can contain a power semiconductor component. Power chips can be used in any type of power application, such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), half-bridge circuits, power modules including a gate driver, etc. For example, power chips can contain or be part of a power device such as a power MOSFET, a low-voltage (LV) power MOSFET, a power IGBT (Insulated Gate Bipolar Transistor), a power diode, a superjunction power MOSFET, etc. In one example, a power semiconductor component can be used as a switch or rectifier in power electronics. Such a component can be called a power component or, when used in an integrated circuit, an integrated power circuit. A power semiconductor element can, for example, have a supply voltage of more than approximately 20V.Power chips may require thick metal components (e.g., clips) to transmit high currents, a small number of interconnects, good insulation properties, and thermal treatment. Often, electrical contacts on power chips can be made via electrically conductive clips.

[0014] The non-power chip 2 can be any type of semiconductor chip that cannot be considered a power chip. For example, the non-power chip 2 can contain at least one sensor chip, one logic chip, one memory chip, etc. A sensor chip can be designed to detect physical variables, such as pressure, temperature, humidity, accelerations, etc. For example, a sensor chip could be a MEMS (Micro-Electro-Mechanical System) chip, which contains a MEMS structure that may be integrated into the chip. A logic chip can be designed to process electrical signals provided by other electronic components of the sensor package 100. The logic chip could, for example, contain an ASIC (Application-Specific Integrated Circuit). Additionally or alternatively, a logic chip can be designed to control and / or drive other electronic components of the semiconductor package 100.In one example, a logic chip can be designed to control and / or drive integrated circuits of the power chip 8.

[0015] The maximum thickness t1 of the first electrical redistribution layer 14 can be in a range of approximately 2 micrometers to approximately 40 micrometers, more precisely from approximately 2 micrometers to approximately 30 micrometers, more precisely from approximately 2 micrometers to approximately 20 micrometers, and even more precisely from approximately 2 micrometers to approximately 10 micrometers. The maximum thickness t2 of the second electrical redistribution layer 18 can be in a range of approximately 150 micrometers to approximately 2000 micrometers, more precisely from approximately 150 micrometers to approximately 1500 micrometers, more precisely from approximately 150 micrometers to approximately 1000 micrometers, and even more precisely from approximately 150 micrometers to approximately 500 micrometers.

[0016] The external electrical contacts 16 and 20 can be arranged on one or more peripheral surfaces of the semiconductor package 100. In the example of the Fig. 1. The first external electrical contact 16 and the second external electrical contact 20 can both be located on the same peripheral surface of the semiconductor package 100. One or more of the external electrical contacts 16 and 20 can be designed to couple the semiconductor package 100 electrically and mechanically to an external component, such as a printed circuit board (not shown). An external electrical contact of the semiconductor package 100 can comprise at least one solder ball, solder deposit, electrically conductive pillar, electrically conductive pad, landing pad, etc.

[0017] While the non-power chip 2 and the power chip 8 can be integrated into the same semiconductor package 100, the electrical redistribution layers 14 and 18 can differ in their thickness and other properties. As will become clearer in further examples described below, different manufacturing processes and different designs for the electrical redistribution layers 14 and 18 can accommodate the specific technical characteristics of the different types of chips 2 and 8.

[0018] The power chip 8 may require high current-carrying capacity, a good thermal path, and a bidirectional connection in the case of vertical current flow. On the other hand, the connection pitches of the power chip 8 can be relatively coarse without requiring close conductor spacing. These requirements of the power chip 8 can be met, for example, by the second electrical redistribution layer 18 with a comparatively large thickness t2. As will become clear later, these requirements can also be met, for example, by providing thick metallization blocks and a clip design for the electrical contacts (e.g., source and drain) of the power chip 8.

[0019] The non-power chip 2 may require narrow traces and tight spaces in the first electrical redistribution layer 14. Furthermore, the non-power chip 2 may require narrow pad pitches and a relatively high number of connections both within the package (e.g., between different chips) and to the outside. These requirements cannot necessarily be met with thick redistribution traces, as required for the power chip 8. The requirements of the non-power chip 2 can be addressed by providing a comparatively thin first redistribution layer 14 based on additive, semi-additive, or subtractive process technologies.

[0020] Fig. Figure 2 illustrates a flowchart of a process for manufacturing a semiconductor package according to the disclosure. The process of Fig. 2 can, for example, be used to manufacture the semiconductor package 100 of the Fig. 1. The procedure of Fig. Section 2 is described in general terms to qualitatively describe aspects of the revelation and may include further aspects. For example, the procedure of Fig. 2. expanded to include each of the aspects described in connection with other examples according to the revelation.

[0021] In 22, a non-power chip can be provided with a first electrical contact located at a first major surface of the non-power chip. In 24, a power chip can be provided with a second electrical contact located at a second major surface of the power chip. In 26, a first electrical redistribution layer can be formed, wherein the first electrical redistribution layer can be configured to provide electrical coupling between the first electrical contact and a first external electrical contact of the semiconductor package. In 28, a second electrical redistribution layer can be formed, wherein the second electrical redistribution layer can be configured to provide electrical coupling between the second electrical contact and a second external electrical contact of the semiconductor package.When measured in a first direction perpendicular to at least one of the first principal surfaces or the second principal surface, a maximum thickness of at least one section of the first electrical redistribution layer may be less than a maximum thickness of the second electrical redistribution layer.

[0022] The following Fig. The procedures described in points 3 to 6 can be considered more detailed versions of the procedure of Fig. 2 are considered. Those related to the Fig. The explanations given in points 3 to 6 can therefore also be applied to the previously described examples of Fig. 1 and Fig. 2 apply. The order of the individual procedural acts that are related to the Fig. The procedures discussed in sections 3 to 6 are exemplary and not exhaustive. The procedural steps can be interchanged if technically feasible and practical. Furthermore, it should be noted that each of the following procedures can be performed as a batch process. This means that the individual procedural steps can be carried out for any number of similar orders.

[0023] Fig. 3 includes the Fig. 3A to 3J, which show a method for manufacturing a semiconductor package 300, which is described in the Fig. 3J is shown. In the Fig. A power chip 8 can be provided at 3A. The power chip 8 can have a first electrical contact 10A and a second electrical contact 10B, which are arranged on the top side of the power chip 8, as well as a third electrical contact 10C, which is arranged on the bottom side of the power chip 8. In the example of the Fig. 3A The power chip 8 can contain or correspond to a power transistor, such as a power MOSFET. In this case, the first electrical contact 10A can be a gate contact of the power transistor, the second electrical contact 10B can be a source contact of the power transistor, and the third electrical contact 10C can be a drain contact of the power transistor. The power chip 8 can have a vertical structure. That is, the power chip 8 can be manufactured such that electrical currents can flow essentially in one direction perpendicular to the main surfaces of the power chip 8, i.e., in the z-direction. Other examples of a vertical power chip are a power HEMT, a PMOS (P-channel metal oxide semiconductor), an NMOS (N-channel metal oxide semiconductor), etc. In other examples, the power chip 8 can have a lateral structure.This means that the power chip 8 can be manufactured in such a way that electrical currents can flow essentially in the xy plane.

[0024] In the Fig. 3B The electrical contacts 10A and 10B of the power chip 8 can be electrically coupled to electrical contact elements 32A and 32B, respectively. The electrical connection can be provided by means of a connection material 34 based on at least one of soldering, sintering, diffusion soldering, reflow soldering, etc. In the example of the Fig. 3B The electrical contact elements 32A and 32B may include or correspond to electrically conductive clips, which may be made of at least one metal or metal alloy. Alternatively, the electrical contact element 32A, which is connected to the gate contact of the power chip 8, may include a wire.

[0025] In the Fig. 3C, a carrier 30 can be provided. An adhesive layer 36 can be arranged over the upper surface of the carrier 36. The adhesive layer 36 can, for example, include an adhesive film or tape, such as Revalpha tape. The power chip 8, including the electrical contact elements 32A and 32B, can be arranged on the carrier 30. Additionally, a non-power chip 2 can be arranged on the top of the carrier 30. The non-power chip 2 can have a lateral structure, i.e., operation of the non-power chip 2 can be based on a lateral current flow. The non-power chip 2 can include one or more electrical contacts 4, which can be arranged on the underside of the non-power chip 2. In the example of the Fig. 3C, the electrical contacts 4 may include at least one copper column or electrically conductive contact pad.

[0026] In the Fig. The non-power chip 2 and the power chip 8 can be encapsulated by an encapsulation material 38. The encapsulation material 38 can comprise at least one of the following: a laminate, an epoxy, a filled epoxy, a glass fiber-filled epoxy, an imide, a thermoplastic, a thermosetting polymer, a polymer mixture, etc. Various techniques can be used to encapsulate the components arranged on the carrier 30 with the encapsulation material 38, for example, at least one of the following: compression molding, injection molding, powder molding, liquid molding, map molding, laminating, etc.

[0027] In the Fig. The carrier 30 and the adhesive layer 36 can be detached and removed. The lower surfaces of the non-power chip 2, the power chip 8, and the encapsulation material 38 can be coplanar, forming a common planar surface. A dielectric material 40 can be arranged over this common planar surface. The dielectric material 40 can be structured such that the electrical contacts 4 and 10C of chips 2 and 8 are exposed by the dielectric material 40. For example, the dielectric material 40 can be structured using a photolithographic process.

[0028] In the Fig. 3F A nucleation layer 42 can be arranged over the lower surface of the arrangement, for example by sputtering. The nucleation layer 42 can, for example, contain at least one of titanium tungsten (TiW) or copper. In particular, the nucleation layer 42 can cover substantially the entire bottom surface of the arrangement. Furthermore, a structured plating resist 44 can be arranged over portions of the nucleation layer 42. In one example, the plating resist 44 can first be deposited over the entire bottom surface of the arrangement and then structured. In this process, the plating resist 44 can be partially removed, so that the nucleation layer 42 can be exposed at the positions of the electrical contacts 4 and 10.

[0029] In the Fig. 3G can arrange a metal layer 46 at the positions of the uncovered nucleus layer 44, for example, based on an electroplating technique. In one example, the metal layer 46 can consist of only a single layer of, for example, copper. In another example, the metal layer 46 can consist of several metal layers forming a metal stack. The thickness of the metal layer 46 in the z-direction can range from approximately 3 micrometers to approximately 12 micrometers, more precisely from approximately 5 micrometers to approximately 10 micrometers. The first portions of the metal layer 46 on the left side can be electrically coupled to the electrical contacts 10 of the power chip 8, while the second portions of the metal layer 46 on the right side can be electrically coupled to the electrical contacts 4 of the non-power chip 2.

[0030] In the Fig. The plating resist 44 can be dissolved and removed in 3H.

[0031] In the Fig. 3I A leadframe 48 (e.g., semi-etched) with one or more die pads and one or more leads (or pins) 50 can be electrically coupled to the first and second parts of the metal layer 46. Such an electrical connection can be made, for example, by at least one of the following processes: soldering, gluing, sintering, diffusion soldering, etc. In this context, a bonding material 34 can be formed between the leadframe 48 and the metal layer 46. It should be noted that the Fig. The number of connecting conductors shown in 3I is 50 for illustrative purposes only and may depend in particular on the specific type of semiconductor package to be manufactured.

[0032] In the example of Fig. 3I A first connecting conductor (not visible due to the chosen perspective) can be connected via the metal layer 36 and the clip 32A to the gate contact 10A of the power chip 8. Furthermore, a second connecting conductor 50B can be connected via the metal layer 36 and the clip 32B to the source contact 10B of the power chip 8, and a third connecting conductor 50C can be connected via the metal layer 36 to the drain contact 10C of the power chip 8. Additionally, a fourth connecting conductor 50D and a fifth connecting conductor 50E can each be connected to the electrical contacts 4 of the non-power chip 2.

[0033] In the Fig. 3J gaps between the connecting conductors 50 of the conductor frame 48 can be filled with an electrically insulating filler material 58, whereby a substantially planar bottom surface of the arrangement can be formed. In one example, the gaps can be filled with a molding material, which can then be sanded from its back side. In another example, the arrangement of the Fig. 3I are arranged on a carrier (not shown) with a release film (not shown) and a molding process is carried out. Afterwards, the carrier and the release film can be removed.

[0034] The procedure of Fig. 3 can correspond to a batch process. In a further step (not shown), the arrangement can be separated into several semiconductor packages 300. The semiconductor package 300 of the Fig. 3J can be considered a more detailed version of the semiconductor package 100 of the Fig. 1.

[0035] The connecting conductors 50 of the conductor frame 48 can form external electrical contacts of the semiconductor package to be manufactured. Returning to the Fig. 1. The connecting conductors can be 50 of the Fig. 3J the external electrical contacts 16 and 20 of the Fig. 1 correspond. The connecting conductors 50 and the parts of the metal layer 46 that are electrically connected to the non-power chip 2 can form a first electrical redistribution layer. The first electrical redistribution layer can be designed to carry electrical currents in the z-direction and in the xy-plane. At least one section of the first electrical redistribution layer can have a maximum thickness t1, as described in the context of the Fig. 1 explained. In the example of the Fig. 3J the section can be arranged in a base area of ​​the non-power chip 2 when viewed in the z-direction.

[0036] Similarly, the connecting conductors 50 and the parts of the metal layer 46 that are electrically connected to the power chip 8 can form a second electrical redistribution layer with a maximum thickness t2. The second electrical redistribution layer can be designed to carry electrical currents in the z-direction. In particular, the second electrical redistribution layer can be designed to carry electrical currents exclusively in the z-direction.

[0037] Fig. 4 includes the Fig. 4A to 4E, which describe a method for producing a product in the Fig. 4E illustrates the semiconductor packages 400 shown. In the Fig. 4A A metal sheet 52 with a thickness t3 can be provided. The metal sheet 52 can, for example, be made of at least one of copper or a copper alloy. The top surface of the metal sheet 52 can be subtractively structured, forming one or more pads 54 with a thickness t4. A ratio t4 / t3 can be in the range of approximately 0.5 to approximately 0.9, more precisely from approximately 0.6 to approximately 0.8. The metal sheet 52 can, for example, be structured by applying an etching technique, which may be based on an MPPL approach. Additionally, one or more landing pads 56 can be formed on the top surface of the structured metal sheet 52. The landing pads 56 can be made of a metal that includes at least one of copper, nickel, gold, etc. For example, the landing pads 56 can be formed by applying at least one of electroplating, electroless plating, inkjet printing, printing, etc.

[0038] In the Fig. 4B A non-power chip 2 and a power chip 8 can be arranged on the top surface of the subtractively structured metal sheet 52. Electrical contacts 10A to 10C of the power chip 8 can be electrically connected to the sockets 54 of the metal sheet 52 via clips 32A, 32B and a connecting material 34. The power chip 8, the clips 32A, 32B and the connecting material 34 can be similar to the same components as those used in connection with Fig. 3 are described. In addition, electrical contacts 4 of the non-power chip 2 can be mechanically and electrically connected to the landing pads 56 via a connecting material 34. This connection can be made, for example, based on a flip-chip technology and a reflow process.

[0039] In the Fig. 4C, the non-power chip 2 and the power chip 8 can be encapsulated by an encapsulation material 38. The action of the Fig. 4C can influence the action of Fig. It should be similar to 3D.

[0040] In the Fig. In 4D, the lower surface of the metal sheet 52 can be subtractively structured, forming external electrical contacts 16 and 20 of the semiconductor package to be manufactured. Since the sections of the metal sheet 52 located below the non-power chip 2 are in the action of the Fig. Since 4A may have been designed to be relatively thin, fine pitches, fine lines and fine gaps can be provided for electrical redistribution.

[0041] In the Fig. 4E gaps in the structured underside can be filled with an electrically insulating filler material 58 so that the external electrical contacts 16 and 20 can be electrically isolated from each other.

[0042] The procedure of Fig. 4 can correspond to a batch process. In a further step (not shown), the arrangement can be separated into several semiconductor packages 400. The semiconductor package 400 of the Fig. 4E can be described as a more detailed version of the semiconductor package 100. Fig. 1.

[0043] The sections of the metal sheet 52, the landing pads 56, and the connecting material 34, which are connected to the non-power chip 2, can form a first electrical redistribution layer. Similarly, the sockets 54 and the connecting material 34, which are connected to the power chip 8, can form a second electrical redistribution layer. When measured in the z-direction, the maximum thickness of the second electrical redistribution layer can be greater than the maximum thickness of the first electrical redistribution layer.

[0044] Fig. 5 includes the Fig. 5A to 5E, which describe a method for producing a [product / service] in the Fig. 5E illustrates the semiconductor packages 500 shown. In the Fig. 5A, a metal sheet 52 can be subtractively structured. The action of Fig. 5A can be the action of Fig. 4A will be similar.

[0045] The plot of Fig. 5B can be the action of Fig. 4B be at least partially similar. In contrast to the Fig. 4B The non-power chip 2 can be mechanically connected to the top surface of the structured metal sheet 52 by means of a non-conductive adhesive 60. For example, the electrical contacts 4 of the non-power chip 2 can include at least one copper pillar or electrically conductive contact pad.

[0046] In the Fig. 5C, the non-power chip 2 and the power chip 8 can be encapsulated by an encapsulation material 38. The action of the Fig. 5C can be the action of the Fig. 4C will be similar.

[0047] In the Fig. In 5D, material can be removed from the underside of the metal sheet 52. The material can be removed until the sockets 54 and the electrical contacts 4 of the non-power chip 2 are exposed. Removing the backside material of the metal sheet 52 can, for example, involve at least one grinding or etching operation.

[0048] In the Fig. 5E An electrical redistribution on the lower surface of the arrangement can be additively formed by applying an electrically conductive material 62 and a dielectric material 64. A first part of the electrically conductive material 62 can be electrically connected to the electrical contacts 4 of the non-power chip 2, and a second part of the electrically conductive material 62 can be electrically connected to the power chip 8 via the sockets 54. The dielectric material 64 can be configured to electrically insulate the different sections of the electrically conductive material 62 from each other.

[0049] The procedure of Fig. 5 can correspond to a batch process. In a further step (not shown), the arrangement can be separated into several semiconductor packages 500. The semiconductor package 500 of the Fig. 5E can be described as a more detailed version of the semiconductor package 100. Fig. 1. Similar to the previous examples, the semiconductor package 500 can have two electrical redistribution layers with different thicknesses in the z-direction.

[0050] Fig. 6 includes the Fig. 6A to 6F, which describe a method for producing a in the Fig. The semiconductor packages shown in 6F illustrate 600. In the Fig. A support 66 can be provided. The support 66 can, for example, be made of at least one aluminum or prepreg material. The support 66 can have a metal coating 68 arranged on the upper surface of the support 66. The metal coating 68 can, for example, contain at least one copper or a copper alloy. The thickness of the metal coating 68 in the z-direction can be less than about 14 micrometers, more precisely less than about 12 micrometers, and even more precisely less than about 10 micrometers.

[0051] In the Fig. 6B The metal coating 68 can be subtractively structured, for example by an etching process. The remaining parts of the metal coating 68 can later be electrically coupled to electrical contacts of a non-power chip and a power chip.

[0052] In the Fig. Electrically conductive columns 70 can be mechanically and electrically connected to one or more sections of the structured metal coating 68 by means of a bonding material 34. For example, the electrically conductive columns 70 can be attached based on at least one of the following processes: soldering, sintering, diffusion brazing, etc. The thickness of the electrically conductive columns 70 in the z-direction can be in the range of approximately 180 micrometers to approximately 220 micrometers, more precisely from approximately 190 micrometers to approximately 210 micrometers.

[0053] In the Fig. In the 6D, a power chip 8 can be attached to the top of the assembly. Similar to the Fig. 4B The electrical contacts of the power chip 8 can be electrically connected to the electrically conductive columns 70 via clips 32A, 32B and a connecting material 34. In the example of the Fig. In 6D, a gate contact 10A of the power chip 8 can be contacted with a clip 32A. In another example, the gate contact 10A can be contacted by a bond wire based on a wire bonding process.

[0054] In the Fig. 6E allows a non-power chip 2 to be attached to the top of the assembly. Similar to the Fig. 4B Several electrical contacts 4 of the non-power chip 2 can be connected to remaining parts of the structured metal coating 68. In the example of the Fig. 6E the electrical contacts 4 may include at least one of copper columns or electrically conductive contact pads.

[0055] In the Fig. 6F the non-power chip 2 and the power chip 8 can be encapsulated by an encapsulation material 38, for example similar to the Fig. 3D. The support 66 can then be removed. In the case of an aluminum support 66, the support 66 can be removed by selectively etching it to copper. After removal of the support 66, the bottom surfaces of the encapsulation material 38 and the parts of the structured metal coating 68 can form a common planar surface. In a further optional step, a passivation material (not shown) can be placed over the bottom surface of the assembly.

[0056] The procedure of Fig. 6 can correspond to a batch process. In a further step (not shown), the arrangement can be separated into several semiconductor packages 600. The semiconductor package 600 of the Fig. 6F can be described as a more detailed version of the semiconductor package 100. Fig. 1. Similar to the previous examples, the fabricated semiconductor package 600 can contain two electrical redistribution layers with different thicknesses in the z-direction. Examples

[0057] The following section explains semiconductor packages and methods for manufacturing semiconductor packages using examples. Example 1 is a semiconductor package comprising: a non-power chip having a first electrical contact located at a first major surface of the non-power chip; a power chip having a second electrical contact located at a second major surface of the power chip; a first electrical redistribution layer, wherein the first electrical redistribution layer is configured to provide electrical coupling between the first electrical contact and a first external electrical contact of the semiconductor package;and a second electrical redistribution layer, wherein the second electrical redistribution layer is designed to provide electrical coupling between the second electrical contact and a second external electrical contact of the semiconductor package, wherein, when measured in a first direction perpendicular to at least one of the first principal surfaces or the second principal surface, a maximum thickness of at least one section of the first electrical redistribution layer is less than a maximum thickness of the second electrical redistribution layer. Example 2 is a semiconductor package according to Example 1, wherein, when viewed in the first direction, the section of the first electrical redistribution layer is arranged in a base area of ​​the non-power chip. Example 3 is a semiconductor package according to Example 1 or 2, wherein the maximum thickness of the first electrical redistribution layer is in a range of 2 micrometers to 40 micrometers. Example 4 is a semiconductor package according to one of the preceding examples, wherein the maximum thickness of the second electrical redistribution layer is in a range of 150 micrometers to 2000 micrometers. Example 5 is a semiconductor package according to one of the preceding examples, wherein the non-power chip comprises at least one logic chip, one memory chip, and one sensor chip. Example 6 is a semiconductor package according to one of the preceding examples, wherein the first external electrical contact and the second external electrical contact are arranged at the same peripheral surface of the semiconductor package. Example 7 is a semiconductor package according to one of the preceding examples, wherein: at least the section of the first electrical redistribution layer is designed to carry electrical currents in a second direction parallel to the first main surface of the non-power chip, and the second electrical redistribution layer is designed to carry electrical currents in the first direction. Example 8 is a semiconductor package according to one of the preceding examples, wherein: operation of the non-power chip is based on a horizontal current flow, and operation of the power chip is based on a vertical current flow. Example 9 is a semiconductor package according to any of the preceding examples, further comprising: an encapsulation material wherein the non-power chip and the power chip are both encapsulated in the same encapsulation material. Example 10 is a method for fabricating a semiconductor package, the method comprising: providing a non-power chip comprising a first electrical contact located at a first major surface of the non-power chip; providing a power chip comprising a second electrical contact located at a second major surface of the power chip; forming a first electrical redistribution layer, the first electrical redistribution layer being configured to provide electrical coupling between the first electrical contact and a first external electrical contact of the semiconductor package;and forming a second electrical redistribution layer, wherein the second electrical redistribution layer is designed to provide electrical coupling between the second electrical contact and a second external electrical contact of the semiconductor package, wherein, when measured in a first direction perpendicular to at least one of the first principal surfaces or the second principal surface, a maximum thickness of at least one section of the first electrical redistribution layer is less than a maximum thickness of the second electrical redistribution layer. Example 11 is a method according to Example 10, wherein the provisioning of the non-power chip and the provisioning of the power chip comprise: providing a support; arranging the non-power chip and the power chip over the support; encapsulating the non-power chip and the power chip in an encapsulation material; and removing the support, wherein the first principal surface, the second principal surface and a principal surface of the encapsulation material form a common planar surface. Example 12 is a method according to Example 11, wherein forming the first electrical redistribution layer and forming the second electrical redistribution layer comprise: arranging at least one first metal layer over the common planar surface, wherein the at least one first metal layer is electrically coupled to the first electrical contact; and arranging at least one second metal layer over the common planar surface, wherein the at least one second metal layer is electrically coupled to the second electrical contact, wherein the at least one first metal layer and the at least one second metal layer are arranged simultaneously in the same process step. Example 13 is a method according to Example 12, wherein forming the first electrical redistribution layer and forming the second electrical redistribution layer further comprises: electrically coupling a conductor frame to the at least one first metal layer and to the at least one second metal layer. Example 14 is a method according to Example 10, further comprising: providing a metal sheet with a first main surface and a second main surface opposite the first main surface, wherein forming the second electrical redistribution layer comprises subtractive structuring of the first main surface of the metal sheet. Example 15 is a method according to Example 14, wherein the subtractive structuring of the first main surface of the metal sheet comprises etching the first main surface of the metal sheet. Example 16 is a method according to Example 14 or 15, further comprising: attaching the non-power chip and the power chip to the subtractively structured first main surface of the metal sheet, wherein forming the first electrical redistribution layer comprises subtractively structuring the second main surface of the metal sheet after attaching the non-power chip and the power chip. Example 17 is a method according to Example 14 or 15, further comprising: attaching the non-power chip and the power chip to the structured first major surface of the metal sheet; and removing material from the second major surface of the metal sheet, wherein forming the first electrical redistribution layer comprises additively forming the first electrical redistribution layer over the second major surface of the metal sheet after removing the material. Example 18 is a method according to Example 17, wherein the removal of the material comprises at least one of grinding or etching the second main surface. Example 19 is a method according to Example 10, further comprising: providing a support comprising a metal coating, wherein forming the first electrical redistribution layer and the second electrical redistribution layer comprises subtractive structuring of the metal coating. Example 20 is a method according to Example 19, wherein at least one of: the support comprises at least one of aluminium or a prepreg material, or the metal coating comprises copper. Example 21 is a method according to Example 19 or 20, wherein the formation of the second electrical redistribution layer comprises arranging electrically conductive columns above the subtractively structured metal coating.

[0058] As used in this description, the terms "connected," "coupled," "electrically connected," and / or "electrically coupled" do not necessarily mean that elements must be directly connected or coupled to each other. Intermediate elements may be provided between the "connected," "coupled," "electrically connected," or "electrically coupled" elements.

[0059] Furthermore, the word "over," used, for example, in reference to a material layer formed or arranged "over" a surface of an object, may be used herein to mean that the material layer may be arranged (e.g., formed, deposited, etc.) "directly on," for example, in direct contact with the implied surface. The word "over," used, for example, in reference to a material layer formed or arranged "over" a surface, may also be used herein to mean that the material layer may be arranged (e.g., formed, deposited, etc.) "indirectly" on the implied surface, with, for example, one or more additional layers arranged between the implied surface and the material layer.

[0060] Where the terms “having”, “containing”, “including”, “with”, or variations thereof are used either in the detailed description or in the claims, these terms are to be understood in a similarly comprehensive manner as the term “comprising”. That is to say, as used herein, the terms “having”, “containing”, “including”, “with”, “comprising”, and the like are open terms that indicate the presence of the specified elements or features but do not exclude additional elements or features. The articles “a”, “an”, and “the” include both the plural and the singular unless the context clearly indicates otherwise.

[0061] Furthermore, the word "exemplary" is used herein to mean that it serves as an example, case, or illustration. Any aspect or design described herein as "exemplary" is not necessarily to be understood as advantageous over other aspects or designs. Rather, the use of the word "exemplary" is intended to illustrate concepts in a concrete way. As used in this application, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or." That is to say, unless otherwise stated or evident from the context, "X uses A or B" means any of the natural, inclusive permutations. That is to say, if X uses A; X uses B; or X uses both A and B, then the condition "X uses A or B" is satisfied in each of the foregoing cases.Furthermore, the articles “a” and “an”, as used in this application and the attached claims, can generally be interpreted as meaning “one or more”, unless otherwise specified or it is clear from the context that they refer to a singular. Likewise, “at least one of A and B” or the like generally means A or B or both A and B.

[0062] Devices and methods for manufacturing devices are described herein. Notes made in connection with a described device may also apply to a corresponding method, and vice versa. For example, if a particular component of a device is described, a corresponding method for manufacturing the device may include an action for providing the component in a suitable manner, even if such an action is not explicitly described or illustrated in the figures.

[0063] Although the disclosure has been shown and described with respect to one or more implementations, equivalent changes and modifications will occur to other skilled persons at least in part based on reading and understanding this description and the accompanying drawings. In particular, with regard to the various functions performed by the components described above (e.g., elements, resources, etc.), the terms used to describe such components, unless otherwise specified, are intended to correspond to any component that performs the stated function of the described component (e.g., that is functionally equivalent), even if it is not structurally equivalent to the disclosed structure that performs the function in the exemplary implementations of the disclosure shown herein.Furthermore, although a particular feature of the disclosure may have been disclosed in respect of only one of several implementations, such a feature may be combined with one or more other features of the other implementations, as may be desired and advantageous for a given or particular application.

Claims

[1] Semiconductor package comprising: a non-power chip (2) comprising a first electrical contact (4) arranged at a first main surface of the non-power chip (2); a power chip (8) comprising a second electrical contact (10) arranged at a second main surface of the power chip (8); a first electrical redistribution layer (14), wherein the first electrical redistribution layer (14) is configured to provide an electrical coupling between the first electrical contact (4) and a first external electrical contact (16) of the semiconductor package; and a second electrical redistribution layer (18), wherein the second electrical redistribution layer (18) is configured to provide an electrical coupling between the second electrical contact (10) and a second external electrical contact (20) of the semiconductor package, wherein the second electrical redistribution layer (18) comprises one of a terminal conductor (50) of a lead frame (48), a base (54) of a structured metal sheet (52), a conductive column (70), wherein, when measured in a first direction perpendicular to at least one of the first main surface or the second main surface, a maximum thickness of at least a portion of the first electrical redistribution layer (14) is less than a maximum thickness of the second electrical redistribution layer (18), and wherein the second main surface faces the second external electrical contact (20). [2] The semiconductor package of claim 1, wherein, when viewed in the first direction, the portion of the first electrical redistribution layer (14) is disposed in a footprint of the non-power chip (2). [3] A semiconductor package according to claim 1 or 2, wherein the maximum thickness of the first electrical redistribution layer (14) is in a range of 2 micrometers to 40 micrometers. [4] Semiconductor package according to one of the preceding claims, wherein the maximum thickness of the second electrical redistribution layer (18) is in a range of 150 micrometers to 2000 micrometers. [5] Semiconductor package according to one of the preceding claims, wherein the non-power chip (2) comprises at least one of a logic chip, a memory chip, a sensor chip. [6] Semiconductor package according to one of the preceding claims, wherein the first external electrical contact (16) and the second external electrical contact (20) are arranged at a same peripheral surface of the semiconductor package. [7] Semiconductor package according to one of the preceding claims, wherein: at least the portion of the first electrical redistribution layer (14) is designed to carry electrical currents in a second direction parallel to the first main surface of the non-power chip (2), and the second electrical redistribution layer (18) is designed to carry electrical currents in the first direction. [8] Semiconductor package according to one of the preceding claims, wherein: an operation of the non-power chip (2) is based on a horizontal current flow, and an operation of the power chip (8) is based on a vertical current flow. [9] Semiconductor package according to one of the preceding claims, further comprising: an encapsulation material (38), wherein the non-power chip (2) and the power chip (8) are both encapsulated in the same encapsulation material (38). [10] A method of manufacturing a semiconductor package, the method comprising: Providing a non-power chip (2) comprising a first electrical contact (4) arranged at a first main surface of the non-power chip (2); Providing a power chip (8) comprising a second electrical contact (10) arranged at a second main surface of the power chip (8); Forming a first electrical redistribution layer (14), wherein the first electrical redistribution layer (14) is configured to provide an electrical coupling between the first electrical contact (4) and a first external electrical contact (16) of the semiconductor package; and Forming a second electrical redistribution layer (18), wherein the second electrical redistribution layer (18) is designed to provide an electrical coupling between the second electrical contact (10) and a second external electrical contact (20) of the semiconductor package, wherein, when measured in a first direction perpendicular to at least one of the first main surface or the second main surface, a maximum thickness of at least a portion of the first electrical redistribution layer (14) is less than a maximum thickness of the second electrical redistribution layer (18), wherein providing the non-power chip (2) and providing the power chip (8) comprises: Providing a carrier (30); Arranging the non-power chip (2) and the power chip (8) above the carrier (30); Encapsulating the non-power chip (2) and the power chip (8) in an encapsulation material (38); and Removing the carrier (30), wherein the first main surface, the second main surface and a main surface of the encapsulation material (38) form a common planar surface. [11] The method of claim 10, wherein forming the first electrical redistribution layer (14) and forming the second electrical redistribution layer (18) comprises: Arranging at least one first metal layer over the common planar surface, wherein the at least one first metal layer is electrically coupled to the first electrical contact (4); and Arranging at least one second metal layer over the common planar surface, wherein the at least one second metal layer is electrically coupled to the second electrical contact (10), wherein the at least one first metal layer and the at least one second metal layer are arranged simultaneously in a same process step. [12] The method of claim 11, wherein forming the first electrical redistribution layer (14) and forming the second electrical redistribution layer (18) further comprises: electrically coupling a lead frame (48) to the at least one first metal layer and to the at least one second metal layer. [13] A method of manufacturing a semiconductor package, the method comprising: Providing a non-power chip (2) comprising a first electrical contact (4) arranged at a first main surface of the non-power chip (2); Providing a power chip (8) comprising a second electrical contact (10) arranged at a second main surface of the power chip (8); Forming a first electrical redistribution layer (14), wherein the first electrical redistribution layer (14) is configured to provide an electrical coupling between the first electrical contact (4) and a first external electrical contact (16) of the semiconductor package; and Forming a second electrical redistribution layer (18), wherein the second electrical redistribution layer (18) is designed to provide an electrical coupling between the second electrical contact (10) and a second external electrical contact (20) of the semiconductor package, wherein, when measured in a first direction perpendicular to at least one of the first major surface or the second major surface, a maximum thickness of at least a portion of the first electrical redistribution layer (14) is less than a maximum thickness of the second electrical redistribution layer (18); and Providing a metal sheet (52) having a first main surface and a second main surface opposite the first main surface, wherein forming the second electrical redistribution layer (18) comprises subtractively structuring the first main surface of the metal sheet (52). [14] The method of claim 13, wherein subtractively structuring the first major surface of the metal sheet (52) comprises etching the first major surface of the metal sheet (52). [15] The method of claim 13 or 14, further comprising: Attaching the non-power chip (2) and the power chip (8) to the subtractively structured first main surface of the metal sheet (52), wherein forming the first electrical redistribution layer (14) comprises subtractively structuring the second main surface of the metal sheet (52) after attaching the non-power chip (2) and the power chip (8). [16] The method of claim 13 or 14, further comprising: Attaching the non-power chip (2) and the power chip (8) to the structured first main surface of the metal sheet (52); and Removing material from the second main surface of the metal sheet (52), wherein forming the first electrical redistribution layer (14) comprises additively forming the first electrical redistribution layer (14) over the second major surface of the metal sheet (52) after removing the material. [17] The method of claim 16, wherein removing the material comprises at least one of grinding or etching the second major surface. [18] A method of manufacturing a semiconductor package, the method comprising: Providing a non-power chip (2) comprising a first electrical contact (4) arranged at a first main surface of the non-power chip (2); Providing a power chip (8) comprising a second electrical contact (10) arranged at a second main surface of the power chip (8); Forming a first electrical redistribution layer (14), wherein the first electrical redistribution layer (14) is configured to provide an electrical coupling between the first electrical contact (4) and a first external electrical contact (16) of the semiconductor package; and Forming a second electrical redistribution layer (18), wherein the second electrical redistribution layer (18) is designed to provide an electrical coupling between the second electrical contact (10) and a second external electrical contact (20) of the semiconductor package, wherein, when measured in a first direction perpendicular to at least one of the first major surface or the second major surface, a maximum thickness of at least a portion of the first electrical redistribution layer (14) is less than a maximum thickness of the second electrical redistribution layer (18); Providing a carrier (66) comprising a metal coating (68), wherein the formation of the first electrical redistribution layer (14) and the second electrical redistribution layer (18) comprises subtractive structuring of the metal coating (68), wherein forming the second electrical redistribution layer (18) comprises disposing electrically conductive pillars (70) over the subtractively patterned metal coating (68). [19] The method of claim 18, wherein: the carrier (66) comprises at least one of aluminum or a prepreg material, and / or the metal coating (68) comprises copper.

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