Semiconductor device with air gaps and method for their manufacture

Abstract

Procedure (100), comprising: Providing a structure with a front and a back side, wherein the structure comprises a substrate (201), a first dielectric layer (203) over the substrate (201), one or more semiconductor channel layers (215) over the first dielectric layer (203) connecting a first source / drain feature (S / D feature) (260) and a second S / D feature (260), and a gate structure (240) engaging with the one or more semiconductor channel layers (215), wherein the substrate (201) is located on the back side of the structure and the gate structure (240) is located on the front side of the structure; Etching the substrate (201) from the back of the structure to form a first trench (272) exposing the first S / D feature (260) and to form a second trench (272) exposing the second S / D feature (260); Forming an S / D contact (282) in the first trench (272); Etching at least a section of the first dielectric layer (203), resulting in a section of the S / D contact (282) protruding from the first dielectric layer (203) on the back side of the structure; and Deposition of a sealing layer (312) over the S / D contact (282), wherein the sealing layer (312) covers an air gap (314) between the gate structure (240) and the sealing layer (312).

Description

BACKGROUND

[0001] The semiconductor IC industry has undergone exponential growth. Technological advances in IC materials and IC design have led to generations of ICs, with each generation featuring smaller and more complex circuits than the previous generation. As ICs have evolved, functional density (i.e., the number of connected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be manufactured using a fabrication process) has decreased. This process of scaling down offers advantages by increasing production efficiency and reducing associated costs. However, this scaling down has also increased the complexity of processing and manufacturing ICs.

[0002] Recently, multi-gate devices have been introduced in an effort to improve gate control by increasing gate-channel coupling, reducing off-state current, and mitigating short-channel effects (SCEs). One such multi-gate device that has been introduced is the fin field-effect transistor (FinFET). The FinFET gets its name from the fin-like structure that extends from a substrate on which it is formed and is used to form the FET channel. Another multi-gate device, introduced in part to address performance issues associated with FinFETs, is the gate-all-around transistor (GAA transistor). GAA devices get their name from the gate structure, which can extend around the channel region, providing access to the channel on four sides.GAA devices are compatible with conventional complementary metal oxide semiconductor (CMOS) processes, and their structure allows them to be greatly reduced in size while preserving gate control and mitigating SCEs.

[0003] Typically, multi-gate devices (e.g., FinFETs and GAA devices) are manufactured in a stacked fashion, with transistors at the bottom level and interconnect structures (vias and wiring) on ​​top of the transistors to provide connectivity to the transistors. Power rails (e.g., metal lines for voltage sources and ground planes) are also located above the transistors and may be part of the interconnect structure. As integrated circuits continue to shrink, so too are the power rails. This inevitably leads to increased voltage drop across the power rails and increased power consumption of the integrated circuits. Therefore, existing approaches to semiconductor fabrication, although generally suitable for their intended purposes, are not entirely satisfactory in all respects.One area of ​​interest is how to form power rails and vias on the back of an IC with reduced resistance and reduced coupling capacitance.

[0004] US 2019 / 0 221 649 A1 describes a method for replacing source / drain regions on the backside of semiconductor devices with metallization on both sides.

[0005] US 2019 / 0 164 882 A1 describes a semiconductor device comprising a substrate, a dielectric layer, a plurality of conductive regions and a conductive structure passing through the substrate and electrically connected to a conductive rail

[0006] US 9 984 936 B1 describes a semiconductor component with an electrically conductive connection between several layers, using special structures and materials to improve layer integration and electrical conductivity.

[0007] US 2020 / 0 105 869 A1 describes a semiconductor device with an arrangement of conductive and insulating layers developed to optimize electrical properties and structural stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] This disclosure is best understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale and are used for illustrative purposes only. Indeed, the dimensions of various features may be arbitrarily exaggerated or reduced for clarity of explanation. Fig. 1A, Fig. 1B, Fig. 1C and Fig. 1D show flow diagrams of various embodiments of a method for forming a semiconductor device with backside metal wiring layers and backside air gaps according to various aspects of the present disclosure. Fig. 2A, Fig. 3A, Fig. 4A, Fig. 5A, Fig. 6A, Fig. 7A, Fig. 8A, Fig. 9A, Fig. 10A, Fig. 11A, Fig. 12A, Fig. 13A, Fig. 14A, Fig. 15A, Fig. 16A, Fig. 17A, Fig. 18A, Fig. 19A, Fig. 20A, Fig. 21A, Fig. 22A, Fig. 23A, Fig. 24A, Fig. 25A, Fig. 26A, Fig. 27A, Fig. 28A, Fig. 29A and Fig. 30A illustrate top views of a portion of a semiconductor device according to some embodiments. Fig. 2B, Fig. 3B, Fig. 4B, Fig. 5B, Fig. 6B, Fig. 7B, Fig. 8B, Fig. 9B, Fig. 10B, Fig. 11B, Fig. 12B, Fig. 13B, Fig. 14B, Fig. 15B, Fig. 16B, Fig. 17B, Fig. 18B, Fig. 19B, Fig. 20B, Fig. 21B, Fig. 22B, Fig. 23B, Fig. 24B, Fig. 25B, Fig. 26B, Fig. 27B, Fig. 28B, Fig. 29B and Fig. 30B show cross-sectional views of a portion of the semiconductor device along the line BB in Fig. 2A, Fig. 3A, Fig. 4A, Fig. 5A, Fig. 6A, Fig. 7A, Fig. 8A, Fig. 9A, Fig. 10A, Fig. 11A, Fig. 12A, Fig. 13A, Fig. 14A, Fig. 15A, Fig. 16A, Fig. 17A, Fig. 18A, Fig. 19A, Fig. 20A, Fig. 21A, Fig. 22A, Fig. 23A, Fig. 24A, Fig. 25A, Fig. 26A, Fig. 27A, Fig. 28A, Fig. 29A and 30A, respectively, according to some embodiments. Fig. 2C, Fig. 4C, Fig. 5C, Fig. 6C, Fig. 7C, Fig. 8C, Fig. 9C, Fig. 10C, Fig. 11C, Fig. 12C, Fig. 13C, Fig. 14C, Fig. 15C, Fig. 16C, Fig. 17C, Fig. 18C, Fig. 19C, Fig. 20C, Fig. 21C, Fig. 22C, Fig. 23C, Fig. 24C, Fig. 25C, Fig. 26C, Fig. 27C, Fig. 28C, Fig. 29C and Fig. 30C show cross-sectional views of a portion of the semiconductor device along the line CC in Fig. 2A, Fig. 4A, Fig. 5A, Fig. 6A, Fig. 7A, Fig. 8A, Fig. 9A, Fig. 10A, Fig. 11A, Fig. 12A, Fig. 13A, Fig. 14A, Fig. 15A, Fig. 16A, Fig. 17A, Fig. 18A, Fig. 19A, Fig. 20A, Fig. 21A, Fig. 22A, Fig. 23A, Fig. 24A, Fig. 25A, Fig. 26A, Fig. 27A, Fig. 28A, Fig. 29A and 30A, respectively, according to some embodiments. Fig. 2D, Fig. 4D, Fig. 5D, Fig. 6D, Fig. 7D, Fig. 8D, Fig. 9D, Fig. 10D, Fig. 11D, Fig. 12D, Fig. 13D, Fig. 14D, Fig. 15D, Fig. 16D, Fig. 17D, Fig. 18D, Fig. 19D, Fig. 20D, Fig. 21D, Fig. 22D, Fig. 23D, Fig. 24D, Fig. 25D, Fig. 26D, Fig. 27D, Fig. 28D, Fig. 29D and Fig. 30D show cross-sectional views of a portion of the semiconductor device along the line DD in Fig. 2A, Fig. 4A, Fig. 5A, Fig. 6A, Fig. 7A, Fig. 8A, Fig. 9A, Fig. 10A, Fig. 11A, Fig. 12A, Fig. 13A, Fig. 14A, Fig. 15A, Fig. 16A, Fig. 17A, Fig. 18A, Fig. 19A, Fig. 20A, Fig. 21A, Fig. 22A, Fig. 23A, Fig. 24A, Fig. 25A, Fig. 26A, Fig. 27A, Fig. 28A, Fig. 29A and 30A, respectively, according to some embodiments. Fig. 2E, Fig. 4E, Fig. 5E, Fig. 6E, Fig. 7E, Fig. 8E, Fig. 9E, Fig. 10E, Fig. 11E, Fig. 12E, Fig. 13E, Fig. 14E, Fig. 15E, Fig. 16E, Fig. 17E, Fig. 18E, Fig. 19E, Fig. 20E, Fig. 21E, Fig. 22E, Fig. 23E, Fig. 24E, Fig. 25E, Fig. 26E, Fig. 27E, Fig. 28E, Fig. 29E and Fig. 30E show cross-sectional views of a portion of the semiconductor device along the line EE in Fig. 2A, Fig. 4A, Fig. 5A, Fig. 6A, Fig. 7A, Fig. 8A, Fig. 9A, Fig. 10A, Fig. 11A, Fig. 12A, Fig. 13A, Fig. 14A, Fig. 15A, Fig. 16A, Fig. 17A, Fig. 18A, Fig. 19A, Fig. 20A, Fig. 21A, Fig. 22A, Fig. 23A, Fig. 24A, Fig. 25A, Fig. 26A, Fig. 27A, Fig. 28A, Fig. 29A and 30A, respectively, according to some embodiments. DETAILED DESCRIPTION

[0009] Furthermore, for ease of description, terms of spatial relationship such as "beneath," "under," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or feature to another element(s) or feature(s) as illustrated in the figures. The terms of spatial relationship are intended to encompass other orientations of the device in use or operation, in addition to the orientation depicted in the figures. The devices may be oriented differently (rotated 90 degrees or have other orientations), and the spatial relationship descriptors used herein may be equally interpreted accordingly. Moreover, when a number or range of numbers is described with "about," "approximately," and the like, the term includes numbers that are within certain ranges of deviation (e.g.,+ / - 10% or other deviation ranges) of the described number, as known to those skilled in the art with respect to the particular technology disclosed herein, unless otherwise specified. For example, the term "about 5 nm" can encompass the dimensional range of 4.5 nm to 5.5 nm, 4.0 nm to 5.0 nm, etc.

[0010] The present application relates generally to semiconductor structures and fabrication methods, and more particularly to semiconductor devices having backside metal wiring layers (e.g., power rails) and backside air gaps. Power rails of an IC need to be further improved to provide the required performance enhancement as well as to reduce power consumption. An object of the present disclosure includes providing power rails (or current guides) on a backside (or rear side) of a structure containing transistors (e.g., gate-all-around (GAA) transistors and / or FinFET transistors), in addition to an interconnect structure (which may also include power rails) on a frontside (or front side) of the structure. This increases the number of metal lines available in the structure for directly connecting to source / drain contacts and vias.It also increases gate density for greater device integration than existing structures without backside power rails. The backside power rails may have a wider dimension than the first-level metal lines (Mo lines) on the front side of the structure, advantageously reducing power rail resistance. The present disclosure also provides backside air gaps disposed between gate stacks and backside power rails. Without backside air gaps, a bottom self-aligned capping (B-SAC) layer may be used to provide insulation between the gate stacks and the backside power rails. A B-SAC layer often requires a dielectric material with a relatively high dielectric constant to provide etch selectivity during a backside etch.However, a B-SAC layer with a high dielectric constant increases the coupling capacitance between the gate stacks and the backside power rails. Incorporating air gaps can reduce this coupling capacitance, helping an IC operate faster. Furthermore, by incorporating air gaps, there is no path for leakage current between the gate stacks and the backside power rails, increasing the TDDB (time-dependent dielectric breakdown) performance of an IC.

[0011] The details of the structure and fabrication methods of the present disclosure are described below in conjunction with the accompanying drawings, which illustrate a method of fabricating a GAA device according to some embodiments. A GAA device refers to a device having vertically stacked, horizontally aligned, multi-channel transistors, such as nanowire transistors and nanosheet transistors. GAA transistors are promising candidates for taking CMOS to the next level due to their better gate control capability, lower leakage current, and full layout compatibility with FinFET devices. For simplicity, the present disclosure uses GAA devices as an example. Those skilled in the art will recognize that they may simply use the present disclosure as a basis for designing or modifying other methods and structures (e.g.,FinFET devices) to achieve the same purposes and / or obtain the same benefits as in the embodiments presented here.

[0012] Fig. 1A to 1D are flowcharts of a method 100 for manufacturing a semiconductor device according to various embodiments of the present disclosure. Further processing is contemplated in the present disclosure. Additional operations may be provided before, during, and after the method 100, and some of the described operations may be shifted, replaced, or omitted for further embodiments of the method 100.

[0013] The method 100 is described below in connection with Fig. 2A to Fig. 30E, which illustrate various top and cross-sectional views of a semiconductor device (or apparatus) 200 in various fabrication steps according to method 100 in accordance with some embodiments. In some embodiments, device 200 is a portion of an integrated circuit (IC) chip, a system-on-chip (SoC), or a portion thereof that includes various passive and active microelectronic devices, such asResistors, capacitors, inductors, diodes, p-type field-effect transistors (PFETs), n-type field-effect transistors (NFETs), FinFET nanosheet FETs, nanowire FETs, other types of multi-gate FETs, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffusing MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, memory devices, other suitable components, or combinations thereof. Fig. Figures 2A through 30E have been simplified for clarity of illustration to better understand the inventive concepts of the present disclosure. Additional features may be added to device 200, and some of the features described below may be replaced, modified, or omitted in other embodiments of device 200.

[0014] In operation 102, in the method 100 ( Fig. 1A) the device 200 is provided, which has a substrate 201 and transistors built on a front side of the substrate 201. Fig. 2A shows a top view of the device 200 and Fig. 2B, Fig. 2C, Fig. 2D and Fig. 2E show partial cross-sectional views of the device 200 along the lines BB, CC, DD and EE, respectively, in Fig. 2A. In particular, line BB is cut along the longitudinal direction of a semiconductor fin 204 (direction “X”), line CC is cut along the longitudinal direction of a gate stack 240 (direction “Y”), line DD is cut into the source regions of the transistors and runs parallel to the gate stacks 240, and line EE is cut into the drain regions of the transistors and runs parallel to the gate stacks 240. Lines BB, CC, DD, and EE in Fig. 3A to 30A are similarly configured. Note that in various embodiments, line DD may alternatively be cut into the drain regions of the transistors, and line EE may alternatively be cut into the source regions of the transistors. In the present disclosure, a source and a drain are used interchangeably.

[0015] Referring to Fig. 2A to 2E, the semiconductor device 200 has the substrate 201 on its back side and various elements are built on the front surface of the substrate 201. These elements include an isolation structure 230 over the substrate 201, a semiconductor fin (or fin) 204 extending from the substrate 201 and disposed adjacent to the isolation structure 230, two source / drain (S / D) features 260 over the fin 204, one or more semiconductor channel layers (or channel layers) 215 overhanging the fin 204 and connecting the two S / D features 260, a gate stack 240 between the two S / D features 260, wrapping around each of the channel layers 215, and a bottom self-aligned capping (B-SAC) layer 203 disposed between the fin 204 and both the channel layers 215 and the gate stack 240.The device 200 further includes inner spacers 255 between the S / D features 260 and the gate stack 240, an (outer) gate spacer 247 over sidewalls of the gate stack 240 and over the topmost channel layer 215, a contact etch stop layer (CESL) 269 adjacent to the gate spacer 247 and over the epitaxial S / D features 260 and the isolation structure 230, and an interlayer dielectric (ILD) layer 270 over the CESL 269. Over the gate stack 240, the semiconductor device 200 further includes a self-aligned cap layer (SAC) 352. Over the epitaxial S / D features 260, the semiconductor device 200 further includes silicide features 273, S / D contacts 275, an S / D cap dielectric layer 356, and an S / D via 358. In the depicted embodiment, the S / D cap layer 356 is disposed over the source feature 260, and the S / D via 358 is disposed over the drain feature 260.In alternative embodiments, the S / D cap layer 356 may be disposed over the drain feature 260, and the S / D cap layer 356 may be disposed over the source feature. In some embodiments, the S / D cap layer 356 may be disposed over both the source and drain features 260. In some embodiments, the S / D via 358 may be disposed over both the source and drain features 260.

[0016] Referring to Fig. 3A and Fig. 3B, the semiconductor device 200 further includes one or more interconnect layers (labeled 277) with wiring and vias embedded in dielectric layers. The one or more interconnect layers connect gate, source, and drain electrodes of various transistors, as well as other circuits in the device 200, to partially or completely form an integrated circuit. The device 200 may further include passivation layers, adhesion layers, and / or other layers constructed on the front side of the semiconductor device 200. These layers and the one or more interconnect layers are collectively labeled 277. It should be noted that the semiconductor device 200 in Fig. 3B has tipped over. The various elements of the semiconductor device 200 are further described below.

[0017] In one embodiment, substrate 201 is a bulk silicon substrate (i.e., it contains monocrystalline silicon). Substrate 201 may, in various embodiments, comprise other semiconductor materials, e.g., germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or combinations thereof. In an alternative embodiment, substrate 201 is a semiconductor-on-insulator substrate, e.g., a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate.

[0018] In embodiments, the fin may comprise silicon, silicon germanium, germanium, or another suitable semiconductor and may be doped with n- or p-type dopants. The fin 204 may be patterned by any suitable method. For example, the fin 204 may be patterned by one or more photolithography methods, including double-patterning or multi-patterning methods. Generally, double-patterning or multi-patterning methods combine photolithography and self-alignment methods, enabling structures to be created that have, for example, center-to-center pitches that are smaller than those otherwise obtainable when using a single direct photolithography method. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned by a photolithography method.Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can then be used as a masking element to pattern fin 204. For example, the masking element can be used to etch recesses in semiconductor layers above or in substrate 201, leaving fin 204 on substrate 201. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable methods. For example, in dry etching, an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBr3), an iodine-containing gas, other suitable gases and / or plasmas, and / or combinations thereof may be used.A wet etching process may include, for example, etching in dilute hydrofluoric acid (DHF); potassium hydroxide (KOH) solution; ammonia; a solution containing hydrofluoric acid (HF), nitric acid (HNO3), and / or acetic acid (CH3COOH); or another suitable wet etchant. Numerous other embodiments of methods for forming fin 204 may be suitable.

[0019] The isolation structure 230 may comprise silicon oxide, silicon nitride, silicon oxynitride, another suitable isolation material (e.g., including silicon, oxygen, nitrogen, carbon, or another suitable isolation component), or combinations thereof. The isolation structure 230 may comprise various structures, such as shallow trench isolation (STI) features and / or deep trench isolation (DTI) features. In one embodiment, the isolation structure 230 may be formed by filling the trenches between the fins 204 with insulator material (e.g., by a CVD process or a glass spin-coating process), performing a chemical mechanical polishing (CMP) process to remove excess insulator material, and / or planarizing a top surface of the insulator material layer and etching back the insulator material layer to form the isolation structure 230.In some embodiments, the isolation structure 230 includes multiple dielectric layers, e.g., a silicon nitride layer disposed over a thermal oxide liner layer.

[0020] The S / D features 260 comprise epitaxially grown semiconductor materials, such as epitaxially grown silicon, germanium, or silicon germanium. The S / D features 260 may be formed by any epitaxial growth method, including chemical vapor deposition (CVD) techniques (e.g., vapor phase epitaxy and / or ultra-high vacuum CVD), molecular beam epitaxy, other suitable epitaxial growth methods, or combinations thereof. The S / D features 260 may be doped with n-type dopants and / or p-type dopants. In some embodiments, the S / D features 260 for n-type transistors comprise silicon and may be doped with carbon, phosphorus, arsenic, other n-type dopants, or combinations thereof (e.g., forming epitaxial Si:CS / D features, epitaxial Si:PS / D features, or epitaxial Si:C:PS / D features).In some embodiments, the S / D features 260 for p-type transistors comprise silicon germanium or germanium and may be doped with boron, other p-type dopants, or combinations thereof (e.g., forming epitaxial Si:Ge:BS / D features). The S / D features 260 may comprise multiple epitaxial semiconductor layers with different dopant densities. In some embodiments, annealing processes (e.g., rapid thermal anneal (RTA) and / or laser annealing) are performed to activate dopants in the S / D features 260.

[0021] In embodiments, the channel layers 215 comprise a semiconductor material suitable for transistor channels, such as silicon, silicon germanium, or other semiconductor material(s). The channel layers 215 may, in various embodiments, be in the form of rods, bars, sheets, or other shapes. In one embodiment, the channel layers 215 are initially part of a stack of semiconductor layers that includes the channel layers 215 and other sacrificial semiconductor layers stacked alternately layer by layer. The sacrificial semiconductor layers and the channel layers 215 have different material compositions (e.g., different semiconductor materials, different atomic percentages of the constituents, and / or different weight percentages of the constituents) to achieve etch selectivity.During a gate replacement process to form the gate stack 240, the sacrificial semiconductor layers are selectively removed, leaving the channel layers 215 suspended over the fin 204.

[0022] In some embodiments, the inner spacers 255 comprise a dielectric material including silicon, oxygen, carbon, nitrogen, another suitable material, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or silicon oxycarbonitride). In some embodiments, the inner spacers 255 comprise a low-k dielectric material such as those described herein. The inner spacers 255 may be formed by deposition and etching processes. For example, after the S / D trenches are etched and before the S / D features 260 are epitaxially grown from the S / D trenches, an etch process may be applied to recess the sacrificial semiconductor layers between the adjacent channel layers 215 to form vertical gaps between the adjacent channel layers 215.Subsequently, one or more dielectric materials are deposited (for example, by CVD or ALD) to fill the gaps. A further etching process is performed to remove the dielectric materials outside the gaps, forming the inner spacers 255.

[0023] In some embodiments, the B-SAC layer 203 may include one or more of La2O3, Al2O3, SiOCN, SiOC, SiCN, SiO2, ZnO, ZrN, Zr2Al3O9, TiO2, TaO2, ZrO2, HfO2, Si3N4, Y2O3, AlON, TaCN, ZrSi, and other suitable materials. In some embodiments, the B-SAC layer 203 may include a low-k dielectric material, e.g., a dielectric material containing Si, O, N, and C. Example low-k dielectric materials include FSG, carbon-doped silicon oxide, Black Diamond® (Applied Materials of Santa Clara, California), xerogel, aerogel, amorphous fluorinated carbon, parylene, BCB, SiLK (Dow Chemical, Midland, Michigan), polyimide, or combinations thereof. The B-SAC layer 203 can be deposited by CVD, ALD, PVD, or oxidation. In one embodiment, the B-SAC layer 203 is initially deposited on the fin 204 and is patterned using the same process used to pattern the fin 204.In another embodiment, a semiconductor sacrificial layer (e.g., SiGe) is initially deposited on the fin 204 and is patterned by the same process used to pattern the fin 204. The sacrificial layer is removed and replaced by the B-SAC layer 203 during a gate replacement process used to form the gate stack 240. As explained in more detail below, the B-SAC layer 203 reserves a space for an air gap to be disposed between the gate stack 240 and a backside metal wiring layer (and a sealing layer) and to be formed in subsequent processes. In some embodiments, the B-SAC layer 203 may have a thickness d1 in a range from about 1 nm to about 20 nm. In some embodiments, if the B-SAC layer 203 is too thin (e.g.,less than 1 nm), the subsequently formed air gap may not provide sufficient isolation between the gate stack 240 and the backside metal wiring layer. In some embodiments, if the B-SAC layer 203 is too thick (e.g., more than 20 nm), the subsequently formed backside S / D contacts and vias would be long and their resistance would be high, which may reduce the speed of the circuit. In some embodiments, portions of the B-SAC layer between two adjacent S / D features 260 have a length d4 (measured along the "x" direction) in a range from about 3 nm to about 30 nm. The length d4 is also the lateral distance between two adjacent S / D features 260. As explained in more detail below, the length d4 defines an opening of a subsequently formed air gap.The range of length d4 is set to facilitate a subsequent capping process for sealing the air gap. If the length d4 is greater than about 30 nm, the opening is too large for the capping process to seal the air gap. If the length d4 is less than about 3 nm, the dimensions of various features in the gate stack 240 may be too close to the critical dimension (CD), resulting in poor process windows.

[0024] In the depicted embodiment, the gate stack 240 includes a gate dielectric layer 349 and a gate electrode layer 350. The gate dielectric layer 349 may comprise a high-k dielectric material such as HfO 2, HfSiO, HfSiO4, HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlO x, ZrO, ZrO2, ZrSiO2, AlO, AlSiO, Al2O3, TiO, TiO2, LaO, LaSiO, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3 (BTO), (Ba,Sr)TiO3 (BST), Si3N4, hafnium dioxide-aluminum oxide alloy (HfO2-Al2O3 alloy), another suitable high-k dielectric material, or combinations thereof. High-k dielectric material generally refers to dielectric materials that have a high dielectric constant, for example, higher than that of silicon oxide (k ≈ 3.9). The gate dielectric layer 349 can be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. In some embodiments, the gate stack 240 further includes an interface layer between the gate dielectric layer 349 and the channel layers 215. The interface layer may include silicon dioxide, silicon oxynitride, or other suitable materials.In some embodiments, the gate electrode layer 350 includes an n-type or p-type work function layer and a metal fill layer. For example, an n-type work function layer may include a metal with a sufficiently low effective work function, such as titanium, aluminum, tantalum carbide, tantalum carbide nitride, tantalum silicon nitride, or combinations thereof. For example, a p-type work function layer may include a metal with a sufficiently high effective work function, such as titanium nitride, tantalum nitride, ruthenium, molybdenum, tungsten, platinum, or combinations thereof. A metal fill layer may include, for example, aluminum, tungsten, cobalt, copper, and / or other suitable materials. The gate electrode layer 350 may be formed by CVD, PVD, plating, and / or other suitable methods. Because the gate stack 240 includes a high-k dielectric layer and a metal layer(s), it is also referred to as a high-k metal gate.

[0025] In one embodiment, the gate spacer 247 comprises, for example, a dielectric material including silicon, oxygen, carbon, nitrogen, another suitable material, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbide, silicon carbonitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN)). In embodiments, the gate spacer 247 may include La2O3, Al2O3, SiOCN, SiOC, SiCN, SiO2, SiC, ZnO, ZrN, Zr2Al3O9, TiO2, TaO2, ZrO2, HfO2, Si3N4, Y2O3, AlON, TaCN, ZrSi, or other suitable material(s). For example, a dielectric layer containing silicon and nitrogen, e.g., a silicon nitride layer, may be deposited over a dummy gate stack (which is subsequently replaced by the high-k metal gate 240) and subsequently etched (e.g., anisotropically etched) to form the gate spacers 247.In some embodiments, the gate spacers 247 have a multi-layer structure, e.g., a first dielectric layer including silicon nitride and a second dielectric layer including silicon oxide. In some embodiments, more than one group of spacers is formed adjacent to the gate stack 240, e.g., sealing spacers, offset spacers, sacrificial spacers, dummy spacers, and / or main spacers. In embodiments, the gate spacers 247 may, for example, have a thickness of about 1 nm to about 40 nm.

[0026] In some embodiments, the SAC layer 352 includes La2O3, Al2O3, SiOCN, SiOC, SiCN, SiO2, SiC, ZnO, ZrN, Zr2Al3O9, TiO2, TaO2, ZrO2, HfO2, Si3N4, Y2O3, AlON, TaCN, ZrSi, or other suitable material(s). The SAC layer 352 protects the gate stacks 240 from the etching and CMP processes used to etch S / D contact holes. The SAC layer 352 may be formed by recessing the gate stacks 240 and, if appropriate, the gate spacers 247, depositing one or more dielectric materials over the recessed gate stacks 240 and, if appropriate, the recessed gate spacers 247, and performing a CMP process on the one or more dielectric materials. The SAC layer 352 may, for example, have a thickness in a range of about 3 nm to about 30 nm.

[0027] In embodiments, the CESL 269 may include La2O3, Al2O3, SiOCN, SiOC, SiCN, SiO2, SiC, ZnO, ZrN, Zr2Al3O9, TiO2, TaO2, ZrO2, HfO2, Si3N4, Y2O3, AlON, TaCN, ZrSi, or other suitable material(s), and may be formed by CVD, PVD, ALD, or other suitable processes. The ILD layer 270 may include tetraethylorthosilicate oxide (TEOS oxide), undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fluorine-doped silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), a low-k dielectric material, another suitable dielectric material, or combinations thereof. The ILD layer 270 may be formed by PE-CVD (plasma-assisted CVD), F-CVD (flowable CVD), or other suitable methods.

[0028] In some embodiments, the silicide features 273 may include titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel platinum silicide (NiPtSi), nickel platinum germanium silicide (NiPtGeSi), nickel germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), or other suitable compounds.

[0029] In one embodiment, the S / D contacts 275 may include a conductive barrier layer and a metal fill layer over the conductive barrier layer. The conductive barrier layer may include titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), ruthenium (Ru), or a conductive nitride such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tantalum nitride (TaN), or combinations thereof, and may be formed by CVD, PVD, ALD, and / or other suitable methods. The metal fill layer may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), nickel (Ni), copper (Cu), or other metals and may be formed by CVD, PVD, ALD, plating, or other suitable methods. In some embodiments, the conductive barrier layer is omitted from the S / D contacts 275.

[0030] In some embodiments, the S / D cap layer 356 includes La2O3, Al2O3, SiOCN, SiOC, SiCN, SiO2, SiC, ZnO, ZrN, Zr2Al3O9, TiO2, TaO2, ZrO2, HfO2, Si3N4, Y2O3, AlON, TaCN, ZrSi, or other suitable material(s). The cap layer 356 protects the S / D contacts 275 from the etching and CMP processes and insulates the S / D contacts 275 from the interconnect structure formed thereon. The S / D cap layer 356 may, for example, have a thickness in a range of about 3 nm to about 30 nm. In some embodiments, the SAC layer 352 and the S / D cap layer 356 comprise different materials, for example, to achieve etch selectivity during the formation of the S / D cap layer 356.

[0031] In one embodiment, the S / D via 358 may include a conductive barrier layer and a metal fill layer over the conductive barrier layer. The conductive barrier layer may include titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), ruthenium (Ru), or a conductive nitride such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tantalum nitride (TaN), or combinations thereof, and may be formed by CVD, PVD, AVD, plating, or other suitable methods. The metal fill layer may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), nickel (Ni), copper (Cu), or other metals and may be formed by CVD, PVD, ALD, plating, or other suitable methods. In some embodiments, the conductive barrier layer is omitted from the S / D via 358.

[0032] In operation 104, in the method 100 ( Fig. 1A) the device 200 is tilted over and the front of the device 200 is attached to a support 370, as in Fig. 3B. This makes the device 200 accessible for further processing from the back of the device 200. During operation 104, any suitable attachment methods may be used, such as direct bonding, hybrid bonding, use of adhesive, or other bonding methods. Operation 104 may further include alignment, annealing, and / or other processes. The carrier 370 may, in some embodiments, be a silicon wafer. In Fig. 2A to 30E, the "z" direction shows from the back of the device 200 to the front of the device 200, while the "-z" direction shows from the front of the device 200 to the back of the device 200.

[0033] In operation 106, in the method 100 ( Fig. 1A), the device 200 is thinned from the back of the device 200 until the fin 204 and the isolation structure 230 are exposed at the back of the device 200. The resulting structure according to one embodiment is shown in Fig. 4A to 4E. For simplicity, Fig. 4C, Fig. 4D and Fig. 4E omitted some features that were already present in Fig. 4B, in particular layer 277 and carrier 370. The thinning process may include a mechanical grinding process and / or a chemical thinning process. During a mechanical grinding process, a substantial amount of substrate material may first be removed from the substrate 201. Subsequently, in a chemical thinning process, an etching chemical may be used on the backside of the substrate 201 to further thin the substrate 201.

[0034] In operation 108, in the method 100 ( Fig. 1A), the fin 204 is selectively etched to form trenches 272 over the backside of the gate stack 240 and the S / D features 260. The trenches 272 expose surfaces of the S / D features 260 from the backside. The resulting structure, according to one embodiment, is shown in Fig. 5A to 5E. In the present embodiment, during operation 108, an etch process is applied that is selective for the materials of the semiconductor material (e.g., silicon) in the fin 204 and that the gate stacks 240, the isolation structure 230, and the B-SAC layer 203 are not etched (or only minimally etched). In the present embodiment, the etch process also etches the S / D features 260 to recess them to a height equal to or below the lowest surface of the channel layers 215. For some embodiments, the recessed S / D features 260 remain higher than an interface between the isolation structure 230 and the CESL 269, as shown in Fig. 5D and Fig. 5E. In some alternative embodiments, operation 108 may further recess the S / D features 260 to below an interface between the isolation structure 230 and the CESL 269 (not shown). More than one etch process may be applied during operation 108. For example, a first etch process may be applied to selectively remove the fin 204 and then a second etch process may be applied to selectively recess the S / D features 260 to a desired height, wherein the first and second etch processes apply different etch parameters, e.g., use different etchants. The etch process(es) may be dry etch, wet etch, reactive ion etch, or other etch processes. The B-SAC layer 203 protects the gate stack 240 from the one or more etch processes.

[0035] In operation 110, in the method 100 ( Fig. 1A), a dielectric layer 276 comprising one or more dielectric materials is deposited to fill the trenches 272. In some embodiments, the dielectric layer 276 may include one or more of La2O3, Al2O3, SiOCN, SiOC, SiCN, SiO2, SiC, ZnO, ZrN, Zr2Al3O9, TiO2, TaO2, ZrO2, HfO2, Si3N4, Y2O3, AlON, TaCN, ZrSi, or other suitable material(s), and may be formed by PE-CVD, F-CVD, or other suitable methods. Furthermore, in the present embodiment, the dielectric layer 276 and the B-SAC layer 203 may comprise different materials so that the B-SAC layer 203 may act as a CMP stop when the dielectric layer 276 is planarized by the CMP process.

[0036] In operation 112, in the method 100 ( Fig. 1A), an etch mask 360 is formed over the backside of the device 200. The etch mask 360 provides openings 362 over the backside of the S / D features 260 to be connected to backside contacts and backside metal wiring layers. The resulting structure according to one embodiment is shown in Fig. 7A to 7E. In the illustrated embodiment, the opening 362 is provided over the backside of the source feature 260, while the backside of the gate stack 240 and the drain feature 260 are covered by the etch mask 360. In various embodiments, the openings 362 may be provided over the backside of only the drain features, only the source features, or both the source and drain features. The etch mask 360 comprises a material that is different from the material of the dielectric layer 276 in order to achieve etch selectivity during the backside contact hole etch. For example, the etch mask 360 comprises a resist material (and may thus be referred to as a patterned and / or patterned photoresist layer). In some embodiments, the etch mask 360 has a multi-layer structure, e.g.a resist layer disposed over a layer of an anti-reflective coating (ARC) and / or a hard mask layer containing silicon nitride or silicon oxide. In the present disclosure, other materials are contemplated for the etch mask 360, as long as they achieve the etch selectivity during the etching of the dielectric layer 276. In some embodiments, a lithography process is applied in operation 112, which includes forming a resist layer over the backside of a device 200 (e.g., by spin coating), performing a pre-irradiation heating process, performing an irradiation process using a mask, performing a post-irradiation heating process, and performing a development process. During the irradiation process, the resist layer is exposed to radiant energy (e.g.,UV light, DUV light or EUV light), wherein the mask blocks, transmits and / or reflects radiation to the resist layer, which depends on a mask structure of the mask and / or a mask type (e.g., binary mask, phase shift mask or EUV mask), so that an image is projected onto the resist layer that corresponds to the mask structure. Since the resist layer is sensitive to radiation energy, irradiated portions of the resist layer change chemically, and during the development process, irradiated (or unirradiated) portions of the resist layer are dissolved, which depends on the properties of the resist layer and the properties of the development solution used in the development process. After development, the patterned resist layer (e.g., the etching mask 360) has a resist structure that corresponds to the mask. Alternatively, the irradiation process can be realized or replaced by other processes, such asmaskless lithography, electron beam writing, ion beam writing, or combinations thereof.

[0037] In operation 114, in the method 100 ( Fig. 1A), the dielectric layer 276 is etched through the etch mask 360 to form an S / D contact hole 278. Subsequently, the etch mask 360 is removed, for example, by a resist stripping process or another suitable process. The resulting structure according to one embodiment is shown in Fig. 8A to 8E. The S / D contact hole 278 exposes the source feature 260. In the illustrated embodiment, the etching process also etches the source feature 260 to recess it to a height equal to or below the interface between the isolation structure 230 and the CESL 269. This serves to prepare the source feature 260 for subsequent silicide formation. As a result, the source feature 260 may be below the drain feature 260, as shown in Fig. 8D and Fig. 8E. In some embodiments, one or more etching processes may be applied during operation 114. For example, a first etching process may be applied to selectively remove the dielectric layer 276, and then a second etching process may be applied to selectively recess the source feature 260 to the desired height, wherein different etching parameters are applied in the first and second etching processes, e.g., different etchants are used. In one embodiment, the first etching process comprises a dry etching process (plasma etching process) which is adjusted to selectively etch the dielectric layer 276 and not (or only minimally) etch the isolation structure 230, the B-SAC layer 203, the inner spacers 255, and the source feature 260. In alternative embodiments, other types of etching (e.g.,A second etching process (e.g., wet etching or reactive ion etching) may be used, provided that it achieves the etch selectivity between the layers, as described above. Since the first etching process does not etch or only minimally etch the isolation structure 230, the B-SAC layer 203, and the inner spacers 255, the contact hole aligns itself in the yz-plane and in the xz-plane with the source feature 260, thereby improving the process window. The second etching process may be dry etching, wet etching, reactive ion etching, or other suitable etching processes to selectively recess the source feature 260 to the desired height.

[0038] In operation 116, the method 100 ( Fig. 1A) a silicide feature 280 and an S / D contact 282 are formed in the S / D contact hole 278. The resulting structure is shown in Fig. 9A to 9E. In one embodiment, in operation 116, one or more metals are first deposited in the trenches 272, an annealing process is performed on the device 200 to cause a reaction between the one or more metals and the source feature 260 to create the silicide feature 280, and unreacted portions of the one or more metals are removed, leaving the silicide feature 280 in the trenches 272. The one or more metals may include titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), platinum (Pt), ytterbium (Yb), iridium (Ir), erbium (Er), cobalt (Co), or a combination thereof (e.g., an alloy of two or more metals), and may be deposited by CVD, PVD, ALD, or other suitable processes.Silicide feature 280 may include titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel platinum silicide (NiPtSi), nickel platinum germanium silicide (NiPtGeSi), nickel germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), a combination thereof, or other suitable compounds. In one embodiment, S / D contact 282 is then deposited over silicide feature 280 during operation 116. The S / D contact 282 may contain tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), nickel (Ni), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or other metals and may be formed by CVD, PVD, ALD, plating, or other suitable processes.

[0039] In operation 118, in the method 100 ( Fig. 1A), a CMP process is performed on the dielectric layer 276 and the isolation structure 230 to remove excess dielectric materials from the surface of the B-SAC layer 203. The resulting structure according to one embodiment is shown in Fig. 9A to 9E. Because the dielectric layer 276 and the isolation structure 230 comprise different materials than the B-SAC layer 203, the B-SAC layer 203 may act as a CMP stop when the device 200 is planarized by the CMP process. After the operation 118, a portion of the dielectric layer 276 remains above the drain feature 260 as an S / D cap layer in the trenches. This portion of the dielectric layer 276 is also referred to as the S / D cap layer 276. The CMP process also removes excess metallic materials in the S / D contact 282 so that surfaces of the S / D contact 282, the S / D cap layer 276, and the B-SAC layer 203 are level. Accordingly, the thickness d1 of the B-SAC layer 203 also defines a distance how far the S / D contact 282 protrudes from the gate stack 240.As described above, in some embodiments, the thickness d1 is in a range from about 1 nm to about 20 nm.

[0040] In operation 130, in the method 100 ( Fig. 1B), the B-SAC layer 203 is selectively etched to recess the B-SAC layer 203 below the surfaces of the S / D contact 282, the S / D cap layer 276, and the isolation structure 230. The resulting structure according to one embodiment is shown in Fig. 10A to 10E. In the present embodiment, during operation 130, an etching process is applied that is set to be selective for the dielectric materials of the B-SAC layer 203 and to not (or only minimally) etch the S / D contact 282, the S / D cap layer 276, and the isolation structure 230. The etching process may be a dry plasma etch, a dry chemical etch, an ashing process, a wet etch, or other suitable etching processes. For example, the dry plasma etch may use a conventional dry etchant for a dielectric material, such as C4F6 mixed with H2 or O2. The dry chemical etching process may use one or more chemicals, such asH2, the ashing process may use oxygen or hydrogen ashing, and the wet etching process may apply a hot SPM solution (a mixture of sulfuric acid and hydrogen peroxide), for example, at a temperature above 100°C. As a result of operation 130, portions of sidewalls of the S / D contact 282, the S / D cap layer 276, and the isolation structure 230 protrude a distance d2 from the B-SAC layer 203. The distance d2 can be controlled by adjusting the duration of the etching process. In some embodiments, the distance d2 is in a range from about 2 nm to about 20 nm. As will be explained in more detail below, the distance d2 defines a vertical length of a dielectric liner to be formed in subsequent processes on the protruding sidewalls of the S / D contact 282, the S / D cap layer 276, and the isolation structure 230.A lateral distance between the S / D contact 282 and the S / D cap layer 276 is approximately like the length d4 in a range of about 3 nm to about 30 nm.

[0041] In operation 132, in the method 100 ( Fig. 1B) a dielectric lining 304 is applied to the back of the device 200. The resulting structure according to one embodiment is shown in Fig. 11A to 11E. In the illustrated embodiment, the dielectric liner 304 is conformally deposited to have a substantially uniform thickness along the various surfaces of the B-SAC layer 203, the isolation structure 230, the S / D contact 282, and the S / D cap layer 276. In various embodiments, the dielectric liner 304 may include La2O3, Al2O3, SiOCN, SiOC, SiCN, SiO2, SiC, ZnO, ZrN, Zr2Al3O9, TiO2, TaO2, ZrO2, HfO2, Si3N4, Y2O3, AlON, TaCN, ZrSi, combinations thereof, or other suitable material(s). The dielectric liner 304 may be formed by ALD, CVD, or other suitable processes and may, in various embodiments, have a thickness of about 0.5 nm to about 10 nm (e.g., measured at the sidewalls of the S / D contact 282 along the “x” direction).

[0042] In operation 134, in the method 100 ( Fig. 1B), an etching process is performed to break through and remove the majority of the horizontal portions of the dielectric liner 304. The etching process is also referred to as a breakdown etch (BT) process. The resulting structure according to one embodiment is shown in Fig. 12A to 12E. In some embodiments, the BT etch process may include an anisotropic dry etch process or the like. In some embodiments, when the dielectric liner 304 is formed from a compound oxide, the BT etch process is a reactive ion etch (RIE) process with etch process gases including CHF3, Ar, CF4, N2, O2, CH2F2, SF3, the like, or a combination thereof. The RIE process may be performed for an etch time of about 2 seconds to about 20 seconds, at a pressure of about 2 mTorr to about 30 mTorr, a temperature of about 10°C to about 100°C, a radio frequency (RF) power of about 100 W to about 1500 W, and a bias voltage of about 10 V to about 800 V. In the illustrated embodiment, as a result of operation 134, portions of the dielectric liner 304 remain on sidewalls of the S / D contact 282, the S / D cap layer 276, and the isolation structure 230.A vertical length of the dielectric liner 304, like the distance d2, ranges from about 2 nm to about 10 nm. As will be described in more detail below, the dielectric liner 304 acts as a landing pad for accumulating deposited dielectric material of a sealing layer during a subsequent capping process for sealing air gaps. In some embodiments, if the length of the dielectric liner 304 is less than 2 nm, it may not provide enough landing area to accumulate sufficient dielectric material to seal the air gaps. In some embodiments, if the length of the dielectric liner 304 is more than 10 nm, deposited dielectric material of a sealing layer may be introduced deeply into air gaps, reducing the volumes of the air gaps.

[0043] In operation 136, in the method 100 ( Fig. 1B) the B-SAC layer 203 is removed in an etching process. The resulting structure according to one embodiment is shown in Fig. 13A to 13E. In the illustrated embodiment, the removal of the B-SAC layer 203 exposes the gate stack 240 and results in gaps 333 between the dielectric liner 304 and the gate stack 240. The gaps 333 are located directly below the dielectric liner 304 and above the gate stack 240 and expose portions of the sidewalls of the S / D contact 282, the S / D cap layer 276, and the isolation structure 230. In various embodiments, a vertical distance d3 between the dielectric liner 304 and the gate stack 240 is in a range from about 0.5 nm to about 10 nm. In one embodiment, the etching process may include a dry plasma etch, a dry chemical etch, an ashing process, a wet etch, or other suitable etching processes. For example, in dry plasma etching, a conventional dry etchant for a dielectric material can be used, such asC4F6 mixed with H2 or O2, in the dry chemical etching process one or more chemicals can be used, such as H2, in the ashing process oxygen or hydrogen ashing can be used and in the wet etching process a hot SPM solution (a mixture of sulfuric acid and hydrogen peroxide) can be applied, for example at a temperature above 100 °C.

[0044] In operation 138, in the method 100 ( Fig. 1B), a sealing layer 312 is applied over the backside of the device 200, and air gaps 314 are covered vertically between the gate stack 240 and the sealing layer 312. The resulting structure according to one embodiment is shown in Fig. 14A to 14E. The deposition of the sealing layer 312 is also referred to as a capping process. As used herein, the term "air gap" is used to describe a gap defined by surrounding substantial features, which gap may include air, nitrogen, ambient gases, gaseous chemicals used in previous or current processes, or combinations thereof. The structure of the device 200 and the formation of the sealing layer 312 are adjusted to effectively close the space horizontally between the S / D contact 282 and the S / D capping layer 276, resulting in the air gaps 314. In particular, the protruding S / D contact 282 and the S / D capping layer 276 act as pillars that support the sealing layer 312 formed thereon.As described above, the distance d4 between the S / D contact 282 and the S / D capping layer 276 is set in a range that facilitates the capping process. The dielectric liner 304 further narrows the opening in an upper portion of the space between the S / D contact 282 and the S / D capping layer 276. Furthermore, the dielectric liner 304 provides a landing field for the accumulation of the deposited dielectric material. In some embodiments, the dielectric liner 304 has a hydrophilic property, so that it is easier to accumulate dielectric material than at the metallic surfaces of the S / D contact 282. In some embodiments, due to covalent bonds between similar material compositions of the dielectric liner 304 and the deposited dielectric material (e.g.,both comprise oxides) to more easily accumulate the deposited dielectric material on the dielectric liner 304. In some embodiments, the deposited material of the sealing layer 312 includes La2O3, Al2O3, SiOCN, SiOC, SiCN, SiO2, SiC, ZnO, ZrN, Zr2Al3O9, TiO2, TaO2, ZrO2, HfO2, Si3N4, Y2O3, AlON, TaCN, ZrSi, combinations thereof, or other suitable material(s). In some embodiments, the sealing layer 312 and the dielectric liner 304 may have the same dielectric material composition. In some alternative embodiments, the sealing layer 312 and the dielectric liner 304 may have different dielectric material compositions.

[0045] The sealing layer 312 may be formed by CVD, PVD, PE-CVD, a coating process, or another suitable process. In one embodiment, the sealing layer 312 is deposited by a PE-CVD process, in which it is easier for deposited dielectric materials to coalesce on top of a narrow opening. The parameters in the PE-CVD process (e.g., pressure, temperature, and gas viscosity) are adjusted so that the gap-filling behavior of deposited dielectric materials maintains the air gap without filling the space between the S / D contact 282 and the S / D cap layer 276. In the present embodiment, a setting with a pressure of less than about 0.75 Torr and a temperature of greater than about 75°C is used in the PE-CVD process.Thus, the dielectric material of the sealing layer 312 can be applied in the upper portion between the dielectric liner 304 to enclose the space between the S / D contact 282 and the S / D cap layer 276 without a significant amount being applied in a lower portion of the space. Corresponding air gaps 314 can therefore be formed below the dielectric material of the sealing layer 312 and above the gate stack 240 for a vertical thickness in a range of about 0.5 nm to about 10 nm. In some embodiments, if the air gaps 314 are too thin (e.g., thinner than 0.5 nm), they may not provide sufficient isolation between the gate stack 240 and a subsequently formed backside metal wiring layer. In some embodiments, if the air gaps 314 are too thick (e.g.,thicker than 10 nm), the backside S / D contacts and vias would be long enough to accommodate the thickness of the air gaps, and their resistance would be high, which may reduce the circuit speed. The sidewalls of the S / D contact 282, the S / D cap layer 276, the isolation structure 230, and the dielectric liner 304 are exposed in the air gaps 314. The gaps 333 vertically between the dielectric liner 304 and the gate stack 240 also become part of the air gaps 314. A gas may be present in the air gaps, e.g., a gas(es) used during the deposition of the dielectric material of the sealing layer 312, or any other species that may diffuse into the air gaps 314. The sealing layer 312 extends laterally from the air gaps 314 to upper surfaces of the S / D contact 282 and the S / D cap layer 27\6.The sealing layer 312 also covers a top surface and a portion of the sidewalls of the dielectric liner 304.

[0046] In operation 140, in the method 100 ( Fig. 1B), a CMP process is performed on the sealing layer 312 to remove excess dielectric materials from the surface of the S / D contact 282. The resulting structure according to one embodiment is shown in Fig. 15A to 15E. Because the sealing layer 312 comprises different materials than the S / D contact 282, the S / D contact 282 may act as a CMP stop when the device 200 is planarized by the CMP process. After operation 140, the air gaps 314 remain covered by the sealing layer 312, and upper surfaces of the S / D contact 282 and the S / D cap layer 276 are exposed. After operation 140, the remaining sealing layer 312 is disposed between the opposing dielectric liners 304. In some embodiments, the remaining sealing layer 312 after operation 140 has a thickness in a range from about 0.5 nm to about 10 nm.

[0047] In operation 142, in the method 100 ( Fig. 1B) a metal wiring layer, e.g., rear bus bars 284, is formed on the back of the device 200. The resulting structure according to one embodiment is shown in Fig. 16A to 16E. As shown in Fig. 16B and Fig. 16D, the back S / D contact 282 is electrically connected to the back bus bars 284. In one embodiment, the back bus bars 284 may be formed by a damascene process, a double damascene process, a metal patterning process, or other suitable processes. The back bus bars 284 may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), nickel (Ni), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or other metals, and may be deposited by CVD, PVD, ALD, plating, or other suitable processes. Although in Fig. 16A to 16E, the backside power rails 284 are embedded in one or more dielectric layers. The backside power rails 284 increase the number of metal lines available in the structure 200 for direct connection to source / drain contacts and vias. They also increase the gate density for greater device integration than existing structures without the backside power rails 284. The backside power rails 284 may have a wider dimension than the first-level metal lines (Mo lines) on the front side of the structure 200, advantageously reducing the backside power rail resistance. In one embodiment, the backside power rails 284 may have a thickness d5 in a range from about 5 nm to about 40 nm.

[0048] In operation 144, the procedure 100 ( Fig. 1B), further fabrication processes are performed on the device 200. For example, one or more interconnect layers may be formed on the backside of the device 200, passivation layers may be formed on the backside of the device 200, other BEOL processes may be performed, and the carrier 370 may be removed.

[0049] Now Fig. 1C, which shows an alternative embodiment of the method 100. In the alternative embodiment of the method 100, the method 100 may be performed after the operation 118 ( Fig. 1A), in which a CMP process exposes surfaces of the S / D contact 282, the S / D cap layer 276 and the B-SAC layer 203, optionally to the operation 120 ( Fig. 1C) before continuing with operation 130. The alternative embodiment of the method 100 is described below in connection with Fig. 17A to 24E, in which the manufacturing operations are explained after the Fig. 9A to 9E is formed. Some aspects in the alternative embodiment of the method 100 are the same as described above and are briefly described below.

[0050] In operation 120, in the method 100 ( Fig. 1C), the S / D cap layer 276 above the drain feature 260 is removed by an etching process. The resulting structure according to one embodiment is shown in Fig. 17A to 17E. The trench 272 above the drain feature 260 reappears after the removal of the S / D cap layer 276, exposing a surface of the drain feature 260 and sidewalls of the inner spacers 255. In the illustrated embodiment, the etch process also etches the drain feature 260 to recess it to a height equal to or below the interface between the isolation structure 230 and the CESL 269 to increase the size of the trench 272. As will be explained in more detail below, the trench 272 becomes part of the air gaps and increases the volumes of the air gaps, advantageously further reducing the coupling capacitance between various features in the device 260. In some embodiments, more than one etch process may be applied during operation 120.For example, a first etching process may be applied to selectively remove the S / D cap layer 276, and then a second etching process may be applied to selectively recess the drain feature 260 to a desired height, wherein different etching parameters, e.g., different etchants, are used in the first and second etching processes. In one embodiment, the first etching process comprises a dry etching process (plasma etching process) which is adjusted to selectively etch the S / D cap layer 276 and not (or only minimally) etch the isolation structure 230, the B-SAC layer 203, the inner spacers 255, and the source feature 260. In alternative embodiments, other types of etching (e.g., wet etching or reactive ion etching) may be applied in the first etching process, provided that the etch selectivity between the layers is achieved as described above.Since the first etching process does not etch, or only minimally etch, the isolation structure 230, the B-SAC layer 203, and the inner spacers 255, the trench 272 aligns itself with the drain feature 260 in the yz-plane and in the xz-plane, thereby improving the process window. The second etching process may be dry etching, wet etching, reactive ion etching, or other suitable etching processes to selectively recess the drain feature 260 to the desired height.

[0051] After the operation 120 the procedure goes 100 ( Fig. 1C) to operation 130, wherein the B-SAC layer 203 is selectively etched to recess the B-SAC layer 203 to below a surface of the S / D contact 282 and the isolation structure 230. The resulting structure according to one embodiment is shown in Fig. 18A to 18E. In the present embodiment, operation 130 applies an etching process that is selective for the dielectric materials of the B-SAC layer 203 and does not etch (or only minimally etch) the S / D contact 282, the internal spacers 255, the drain feature 260, and the isolation structure 230. The etching process may be a dry plasma etch, a dry chemical etch, an ashing process, a wet etch, or other suitable etching processes. As a result of operation 130, portions of sidewalls of the S / D contact 282 and the isolation structure 230 protrude a distance d2 from the B-SAC layer 203. The distance d2 may be controlled by adjusting the duration of the etching process. In some embodiments, the distance d2 is in a range from about 2 nm to about 20 nm.

[0052] In operation 132, in the method 100 ( Fig. 1C) a dielectric lining 304 is applied to the back of the device 200. The resulting structure according to one embodiment is shown in Fig. 19A to 19E. In the illustrated embodiment, the dielectric liner 304 is conformally deposited to have a substantially uniform thickness along the various surfaces of the B-SAC layer 203, the isolation structure 230, the S / D contact 282, and the trench 272, including the sidewalls of the inner spacers 255 and a top surface of the drain feature 260. In various embodiments, the dielectric liner 304 may include La2O3, Al2O3, SiOCN, SiOC, SiCN, SiO2, SiC, ZnO, ZrN, Zr2Al3O9, TiO2, TaO2, ZrO2, HfO2, Si3N4, Y2O3, AlON, TaCN, ZrSi, combinations thereof, or other suitable material(s). The dielectric liner 304 may be formed by ALD, CVD, or other suitable processes and, in various embodiments, may have a thickness of about 0.5 nm to about 10 nm (e.g., measured at the sidewalls of the S / D contact 282 along the "x" direction).

[0053] In operation 134, in the method 100 ( Fig. 1C) a BT etching process is performed to break through and remove the majority of the horizontal sections of the dielectric liner 304. The resulting structure is shown in Fig. 20A to 20E. In some embodiments, the BT etch process may include an anisotropic dry etch process or the like. In some embodiments, when the dielectric liner 304 is formed from a compound oxide, the BT etch process is a reactive ion etch (RIE) process with etch process gases including CHF3, Ar, CF4, N2, O2, CH2F2, SF3, the like, or a combination thereof. In the illustrated embodiment, as a result of operation 134, portions of the dielectric liner 304 remain on sidewalls of the S / D contact 282, the trench 272, and the isolation structure 230. The portion of the dielectric liner 304 on the sidewalls of the trench contacts the drain feature 260.

[0054] In operation 136, in the method 100 ( Fig. 1C) the B-SAC layer 203 is removed in an etching process. The resulting structure according to one embodiment is shown in Fig. 21A to 21E. In the illustrated embodiment, the removal of the B-SAC layer 203 exposes the gate stack 240 and results in gaps 333 between the dielectric liner 304 on the sidewall of the S / D contact 282 and the gate stack 240. The gaps 333 are located directly below the dielectric liner 304 on the sidewall of the S / D contact 282 and above the gate stack 240. In various embodiments, a vertical distance d3 between the dielectric liner 304 on the sidewall of the S / D contact 282 and the gate stack 240 is in a range from about 0.5 nm to about 10 nm. In addition, due to the removal of the B-SAC layer 203, the dielectric liner 304 on sidewalls of the trench 272 protrudes from the gate stack 240. The projection distance is approximately equal to d3.In other words, one end of the dielectric liner 304 at the sidewalls of the S / D contact 282 and one end of the dielectric liner 304 at the sidewalls of the trench 272 are at the same height. In the yz-plane, the dielectric liner 304 further covers the sidewalls of the trench 272 and remains flush with a top surface of the isolation structure 230, as shown in FIG. Fig. 21E. In one embodiment, the etching process may include a dry plasma etch, a dry chemical etch, an ashing process, a wet etch, or other suitable etching processes.

[0055] In operation 138, in the method 100 ( Fig. 1C), a sealing layer 312 is applied over the backside of the device 200, and air gaps 314 are covered vertically between the gate stack 240 and the sealing layer 312. The resulting structure according to one embodiment is shown in Fig. 22A to 22E. The structure of the device 200 and the formation of the sealing layer 312 are adjusted to effectively close the space horizontally between adjacent (or neighboring) S / D contacts 282, resulting in the air gaps 314. In particular, the protruding adjacent S / D contacts 282 (one is shown in Fig. 22B) as pillars that support the sealing layer 312 formed thereon. The distance between two adjacent S / D contacts 282 is set in a range that facilitates the capping process. The dielectric liner 304 further narrows the opening in an upper portion of the space between two adjacent S / D contacts 282. Furthermore, the dielectric liner 304 provides a landing field for the accumulation of the deposited dielectric material. In some embodiments, the dielectric liner 304 has a hydrophilic property, so that it is easier to accumulate dielectric material than with the metallic surfaces of the S / D contact 282. In some embodiments, due to covalent bonds between similar material compositions of the dielectric liner 304 and the deposited dielectric material (e.g.,both comprise oxides) to more easily accumulate the deposited dielectric material on the dielectric liner 304. In some embodiments, the deposited material of the sealing layer 312 includes La2O3, Al2O3, SiOCN, SiOC, SiCN, SiO2, SiC, ZnO, ZrN, Zr2Al3O9, TiO2, TaO2, ZrO2, HfO2, Si3N4, Y2O3, AlON, TaCN, ZrSi, combinations thereof, or other suitable material(s). In some embodiments, the sealing layer 312 and the dielectric liner 304 may have the same dielectric material composition.

[0056] The sealing layer 312 can be formed by CVD, PVD, PE-CVD, a coating process, or another suitable process. In one embodiment, the sealing layer 312 is deposited by a PE-CVD process, in which it is easier for deposited dielectric materials to coalesce at the top of a narrow opening. The parameters in the PE-CVD process (e.g., pressure, temperature, and gas viscosity) are adjusted so that the gap-filling behavior of deposited dielectric materials maintains the air gap without filling the space between two adjacent S / D contacts 282. The sidewalls of the S / D contact 282, the isolation structure 230, and the dielectric liner 304 are exposed in the air gaps 314. The trench 272 becomes part of the air gaps 314, thereby increasing the volume of the air gaps.The dielectric liner 304 on the sidewalls of the trench 272 has a distance d6 from the sealing layer 312, which in some embodiments ranges from about 0.5 nm to about 10 nm. The distance d6 enables the trench 272 to be in fluid communication with two adjacent air gaps 314, thereby forming a larger air gap extending between two adjacent S / D contacts 282. A gas may be present in the air gaps, e.g., a gas(es) used during the deposition of the dielectric material of the sealing layer 312, or any other species that may diffuse into the air gaps 314. The sealing layer 312 extends laterally from the air gaps 314 to upper surfaces of the S / D contact 282.The sealing layer 312 also covers a top surface and a portion of the sidewall of the dielectric liner 304 applied to the sidewalls of the S / D contact 282.

[0057] In operation 140, in the method 100 ( Fig. 1C), a CMP process is performed on the sealing layer 312 to remove excess dielectric materials from the surface of the S / D contact 282. The resulting structure according to one embodiment is shown in Fig. 23A to 23E. Because the sealing layer 312 comprises different materials than the S / D contact 282, the S / D contact 282 may act as a CMP stop when the device 200 is planarized by the CMP process. After operation 140, the air gaps 314 remain covered by the sealing layer 312, and back surfaces of the S / D contact 282 are exposed. After operation 140, the remaining sealing layer 312 is disposed between the opposing dielectric liners 304 on sidewalls of two adjacent S / D contacts 282. In some embodiments, the remaining sealing layer 312 after operation 140 has a thickness in a range from about 0.5 nm to about 10 nm.

[0058] In operation 142, in the method 100 ( Fig. 1C) a metal wiring layer, e.g., rear bus bars 284, is formed on the back of the device 200. The resulting structure according to one embodiment is shown in Fig. 24A to 24E. As shown in Fig. 24B and Fig. 24D, the back S / D contact 282 is electrically connected to the back bus bars 284. In one embodiment, the back bus bars 284 may be formed by a damascene process, a double damascene process, a metal patterning process, or other suitable processes. The back bus bars 284 may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), nickel (Ni), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or other metals and may be deposited by CVD, PVD, ALD, plating, or other suitable processes. In one embodiment, the back bus bars 284 may have a thickness d5 in a range of about 5 nm to about 40 nm.

[0059] In operation 144, the procedure 100 ( Fig. 1C), further fabrication processes are performed on the device 200. For example, one or more interconnect layers may be formed on the backside of the device 200, passivation layers may be formed on the backside of the device 200, other BEOL processes may be performed, and the carrier 370 may be removed.

[0060] Now Fig. 1D, which shows yet another alternative embodiment of the method 100. In this second alternative embodiment of the method 100, the method 100 may be performed after the operation 118 ( Fig. 1A), in which a CMP process exposes surfaces of the S / D contact 282, the S / D cap layer 276 and the B-SAC layer 203, optionally to the operation 131 ( Fig. 1D) before proceeding to operation 132, and operation 130 may be omitted. The second alternative embodiment of the method 100 is described below in connection with Fig. 25A to 30E, in which the manufacturing operations are explained after the Fig. 9A to 9E is formed. Some aspects in the second alternative embodiment of the method 100 are the same as described above and are briefly described below.

[0061] In operation 131, in the method 100 ( Fig. 1D) the B-SAC layer 203 is removed in an etching process. The resulting structure according to one embodiment is shown in Fig. 25A to 25E. In the illustrated embodiment, the removal of the B-SAC layer 203 removes a top surface of the gate stack 240 and sidewalls of the S / D contact 282 and the S / D cap layer 276. In one embodiment, the etching process may include a dry plasma etch, a dry chemical etch, an ashing process, a wet etch, or other suitable etching processes.

[0062] After the operation 131, the procedure goes 100 ( Fig. 1D) proceeds to operation 132, wherein a dielectric lining 304 is applied to the back of the device 200. The resulting structure according to one embodiment is shown in Fig. 26A to 26E. In the illustrated embodiment, the dielectric liner 304 is conformally deposited to have a substantially uniform thickness along the various surfaces of the top surface of the gate stack 240 and the top and sidewall surfaces of the isolation structure 230, the S / D contact 282, and the S / D cap layer 276. In various embodiments, the dielectric liner 304 may include La2O3, Al2O3, SiOCN, SiOC, SiCN, SiO2, SiC, ZnO, ZrN, Zr2Al3O9, TiO2, TaO2, ZrO2, HfO2, Si3N4, Y2O3, AlON, TaCN, ZrSi, combinations thereof, or other suitable material(s). The dielectric liner 304 may be formed by ALD, CVD, or other suitable processes and, in various embodiments, may have a thickness of about 0.5 nm to about 10 nm (e.g., measured at the sidewalls of the S / D contact 282 along the "x" direction).

[0063] In operation 134, in the method 100 ( Fig. 1D) a BT etching process is performed to break through and remove the majority of the horizontal sections of the dielectric liner 304. The resulting structure is shown in Fig. 27A to 27E. In some embodiments, the BT etching process may include an anisotropic dry etching process or the like. In some embodiments, when the dielectric liner 304 is formed from a compound oxide, the BT etching process is a reactive ion etching (RIE) process with etching gases including CHF3, Ar, CF4, N2, O2, CH2F2, SF3, the like, or a combination thereof. In the illustrated embodiment, as a result of operation 134, portions of the dielectric liner 304 remain on sidewalls of the S / D contact 282, the S / D cap layer 276, and the isolation structure 230, extending from a back surface of the gate stack 240 (particularly from the inner spacers 255) to top surfaces of the S / D contact 282, the S / D cap layer 276, and the isolation structure 230.A vertical length of the dielectric liner 304 is in a range of about 2 nm to about 10 nm in some embodiments.

[0064] In operation 138, in the method 100 ( Fig. 1D), a sealing layer 312 is applied over the backside of the device 200, and air gaps 314 are covered vertically between the gate stack 240 and the sealing layer 312. The resulting structure according to one embodiment is shown in Fig. 28A to 28E. The structure of the device 200 and the formation of the sealing layer 312 are adjusted to effectively close the space horizontally between the S / D contact 282 and the S / D cap layer 276, resulting in the air gaps 314. In particular, the protruding S / D contact 282 and the S / D cap layer 276 act as pillars that support the sealing layer 312 formed thereon. As described above, the distance between the S / D contact 282 and the S / D cap layer 276 is adjusted within a range that facilitates the capping process. The dielectric liner 304 further narrows the opening in an upper portion of the space between the S / D contact 282 and the S / D cap layer 276. Furthermore, the dielectric liner 304 provides a landing field for the accumulation of the deposited dielectric material.In some embodiments, the dielectric liner 304 has a hydrophilic property, making it easier to accumulate dielectric material than the metallic surfaces of the S / D contact 282. In some embodiments, due to covalent bonds between similar material compositions of the dielectric liner 304 and the deposited dielectric material (e.g., both comprise oxides), the deposited dielectric material is easier to accumulate on the dielectric liner 304. In some embodiments, the deposited material of the sealing layer 312 includes La2O3, Al2O3, SiOCN, SiOC, SiCN, SiO2, SiC, ZnO, ZrN, Zr2Al3O9, TiO2, TaO2, ZrO2, HfO2, Si3N4, Y2O3, AlON, TaCN, ZrSi, combinations thereof, or other suitable material(s). In some embodiments, the sealing layer 312 and the dielectric liner 304 may have the same dielectric material composition.In some alternative embodiments, the sealing layer 312 and the dielectric liner 304 may have different dielectric material compositions.

[0065] Sealing layer 312 may be formed by CVD, PVD, PE-CVD, a coating process, or another suitable process. In one embodiment, sealing layer 312 is deposited by a PE-CVD process, in which it is easier for deposited dielectric materials to coalesce at the top of a narrow opening. The parameters in the PE-CVD process (e.g., pressure, temperature, and gas viscosity) are adjusted so that the gap-filling behavior of deposited dielectric materials maintains the air gap without filling the space between S / D contact 282 and S / D cap layer 276. Thus, the dielectric material of the sealing layer 312 can be applied in the upper portion between the dielectric liner 304 to enclose the space between the S / D contact 282 and the S / D cap layer 276 without applying a significant amount in a lower portion of the space.Corresponding air gaps 314 may therefore be formed below the dielectric material of the sealing layer 312 and above the gate stack 240 and surrounded by sidewalls of the dielectric liner 304, which extends from the gate stack 240 into the sealing layer 312. A gas may be present in the air gaps, e.g., a gas(es) used during the deposition of the dielectric material of the sealing layer 312, or any other species that can diffuse into the air gaps 314. The sealing layer 312 extends laterally from the air gaps 314 to upper surfaces of the S / D contact 282 and the S / D cap layer 276. The sealing layer 312 also covers a top surface and a portion of the sidewall of the dielectric liner 304.

[0066] In operation 140, in the method 100 ( Fig. 1D), a CMP process is performed on the sealing layer 312 to remove excess dielectric materials from the surface of the S / D contact 282. The resulting structure according to one embodiment is shown in Fig. 29A to 29E. Because the sealing layer 312 comprises different materials than the S / D contact 282, the S / D contact 282 may act as a CMP stop when the device 200 is planarized by the CMP process. After operation 140, the air gaps 314 remain covered by the sealing layer 312, and upper surfaces of the S / D contact 282 and the S / D cap layer 276 are exposed. After operation 140, the remaining sealing layer 312 is disposed between the opposing dielectric liners 304. In some embodiments, the remaining sealing layer 312 after operation 140 has a thickness in a range from about 0.5 nm to about 10 nm.

[0067] In operation 142, in the method 100 ( Fig. 1D) a metal wiring layer, e.g., rear bus bars 284, is formed on the back of the device 200. The resulting structure according to one embodiment is shown in Fig. 30A to 30B. As shown in Fig. 30B and Fig. 30D, the back S / D contact 282 is electrically connected to the back bus bars 284. In one embodiment, the back bus bars 284 may be formed by a damascene process, a double damascene process, a metal patterning process, or other suitable processes. The back bus bars 284 may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), nickel (Ni), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or other metals and may be deposited by CVD, PVD, ALD, plating, or other suitable processes. In one embodiment, the back bus bars 284 may have a thickness d5 in a range from about 5 nm to about 40 nm.

[0068] In operation 144, the procedure 100 ( Fig.1D), further fabrication processes are performed on the device 200. For example, one or more interconnect layers may be formed on the backside of the device 200, passivation layers may be formed on the backside of the device 200, other BEOL processes may be performed, and the carrier 370 may be removed.

[0069] Although not intended to be limiting, embodiments of the present disclosure provide one or more of the following advantages. For example, in embodiments of the present disclosure, air gaps are formed that are disposed between gate stacks and backside wiring layers. This advantageously reduces coupling capacitance in the device, which helps the circuit operate faster. Additionally, in embodiments of the present disclosure, the risk of paths for leakage currents between gate stacks and backside wiring layers is minimized. Furthermore, in embodiments of the present disclosure, backside wiring layers, e.g., backside power rails, are formed to increase the number of metal lines available in an integrated circuit and to increase gate density for greater device integration.Embodiments of the present disclosure can be easily integrated into existing semiconductor manufacturing processes.

[0070] In one exemplary aspect, the present disclosure relates to a method. The method includes providing a structure having a front side and a back side, the structure comprising a substrate, a first dielectric layer over the substrate, one or more semiconductor channel layers over the first dielectric layer connecting a first source / drain (S / D) feature and a second S / D feature, and a gate structure engaging the one or more semiconductor channel layers, the substrate being on the back side of the structure and the gate structure being on the front side of the structure; etching the substrate from the back side of the structure to form a first trench exposing the first S / D feature and a second trench,which exposes the second S / D feature; forming an S / D contact in the first trench; etching at least a portion of the first dielectric layer, resulting in a portion of the S / D contact protruding from the first dielectric layer on the backside of the structure; and depositing a sealing layer over the S / D contact, wherein the sealing layer covers an air gap between the gate structure and the sealing layer. In some embodiments, the method further comprises forming a dielectric liner on sidewalls of the portion of the S / D contact,wherein the sealing layer is in contact with the dielectric liner. In some embodiments, etching at least the portion of the first dielectric layer comprises completely removing the first dielectric layer prior to forming the dielectric liner. In some embodiments, forming the dielectric liner comprises conformally depositing the dielectric liner on the backside of the structure and anisotropically etching the dielectric liner.whereby the dielectric lining is removed from a top surface of the S / D contact. In some embodiments, the method further comprises depositing a second dielectric layer to fill the second trench prior to forming the S / D contact in the first trench. In some embodiments, the method further comprises etching the second dielectric layer to expose the second S / D feature after forming the S / D contact in the first trench. In some embodiments, the method further comprises thinning the sealing layer, thereby exposing the S / D contact; and forming a metal wiring layer on the backside of the structure,wherein the metal wiring layer is in contact with the S / D contact. In some embodiments, depositing the sealing layer comprises a plasma-enhanced chemical vapor deposition (PE-CVD) process. In some embodiments, the air gap extends vertically from a surface of the gate structure to a surface of the sealing layer for a distance in the range of about 0.5 nm to about 10 nm.

[0071] In another exemplary aspect, the present disclosure relates to a method. The method includes providing a structure having a front side and a back side, the structure comprising a substrate, a semiconductor fin over the substrate, a first source / drain (S / D) feature and a second S / D feature over the semiconductor fin, a dielectric cap layer over the semiconductor fin, one or more semiconductor channel layers over the dielectric cap layer connecting the first and second S / D features, and a gate structure engaging the one or more semiconductor channel layers, the substrate being on the back side of the structure and the gate structure being on the front side of the structure; thinning the structure from the back side of the structure until the semiconductor fin is exposed; etching the semiconductor fin from the back side of the structure,to form a first trench exposing the first S / D feature and a second trench exposing the second S / D feature; depositing a dielectric layer in the second trench; forming an S / D contact in the first trench; recessing the dielectric cap layer from the backside of the structure, thereby exposing sidewalls of the S / D contact; forming a dielectric liner on the sidewalls of the S / D contact; depositing a sealing layer over the S / D contact, resulting in an air gap disposed between the gate structure and the sealing layer; and forming a metal wiring layer over the sealing layer,wherein the metal wiring layer electrically connects to the S / D contact. In some embodiments, recessing the dielectric layer prior to forming the dielectric liner exposes a surface of the gate structure. In some embodiments, after forming the dielectric liner, the method further comprises removing the dielectric cap layer, thereby creating a gap between the dielectric liner and the gate structure. In some embodiments, recessing the dielectric cap layer further exposes sidewalls of the dielectric layer, wherein forming the dielectric liner comprises forming the dielectric liner on the sidewalls of the dielectric layer. In some embodiments, the method further comprises etching the dielectric layer,to expose a surface of the second S / D feature and sidewalls of the dielectric cap layer prior to forming the dielectric liner, wherein forming the dielectric liner comprises forming the dielectric liner on the sidewalls of the dielectric cap layer. In some embodiments, the air gap extends vertically from the surface of the second S / D feature to a surface of the sealing layer. In some embodiments, the method further comprises thinning the sealing layer to expose the S / D contact prior to forming the metal wiring layer.

[0072] In yet another exemplary aspect, the present disclosure relates to a semiconductor structure. The semiconductor structure includes first and second source / drain (S / D) features; one or more semiconductor channel layers connecting the first and second S / D features; a gate structure engaging the one or more semiconductor channel layers, wherein the first and second S / D features, the one or more semiconductor channel layers, and the gate structure are located on a front side of the semiconductor structure; a metal wiring layer on a back side of the semiconductor structure; and a sealing layer between the metal wiring layer and the gate structure, the sealing layer being spaced from the gate structure by an air gap therebetween.In some embodiments, the semiconductor structure further comprises an S / D contact electrically connecting to the first S / D feature; and a dielectric liner on sidewalls of the S / D contact, wherein the dielectric liner is in contact with the sealing layer. In some embodiments, the dielectric liner is spaced from the gate structure by the air gap. In some embodiments, the semiconductor structure further comprises a dielectric liner extending from a surface of the second S / D feature toward the sealing layer, wherein the dielectric liner is spaced from the sealing layer by the air gap.

Claims

[1] Procedure (100), comprising: Providing a structure with a front and a back side, wherein the structure comprises a substrate (201), a first dielectric layer (203) over the substrate (201), one or more semiconductor channel layers (215) over the first dielectric layer (203) connecting a first source / drain feature (S / D feature) (260) and a second S / D feature (260), and a gate structure (240) engaging with the one or more semiconductor channel layers (215), wherein the substrate (201) is located on the back side of the structure and the gate structure (240) is located on the front side of the structure; Etching the substrate (201) from the back of the structure to form a first trench (272) exposing the first S / D feature (260) and a second trench (272) exposing the second S / D feature (260); Forming an S / D contact (282) in the first trench (272); Etching at least a section of the first dielectric layer (203), resulting in a section of the S / D contact (282) protruding from the first dielectric layer (203) on the back side of the structure; and Deposition of a sealing layer (312) over the S / D contact (282), wherein the sealing layer (312) covers an air gap (314) between the gate structure (240) and the sealing layer (312). [2] The method of claim 1, further comprising: Forming a dielectric lining (304) on side walls of the section of the S / D contact (282), wherein the sealing layer (312) is in contact with the dielectric lining (304). [3] Method according to claim 2, wherein the etching of at least the section of the first dielectric layer (203) comprises the complete removal of the first dielectric layer (203) prior to the formation of the dielectric lining (304). [4] Method according to claim 2 or 3, wherein forming the dielectric lining (304) comprises: Shape-adapted deposition of the dielectric lining (304) on the back side of the structure; and anisotropic etching of the dielectric lining (304), whereby the dielectric lining (304) is removed from an upper surface of the S / D contact (282). [5] Method according to any one of the preceding claims, further comprising: Deposition of a second dielectric layer (276) to fill the second trench (272) prior to forming the S / D contact (282) in the first trench (272). [6] The method of claim 5, further comprising: Etching of the second dielectric layer (276) to expose the second S / D feature (260) after forming the S / D contact (282) in the first trench (272). [7] Method according to any one of the preceding claims, further comprising: Thinning the sealing layer (312), thereby exposing the S / D contact (282); and Forming a metal wiring layer (284) on the back of the structure, wherein the metal wiring layer (284) is in contact with the S / D contact (282). [8] Method according to any of the preceding claims, wherein the deposition of the sealing layer (312) comprises a plasma-enhanced chemical deposition from the gas phase (PE-CVD) method. [9] Method according to one of the preceding claims, wherein the air gap (314) extends vertically from a surface of the gate structure (240) to a surface of the sealing layer (312) for a distance in the range of about 0.5 nm to about 10 nm. [10] Procedures, including: Providing a structure with a front and a back side, wherein the structure comprises a substrate (201), a semiconductor fin (204) over the substrate (201), a first source / drain feature (S / D feature) (260) and a second S / D feature (260) over the semiconductor fin (204), a dielectric cover layer (203) over the semiconductor fin, one or more semiconductor channel layers (215) over the dielectric cover layer (203) connecting the first and second S / D features (260), and a gate structure (240) engaging with the one or more semiconductor channel layers (215), wherein the substrate (201) is located on the back side of the structure and the gate structure (240) is located on the front side of the structure; thinning the structure from the back side of the structure until the semiconductor fin (204) is exposed; Etching the semiconductor fin (204) from the back side of the structure to form a first trench (272) that exposes the first S / D feature (260) and to form a second trench (272) that exposes the second S / D feature (260); Deposition of a dielectric layer (276) in the second trench (272); Forming an S / D contact (282) in the first trench (272); Recessing the dielectric cover layer (203) from the back of the structure, thereby exposing side walls of the S / D contact (282); Forming a dielectric lining (304) on the side walls of the S / D contact (282); Deposition of a sealing layer (312) over the S / D contact (282), resulting in an air gap (314) arranged between the gate structure (240) and the sealing layer (312); and Forming a metal wiring layer (284) over the sealing layer (312), wherein the metal wiring layer (284) electrically connects to the S / D contact (282). [11] Method according to claim 10, wherein by removing the dielectric cover layer (203) prior to forming the dielectric lining (304) an area of ​​the gate structure (240) is exposed. [12] Method according to claim 10 or 11, further comprising: Removing the dielectric cover layer (203) after forming the dielectric lining (304), thereby creating a gap between the dielectric lining (304) and the gate structure (240). [13] Method according to any one of claims 10 to 12, wherein by removing the dielectric cover layer (203) side walls of the dielectric layer (276) are also exposed and wherein the formation of the dielectric lining (304) comprises the formation of the dielectric lining (304) on the side walls of the dielectric layer (276). [14] Method according to any one of claims 10 to 13, further comprising: Etching of the dielectric layer (276) to expose an area of ​​the second S / D feature (260) and side walls of the dielectric cover layer (203) prior to the formation of the dielectric lining (304), wherein the formation of the dielectric lining (304) includes the formation of the dielectric lining (304) on the side walls of the dielectric cover layer (203). [15] Method according to claim 14, wherein the air gap (314) extends vertically from the surface of the second S / D feature (260) to a surface of the sealing layer (312). [16] Method according to any one of claims 10 to 15, further comprising: Thinning the sealing layer (312) to expose the S / D contact (282) before forming the metal wiring layer (284). [17] Semiconductor structure, having: a first and a second source / drain feature (S / D feature) (260); one or more semiconductor channel layers (215) connecting the first and second S / D feature (260); a gate structure (240) which engages with the one or more semiconductor channel layers (215), wherein the first and second S / D feature (260), the one or more semiconductor channel layers (215) and the gate structure (240) are located on a front face of the semiconductor structure; a metal wiring layer (284) on a back side of the semiconductor structure; and a sealing layer (312) between the metal wiring layer (284) and the gate structure (240), wherein the sealing layer (312) is spaced apart from the gate structure (240) by an air gap (314) in between. [18] Semiconductor structure according to claim 17, further comprising: an S / D contact (282) that electrically connects to the first S / D feature (260); and a dielectric lining (304) on side walls of the S / D contact (282), wherein the dielectric lining (304) is in contact with the sealing layer (312). [19] Semiconductor structure according to claim 18, wherein the dielectric lining (304) is spaced apart from the gate structure (240) by the air gap (314). [20] Semiconductor structure according to any one of claims 17 to 19, further comprising: a dielectric lining (304) which extends from a surface of the second S / D feature (260) in the direction of the sealing layer (312), wherein the dielectric lining (304) is spaced apart from the sealing layer (312) by the air gap (314).

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