NEUROMORPHIC CIRCUIT STRUCTURE AND METHOD FOR MAKING THE SAME

Abstract

Neuromorphic circuit structure (100), comprising: a first vertically extending neural node (102A) configured to generate an output signal based on at least one input to the first vertically extending neural node (102A); a connection stack (104) adjacent to the vertically extending neural node (102A), wherein the connection stack (104) includes a first conductor (106) coupled to the first vertically extending neural node (120A) and configured to receive the output signal, wherein a second conductor (108) is vertically separated from the first conductor (106), and wherein a memory via (114) vertically couples the first conductor (106) to the second conductor (108); and a second vertically extending neural node (102B) next to the connection stack (104), wherein the second vertically extending neural node (102B) is coupled to the second conductor (108) for receiving the output signal from the first vertically extending neural node (102A).

Description

Technical field

[0001] The present invention relates generally to the technology of artificial neural networks (ANNs). The invention relates in particular to neuromorphic circuit structures configured to use ANNs and corresponding methods for fabricating them. background

[0002] The creation and use of artificial neural networks (ANNs) is a rapidly developing sector of electronics. ANNs provide a signal processing infrastructure in which a product remembers frequently used signal processing pathways and applies them in future operations. ANNs enable a product to remember, learn, and predict various electronic processes to meet different needs. The ANN infrastructure is crucial for delivering machine learning capabilities in a product. The performance of the ANN infrastructure depends on the performance of its individual components. In a natural neural network, such as the human central nervous system, individual nerve cells define fan-in / fan-out connections that can link a single cell to over ten thousand other cells.Conventional ANN infrastructure is far less powerful than natural neural networks and generally offers fewer than ten connections between a given artificial neuron and interconnected artificial neurons in the same network.

[0003] Various ANN architectures have attempted, with limited success, to increase the number of connections between individual neurons. Most commonly, an ANN can provide a stack of memory elements to connect the input from one array of neurons to the output from another. However, as the size of devices and components continues to shrink, such an arrangement is incompatible with most device architectures. Other proposed ANN configurations offer only hypothetical processing paths between individual neurons, without describing the infrastructure necessary to create such paths within a device. The ever-increasing complexity of ANN designs and device hardware also presents a barrier to the mass production of ANN technology at reasonable costs.

[0004] Document DE 11 2008 003 510 T5 relates to micro- and nanoscale neuromorphic integrated hybrid circuits comprising an array of analog computation cells fabricated on an integrated circuit substrate. The analog electronic circuitry within each computation cell is connected to one or more pins of a first type and to one or more pins of a second type, extending approximately vertically from the computation cells. The computation cells are further interconnected by one or more nanowire interconnection layers, each nanowire interconnection layer comprising two nanowire sublayers on either side of a memristive sublayer, with each nanowire in each nanowire sublayer of an interconnection layer being connected to a single computation cell pin and to a number of nanowires in the other nanowire sublayer of the interconnection layer.

[0005] Document DE 11 2010 004 470 B4 relates to a neuromorphic circuit comprising a first field-effect transistor in a first diode configuration, which establishes an electrical connection between a first gate and a first drain of the first field-effect transistor. The neuromorphic circuit also comprises a second field-effect transistor in a second diode configuration, which establishes an electrical connection between a second gate and a second drain of the second field-effect transistor. The neuromorphic circuit further comprises a variable-resistance material that is electrically connected to both the first drain and the second drain, the variable-resistance material providing a programmable resistance value.The neuromorphic circuit additionally includes a first connection that is electrically connected to the material with variable resistance and provides a first connection point to an output of a neuronal circuit, as well as a second connection that is electrically connected to the material with variable resistance and provides a second connection point to the output of the neuronal circuit.

[0006] Document US 2015 / 0088797A1 concerns a synaptic circuit connecting multiple neuronal circuits, the synaptic circuit comprising: a first memristor connected to a presynaptic neuronal circuit; a second memristor connected to the presynaptic neuronal circuit; and an adder configured to output a sum of signals, respectively, from the first and second memristor to a postsynaptic neuronal circuit. Summary

[0007] A first aspect of the present invention provides a neuromorphic circuit structure comprising: a first vertically extending neural node configured to generate an output signal based on at least one input to the first vertically extending neural node; a connection stack adjacent to the vertically extending neural node, the connection stack comprising a first conductor coupled to the first vertically extending neural node and configured to carry the output signal, a second conductor vertically separated from the first conductor, and a memory via connecting the first conductor to the second conductor;and a second vertically extending neural node adjacent to the connection stack, the second vertically extending node being coupled to the second conductor to receive the output signal from the first vertically extending neural node.

[0008] A second aspect of the present invention provides a neuromorphic circuit structure comprising: a first vertically extending neural node configured to receive at least one excitatory input signal and at least one inhibitory input signal, wherein the first vertically extending neural node generates an output signal based on the at least one excitatory input signal and the at least one inhibitory input signal;a connection stack adjacent to the vertically extending neural node, the connection stack comprising a plurality of conductive traces alternating with a plurality of dielectric layers, a first conductive trace of the connection stack being coupled to and configured to receive the output signal to the first vertically extending neural node, one of the plurality of dielectric layers separating the first conductive trace from a second conductive trace of the connection stack, and a storage via vertically connecting the first conductive trace to the second conductive trace; and a second vertically extending neural node adjacent to the connection stack, the second vertically extending neural node being connected to the second conductive trace to receive the output signal from the first vertically extending neural node.

[0009] A third aspect of the present invention provides a method for forming a neuromorphic circuit structure, the method comprising: forming a first conductor track; forming a dielectric layer on the first conductor track; forming a storage via within the dielectric layer in contact with the first conductor track; forming a second conductor track on the dielectric layer such that the storage via connects the second conductor track to the first conductor track; forming a first opening and a second opening by removing corresponding sections of the first conductor track, the dielectric layer, and the second conductor track at locations horizontally offset from the via, wherein the first opening is arranged directly longitudinally adjacent to the first conductor track and the second opening is arranged directly longitudinally adjacent to the second conductor track;a formation of a first and second vertically extending neural node, respectively, within the first opening and the second opening, wherein the first vertically extending neural node is coupled to the first conductor and the second vertically extending neural node is coupled to the second conductor. Brief description of the drawings

[0010] These and other features of this invention will become clearer from the following detailed description of the various aspects of the invention in conjunction with the accompanying drawings, which depict different embodiments of the invention, in which: Fig. Figure 1 shows a schematic representation of the signal pathways through an exemplary artificial neural network (ANN). Fig. Figure 2 shows a schematic top-down view of a neuromorphic circuit structure according to embodiments of the invention. Fig. Figure 3 shows a schematic cross-sectional view of a neuromorphic circuit structure according to embodiments of the invention. Fig. Figure 4 shows a perspective view of a neuromorphic circuit structure according to embodiments of the invention. Fig. Figure 5 shows an extended schematic cross-sectional view of a neural node and connection stack according to embodiments of the invention. Fig. Figure 6 shows a cross-sectional view of a formation of a first conductor track and a dielectric layer according to embodiments of the invention. Fig. Figure 7 shows a cross-sectional view of the formation of a storage via in the dielectric layer according to embodiments of the invention. Fig. Figure 8 shows a cross-sectional view of a formation of a second conductor track and a dielectric layer according to embodiments of the invention. Fig. Figure 9 shows a cross-sectional view of a formation of a connecting stack and a pair of openings according to embodiments of the invention. Fig. Figure 10 shows a cross-sectional view of a formation of vertically extending neural nodes next to the connection stack according to embodiments of the invention.

[0011] It should be noted that the drawings of the invention are not necessarily to scale. The drawings are intended to illustrate only typical aspects of the invention and should therefore not be considered to limit its essence. Similar numbering within the drawings indicates similar elements. Detailed description

[0012] The following description refers to the accompanying drawings, which form part thereof and clearly illustrate specific exemplary embodiments in which the present invention can be implemented. These embodiments are described in sufficient detail to enable a person skilled in the art to put the present teaching into practice. It is understood that other embodiments may be used and modifications may be made without departing from the scope of the present teachings. The following description is therefore for illustrative purposes only.

[0013] With reference to Fig. Figure 1 shows an example of an artificial neural network (ANN) 10. The ANN 10 can represent at least a part of one or more computer systems and / or software components that can be programmed, adapted, or otherwise used to implement various processes. Embodiments of the present invention can represent individual components that form part or all of a particular ANN 10.

[0014] The ANN 10 can be configured to provide a mathematical model (machine learning) that links one or more inputs 12 with one or more outputs 20. Since successive groups of inputs are passed to the ANN 10, the generated mathematical model can be adapted based on comparing different outputs with verified, ideal values ​​and / or other related groups of inputs and outputs. The inputs 12 denote signals provided to the ANN 10. An input layer 14 comprises one or more nodes (e.g., neural nodes 102), specifically individual structures, to generate one or more inputs for producing one or more outputs in a fan-in / fan-out configuration. Each node of the input layer 14 can, in turn, be connected to other nodes in a hidden layer 16 that implement specific mathematical functions.The inputs 12 for input layer 14 can include, for example, measurements, signals, commands, and / or other human or machine inputs that are passed to ANN 10 for processing. Each node of input layer 14 and / or hidden layer 16 can have its own set of inputs and outputs. Signals from different paths can represent different variables, operations, and / or other processes that influence the mathematical relationship between the inputs and outputs of ANN 10. Each node of hidden layer 16 can have a corresponding weight ("W"), which represents a factor or other mathematical adjustment for converting input signals into output signals. The nodes of hidden layer 16 can finally connect to an output layer 18, which transmits one or more signals as outputs 20 according to the inputs 12.

[0015] To enable a type of machine learning in ANN 10, signals at output layer 18 can be compared to predefined or ideal values ​​to calculate errors in a process, a process known as "error backpropagation." If the error between an output signal at output layer 18 and a predefined value exceeds a certain threshold, ANN 10 can have self-correcting functions. For example, process steps encoded in hardware and / or software can use values ​​at output layer 18 to adjust the weights W of hidden layer 16 and / or connections between nodes at input layer 14 and hidden layer 16.In an exemplary embodiment, error feedback can include "Bayesian regulation," a series of mathematical steps that use probability for weighting calculations to minimize the mean squared error (MSE) (i.e., the squared value of the difference between an output and a predetermined value, whether positive or negative) between values ​​in output layer 18 and the predetermined values. This aids in generalization and avoids data overload. Thus, ANN 10 can develop and adjust mathematical models by processing multiple inputs 12 to produce an output 20 and comparing the output 20 with corresponding estimates.

[0016] With a joint reference to the Fig. 2 and Fig. 3 A neuromorphic circuit structure (hereinafter simply a “structure”) 100 is shown according to various embodiments. Fig. Figure 2 represents the structure 100 in the XY plane according to a first exemplary embodiment, while Fig. 3 the structure 100 in the plane ZY according to a further exemplary embodiment. Various sections of the in Fig. The structure shown in Figure 2 appears at different locations within the structure. Fig. 3, to facilitate the illustration and to show possible variations between the embodiments. Additionally, some components of structure 100 are shown in Fig. 2 are shown with dashed lines to indicate that they are above or below the in Fig. The various components of the structure 100 discussed herein can be positioned in the XY cross-section shown in Figure 2. Despite possible differences in their position between the embodiments, the different components can be functionally consistent. The structure 100 can consist of several vertically extending neural nodes (hereinafter simply referred to as "neural nodes") 102 that extend transversely to the XY plane, e.g., as shown in Figure 2. Fig. Figure 3. It is understood that the structure 100 can have any number of neural nodes 102 which are interconnected according to the embodiments of the invention. In the structure 100 of the Fig. 2 and Fig. Figure 3 shows three neural nodes 102 to illustrate how other components can connect neural nodes 102 together.

[0017] The neuronal nodes 102 are analogous to individual nerve cells in a biological network. That is, each neuronal node 102 is structured to include one or more inputs (i.e., dendrites) for receiving signal inputs, which are processed and relayed to other neuronal nodes 102 in the structure 100. As explained in more detail below, neuronal nodes 102 can be structured to receive multiple excitatory and / or inhibitory inputs, which can be converted into an output signal and relayed to other neuronal nodes 102 and / or the output of ANN 10 ( Fig. 1) A fundamental feature of both natural and artificial neural networks is the network's ability to remember paths between individual cells over their lifetime, so that more frequent paths transmit signals faster when used repeatedly. In an artificial neural network such as ANN 10, neural nodes 102 each form one of the individual cells in a layer and can be connected to other cells via various pathways.

[0018] A neural node 102 of structure 100 can comprise a semiconductor substrate or be configured in some other way. In further examples, neural nodes 102 can have metallic conductors that may be configured planarly within structure 100. In the case of a semiconductor material, the substrate material of neural node 102 can comprise a base semiconductor material suitable for forming one or more devices, and in some cases, it can serve as a foundation for subsequently formed metal wiring layers of a structure. One or more substrate materials within neural node 102 can, for example, comprise one or more currently known or subsequently developed semiconductor substances that are generally used in semiconductor fabrication, including, but not limited to, silicon (e.g.,crystalline silicon), germanium, silicon germanium, silicon carbide and those which are essentially formed from one or more III-V compound semiconductors with a composition described by the formula Al. X1 Ga X2 In X3 As Y1 P Y2 N Y3 Sb Y4 is defined where X1, X2, X3, Y1, Y2, Y3, Y3, and Y4 represent relative fractions, each greater than or equal to zero, and X1+X2+X3+X3+Y1+Y2+Y2+Y3+Y3+Y3+Y4=1 (1 being the total relative molar quantity). Other suitable substrates are II-VI compound semiconductors with a Zn composition. A1 CD A2 See B1 Te B2, where A1, A2, B1, and B2 are relative fractions, each greater than or equal to zero, and A1 + A2 + B1 + B1 + B2 = 1 (1 being a total molar quantity). If neural node 102 includes a conductive material such as a metallic conductor, various components connected to it (e.g., input and output leads) may also include conductive metals configured to form a Schottky barrier, as mentioned elsewhere herein.

[0019] The structure 100 can include a connection stack 104 arranged adjacent to the neural node 102. The connection stack 104 can comprise several vertically stacked layers of an insulating material, each having one or more electrically conductive pathways 106, as shown in Fig. Figure 3 illustrates this. Each conductive wire provided in the interconnect stack 104 can be configured to transmit input signals to each neural node 102 or output signals from it. The interconnect stack 104 of structure 100 differs from conventional ANN technology in that each conductive layer is assigned to a specific type of signal, e.g., excitatory inputs, inhibitory inputs, outputs, etc. This stacked arrangement of conductive wires allows a circuit designer to interconnect neural nodes 102 according to a specific design and, as mentioned herein, enables a vertically extending memory via to connect the various layers of the interconnect stack 104. The interconnect stack 104 may, for example, include a first conductor 106 coupled to a neural node 102.The first conductor 106 can take the form of a metal wire made of any electrically conductive material currently known or subsequently developed, including, for example, copper (Cu), aluminum (Al), silver (Ag), gold (Au), combinations thereof, as well as non-metallic conductors such as carbon nanotubes, etc.

[0020] The connection stack 104 can also include one or more secondary conductors 108, each vertically separated from the first conductor(s) 106. The first and second conductors 106, 108 are shown with different cross-hatching to emphasize their function of transmitting different types of signals. Each conductor 106, 108 can be made of the same material or of different conductive materials. The second conductor can be electrically coupled to a different neural node 102. As shown, the first and second conductors 106, 108 can be at least partially vertically aligned with each other but connected to different neural nodes 102, e.g., 102A and 102B.The first conductor 106 can be positioned in a layer of the interconnect stack 104 configured to transmit output signals from respective neural nodes 102, while the second conductor 108 can be positioned in a layer of the interconnect stack 104 configured to transmit input signals to neural nodes 102. The interconnect stack 104 can also include a third conductor 110 electrically coupled to neural node 102 in parallel with the second conductor 108. In this arrangement, the second conductor 108 can transmit an excitatory input to neural node 102, while the third conductor 110 can transmit an inhibitory input to neural node 102. Internal features of each neural node 102 can process excitatory and inhibitory inputs to transmit an output signal via the first conductor 106. An example of such internal features of neural nodes 102 is shown in [reference missing]. Fig. 5 is shown and is explained in more detail elsewhere herein.

[0021] Each conductor track 106, 108, 110 can be positioned within a corresponding dielectric layer 112 of the interconnect stack 104. One or more dielectric layers 112 can be formed from any currently known or subsequently developed substance for electrical insulation, and examples include: silicon nitride (Si3N4), silicon dioxide (SiO2), fluorinated SiO2 (FSG), hydrogenated silicon dioxide (SiCOH), porous SiCOH, boron phosphosilicate glass (BPSG), silsesquioxanes, carbon (C)-doped oxides (i.e., organosilicates) containing atoms of silicon (Si), carbon (C), oxygen (O), and / or hydrogen (H), heat-curing polyarylene ethers, a silicon-carbon polymer material, near-frictionless carbon (NFC), or layers thereof. The various dielectric layers 112 of the interconnect stack are arranged in Fig. 3 are separately designated, i.e., as 112A, 112B, 112C. Each dielectric layer 112 may comprise only one type of conductor. For example, dielectric layer 112A may comprise at least one second conductor 108 for transmitting input signals to neural nodes 102, dielectric layer 112B may comprise at least one first conductor 106 for transmitting output signals from neural nodes 102, and insulator 112C may comprise at least one third conductor 110 for transmitting different input signals to neural nodes 102. In this arrangement, the interconnect stack 104 may be configured to have a predetermined number of input and / or output layers for transmitting signals to and from individual neural nodes 102.The connection stack 104 can vary in size between implementations and, in different embodiments, can have up to ten or more different memory vias 114, each connected to a corresponding conductor track 106, 108, 110 and corresponding sections of neural nodes 102. In contrast to conventional ANN structures, individual layers can have conductor tracks for inputs and / or outputs as well as memory elements, which allows for a less modular architecture and necessitates the formation of horizontally oriented neural nodes.

[0022] To electrically couple the neural nodes 102 of the structure 100, the connection stack 104 includes a set of storage vias 114, each of which vertically couples a corresponding pair of conductors 106, 108, 110. Fig. Figure 3 illustrates, in particular, memory vias 114 that extend vertically from the first conductor 106 to the second conductor 108. In this case, memory vias 114 can provide an output signal from the first conductor 106 to the second conductor 108, thereby transmitting an input signal to another neural node 102 of the structure 100. Memory vias 114 exhibit different material and electrical properties compared to conductors 106, 108, 110 and other conventional wiring or vias in electronics. Memory vias 114 provide a machine learning hardware with variable conductivity. At the time of fabrication, memory vias 114 may exhibit a state with higher electrical resistance compared to other conductive elements (e.g., conductors 106, 108, 110) of the structure 100.When an electric current flows along at least one storage via 114, its electrical resistance decreases proportionally to the amount of electric current. As signals continue to propagate through the structure 100, the storage via(s) 114 become increasingly conductive with increasing use. During operation of the structure 100, and because signals are repeatedly transmitted along certain paths, the storage vias 114 "remember" the preferred paths and offer lower electrical resistance along those paths. Meanwhile, less frequently used storage vias 114 will exhibit higher resistance. During operation, the varying resistance of the storage vias 114 causes frequently activated pathways to operate faster than less frequently activated pathways.

[0023] Storage vias 114 can comprise any currently known or subsequently developed electrical material with variable conductivity. The conductivity of the storage via(s) 114 can depend on previous levels of electrical current transmitted through them, as mentioned above. Storage vias 114 can be configured as unidirectional memristors, i.e., as a two-terminal electrical path configured to transmit signals in only one direction and with a resistance that depends on the past current flowing through the structure. Unidirectional memristors exhibit non-constant resistance and may initially have a high resistance before current is applied to their terminals. The electrical resistance of a memristor decreases in response to receiving and transmitting signals, as mentioned above, even after a power cycle of the device.The ability of a memristor to store and recall a specific electrical resistance is known in engineering as the non-volatile property. Memory Vias 114 can therefore include a unidirectional memristor or other switching elements exhibiting the non-volatile property or similar characteristics. For example, Memory Vias 114 can include a unidirectional memristor made of oxygen-depleted titanium oxide (TiO). 2-x) or other titanium oxide materials. Such materials exhibit non-volatile properties when processed into electrical cables or vias, e.g., Storage Vias 114. Storage Vias 114 in an exemplary embodiment can be directional or electrically rectifying to form unidirectional memristors for isolating different output traces from a common input trace. This can be achieved, for example, by integrating a Schottky barrier interface in series with the unidirectional memristor. Schottky barriers are generally formed by a metal contacting a lightly doped semiconductor. In this case, the Storage Vias 114 can include a unidirectional memristor electrically connected in series with a Schottky barrier diode.If a first connection represents a signal or pulse to an input connection, other output connections will not receive the signal because the Schottky barrier diodes block it in their respective storage vias.

[0024] According to the presentation in the Fig. 2 and Fig. 3. Memory vias 114 can extend vertically between aligned segments of two conductors, e.g., the first conductor 106 and the second conductor 108. In further examples, memory vias 114 can vertically connect any two vertically aligned segments of two conductors, such as the first, second, or third conductors 106, 108, 110. As mentioned elsewhere herein, the connection stack 104 can have any number of layers, each containing the conductors 106, 108, 110 for transmitting inputs and outputs between neural nodes 102. Memory vias 114 can thus vertically connect conductors 106, 108, 110 within the connection stack 104, forming a path between neural nodes 102.When signals are routed from one neural node 102 to another through specific storage vias 114, the transmitted signals can more easily traverse the frequently used and less resistive electrical pathways in the structure 100.

[0025] With reference to Fig. Figure 4 shows a partially perspective view of structure 100 to illustrate possible arrangements of neural nodes 102 and connecting stack(s) 104 between them. Fig. 4. One or more dielectric layers 112 are not shown for illustrative purposes. In the example of Fig. Each neural node 102 can extend vertically through the structure 100, with the conductors 106, 108, 110 extending radially outward from the neural node 102. The first conductors 106 can provide the fan-out connections from the neural node 102 when transmitting output signals. The second and third conductors 108, 110 can provide the fan-in connections to the neural node 102 when transmitting input signals. In each case, the storage vias 114 vertically connect different sets of conductors 106, 108, 110 to create an electrical path between neural nodes 102.

[0026] Fig. Figure 5 provides an extended cross-sectional view of the connection stack 104 along a neural node 102. As shown, the connection stack 104 can comprise a set of ten or more memory vias 114 for transferring outputs from a first neural node to inputs at other neural nodes. A neural node 102 can be electrically coupled to only selected traces 106, 108, 110 of the connection stack 104 or to every trace 106, 108, 110 of the connection stack 104. In the example of Fig. In section 5, a segment of neural node 102 receives an excitatory input signal from the second conductor 108, an inhibitory input signal from the third conductor 110, and generates an output signal at the first conductor 106. The in Fig. The structure shown in Figure 5 can, for example, represent a process for comparing positive excitatory inputs with positive inhibitory inputs to implement a logic function of the circuit. The neural node 102 can thus include a voltage-controlled monostable vibrator (“VCMV”) 116 for accepting two input signals, comparing the input signals, and generating an output signal based on the comparison between the two input signals. Although VCMV 116 in Fig. Since VCMV 5 is integrated into the neural node 102, it is understood that other circuit structures for generating an output signal based on one or more input signals are also possible. As is known in engineering, VCMV 116 can be formed within the substrate 102 by creating several doped regions of the semiconductor substrate and connecting these regions to each other via PN junctions, capacitive connections with opposite polarity, etc., to generate the desired electrical behavior.

[0027] A supply voltage (Vss) and a reference voltage (Vref) can be coupled to the VCMV 116 to provide gain and reference voltages during operation. Excitatory input signals to VCMV 116 from the second conductor track 108 can define a first input voltage (Vin1) to VCMV 116. Oppressive input signals to VCMV 116 from the third conductor track 110 can optionally define a second input voltage (Vin2) to VCMV 116. Each input voltage can be coupled to the supply voltage Vss via one or more inhibitory elements 120, which are generally represented as a corresponding parallel capacitive impedance element coupled between Vss and the first or second conductor track(s) 108, 110. Each voltage input can be transferred to a differential amplifier 120, which is configured to convert the exciting and inhibiting input signals into a differential input signal (Vdiff).The differential amplifier 120 can be configured to receive two different input signals and generate an output signal that represents the difference between the two received input signals. If only excitatory input signals enter the differential amplifier 120, Vdiff can be proportional to the excitatory input signals entering the differential amplifier 120. In contrast, Vdiff can be smaller than the original excitatory input signal if a combination of excitatory and inhibitory input pulses arrives at neural node 102.

[0028] The VCMV 116 can be configured to generate signal pulses when the magnitude of the differential input signal Vdiff exceeds a reference voltage (Vref) also supplied to the VCMV 116. A signal amplifier 122 receives Vdiff as the first input and Vref as the second input and can output signal pulses only when Vref is exceeded by Vdiff. Furthermore, signals generated in the signal amplifier 122 can have a frequency proportional to the magnitude of the difference between Vdiff and Vref. The reference voltage Vref can be provided by a current source other than Vss or by the supply voltage Vss. Thus, the VCMV 116 can be configured to generate an output voltage with a frequency that depends on the voltage difference between Vdiff and Vref.The combination of differential amplifier 120 and signal amplifier 122 thus enables the neural node 102 to receive excitatory and inhibitory reference signals from conductors 108 and 110 and to selectively generate output signal pulses on the first conductor 106. During operation, inhibitory input signals increase the required magnitude of excitatory input signals to generate signal pulses, allowing each neural node 102 to implement a specific logic function. The ability of the neural nodes 102 to communicate with each other via the interconnect stack 104 enables the structure 100 to function as an ANN architecture, for example, by sending and receiving signals via more common electrical pathways.

[0029] To Fig. Returning to point 6, embodiments of the invention can provide a method for forming the structure 100 ( Fig. 2-5). Embodiments of the method discussed herein can be operated to create any desired arrangement of neural nodes 102 ( Fig. 2-5), connection stack(s) 104 ( Fig. 2-5) and various subcomponents. First, methods according to the invention can include forming the various components of the connection stack 104 with a desired shape and subsequently forming neural nodes 102 for connecting the conductive elements within the connection stack 104.

[0030] According to one embodiment, the method may include forming the first conductive track 106 as a layer of a conductive material (e.g., on an underlying substrate, a dielectric layer, etc. – not shown). The first conductive track 106 may be formed by deposition to define a conductive path for transmitting signals to a subsequently formed neural node. As used herein, “deposition” or “laying down” of a material (e.g.,first conductor track 106) include any technique known today or developed later that is suitable for the material to be deposited, including, but not limited to, for example: chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), semi-atmospheric CVD (SACVD) and high-density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited reaction treatment CVD (LRPCVD), metal-organic CVD (MOCVD), sputtering, ion beam deposition, electron beam deposition, laser-assisted deposition, thermal oxidation, thermal nitriding, spin deposition, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating, evaporation, in addition to other deposition processes known today or developed later.The material deposited to form the first conductor track 106 may comprise one or more of the exemplary conductive materials described elsewhere herein. To define the shape of the first conductor track 106, sections of the deposited conductive material may be etched using a temporary mask (not shown) to obtain the desired shape of the conductor track 106. Subsequent conductor tracks may be formed in essentially the same manner.

[0031] Methods according to the invention can also include forming the insulating layer 112 above the first conductor track 106. The insulating layer 112 can be formed by depositing one or more electrically insulating materials on the first conductor track 106 to a desired height above the first conductor track 106. As illustrated, the insulating layer 112 can form a zone with a vertical distance between the first conductor track 106 and the top surface of the insulating layer 112. The height of the insulating layer 112 can thus vertically separate the first conductor track 106 from the subsequently formed layers of conductive material. As explained elsewhere herein, storage elements such as storage vias 114 ( Fig. 2-5) vertically connect different conductive layers to each other, thus creating a connection between different neuronal nodes in a structure.

[0032] With reference to Fig. 7. The invention may comprise the formation of storage vias 114 within the insulating layer 112 and in contact with the first conductor track 106. Forming the storage via 114 may include creating an opening within the insulating layer 112 above the first conductor track 106 (e.g., by etching) and filling the opening with one or more materials suitable for forming the storage via 114. By way of example, forming the storage via 114 may involve the deposition of titanium oxide (TiO₂). 2-x ) on the first conductor track 106 and filling the aforementioned opening. As shown, the deposited material of the storage via 114 can also initially coat a top surface of the insulating layer 112. The deposited material can then be removed, e.g., by chemical-mechanical planarization (CMP), before other materials are formed on the insulating layer 112 and the storage via 114.

[0033] Fig. Figure 8 illustrates a process for forming a second conductive track 108 on the storage via 114 and the insulating layer 112. The second conductive track 108 can be formed in essentially the same way as the first conductive track 106, for example, by depositing a conductive metal on the insulating layer 112 and the storage via 114 and subsequently etching sections of the deposited conductive material to form a desired shape. As discussed in relation to other processes, another insulating layer 112 can be deposited over the second conductive track 108 to vertically separate the second conductive track 108 from the subsequently formed materials. In any case, the storage via 114 can vertically connect the first and second conductive tracks 106, 108 to form a path for electric current in the subsequent structure. The Fig. The processes shown in 6-8 can be repeated any number of times to subsequently create conductor tracks 106, 108, 110 ( Fig. 2-5, 9, 10) and to form storage vias 114 at desired locations.

[0034] With further reference to Fig. 9. Subsequent processing can be provided to form the neural nodes for receiving inputs and sending outputs through an ANN structure. Fig. Figure 9 shows a partially completed structure with an arranged connection stack 104. The connection stack 104 can be assembled by repeatedly implementing the steps shown in the Fig. The processes shown in Figures 6-8 and explained above are used to form several conductor tracks 106, 108, 110 and insulator layers 112. Five layers of the interconnect stack 104 are shown only as an example, and it is understood that the interconnect stack can have any number of layers (e.g., ten layers, fifty layers, one hundred layers, several hundred layers, etc.). Thus, the interconnect stack 104 can include any number of conductor tracks 106, 108, 110. After forming the interconnect stack 104 to a desired height, the subsequent processing can involve forming a mask 130 on the interconnect stack 104. The mask 130 can have several openings 132 (two of which are shown in Fig. (9 shown) comprise, which are configured to remove the underlying portions of the interconnect stack 104. After forming the mask 130, further processing may include non-selective downward etching (e.g., reactive ion etching (RIE) of the interconnect stack to form openings in which neural nodes can be formed. The downward etching can remove sections from each insulator layer 112 and underlying sections of conductors 106, 108, 110 that are horizontally offset from the respective storage vias 114. The etching can result in openings 132 being positioned directly adjacent to the respective sections of conductors 106, 108, 110 of the interconnect stack 104.

[0035] Fig. 10 represents a process for the formation of structure 100 by forming neuronal nodes 102 within openings 132 ( Fig. 9) As illustrated, the formation of neural nodes 102 can include the deposition of doped or undoped semiconductor material within the openings 132 to a desired height. For example, the formation of neural nodes 102 can include the deposition of undoped semiconductor material at locations where the neural nodes 102 do not touch conductor tracks 106, 108, 110, and the formation of p- and / or n-doped semiconductor materials in contact with the conductor tracks 106, 108, 110 to form pn junctions within the neural nodes 102. The resulting pn junctions can define the electrical pathways of VCMV(s) 116 between the sets of conductor tracks 106, 108, 110. The presence of doped semiconductor material in neural nodes 102 is shown schematically in the neural node 102.In further implementations, neural nodes 102 can be formed such that they at least partially comprise a non-substrate material to provide VCMV(s) 116 and / or other amplifier components coupled to the conductor tracks 106, 108, 110. In each case, the formed neural nodes 102 can be planarized to a desired height after formation (e.g., the top of the connection 104). In further embodiments, neural nodes 102 can be in the form of planar conductive metals and / or other conductive materials that do not contain semiconductors. The formation of neural nodes 102 within the openings 132 as shown creates an electrical path between neural nodes 102 through the connection stack 104.In particular, conductors 106, 108, 110 and storage via(s) 114 provide an electrical path to transmit signals from one neural node 102 to another in the structure 100.

[0036] To power the VCMV(s) 116, neural nodes 102 can be coupled to an adjacent neural node 102 via one or more of the various conductor tracks 106, 108, 110. The voltage source(s) V can be integrated into a part of the device outside the structure 100 or provided on any electrical structure coupled to the neural node 100 via the interconnect stack 104. Each voltage source V can supply an alternating current voltage (AC voltage) for amplifying input and / or output signals within the structure 100, and each can supply an independent voltage by being coupled to ground (GND). The voltage source(s) V can provide the supply voltage Vss ( Fig. 5) and / or the reference voltage Vref ( Fig. 5) represent.

Claims

[1] Neuromorphic circuit structure (100), comprising: a first vertically extending neural node (102A) configured to generate an output signal based on at least one input to the first vertically extending neural node (102A); a connection stack (104) adjacent to the vertically extending neural node (102A), wherein the connection stack (104) includes a first conductor (106) coupled to the first vertically extending neural node (120A) and configured to receive the output signal, wherein a second conductor (108) is vertically separated from the first conductor (106), and wherein a memory via (114) vertically couples the first conductor (106) to the second conductor (108); and a second vertically extending neural node (102B) next to the connection stack (104), wherein the second vertically extending neural node (102B) is coupled to the second conductor (108) for receiving the output signal from the first vertically extending neural node (102A). [2] Neuromorphic circuit structure (100) according to claim 1, wherein the interconnect stack (104) further comprises a dielectric layer (112) arranged between the first and second conductor tracks (106, 108), and wherein the storage via (114) extends vertically through the dielectric layer (112). [3] Neuromorphic circuit structure (100) according to claim 1, wherein the storage via (114) comprises a unidirectional memristor. [4] Neuromorphic circuit structure (100) according to claim 3, wherein the memristor is a titanium oxide (TiO₂). 2-x ) -Material included. [5] Neuromorphic circuit structure (100) according to claim 1, wherein the second conductor (108) is configured to transmit an excitatory input signal or an inhibitory input signal to the second vertically extending neural node (120B). [6] Neuromorphic circuit structure (100) according to claim 1, wherein the first vertically extending neural node (102A) comprises a voltage-controlled monostable vibrator (116) configured to generate an output signal, wherein a frequency of the output signal is based on a difference between the at least one input to the first vertically extending neural node (102A) and a reference voltage (Vref). [7] Neuromorphic circuit structure (100) according to claim 6, wherein the vertically extending neural node (102A) comprises a silicon substrate and wherein the voltage-controlled monostable vibrator (116) is formed within the silicon substrate. [8] Neuromorphic circuit structure (100), comprising: a first vertically extending neural node (120A) configured to receive at least one excitatory input signal and at least one inhibitory input signal, wherein the first vertically extending neural node (102A) generates an output signal based on the at least one excitatory input signal and the at least one inhibitory input signal; a connection stack (104) adjacent to the vertically extending neural node (102A), wherein the connection stack (104) comprises a plurality of conductor tracks (106, 108, 110) alternating with a plurality of dielectric layers (112A, 112B, 112C), wherein a first conductor track (106) of the connection stack (104) is coupled to the first vertically extending neural node (102A) and configured to receive the output signal, one of the plurality of dielectric layers (112A, 112B, 112C) separates the first conductor track (106) from a second conductor track (108, 110) of the connection stack (104), and a storage via (114) vertically connects the first conductor track (106) to the second conductor track (108, 110); and a second vertically extending neural node (102B) next to the connection stack (104), wherein the second vertically extending neural node (120B) is coupled to the second conductor (108, 110) for receiving the output signal from the first vertically extending neural node (102A). [9] Neuromorphic circuit structure (100) according to claim 8, wherein the storage via (114) comprises a unidirectional memristor. [10] Neuromorphic circuit structure (100) according to claim 9, wherein the memristor is a titanium oxide (TiO₂). 2-x ) -Material included. [11] Neuromorphic circuit structure according to claim 8, wherein the first vertically extending neural node (102A) comprises a voltage-controlled monostable vibrator (116) configured to generate the output signal, wherein a frequency of the output signal is based on an input voltage (Vin1) for the voltage-controlled monostable vibrator and a reference voltage (Vref). [12] Neuromorphic circuit structure (100) according to claim 11, wherein the input voltage (Vin1) for the voltage-controlled monostable vibrator (116) is proportional to a voltage difference between the at least one excitatory input signal and the at least one inhibiting input signal. [13] Neuromorphic circuit structure (100) according to claim 8, wherein the first vertically extending neural node (102A) comprises a silicon substrate and wherein the voltage-controlled monostable vibrator (116) is formed within the silicon substrate. [14] Neuromorphic circuit structure (100) according to claim 8, wherein the first vertically extending neural node (102A) is coupled to a set of at least ten storage vias (114), wherein the set of at least ten storage vias (114) is configured to transmit the at least one excitatory input signal and the at least one inhibitory input signal to the first vertically extending neural node (102A). [15] Method for forming a neuromorphic circuit structure (100), wherein the method comprises: forming a first conductor track (106); a formation of a dielectric layer (112) on the first conductor track (106); a formation of a storage via (114) within the dielectric layer (112) in contact with the first conductor track (106); a formation of a second conductor track (108) on the dielectric layer (112), such that the storage via (114) vertically connects the second conductor track (108) with the first conductor track (106); a first opening and a second opening by removing corresponding sections of the first conductor (106), the dielectric layer (112) and the second conductor (108) at locations horizontally offset from the via (114), wherein the first opening is arranged longitudinally directly next to the first conductor (106) and the second opening is arranged longitudinally directly next to the second conductor (108); a formation of a first and second vertically extending neural node (102A, 102B) accordingly within the first opening and the second opening, wherein the first vertically extending neural node (102A) is coupled to the first conductor (106) and the second vertically extending neural node (102B) is coupled to the second conductor (108). [16] Method according to claim 15, further comprising forming a plurality of additional conductor tracks (110) and dielectric layers (112) to form a connecting stack (104) before forming the pair of openings. [17] Method according to claim 15, wherein the formation of one of the two vertically extending neural nodes (102A, 102B) comprises forming a voltage-controlled monostable vibrator (116) coupled to the first conductor (106) or the second conductor (108). [18] Method according to claim 17, further comprising coupling a reference terminal of the voltage-controlled monostable vibrator (116) to a voltage source (V). [19] Method according to claim 15, wherein forming the storage via (114) comprises forming a memristor material. [20] Method according to claim 19, wherein the formation of the memristor material involves the deposition of a titanium oxide (TiO₂). 2-x ) -Material above the first conductor track (106).

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