Image display methods and image display systems capable of stabilizing image brightness

Abstract

Image display methods, comprehensive: Determining a plurality of backlight driver signal setting modes according to a plurality of frame rate intervals, wherein the plurality of backlight driver signal setting modes specify different frequencies of a backlight driver signal (S501); Receiving a data clock signal (S502); Capturing a first frame rate of the data clock signal (S503); Setting an initial power distribution and a first frequency of the backlight driver signal according to a first backlight driver signal setting mode of the plurality of backlight driver signal setting modes, when the first frame rate falls within a first frame rate interval of the plurality of frame rate intervals (S504); and Displaying an image according to at least the data clock signal and the backlight driver signal (S505); where the first frequency of the backlight driver signal is N times the first frame rate of the data clock signal and N is a positive integer.

Description

Background of the invention 1. Field of the invention

[0001] The present invention presents an image display method and an image display system, and more precisely an image display method and an image display system, which are capable of stabilizing image brightness and reducing image flicker. 2. Description of the state of the art

[0002] Liquid crystal display (LCD) devices and organic light-emitting diode (OLED) display devices have been widely used in multimedia products, mobile phones, personal digital assistants, computer monitors or flat-screen televisions because they offer advantages of low energy consumption, no radiation and slim designs.WO 2018 / 080000A1 discloses a display device comprising: a display unit for outputting an image; a backlight unit for controlling a backlight source of the display unit; a signal receiving unit for receiving an image signal; an image processing unit for processing the input image signal and transmitting the processed image signal to the display unit so that the image can be output according to a specified frequency; and a control unit for controlling the backlight unit and the image processing unit to change an illumination time of the backlight source and / or the frequency according to the characteristics of the input image signal.

[0003] Nowadays, many advanced display devices are often used to show images from video games or movies. These games and movies often contain a lot of moving objects. Therefore, to provide a satisfactory visual experience, advanced display devices can implement a "Dynamic Accuracy (DyAc)" function. The DyAc function can be used to improve the sharpness of dynamic moving images. Therefore, the DyAc function is helpful in reducing excessive image vibrations, especially in video games or movies. Furthermore, advanced display devices also feature a dynamic frame rate refresh function (i.e., for example, a free sync function).The free sync function can be used to display images by dynamically adjusting the frame rate according to video data played back by a game console or graphics card. In other words, when the display device receives video data with a non-constant frame rate (30-240 Hz), it can use the free sync function to display the images.

[0004] However, when the Free Sync and DyAc functions are enabled to improve the sharpness of dynamic moving images transmitted using a non-constant frame rate, the human eye can easily perceive image flicker, especially at frame rates below 100 Hz. Furthermore, when Free Sync is enabled, the image brightness can be unstable due to the frame rate changing over time. Therefore, for current display devices, the visual quality may be reduced after Free Sync and DyAc are enabled, as the image flicker is severe and the image brightness is unstable at low frame rates. Summary of the invention

[0005] The present invention relates to an image display method. The image display method comprises determining a plurality of backlight driver signal setting modes according to a plurality of frame rate intervals, wherein the plurality of backlight driver signal setting modes specify different frequencies of a backlight driver signal, receiving a data clock signal, detecting a first frame rate of the data clock signal, setting a first power distribution and a first frequency of the backlight driver signal according to a first backlight driver signal setting mode of the plurality of backlight driver signal setting modes when the first frame rate falls within a first frame rate interval of the plurality of frame rate intervals, and displaying an image according to at least the data clock signal and the backlight driver signal.where the first frequency of the backlight driver signal is N times the first frame rate of the data clock signal, and N is a positive integer.

[0006] The present invention also relates to an image display system. The image display system comprises a display panel, a driver circuit, a processor, a backlight device, and a memory. The display panel has a plurality of pixels and is designed to display an image. The driver circuit is connected to the display panel and is designed to drive / control the plurality of pixels. The processor is connected to the driver circuit and is designed to control the driver circuit. The backlight device is connected to the processor and is designed to generate a backlight signal. The memory is connected to the processor and is designed to store data from a plurality of frame rate intervals and data from a plurality of backlight driver signal setting modes.The processor determines the plurality of backlight driver signal setting modes according to a plurality of frame rate intervals, wherein the plurality of backlight driver signal setting modes specify different frequencies of a backlight driver signal. The processor receives a data clock signal sent from a signal source and detects an initial frame rate of the data clock signal. The processor sets an initial power distribution and a first frequency of the backlight driver signal according to a first backlight driver signal setting mode of the plurality of backlight driver signal setting modes when the first frame rate falls within a first frame rate interval of the plurality of frame rate intervals. The backlight device generates the backlight signal according to the backlight driver signal.The driver circuit drives the display area to show the image according to at least the data clock signal and the backlight driver signal. The first frequency of the backlight driver signal is N times the first frame rate of the data clock signal, and N is a positive integer.

[0007] These and other problems of the present invention will undoubtedly become apparent to those with ordinary knowledge in the field after reading the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings. Brief description of the drawings Fig. Figure 1 is a block diagram of an image display system according to an embodiment of the present invention.

[0008] Fig. Figure 2 shows a first correlation between a data clock signal and a backlight driver signal of the image display system in Fig. 1.

[0009] Fig. Figure 3 shows a second correlation between the data clock signal and the backlight driver signal of the image display system in Fig. 1.

[0010] Fig. Figure 4 shows a third correlation between the data clock signal and the backlight driver signal of the image display system in Fig. 1.

[0011] Fig. 5 is a flowchart of an image display procedure implemented by the image display system in Fig. 1 is executed. Detailed description

[0012] Fig.Figure 1 is a block diagram of an image display system 100 according to an embodiment of the present invention. The image display system 100 comprises a display area 10, a driver circuit 11, a processor 12, a backlight device 13, a memory 14, and a signal source 15. The display area 10 can be any type of display area, such as a display area of ​​a liquid crystal display (LCD) device or a display area of ​​a display device with organic light-emitting diodes (OLEDs). The display area 10 has a plurality of pixels P for displaying an image. The plurality of pixels P can be arranged in the form of a pixel array for displaying a rectangular image. The driver circuit 11 is connected to the display area 10 for driving / controlling the plurality of pixels P.The driver circuit 11 can include a circuit component for controlling the plurality of pixels P, such as a gate driver circuit and a data driver circuit. For example, the gate driver circuit can generate gate voltages to control control terminals of the plurality of pixels P by using a line-by-line sampling process. Therefore, the plurality of pixels P can be controlled to assume an enabled or disabled state. The data driver circuit can send data voltages to the plurality of pixels P. Therefore, the plurality of pixels can display different colors and shades of gray. The processor 12 is connected to the driver circuit 11 to control the driver circuit 11. The processor 12 can be a scaler located within the display system 100, or it can be a microprocessor capable of performing at least one programmable operation.The processor 12 can store multiple timing parameters. Furthermore, the processor 12 can be integrated into a timing circuit for determining various timing signals of the driver circuit 11 to sample multiple pixels P. The backlight device 13 is connected to the processor 12 to generate a backlight signal. The backlight device 13 can be any controllable light-emitting device. For example, the backlight device 13 can be an array of light-emitting diodes (LEDs), an incandescent lamp, an electroluminescent panel (ELP), or a cold cathode fluorescent lamp (CCFL). The memory 14 is connected to the processor 12 to store data for multiple frame rate intervals and data for multiple backlight driver signal setting modes.In the display system 100, the processor 12 can receive a data clock signal sent by the signal source 15. The signal source 15 can be a computer graphics card or a DVD player.

[0013] In the display system 100, after the processor 12 receives the data clock signal sent from the signal source 15, the processor 12 can detect a first frame rate of the data clock signal. The processor 12 can set a first power distribution of a backlight driver signal according to one of the first backlight driver signal setting modes stored in the memory 14, if the first frame rate falls within a first frame rate interval of the multiple frame rate intervals. Then, the backlight device 13 can generate the backlight signal according to the backlight driver signal. The driver circuit 11 can control the display area 10 to display the image according to at least the data clock signal and the backlight driver signal.Furthermore, the image display system 100 can provide a dynamic refresh of the frame rate function (hereinafter referred to as "a free sync function"). Therefore, the initial frame rate of the data clock signal is varied over time. For example, the initial frame rate can range from 30 to 240 Hertz. The majority of frame rate intervals and the majority of backlight driver signal setting modes stored in memory 14 can be shown in Table T1. Table T1 Frame rate, FR intervals Backlight driver signal adjustment modes FR≤40 Hertz Adjusting the frequency of the backlight driver signal so that it approximates three times the frame rate, to drive the backlight device 13 40 Hertz <FR<100 Hertz Adjusting the frequency of the backlight driver signal so that it approximates double the frame rate, to drive the backlight device 13 FR≥100 Hertz Adjusting the frequency of the backlight driver signal so that it approximates the frame rate, to drive the backlight device 13

[0014] The decision limits and intervals listed in Table T1 are the embodiment of the display system 100. Any suitable frame rate interval modification or backlight driver signal setting mode falls within the scope of the present invention. Details of each backlight driver signal setting mode are described below.

[0015] Fig.Figure 2 shows a first correlation between a data clock signal DLK and a backlight driver signal BL of the image display system 100. Backlight driver signal BL setting modes are shown in Figure 2. Fig. 2 can be referenced in table T1. In other words, a frequency of the backlight driver signal BL can be found in Fig. 2 according to table T1. In Fig.2. An X-axis is referred to as a timeline. First, the processor 12 detects an initial frame rate R1 of the data clock signal DLK, which is generated by the signal source 15. For example, the initial frame rate R1 is 40 Hertz. If the initial frame rate R1 is 40 Hertz, it falls within an initial frame rate interval, such as "FR < 40 Hertz" in Table T1. Therefore, the processor 12 can adjust the frequency of the backlight driver signal BL so that it approaches three times the initial frame rate to drive the backlight device 13. As shown in Fig.As shown in Figure 2, during a first frame F1 interval, processor 12 can adjust the frequency of the backlight driver signal BL so that it approximates three times the first frame rate R1 (i.e., 3 × R1 = 3 × 40 = 120 Hz). Such a adjusted frequency of the backlight driver signal BL is subsequently referred to as "a first frequency Freq1". In other words, during the first frame F1 interval, the backlight driver signal BL has three first square waveforms S1, each with an energy E11, an energy E12, and an energy E13. Here, the energy of a square waveform is defined as an integrated value of its area. Therefore, although the first frame rate R1 (40 Hz) of the data clock signal DLK is small, the first frequency Freq1 of the backlight driver signal BL is set to 120 Hz.Therefore, even if a dynamic accuracy (DyAc) function is enabled in the image display system 100, image flicker can be mitigated or eliminated. As mentioned above, the image display system 100 can provide the free sync function. Therefore, the first frame rate R1 of the data clock signal DLK is varied over time. For example, the range of the first frame rate R1 can be 30-240 Hertz. Therefore, after Q frame intervals have elapsed, the processor 12 can detect a frequency shift of the data clock signal DLK from the first frame rate R1 to a second frame rate R2. For example, the second frame rate R2 can be 75 Hertz. Then, the processor 12 can determine that the second frame rate R2 should be shifted to a second frame rate interval, such as 40 Hertz. <FR<100 Hertz“ in der Tabelle T1, fällt.Therefore, the processor 12 can adjust the frequency of the backlight driver signal BL so that it approaches double the frame rate to drive the backlight device 13. As shown in . Fig.As shown in Figure 2, during the Q-th frame FQ interval, the processor 12 can adjust the frequency of the backlight driver signal BL so that it approximates twice the second frame rate R2 (i.e., 2 × R2 = 2 × 75 Hz = 150 Hz). Such a set frequency of the backlight driver signal BL is subsequently referred to as "a second frequency Freq2". Therefore, image flicker can be mitigated or eliminated. In other words, since image flicker tends to occur for frame rates below 100 Hz, the human eye finds low frame rates unpleasant. Therefore, the image display system 100 can dynamically adjust the frequency of the backlight driver signal BL according to a received current frame rate of the data clock signal DLK. Furthermore, since the frequency of the backlight driver signal BL (i.e.,, for example, if the first frequency Freq1=120 Hz or the second frequency Freq2=150 Hz) is greater than 100 Hz, the image flicker can be reduced.

[0016] In other words, for the first frame rate R1 of the data clock signal DLK, the processor 12 can set the first frequency Freq1 of the backlight driver signal BL according to the first backlight driver signal setting mode (i.e., as shown in Table T1) of the plurality of backlight driver signal setting modes stored in memory 14. The processor 12 can set the first frequency Freq1 of the backlight driver signal BL so that it approximates an N-fold of the first frame rate R1 of the data clock signal DLK, according to the first backlight driver signal setting mode. N is a positive integer. Furthermore, if the first frame rate R1 of the data clock signal DLK is increased, the processor 12 can decrease a value of N. As shown in Table T1, if the first frame rate R1 falls within a frame interval of "FR < 40 Hz", N is set to 3.If the first frame rate R1 is in a frame interval of "40 Hertz <FR<100 Hertz“ fällt, wird N auf 2 festgelegt. Wenn die erste Rahmenrate R1 in ein Rahmenintervall von „FR≥100 Hertz“ fällt, wird N auf 1 festgelegt. Ein Frequenzeinstellverfahren des Hintergrundbeleuchtungstreibersignals BL gemäß der zweiten Rahmenrate R2 ist ähnlich dem Frequenzeinstellverfahren des Hintergrundbeleuchtungstreibersignals BL gemäß der ersten Rahmenrate R1. Somit werden dessen Details hier weggelassen.

[0017] Furthermore, the image display system 100 can set a waveform of the backlight driver signal BL. The processor 12 can set an initial power distribution of the backlight driver signal BL according to the first backlight driver signal setting mode of the plurality of backlight driver signal setting modes stored in memory 14. For example, as mentioned above, during the first frame F1 interval, the first frequency Freq1 of the backlight driver signal BL can be set so that it approximates three times the first frame rate R1 (3×R1=3×40=120 Hertz). Furthermore, the processor 12 can set the power E11, the power E12, and the power E13 of a plurality of first square waveforms S1 of the backlight driver signal BL during the first frame F1 interval.Similarly, during the Q-th frame FQ interval, the second frequency Freq2 of the backlight driver signal BL can be adjusted to approximate twice the second frame rate R2 (2×R2=2×75=150 Hertz). Furthermore, the processor 12 can adjust the energy E21 and the energy E22 of a plurality of second square waveforms S2 of the backlight driver signal BL during the Q-th frame FQ interval. Therefore, by adjusting the square waveforms of the backlight driver signal BL, the display system 100 can reconfigure the energy distribution of the backlight driver signal BL during each frame interval. Furthermore, the energy values ​​of the backlight driver signal BL are essentially identical during all frame intervals of the data clock signal DLK. For example, the energy values ​​of the backlight driver signal BL can satisfy a condition E11+E12+E13=E21+E22.In this way, since the energy values ​​of the backlight driver signal BL are essentially identical during all frame intervals, the image brightness can be stabilized, resulting in a satisfactory quality of visual perception.

[0018] Fig. Figure 3 shows a second correlation between the data clock signal DLK and the backlight driver signal BL of the image display system 100. Fig.3 is an X-axis referred to as the timeline. Likewise, the processor 12 detects a first frame rate R1 of the data clock signal DLK, which is generated by the signal source 15. For example, the first frame rate R1 is 40 Hertz. If the first frame rate R1 is 40 Hertz, it falls within the first frame rate interval, as “FR≤40 Hertz” in Table T1. Therefore, the processor 12 can adjust the frequency of the backlight driver signal BL so that it approaches three times the frame rate to drive the backlight device 13. As shown in Fig.As shown in Figure 3, during the first frame F1 interval, the processor 12 can adjust the frequency of the backlight driver signal BL so that it approximates three times the first frame rate R1 (i.e., 3 × R1 = 3 × 40 = 120 Hz). After Q frame intervals have elapsed, the processor 12 detects a frequency shift of the data clock signal DLK from the first frame rate R1 to a second frame rate R2. For example, the second frame rate R2 may be 100 Hz. The processor 12 can then determine that the second frame rate R2 falls within a third frame rate interval, such as "FR ≥ 100 Hz" in Table T1. Therefore, the processor 12 can adjust the frequency of the backlight driver signal BL so that it approximates the second frame rate R2 to drive the backlight device 13. As shown in Figure 3, the processor 12 can adjust the frequency of the backlight driver signal BL so that it approximates the second frame rate R2 to drive the backlight device 13. Fig.As shown in Figure 3, during the Q-th frame FQ interval, the processor 12 can adjust the frequency of the backlight driver signal BL so that it approximates the second frame rate R2 (i.e., R2 = 100 Hz). Such a adjusted frequency of the backlight driver signal BL is subsequently referred to as "a second frequency Freq2". Furthermore, the backlight driver signal BL has at least one square waveform. The processor 12 can adjust the height and / or width of this at least one square waveform. For example, during the first frame F1 interval, the backlight driver signal BL can have three first square waveforms S1. The processor 12 can adjust the height H1 and / or width W1 of each first square waveform S1. As mentioned above, the energy of the square waveform is defined as the integrated value of its area.Therefore, the first rectangular waveform S1, which has the first height H1 and the first width W1, corresponds to the energy E11 = W1 × H1. In this way, the processor 12 can adjust the distribution of the energy E11, energy E12, and energy E13 of the backlight driver signal BL during the first frame F1 interval. Similarly, the backlight driver signal BL has a second rectangular waveform S2 during the Q-th frame FQ interval. The processor 12 can adjust the height H2 and / or width W2 of the second rectangular waveform S2. Therefore, the second rectangular waveform S2, which has the second height H2 and the second width W2, corresponds to the energy E21 = W2 × H2. In this way, the processor 12 can adjust the distribution of the energy E21 of the backlight driver signal BL during the Q-th frame FQ interval.

[0019] Furthermore, as mentioned above, processor 12 can adjust the power distribution of the backlight driver signal BL. Therefore, once the power distribution of the backlight driver signal BL is adjusted, the power values ​​of the backlight driver signal BL are essentially identical during all frame intervals of the data clock signal DLK, resulting in stabilized image brightness. In other words, in Fig. 3. If the first frame rate R1 (40 Hertz) is lower than the second frame rate R2 (100 Hertz), the energy value of a single first square waveform S1 of the backlight driver signal BL with the first energy distribution is lower than the energy value of a single second square waveform S2 of the backlight driver signal BL with the second energy distribution. Therefore, in Fig.3. The energy of the backlight driver signal BL (i.e., including the plurality of first square waveforms S1) during the first frame F1 interval is adjusted so that it approximates the energy of the backlight driver signal BL (i.e., including a single second square waveform S2) during the Q-th frame FQ interval. Conversely, if the first frame rate R1 is greater than the second frame rate R2, an energy value of the single first square waveform S1 of the backlight driver signal BL with the first energy distribution is greater than an energy value of the single second square waveform S2 of the backlight driver signal with the second energy distribution. Furthermore, energy values ​​of the plurality of first waveforms S1 configured by the image display system 100 can be substantially identical, such that E11=E12=E13.Therefore, the stability of the image brightness can be further improved during the first frame F1 interval.

[0020] In the image display system 100, the processor 12 can adjust the frequency of the backlight driver signal BL and / or the square waveforms of the backlight driver signal BL according to a suitable backlight driver signal adjustment mode from the majority of backlight driver signal adjustment modes stored in memory 14. Increasing the frequency of the backlight driver signal BL can prevent image banding. Adjusting the square waveforms of the backlight driver signal BL ensures that the energy values ​​of the backlight driver signal BL are essentially identical throughout all frame intervals, resulting in high image brightness stability. However, the energy distributions of the backlight driver signal BL are not limited to satisfying E11+E12+E13≈E21+E22 or E11≈E12≈E13.Any suitable technology for stabilizing image brightness falls within the scope of the present invention.

[0021] Fig. Figure 4 shows a third correlation between the data clock signal DLK and the backlight driver signal BL of the image display system 100. Fig.Figure 4 is an x-axis, referred to as the timeline. Similarly, processor 12 detects the first frame rate R1 of the data clock signal DLK, generated by signal source 15. For example, the first frame rate R1 is 40 Hertz. If the first frame rate R1 is 40 Hertz, it falls within the first frame rate interval, as shown in Table T1 with "FR < 40 Hertz". Therefore, processor 12 can adjust the first frequency Freq1 of the backlight driver signal BL to approximate three times the first frame rate R1 (i.e., 3 × R1 = 3 × 40 = 120 Hertz). If the second frame rate R2 is 120 Hertz, it falls within the third frame rate interval, as shown in Table T1 with "FR ≥ 100 Hertz". Therefore, the processor 12 can adjust the second frequency Freq2 of the backlight driver signal BL so that it approximates the second frame rate R2 to drive the backlight device 13.Therefore, during the Q-th frame FQ interval, the second frequency Freq2 is equal to 120 Hertz. Therefore, in . Fig. 4. After the backlight driver signal BL is set, the first frequency Freq1 and the second frequency Freq2 are exactly identical (120 Hertz). In other words, at some specific frame rates, the frequency of the backlight driver signal BL can be constant. Processor 12 can further adjust square waveforms of the backlight driver signal BL. However, details of adjusting the width W1 and / or height H1 of each first square waveform S1, adjusting the width W2 and / or height H2 of each second square waveform S2, and adjusting the energy distribution of energy E11, energy E12, energy E13, energy E21, energy E22, and energy E23 have been described above. Therefore, they are omitted here.

[0022] Furthermore, the procedure for adjusting the energy distribution of the backlight driver signal BL is not limited to technologies in Fig. 2 to Fig. 4 limited. In Fig.2. The energy distribution of the plurality of first square waveforms S1 and the plurality of second square waveforms S2 can be suitably adjusted. For example, the first square waveform S1, which has energy E13, can be generated during a blanking interval of the first frame F1. The first square waveform S1, which has energy E11 and energy E12, can be generated during any two periods during an active interval of the first frame F1. Furthermore, the second square waveform S2, which has energy E22, can be generated during a blanking interval of the Q-th frame FQ. The second square waveform S2, which has energy E21, can be generated during any period during an active interval of the Q-th frame FQ. Any suitable technology for adjusting the energy distribution of the backlight driver signal BL falls within the scope of the present invention.

[0023] In the image display system 100, the processor 12 can adjust the power distribution and the frequency of the backlight driver signal BL to prevent image flicker and stabilize image brightness. However, the image display system 100 can introduce hybrid modes to further improve visual quality. For example, in the image display system 100, the memory 14 can store data from a plurality of overdrive modes (OD modes). If the first frame rate R1 falls within the first frame rate interval of the plurality of frame rate intervals, the processor 12 can use one of the plurality of OD modes to accelerate pixel driving. By introducing the plurality of OD modes into the image display system 100, a plurality of hybrid modes can be generated by integrating the backlight driver signal adjustment modes with the OD modes, as shown in Table T2. Table T2 Frame rate FR intervals Backlight driver signal adjustment modes and OD modes (hybrid modes) FR≤40 Hertz A) Adjusting the frequency of the backlight driver signal so that it approximates three times the frame rate to drive the backlight device 13B) OD mode: weak 40 Hertz <FR<100 Hertz A) Setting a frequency of the backlight driver signal, so that it approaches double the frame rate, to drive the backlight device 13B) OD mode: medium FR≥100 Hertz A) Adjusting the frequency of the backlight driver signal so that it approximates the frame rate, to drive the backlight device 13B) OD mode: strong

[0024] The image display system 100 can introduce multiple OD modes to determine the pixel drive voltage. A high pixel drive voltage intensity implies a short refresh time for the pixel's liquid crystal molecules. Therefore, if the first frame rate R1 of the data clock signal DLK is low (i.e., for example, less than 40 Hz), the signal source 15 will generate a static image or an image containing slow-moving objects, such as text documents. In this case, the OD mode can be set to a "weak" mode. The processor 12 can then use a low-intensity pixel drive voltage to drive the display area 10. If the first frame rate R1 of the data clock signal DLK is high (i.e., less than 40 Hz), the signal source 15 will generate a static image or an image containing slow-moving objects, such as text documents.For example, if the first frame rate R1 is greater than 100 Hertz, this implies that the signal source 15 generates a dynamic image or an image containing fast-moving objects, such as an image from video games. Therefore, the OD mode can be set to a "strong" mode. Then, the processor 12 can use a high-intensity pixel drive voltage to drive the display area 10. After the display area 10 is driven by the high-intensity pixel drive voltage, the afterimage effect can be mitigated. Therefore, after the image display system 100 adjusts the power distribution of the backlight driver signal BL and introduces the majority of OD modes, the image display system 100 can reduce image flicker, stabilize image brightness, and mitigate the afterimage effect. Thus, the image display system 100 can significantly improve the quality of visual perception.

[0025] Fig. Figure 5 is a flowchart of an image display method executed by the image display system 100. The image display system 100 comprises steps S501 to S505. Any suitable technology modification falls within the scope of the present invention. Details of steps S501 to S505 are shown below. Step S501: Setting the majority of frame rate intervals and the majority of backlight driver signal adjustment modes; Step S502: Receiving the data clock signal DLK; Step S503: Capturing the first frame rate R1 of the data clock signal DLK; Step S504: Adjusting the first power distribution of the backlight driver signal BL according to the first backlight driver signal adjustment mode of the plurality of backlight driver signal adjustment modes, when the first frame rate R1 falls within the first frame rate interval of the plurality of frame rate intervals; Step S505: Display the image according to at least the data clock signal DLK and the backlight driver signal BL.

[0026] Details from step S501 to step S505 are described above and are therefore omitted here. By adjusting the backlight driver signal BL, the Image Display System 100 can prevent image flicker and stabilize image brightness. In other words, even when the Image Display System 100 is performing the free sync function, the frequency of the backlight driver signal BL can be dynamically adjusted. The set frequency is greater than a threshold (i.e., greater than 100 Hertz) for each frame rate. Therefore, image flicker can be prevented. In this way, the Image Display System 100 can improve the quality of visual perception.

[0027] In summary, the present invention presents an image display method and an image display system. The image display system can dynamically adjust the frequency of a backlight driver signal according to the frame rate variability of a data clock signal. If the frame rate of the data clock signal is very low, the image display system can increase the frequency of the backlight driver signal to prevent image flicker from being perceived by the human eye. Furthermore, to optimize the energy distribution of the backlight driver signal throughout all image frames, the image display system can also adjust the height and / or width of square waveforms of the backlight driver signal, resulting in high image brightness stability. The image display system can also introduce multiple overdrive (OD) modes to mitigate image retention.Therefore, the Image Display System 100 can reduce image flicker, stabilize image brightness, and mitigate the afterimage effect. Thus, the Image Display System 100 can significantly improve the quality of visual perception.

[0028] Those with expertise in the field will readily recognize that numerous modifications and alterations to the apparatus and the method can be made while retaining the teachings of the invention. Accordingly, the foregoing disclosure should be considered as limited only by the dimensions and boundaries of the appended claims.

[0029] In summary, an image display method comprises setting a plurality of frame rate intervals and a plurality of backlight driver signal setting modes, receiving a data clock signal, acquiring a first frame rate of the data clock signal, setting a first power distribution of a backlight driver signal according to a first backlight driver signal setting mode of the plurality of backlight driver signal setting modes when the first frame rate falls within a first frame rate interval of the plurality of frame rate intervals, and displaying an image according to at least the data clock signal and the backlight driver signal. Reference symbol list 10 Display area 11 Driver circuit 12 processor 13 Backlight device 14 storage 15 Signal source 100 Image Display System

Claims

[1] Image display methods, including: Determining a plurality of backlight driver signal setting modes according to a plurality of frame rate intervals, wherein the plurality of backlight driver signal setting modes specify different frequencies of a backlight driver signal (S501); Receiving a data clock signal (S502); Capturing a first frame rate of the data clock signal (S503); Setting an initial power distribution and a first frequency of the backlight driver signal according to a first backlight driver signal setting mode of the plurality of backlight driver signal setting modes, when the first frame rate falls within a first frame rate interval of the plurality of frame rate intervals (S504); and Displaying an image according to at least the data clock signal and the backlight driver signal (S505); where the first frequency of the backlight driver signal is N times the first frame rate of the data clock signal and N is a positive integer. [2] Method according to claim 1, wherein the first frame rate of the data clock signal is varied over time. [3] Method according to claim 1 or 2, further comprising: Detecting a frequency shift of the data clock signal from the first frame rate to a second frame rate; and Setting a second power distribution of the backlight driver signal according to a second backlight driver signal setting mode of the plurality of backlight driver signal setting modes, when the second frame rate falls within a second frame rate interval of the plurality of frame rate intervals; where the energy values ​​of the backlight driver signal are essentially identical during all frame intervals of the data clock signal. [4] Method according to claim 3, wherein, if the first frame rate is greater than the second frame rate, an energy value of a first rectangular waveform of the backlight driver signal with the first energy distribution is greater than an energy value of a second rectangular waveform of the backlight driver signal with the second energy distribution. [5] Method according to claim 3 or 4, wherein, if the first frame rate is smaller than the second frame rate, an energy value of a first rectangular waveform of the backlight driver signal with the first energy distribution is smaller than an energy value of a second rectangular waveform of the backlight driver signal with the second energy distribution. [6] Method according to any one of claims 1 to 5, wherein the backlight driver signal has at least one first rectangular waveform, and the method further comprises: Setting a first height and / or a first width of the at least one first rectangular waveform according to the first backlight driver signal setting mode of the majority of backlight driver signal setting modes. [7] Method according to any one of claims 1 to 6, wherein when the first frame rate of the data clock signal is increased, N is decreased. [8] Image display system (100), comprising: a display area (10) having a plurality of pixels (P) and designed to display an image; a driver circuit (11) connected to the display area (10) and designed to drive the plurality of pixels (P); a processor (12) which is connected to and designed to control the driver circuit (11); a backlight device (13) connected to the processor (12) and designed to generate a backlight signal; and a memory (14) connected to the processor (12) and designed to store data of a plurality of frame rate intervals and data of a plurality of backlight driver signal setting modes; wherein the processor (12) determines the plurality of backlight driver signal setting modes according to a plurality of frame rate intervals, wherein the plurality of backlight driver signal setting modes specify different frequencies of a backlight driver signal, the processor (12) receives a data clock signal sent from a signal source (15), the processor (12) detects a first frame rate of the data clock signal, the processor sets a first power distribution and a first frequency of the backlight driver signal according to a first backlight driver signal setting mode of the plurality of backlight driver signal setting modes, when the first frame rate falls within a first frame rate interval of the plurality of frame rate intervals, the backlight device (13) generates the backlight signal according to the backlight driver signal,and the driver circuit (11) drives the display area (10) to display the image according to at least the data clock signal and the backlight driver signal, wherein the first frequency of the backlight driver signal is N times the first frame rate of the data clock signal and N is a positive integer. [9] System according to claim 8, wherein the first frame rate of the data clock signal is varied over time. [10] System according to claim 8 or 9, wherein the processor (12) detects a frequency shift of the data clock signal from the first frame rate to a second frame rate, the processor (12) sets a second energy distribution of the backlight driver signal according to a second backlight driver signal setting mode of the plurality of backlight driver signal setting modes when the second frame rate falls into a second frame rate interval of the plurality of frame rate intervals, and energy values ​​of the backlight driver signal are substantially identical during all frame intervals of the data clock signal. [11] System according to claim 10, wherein, if the first frame rate is greater than the second frame rate, an energy value of a first rectangular waveform of the backlight driver signal with the first energy distribution is greater than an energy value of a second rectangular waveform of the backlight driver signal with the second energy distribution. [12] System according to claim 10 or 11, wherein, if the first frame rate is smaller than the second frame rate, an energy value of a first rectangular waveform of the backlight driver signal with the first energy distribution is smaller than an energy value of a second rectangular waveform of the backlight driver signal with the second energy distribution. [13] System according to any one of claims 8 to 12, wherein the backlight driver signal has at least one first square waveform, and the processor (12) sets a first height and / or a first width of the at least one first square waveform according to the first backlight driver signal setting mode of the plurality of backlight driver signal setting modes stored in the memory (14). [14] System according to any one of claims 8 to 13, wherein when the first frame rate of the data clock signal is increased, N is decreased.

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