TRANSISTORS WITH SEPARATE SOURCE AND DRAIN

Abstract

Structure (10) for a field-effect transistor, wherein the structure (10) comprises: a semiconductor body with a channel region (17); a gate structure (18) over the channel area (17); a first source / drain area (26); and a second source / drain region (28) in a second section of the semiconductor body, wherein the second source / drain region (28) comprises a second concentration of the dopant, wherein the channel region (17) is arranged in the semiconductor body between the first source / drain region (26) and the second source / drain region (28), wherein of the first source / drain region (26) and the second source / drain region (28) only the first source / drain region (26) is formed from an epitaxial semiconductor layer coupled to a first section of the semiconductor body, and wherein the epitaxial semiconductor layer comprises an initial concentration of a dopant.

Description

background

[0001] The present invention relates to the fabrication of semiconductor devices and integrated circuits. In particular, it relates to structures for a field-effect transistor and methods for fabricating a structure for a field-effect transistor.

[0002] Complementary metal oxide semiconductor (CMOS) processes can be used to fabricate a combination of p-type and n-type field-effect transistors, which are used as components to construct, for example, logic cells. Field-effect transistors generally comprise a source, a drain, a body that provides a channel region between the source and drain, and a gate electrode that overlaps the channel region. When a control voltage exceeding a characteristic threshold voltage is applied to the gate electrode, a charge carrier flow occurs in the channel region between the source and drain, generating an output current of the device.

[0003] The source and drain of a field-effect transistor are formed simultaneously. One approach involves implanting ions containing a p-type or n-type dopant into regions of the body at the gate electrode to form the source and drain. Another approach involves epitaxially growing sections of semiconductor material from the body to form the source and drain. During epitaxial growth, the semiconductor material is doped in situ with either a p-type or an n-type dopant.

[0004] The operating characteristics of a field-effect transistor depend, among other things, on how the source and drain are formed. Because they form simultaneously, either through ion implantation or epitaxial growth, the source and drain properties cannot be designed separately to optimize the transistor's operating characteristics for specific design applications.

[0005] Patent US 10,249,755 B1 discloses a method for fabricating an asymmetric field-effect transistor device. This method includes obtaining a structure comprising a semiconductor substrate, sacrificial mandrels on the semiconductor substrate, dummy gates on the sidewalls of the sacrificial mandrels, and a vertical trench between a pair of dummy gates; filling the vertical trench with a filler material having a different composition than the mandrels and dummy gates; selectively removing the mandrels to expose initial sections of the semiconductor substrate; subjecting the initial sections of the semiconductor substrate to a first etching process, thereby forming initial depressions within the initial sections of the semiconductor substrate; removing the filler material from the vertical trench to expose a second section of the semiconductor substrate; and subjecting the first and second sections of the semiconductor substrate to a second etching process.This process enlarges the first wells within the first sections of the semiconductor substrate and forms a second well in the second section of the semiconductor substrate, with the first wells extending vertically further within the semiconductor substrate than the second well after the second etching process, epitaxial growth of embedded source regions within the first wells in the first sections of the semiconductor substrate, epitaxial growth of an embedded drain region within the second well on the second section of the semiconductor substrate, removal of the blind gates, and replacement of the dummy gates with a gate dielectric layer and metallic gate material on the gate dielectric layer.

[0006] Improved structures for a field-effect transistor and methods for forming a structure for a field-effect transistor are required. Summary

[0007] In one embodiment of the invention, a structure for a field-effect transistor is provided according to independent claim 1. Further advantageous embodiments thereof are defined in dependent claims 2 to 10.

[0008] In one embodiment of the invention, a method for manufacturing a field-effect transistor according to independent claim 11 is provided. Further advantageous embodiments thereof are defined in dependent claims 12 to 20. Brief description of the drawings

[0009] The accompanying drawings, which are included in and form part of this description, illustrate various embodiments of the invention and, together with a general description of the invention above and a detailed description of the embodiments below, serve to explain these embodiments. In the drawings, the same reference numerals in the different views refer to the same features. Fig. Figure 1 is a cross-sectional view of a structure for a fin-type field-effect transistor according to embodiments of the invention. Fig. Figure 2 is a cross-sectional view of a structure similar to Fig. 1 according to alternative embodiments of the invention. Fig. Figure 3 is a cross-sectional view of a structure for a planar field-effect transistor according to embodiments of the invention. Fig.Figure 4 is a cross-sectional view of a structure similar to Fig. 3 according to alternative embodiments of the invention. Detailed description

[0010] With reference to Fig. 1 and according to embodiments of the invention, a structure 10 for a field-effect transistor has a fin 12 which is arranged above a substrate 14 and projects upwards from it. The fin 12 and the substrate 14 can be formed from a single-crystal semiconductor material, such as single-crystal silicon. The fin 12 can be formed by structuring the substrate 14 using lithography and etching processes or by a self-aligning multi-structuring process.

[0011] A shallow trench insulation area 16 can surround the fin 12. The shallow trench insulation area 16 can be formed by depositing a layer of a dielectric material, such as silicon dioxide, by means of chemical vapor deposition and removing the deposited layer by means of an etching process. An upper section of the fin 12 is exposed above an upper surface of the shallow trench insulation area 16.

[0012] A gate structure 18 extends laterally along a longitudinal axis over and transversely to the fin 12. The gate structure 18 is oriented transversely to the fin 12 and overlaps and envelops the upper surface 11 and the side walls of a section (e.g., a channel region 17) of the fin 12. The gate structure 18 is also partially located on the upper surface of the shallow trench insulation region 16 on opposite sides of the fin 12. The gate structure 18 can comprise a gate electrode 20 made of a conductor, such as doped polycrystalline silicon (i.e., polysilicon) or an exit work metal, and a gate dielectric 22 made of an electrical insulator, such as silicon dioxide or a high-k dielectric material such as hafnium oxide. The gate structure 18 can be formed by a gate-first process flow or by a gate-last process flow, in which a dummy gate structure is replaced.The gate structure 18 can be a metal gate with a width in the range of 20 nanometers to 300 nanometers (e.g. 150 nanometers) and the gate dielectric 22 can be made of hafnium oxide with a thickness of about 2 nanometers.

[0013] In addition to the side surfaces or side walls 19 of the gate structure 18, side wall spacers 24 are arranged. The side wall spacers 24 can be formed by depositing a conformal layer of a dielectric material, such as silicon nitride, and etching the deposited conformal layer using an anisotropic etching process, such as reactive ion etching.

[0014] The structure 10 has source / drain regions 26, 28, which are arranged adjacent to the opposing side walls 19 of the gate structure 18, which are lined with spacers. The term "source / drain region" used here refers to a doped region of semiconductor material that can function as either the source or the drain of a field-effect transistor. In one embodiment, the source / drain region 26 in the structure 10 can provide a source, and the source / drain region 28 in the structure 10 can provide a drain. In an alternative embodiment, the source / drain region 26 in the structure 10 can provide a drain, and the source / drain region 28 in the structure 10 can provide a source.The source / drain regions 26 and 28 are doped to have a conductivity type of the same polarity, are formed at different times during the process flow, and are located next to opposing sidewalls 19 of the same gate structure 18, which are lined with spacers. The source / drain region 26 can be formed either before or after the formation of the source / drain region 28. The fin 12 represents a semiconductor body used to form the source / drain regions 26 and 28, which are asymmetrical due to the different ways in which they are formed.

[0015] The source / drain region 26 is formed by an epitaxial semiconductor layer coupled to a section of the semiconductor body formed by the fin 12. More precisely, a recess 30 adjacent to the gate structure 18 is etched into the fin 12, and the source / drain region 26 is subsequently formed within the recess 30. An etch mask can be formed by lithography over a section of the fin 12 that includes or will include the source / drain region 28 to create the recess 30. The etch mask can, for example, consist of a layer of an organic photoresist applied by a spin coating process, pre-fired, exposed to light projected through a photomask, fired after exposure, and developed with a chemical developer. After the formation of the etch mask, the recess 30 in the fin 12 can be formed by one or more etching processes.

[0016] The source / drain region 26 can be formed by the epitaxial growth of a layer of semiconductor material from the surfaces of the fin 12 adjacent to the recess 30. The etching mask is removed, and the section of the fin 12 in which the source / drain region 28 is or will be formed can be temporarily covered by a protective layer, e.g., a protective layer of a dielectric material (e.g., silicon nitride) that does not support epitaxial growth and that can be removed after the formation of the source / drain region 26. The source / drain region 26 can be in direct contact with the surfaces of the fin 12 adjacent to the recess 30.

[0017] The source / drain region 26 can be doped in situ with a concentration of a dopant during epitaxial growth. In one embodiment, the source / drain region 26 can be doped in situ with a p-type dopant (e.g., boron) during epitaxial growth, providing p-type conductivity. In an alternative embodiment, the source / drain region 26 can be doped in situ with an n-type dopant (e.g., phosphorus and / or arsenic) during epitaxial growth, providing n-type conductivity. The source / drain region 26 can comprise germanium, and in one embodiment, the source / drain region 26 can be formed from silicon germanium. In another embodiment, the source / drain region 26 can be formed from silicon germanium and comprise a p-type dopant.In an alternative embodiment, the source / drain region 26 can be made of silicon and contain an n-type dopant.

[0018] The source / drain region 28 can be formed by a masked ion implantation process in a section of the semiconductor body provided by the fin 12. For this purpose, an implantation mask can be formed by lithography over the section of the fin 12 that comprises the source / drain region 26. The implantation mask can, for example, have a layer of an organic photoresist applied by a spin coating process, pre-fired, exposed to light projected through a photomask, fired after exposure, and developed with a chemical developer. After the formation of the implantation mask, the source / drain region 28 can be formed in a section of the fin 12 by implantation of ions of a dopant.

[0019] The source / drain region 28 contains a concentration of an n-type or a p-type dopant. In one embodiment, the source / drain region 28 in the fin 12 can be formed by the implantation of ions of a p-type dopant (e.g., boron) that provides p-type electrical conductivity. In an alternative embodiment, the source / drain region 28 in the fin 12 can be formed by the implantation of ions of an n-type dopant (e.g., phosphorus and / or arsenic) that provides n-type conductivity. In one embodiment, the dopant concentrations of the source / drain region 26 and the source / drain region 28 can be equal or substantially equal. In one embodiment, the dopant concentrations of the source / drain region 26 and the source / drain region 28 can be different (i.e., not essentially the same), which is made possible by the differences in their formation.

[0020] During ion implantation, high-energy ions with ion trajectories terminating in the fin 12 over a depth range are introduced, as schematically indicated by the individual implantation arrows. The ions can be generated from a suitable source gas and implanted into the fin 12 under specified implantation conditions using an ion implantation tool. The implantation conditions (e.g., ion species, dose, kinetic energy, angle of inclination) can be selected to adjust the properties (e.g., depth profile) of the source / drain region 28. The implantation mask has a thickness sufficient to stop the high-energy ions before they reach the section of the fin 12 where the source / drain region 26 is formed. After the formation of the source / drain region 28, the implantation mask can be removed, for example, by ashing.

[0021] The source / drain region 28 has an upper surface that can coincide with an upper surface 11 of the fin 12, and the source / drain region 28 is located entirely on and below the upper surface 11 of the fin 12. In contrast, the upper surface 27 of the source / drain region 26 is not restricted to coinciding with the upper surface 11 of the fin 12, since the source / drain region 26 is a semiconductor material added to the fin 12. Accordingly, the upper surface 27 of the source / drain region 26 can either be raised above the upper surface 11 of the fin 12 or recessed below the upper surface 11 of the fin 12. Alternatively, the upper surface 27 of the source / drain area 26 can be coplanar to the upper surface 11 of the fin 12.

[0022] The field-effect transistor implemented in structure 10 can exhibit reduced leakage at the source / drain region 28 due to the use of ion implantation for its formation, while retaining the performance advantages of the source / drain region 26, which features a semiconductor material formed by epitaxial growth. In one embodiment, the field-effect transistor can be used as an input / output transistor in an integrated circuit and can have a gate length longer than typical gate lengths for a logic transistor.

[0023] With reference to Fig. 2, in which identical reference signs refer to identical features in Fig.1, and according to embodiments of the invention, the source / drain regions 26, 28 can be provided in a structure 10a for a fin-type field-effect transistor in which several gate structures 18 extend transversely to the fin 12 and overlap with corresponding channel regions 17 in the fin 12. The source / drain region 26 is arranged between an adjacent pair of gate structures 18, and the source / drain region 28 is arranged between an adjacent pair of gate structures 18. The formation of the source / drain region 26 and the separate formation of the source / drain region 28 can each be at least partially self-aligned by the gate structures 18.

[0024] With reference to Fig. 3, in which identical reference signs refer to identical features in Fig.1, and according to embodiments of the invention, the source / drain regions 26, 28 can be provided in a structure 32 for a planar field-effect transistor instead of the structure 10 for a fin-type field-effect transistor. The substrate 14a provides the sections of the semiconductor body used to form the source / drain regions 26, 28, as described above. The substrate 14a can be a bulk semiconductor substrate, such as a bulk wafer of single-crystal silicon, or a silicon-on-insulator substrate having a device layer of a single-crystal semiconductor material (e.g., single-crystal silicon). In one embodiment, the top surface 27 of the source / drain region 26 can be raised relative to a top surface 13 of the substrate 14a.In one embodiment, the upper surface 27 of the source / drain area 26 can be recessed relative to the upper surface 13 of the substrate 14a.

[0025] With reference to Fig. 4, in which the same reference signs refer to the same features in Fig. 3, and according to embodiments of the invention, the source / drain regions 26, 28 can be provided in a structure 32a for a planar field-effect transistor in which several gate structures 18 with corresponding channel regions 17 overlap in the substrate 14a. The source / drain region 26 is arranged between an adjacent pair of gate structures 18, and the source / drain region 28 is arranged between an adjacent pair of gate structures 18. The formation of the source / drain region 26 and the separate formation of the source / drain region 28 can each be at least partially self-aligned by the gate structures 18. Example

[0026] Various device structures for a fin-type field-effect transistor were evaluated by computer simulation using TCAD (Technology Computer-Aided Design) tools to model the electrical properties of the different device structures. The modeled device structures were identical except for the source and drain regions. The modeled device structures had a total device length of 260 nm, comprising a gate length of 150 nm, a source contact length of 35 nm, and a drain contact length of 35 nm.

[0027] For one of the modeled device structures (in particular epitaxial S / D regions), both source / drain regions were formed from an epitaxial semiconductor material containing boron as a p-type dopant. For another of the modeled device structures (in particular implanted S / D regions), both source / drain regions were formed by an implanted dopant profile located in the substrate and containing boron as a p-type dopant. In yet another of the modeled device structures (in particular an asymmetric device), the source was formed from an epitaxial semiconductor material containing boron as a p-type dopant, and the drain was formed by an implanted dopant profile located in the substrate and containing boron as a p-type dopant.

[0028] The values ​​of the electrical properties determined by the TCAD computer simulation for the various device structures are summarized in the table. TABEL Idlin Idsat Rodlin Idoff Isoff µA / µm µA / µm Ωµm nA / Finne nA / Finne epitaxial S / D areas 55 707 1970 7,77 0,02 implanted S / D areas 26 441 4531 0,195 0,038 asymmetric device with epitaxial layer on the side of drain 41 631 3201 0,199 0,031

[0029] As can be seen from the table, when the transistor is biased in the linear region (Idlin) for the asymmetric device, the drain current value lies between the Idlin value for the device with epitaxial source / drain regions and the Idlin value for the device with ion-implanted source / drain regions. Similarly, when the transistor is biased in the saturation region (Idsat) for the asymmetric device, the drain current value lies between the Idsat value for the device with epitaxial source / drain regions and the Idsat value for the device with ion-implanted source / drain regions. The contact resistance (Rodlin) value for the asymmetric device lies between the Rodlin value for the device with epitaxial source / drain regions and the Rodlin value for the device with ion-implanted source / drain regions.

[0030] As can be seen from the table, the value of the drain leakage current in the off-state (Idoff) of the asymmetric device is comparable to the value of Idoff for the device with ion-implanted source / drain regions and is significantly lower than the value of Idoff for the device with epitaxial source / drain regions. The value of the source leakage current when the transistor is in the off-state (Isoff) of the asymmetric device lies between the value of Isoff for the device with epitaxial source / drain regions and the value of Isoff for the device with ion-implanted source / drain regions.

[0031] Reducing the drain leakage current for the asymmetric device when the transistor is in the off state can be achieved without significantly impairing the device's performance.

[0032] The processes described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of raw wafers (e.g., a single wafer with multiple unpacked chips), as bare chips, or in a packaged form. In the latter case, the chip is mounted in a single-chip package (e.g., a plastic substrate with traces arranged on a mainboard or other higher-level substrate) or in a multi-chip package (e.g., a ceramic substrate with surface and / or buried interconnects). In each case, the chip can be integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of an intermediate or final product.

[0033] References to terms such as "vertical," "horizontal," etc., serve here as examples and not as limitations to establish a frame of reference. The term "horizontal," as used here, is defined as a plane parallel to a conventional plane of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms "vertical" and "normal" refer to a direction perpendicular to the horizontal just defined. The term "lateral" refers to a direction within the horizontal plane.

[0034] References herein to terms modified by approximate language, such as "approximately," "about," and "essentially," are not limited to the precisely stated value. The approximate language may correspond to the accuracy of an instrument used to measure the value and, unless otherwise dependent on the accuracy of the instrument, may indicate + / - 10% of the stated value(s).

[0035] A feature that is "connected" or "coupled" to another feature can be directly connected or coupled to the other feature, or one or more intervening features can be present. A feature can be "directly connected" or "directly coupled" to another feature if no intervening features are present. A feature can be "indirectly connected" or "indirectly coupled" to another feature if at least one intervening feature is present. A feature that is "on" another feature or "contacts" another feature can be directly on top of or in direct contact with the other feature, or one or more intervening features can be present. A feature can be "directly on" another feature or in "direct contact" with another feature if no intervening features are present.A feature can be “indirectly on” another feature or in “indirect contact” with another feature if at least one intermediate feature is present.

Claims

Structure (10) for a field-effect transistor, wherein the structure (10) comprises: a semiconductor body with a channel region (17); a gate structure (18) over the channel region (17); a first source / drain region (26); and a second source / drain region (28) in a second section of the semiconductor body, wherein the second source / drain region (28) comprises a second concentration of the dopant, wherein the channel region (17) is arranged in the semiconductor body between the first source / drain region (26) and the second source / drain region (28), wherein of the first source / drain region (26) and the second source / drain region (28), only the first source / drain region (26) is formed from an epitaxial semiconductor layer coupled to a first section of the semiconductor body, and wherein the epitaxial semiconductor layer comprises a first concentration of a dopant. Structure (10) according to claim 1, wherein the dopant is a p-type dopant. Structure (10) according to claim 1, wherein the semiconductor body is a fin (12). Structure (10) according to claim 3, wherein the fin (12) has an upper surface (11) and the second source / drain area (28) is formed completely under the upper surface (11) of the fin (12). Structure (10) according to claim 3, wherein the fin (12) has an upper surface, the first source / drain area (26) is formed in a recess in the fin (12) and the first source / drain area (26) has an upper surface which is raised above the upper surface (11) of the fin (12) or recessed below the upper surface (11) of the fin (12). Structure (10) according to claim 1, wherein the semiconductor body is a bulk semiconductor substrate or a device layer of a silicon-on-insulator substrate. Structure (10) according to claim 6, wherein the first source / drain region (26) has a top surface (27) located above or below a top surface of the bulk semiconductor substrate or a top surface of the device layer of the silicon-on-insulator substrate. Structure (10) according to claim 1, wherein the epitaxial semiconductor layer comprises germanium. Structure (10) according to claim 1, wherein the epitaxial semiconductor layer comprises silicon germanium and the dopant is a p-type dopant. Structure (10) according to claim 1, wherein the first concentration of the dopant differs from the second concentration of the dopant. A method for forming a field-effect transistor, comprising: forming a gate structure (18) over a channel region (17) in a semiconductor body; epitaxially growing an epitaxial semiconductor layer having a first concentration of a dopant from a first section of the semiconductor body to provide a first source / drain region (26); and implanting ions into a second section of the semiconductor body to form a second source / drain region (28) having a second concentration of the dopant, wherein the channel region (17) in the semiconductor body is arranged between the first source / drain region (26) and the second source / drain region (28), wherein of the first source / drain region (26) and the second source / drain region (28), only the first source / drain region (26) is formed from the epitaxial semiconductor layer. Method according to claim 11, wherein the dopant is a p-type dopant. Method according to claim 11, wherein the semiconductor body is a fin (12). The method of claim 13, further comprising: etching a recess (30) into the fin (12), wherein the first source / drain region (26) is formed by an epitaxial growth process in the recess (30) in the fin (12). Method according to claim 14, wherein the first source / drain region (26) has an upper surface (27) which is located above or below the upper surface (11) of the fin (12). Method according to claim 11, wherein the semiconductor body is a bulk semiconductor substrate or a device layer of a silicon-on-insulator substrate. Method according to claim 16, wherein the first source / drain region (26) has a top surface (27) that is located above or below a top surface of the bulk semiconductor substrate or a top surface of the device layer of the silicon-on-insulator substrate. Method according to claim 11, wherein the semiconductor layer comprises germanium. The method of claim 11, wherein the semiconductor layer comprises silicon germanium and the dopant is a p-type dopant. Method according to claim 11, wherein the first concentration of the dopant differs from the second concentration of the dopant.

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