ULTRA-COMPACT SIDE BUFFER

Abstract

Device comprising: a storage array; a measuring amplifier (SA) coupled to the memory array and to an input / output data line (I / O data line), wherein the SA is configured to receive data bits via the I / O data line in conjunction with a program operation; a digital-to-analog converter (DAC) coupled to the SA, wherein the DAC is designed to convert the data bits into an analog voltage value; and an analog storage element coupled to the DAC, wherein the analog storage element is designed to store the analog voltage value for a period of time until the data bits are programmed into the memory array.

Description

TECHNICAL FIELD

[0001] Exemplary embodiments of the invention relate generally to storage subsystems, and in particular to an ultra-compact side buffer of a storage device. BACKGROUND

[0002] A storage subsystem can contain one or more storage devices that store data. These storage devices can be, for example, non-volatile or volatile. Generally, a host system can use a storage subsystem to store data in and retrieve data from the storage devices. German patent application DE 11 2018 006 639 T5 describes a storage device that includes a plurality of memory cells arranged in a matrix, each containing a transistor and a capacitor. The transistor includes a first gate and a second gate, each encompassing an overlapping area with a semiconductor layer between them. The storage device is capable of operating in "write mode," "read mode," "update mode," and "non-volatile mode."In "update mode," after data held in the memory cell has been read, the data is written back to the memory cell for a period of time. In "NV mode," after data stored in the memory cell has been read, the data is written back to the memory cell for a second period of time, and then a potential is applied to the second gate, at which point the transistor is switched off. By operating the storage device in "NV mode," data can be stored for a long time even if the power supply to the memory cell is interrupted. Multi-level data can be stored in the memory cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The present invention will be more fully understood with reference to the detailed description below and the accompanying drawings of some embodiments of the invention. Fig. Figure 1 shows an exemplary computer system that includes a memory subsystem according to some embodiments. Fig. Figure 2 is a block diagram of a storage device communicating with a storage subsystem controller of a storage subsystem according to an exemplary embodiment. Fig. 3A is an example of a side buffer circuit from one of the storage devices from Fig. 1-2 according to some embodiments. Fig. 3B is an exemplary measuring amplifier (SA) of the side buffer circuit from Fig. 3A according to some exemplary embodiments. Fig. 3C is an exemplary analog storage element and a transistor logic of the side buffer circuit from Fig. 3A according to some exemplary embodiments. Fig. 4 is a set of corresponding timing diagrams that map SA signals at the transistor logic to clock signals and analog signal values ​​within the side buffer circuit. Fig. 3A-3C correlate, according to some exemplary embodiments. Fig. Figure 5 is a timing diagram and a corresponding set of digital and analog values ​​illustrating an exemplary refresh operation for a value of voltage stage five (L5) stored in the analog memory component according to an embodiment. Fig. Figure 6 is a timing diagram and a corresponding set of digital and analog values ​​illustrating an exemplary analog-to-digital (A2D) conversion of a value stored in the analog memory component according to some embodiments. Fig. 7A is a timing diagram and a corresponding set of digital and analog values ​​that show the steps for performing a read operation through the side buffer circuit. Fig. 3A-3C, according to one exemplary embodiment. Fig. Figure 7B is a diagram illustrating various analog voltage read levels to be copied into the measuring amplifier of the side buffer circuit for transmission on an I / O data line, according to one embodiment. Fig. Figure 8A is a flowchart of an exemplary method for operating a side buffer circuit according to an embodiment. Fig. Figure 8B is a flowchart of another example of operating a side buffer circuit according to an embodiment. Fig. Figure 9 is a block diagram of an exemplary computer system in which embodiments of the present invention can function. DETAILED DESCRIPTION

[0004] Exemplary embodiments of the present invention relate to an ultra-compact side buffer of a storage device of a storage subsystem. A storage subsystem can be a storage device, a storage module, or a hybrid of a storage device and a storage module. Examples of storage devices and storage modules are given below in connection with Fig. 1. In general, a host system can use a storage subsystem that contains one or more components, such as storage devices that store data. The host system can provide data to be stored in the storage subsystem and can request data to be retrieved from the storage subsystem.

[0005] A storage device can be a non-volatile storage device. An example of a non-volatile storage device is a negative AND storage device (NAND storage device). Other examples of non-volatile storage devices are discussed below in connection with Fig. 1. A non-volatile memory device is a component consisting of one or more chips. Each chip can contain one or more layers. The layers can be grouped into logic units (LUNs). In some types of non-volatile memory devices (e.g., NAND devices), each layer contains a set of physical blocks. Each block contains a set of pages. Each page contains a set of memory cells ("cells"). A cell is an electronic circuit that stores information. Depending on the cell type, a cell can store one or more bits of binary information and has different logical states that correlate with the number of bits stored. The logical states can be represented by binary values, such as "0" and "1," or combinations of such values.

[0006] A storage device can consist of bits arranged in a two-dimensional grid, also known as a memory array. The memory cells are etched onto a silicon wafer in an array of columns (hereinafter also referred to as bit lines) and rows (hereinafter also referred to as word lines). A word line can refer to one or more rows of memory cells of a storage device, which are used with one or more bit lines to generate the address of each of the memory cells. The intersection between a bit line and a word line forms the address of the memory cell. A block, as used below, refers to a unit of the storage device used to store data and can comprise a group of memory cells, a group of word lines, a single word line, or individual memory cells.

[0007] In certain storage subsystems, it is common to receive a request to perform a memory access operation, such as a program operation to transfer data from a host system to a memory array of a storage device, and then subsequently receive a request to perform another memory access operation, such as a read operation, on the same data from the host system. The storage device to be programmed contains a number of page buffers (also called page caches).

[0008] The data to be programmed is stored in a page buffer circuit, with the data being written to the corresponding cells of the memory array. Using a multi-pass programming scheme, specific page types of a particular memory cell can also be programmed at different times. A quad-level cell (QLC) memory cell, for example, can have a total of four logical pages: a lower logical page (LP), an upper logical page (UP), an additional logical page (XP), and a top logical page (TP), with each logical page storing one data bit. Depending on the programming scheme, the LP might be programmed in one pass, and the UP, XP, and TP in a second pass. Other programming schemes are possible.In this example, however, before programming UP, XP, and TP in the second pass, the data from the LP can first be read from the memory cell and stored in the side buffer circuit of the storage device. In this way, the side buffer circuit holds a certain amount of data that is to be programmed into or read from the memory array.

[0009] In certain storage devices, adding an extra memory level requires adding eight pages, each 64 kilobytes (KB) in size, thus necessitating a significant additional page buffer area to accommodate the extra memory level. Each page buffer circuit of a storage device contains, for example, a measuring amplifier, which includes a latch, a capacitor, other circuitry, memory elements, and facilities. The memory elements can be digital memory elements, such as dynamic random-access memory (DRAM), static random-access memory (SRAM), or similar memory elements for storing data bits. The page buffer circuit also includes an input / output (I / O) sub-circuit with a latch and a column selector circuit.This side buffer area increases in storage devices as the storage devices become larger, so the side buffer area can be a hindrance to the manufacture of larger storage devices and components.

[0010] Aspects of the present invention address the above and other shortcomings by reducing the size of the side buffer circuits, thereby creating space for additional memory cells, such as NAND-type or other types of memory arrays. One way to reduce the size of side buffer circuits is to decrease the number of digital memory elements (e.g., data registers) required to buffer data to be written to or read from the memory array. In various embodiments, two or more (e.g., multiple) digital memory elements in a side buffer circuit are replaced by a single analog memory element that can store multiple different analog voltage values ​​(or states) corresponding to multiple different digital values ​​or states, e.g., of multiple data bits.Furthermore, the logic of the side buffer circuit is configured to distinguish the data bits that are related to the voltage value stored in the analog memory element, e.g. when performing a digital / analog and analog / digital conversion between the data bits and the voltage values ​​(or states).

[0011] In one embodiment, the analog storage element is a capacitor. In another embodiment, the analog storage element is a power cell or an energy cell that stores energy at a level corresponding to the analog voltage value or state that corresponds to the digital bits stored (or to be stored) in the memory array. The described side-buffer circuit can also include a digital-to-analog converter (DAC) to convert data bits into analog voltage values ​​to be temporarily stored in the analog storage element. Furthermore, the side-buffer circuit can also include an analog-to-digital converter (ADC) to convert the analog voltage values ​​of the analog storage element into data bits to be stored in the memory array or read out via an I / O data line of the I / O sub-circuit.In some embodiments, the DAC and ADC circuits have overlapping components and therefore do not need to take up much space compared to the digital storage elements that are replaced by the analog storage element.

[0012] Among the advantages of the systems and methods implemented according to some embodiments of the present invention are the reduction of side buffer circuits, thereby reducing the side buffer area of ​​a storage device by 40-50% or more without additional latency or performance loss. This is a significant reduction in the overhead of side buffer circuits, making it possible to increase the area of ​​the storage array without such a significant additional side buffer area overhead. Further advantages are obvious to those skilled in the art in the field of managing thermally induced processes in a storage subsystem, which are explained below.

[0013] Fig. Figure 1 shows an exemplary computer system 100, which includes a storage subsystem 110 according to some embodiments of the present invention. The storage subsystem 110 can contain media such as one or more volatile storage devices (e.g., storage device 140), one or more non-volatile storage devices (e.g., storage device 130), or a combination thereof.

[0014] A Memory Subsystem 110 can be a storage device, a memory module, or a combination of both. Examples of a storage device include a solid-state drive (SSD), a flash drive, a USB flash drive (Universal Serial Bus Flash Drive), an eMMC drive (Embedded Multi-Media Controller Drive), a UFS drive (Universal Flash Storage Drive), an SD card (Secure Digital Card), and a hard disk drive (HDD). Examples of memory modules include a dual inline memory module (DIMM), a small-outline DIMM (SO-DIMM), and various types of non-volatile dual inline memory modules (NVDIMMs).

[0015] The computer system 100 can be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other means of transport), an Internet of Things (IoT)-enabled device, an embedded computer (e.g., one such as is contained in a vehicle, an industrial plant, or a networked commercial device), or a computing device that includes a storage and processing device.

[0016] The computer system 100 can comprise a host system 120 connected to one or more storage subsystems 110. In some embodiments, the host system 120 is connected to several storage subsystems 110 of different types. Fig. Figure 1 shows an example of a host system 120 connected to a storage subsystem 110. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which may be an indirect communicative connection or a direct communicative connection (e.g., without intermediary components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0017] The Host System 120 can contain a processor chipset and a software stack that is executed by the processor chipset. The processor chipset can contain one or more cores, one or more caches, a memory controller (e.g., NVDIMM controller), and a memory protocol controller (e.g., PCIe controller, SATA controller). The Host System 120 uses the Memory Subsystem 110 to, for example, write data to and read data from the Memory Subsystem 110.

[0018] The Host System 120 can be connected to the Storage Subsystem 110 via a physical host interface. Examples of a physical host interface include, but are not limited to, a SATA (Serial Advanced Technology Attachment) interface, a PCIe (Peripheral Component Interconnect Express) interface, a USB (Universal Serial Bus) interface, Fibre Channel, SAS (Serial Attached SCSI), a DDR (Double Data Rate) memory bus, SCSI (Small Computer System Interface), a DIMM (Dual Inline Memory Module) interface (e.g., a DIMM socket interface that supports DDR (Double Data Rate)), etc. The physical host interface can be used for data transfer between the Host System 120 and the Storage Subsystem 110. The Host System 120 can also use an NVM Express (NVMe) interface to access components (e.g.,Storage devices 130) can be accessed when the storage subsystem 110 is connected to the host system 120 via the physical host interface (e.g., PCIe bus). The physical host interface can provide an interface for the transmission of control, address, data, and other signals between the storage subsystem 110 and the host system 120. Fig. Figure 1 shows a storage subsystem 110 as an example. In general, the host system 120 can access multiple storage subsystems via a shared communication link, multiple separate communication links, and / or a combination of communication links.

[0019] The storage devices 130 and 140 can comprise any combination of different types of non-volatile and / or volatile storage devices. The volatile storage devices (e.g., storage device 140) can be random-access memory (RAM), such as dynamic random-access memory (DRAM) and synchronous dynamic random-access memory (SDRAM), but are not limited to these.

[0020] Some examples of non-volatile storage devices (e.g., storage device 130) include negative-AND-type flash memory (NAND-type) and write-in-place memory, such as a three-dimensional interface storage device (3D cross-point storage device), which is an interface array of non-volatile memory cells. An interface array of non-volatile memory cells, in conjunction with a stackable cross-grid data access array, can perform bit storage based on a change in bulk resistance. Furthermore, unlike many flash memories, non-volatile interface memory can perform a write-in-place operation, in which a non-volatile memory cell can be programmed without first erasing it. NAND-type flash memories include, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0021] Each of the memory devices 130 can contain one or more arrays of memory cells. One type of memory cell, for example, single-level cells (SLCs), can store one bit per cell. Other types of memory cells, such as multi-level cells (MLCs), triple-level cells (TLCs), quad-level cells (QLCs), and penta-level cells (PLCs), can store multiple bits per cell. In some embodiments, each of the memory devices 130 can comprise one or more arrays of memory cells, such as SLCs, MLCs, TLCs, QLCs, PLCs, or any combination thereof. In some embodiments, a particular memory device can contain an SLC area and an MLC area, a TLC area, a QLC area, or a PLC area of ​​memory cells.The memory cells of storage devices 130 can be grouped as pages, which can refer to a logical unit of the storage device used to store data. In some memory types (e.g., NAND), the pages can be grouped into blocks.

[0022] Although non-volatile memory components, such as a 3D interface array of non-volatile memory cells and NAND-type flash memory (e.g., 2D NAND, 3D NAND), are described, the storage device 130 can be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-selecting memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magneto-random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), negative or (NOR) flash memory, or electrically erasable programmable read-only memory (EEPROM).

[0023] A memory subsystem controller 115 (or controller 115 for simplicity) can communicate with the memory devices 130 to perform operations such as reading, writing, or erasing data from the memory devices 130, and other such operations. The memory subsystem controller 115 can include hardware such as one or more integrated circuits and / or discrete components, a buffer memory, or a combination thereof. The hardware can include a digital circuit with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 can be a microcontroller, a special logic circuit (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or another suitable processor.

[0024] The memory subsystem controller 115 can include a processing device containing one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the example shown, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logical sequences, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0025] In some embodiments, the local memory 119 can contain memory registers that store memory pointers, retrieved data, etc. The local memory 119 can also contain a read-only memory (ROM) for storing microcode. Although the exemplary memory subsystem 110 consists of Fig. 1 is shown to contain the memory subsystem controller 115, in another embodiment of the present invention a memory subsystem 110 may not contain a memory subsystem controller 115 and instead rely on external control (e.g. provided by an external host or by a processor or controller separate from the memory subsystem).

[0026] In general, the storage subsystem controller 115 can receive commands or operations from the host system 120 and translate these commands or operations into instructions or appropriate commands to achieve the desired access to the storage devices 130. The storage subsystem controller 115 can also be responsible for other operations, such as wear-leveling operations, garbage collection operations, error detection and correction (ECC) code operations, encryption operations, caching operations, and address translations between a logical address (e.g., logical block address (LBA), namespace) and a physical address (e.g., physical block address) related to the storage devices 130. The storage subsystem controller 115 can also include a host interface circuit to communicate with the host system 120 via the physical host interface.The host interface circuit can convert commands received from the host system into command instructions to access the storage devices 130, and convert responses related to the storage devices 130 into information for the host system 120.

[0027] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and addressing circuitry (e.g., a row decoder and a column decoder) that can receive an address from the memory subsystem controller 115 and decode the address to access the memory devices 130.

[0028] In some embodiments, the storage devices 130 include local media controllers 135 that work in conjunction with the memory subsystem controller 115 to perform operations on one or more memory cells of the storage devices 130. An external controller (e.g., memory subsystem controller 115) can manage the storage device 130 externally (e.g., perform media management operations on the storage device 130). In some embodiments, the memory subsystem 110 is a managed storage device comprising a raw storage device 130 with control logic (e.g., local media controller 135) on the chip and a controller (e.g., memory subsystem controller 115) for media management within the same storage device chip. An example of a managed storage device is a managed NAND device (MNAND device).In various embodiments, the storage devices 130 include a side buffer circuit 138 to temporarily store (e.g., buffer) data before it is stored in or read from the storage devices 130. Numerous space-saving improvements to the side buffer circuit 138 (or similar types of side caches) are discussed in more detail below.

[0029] Fig. Figure 2 is a simplified block diagram of a first device in the form of a storage device 130, which according to an embodiment is connected to a second device in the form of a storage subsystem controller 115 of a storage subsystem (e.g. the storage subsystem 110 from Fig. 1) communicates. Some examples of electronic systems are personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recording devices, games, appliances, vehicles, wireless devices, mobile phones, and the like. The memory subsystem controller 115 (e.g., a controller outside the memory device 130) can be a memory controller or another external host device.

[0030] The storage device 130 comprises an array of memory cells 204, logically arranged in rows and columns. Memory cells of a logical row are normally connected to the same access line (e.g., a word line), while memory cells of a logical column are normally selectively connected to the same data line (e.g., a bit line). A single access line can be connected to more than one logical row of memory cells, and a single data line can be connected to more than one logical column. Memory cells (in Fig. 2 (not shown) of at least one area of ​​the array of memory cells 204 can be programmed to one of at least two target data states.

[0031] Row decoder circuits 208 and column decoder circuits 210 are provided to decode address signals. Address signals are received and decoded to access the array of memory cells 204. The storage device 130 also includes an input / output control circuit 212 (I / O controller) to manage the input of commands, addresses, and data to the storage device 130, as well as the output of data and status information from the storage device 130. An address register 214 is connected to the I / O controller 212 and the row decoder circuit 208 and the column decoder circuit 210 to lock the address signals before decoding. An instruction register 224 is connected to the I / O controller 212 and the control logic of the local media controller 135 to lock incoming commands.

[0032] A controller (e.g., the local media controller 135 within the storage device 130) controls access to the array of memory cells 204 in response to instructions and generates status information for the external storage subsystem controller 115. That is, the local media controller 135 is configured to perform access operations (e.g., read operations, program operations, and / or erase operations) on the array of memory cells 204. The local media controller 135 communicates with the row decoder circuit 208 and the column decoder circuit 210 to control these circuits in response to addresses.

[0033] The local media controller 135 is also connected to a cache register 218. The cache register 218 stores incoming or outgoing data according to the instructions of the local media controller 135 to temporarily store data while the array of memory cells 204 is busy writing or reading other data. During a programming operation (e.g., a write operation), data can be passed from the cache register 218 to the data register 22 to be transferred to the array of memory cells 204; then, new data can be temporarily stored in the cache register 218 by the I / O controller 212. During a read operation, data can be passed from the cache register 218 to the I / O controller 212 to be output to the memory subsystem controller 115; then, new data can be passed from the data register 220 to the cache register 218.The cache register 218 and / or the data register 220 can form a side buffer of the storage device 130 (e.g., a part thereof). A side buffer can also contain acquisition devices (in . Fig. (2 not shown) to capture a data state of a memory cell of the array of memory cells 204, e.g., by capturing a state of a data line connected to that memory cell. A status register 222 can communicate with the I / O controller 212 and the local memory controller 135 to store the status information for output to the memory subsystem controller 115.

[0034] The storage device 130 receives control signals at the storage subsystem controller 115 from the local media controller 135 via a control link 232. These control signals can include, for example, a chip enable (CE#), a command latch enable (CLE), an address latch enable (ALE), a write enable (WE#), a read enable (RE#), and a write protect (WP#). Additional or alternative control signals (not shown) can be received via the control link 232, depending on the type of storage device 130. The storage device 130 receives command signals (representing commands), address signals (representing addresses) and data signals (representing data) from the storage subsystem controller 115 via a multiplexed input / output bus (I / O bus) 234 and outputs data to the storage subsystem controller 115 via the I / O bus 234.

[0035] Commands can be received, for example, via the input / output pins (I / O pins) [7:0] of I / O bus 234 at I / O controller 212 and then written to instruction register 224. Addresses can be received via the input / output pins (I / O pins) [7:0] of I / O bus 234 at I / O controller 212 and then written to address register 214. Data can be received via the input / output pins (I / O pins) [7:0] for an 8-bit device or the input / output pins (I / O pins) [15:0] for a 16-bit device at I / O controller 212 and subsequently written to cache register 218. The data can then be written to data register 220 for programming the array of memory cells 204.

[0036] In one embodiment, the cache register 218 can be omitted, and the data can be written directly to the data register 220. The data can also be output via input / output (I / O) pins [7:0] for an 8-bit device or the input / output (I / O) pins [15:0] for a 16-bit device. Although reference is made to I / O pins, they can include any conductive node that allows an electrical connection to the storage device 130 through an external device (e.g., the memory subsystem controller 115), such as conductive pads or conductive bumps as are commonly used.

[0037] It is obvious to the person skilled in the art that additional circuits and signals may be provided and that the storage device 130 consists of Fig. 2 has been simplified. It should be recognized that the functionality of the various block components, which refer to Fig. 2. The functions described do not necessarily have to be divided among different components or component parts of an integrated circuit device. For example, a single component or a section of a component of an integrated circuit device can be adapted to provide the functionality of more than one block component. Fig. 2. Alternatively, one or more components or component parts of an integrated circuit can be combined to provide the functionality of a single block component. Fig. 2 to fulfill.

[0038] Furthermore, although specific I / O pins are described according to common conventions for receiving and outputting the various signals, it is additionally noted that other combinations or numbers of I / O pins (or other I / O node structures) may be used in the various implementation examples.

[0039] Fig. 3A is an exemplary side buffer circuit 338 of one of the storage devices 130. Fig. 1-2, e.g., a storage device 330, according to some embodiments. In various embodiments, the storage device 330 comprises a storage array 302 and the side buffer circuit 338. In some embodiments, the side buffer circuit 338 is the side buffer circuit 128 from Fig. 1.

[0040] In these embodiments, the side buffer circuit 338 comprises a measuring amplifier (SA) 308 coupled to the memory array 302, an I / O sub-circuit 312 coupled to the SA 308, one or more analog memory elements 322, and transistor logic 328. The side buffer circuit 338 may further comprise an ADC 316 coupled between the SA 308 and the one or more analog memory element(s) 322, and a DAC 318 coupled between the SA 308 and the analog memory element 322. The transistor logic 328 may also be coupled to the ADC 316 and the DAC 318.

[0041] In one embodiment, the analog storage element 322 is a capacitor, for example, a high-capacitance capacitor. The capacitor can be a discrete component, such as one mounted on a printed circuit board (PCB), or an integrated component formed within the substrate of the chip or component underlying the side-buffer circuit 338 in various embodiments. In another embodiment, the analog storage element 322 is a power cell or energy cell that stores energy at a level corresponding to the analog voltage value or state corresponding to the digital bits stored (or to be stored) in the memory array 302.

[0042] The storage device 330 may further include an I / O data line 314, which is connected to the I / O sub-circuit 312. In one embodiment, the I / O data line 314 is coupled to a local media controller, such as the local media controller 135, to exchange data bits with the host system 120, for example, by executing program operations and read operations. Furthermore, in another embodiment, the I / O sub-circuit 312 is part of or integrated into the SA 308, an example of which is shown in Fig. 3B is shown.

[0043] In some embodiments, the SA 308 receives data bits via the I / O data line 314 in conjunction with a program operation, e.g., using the I / O sub-circuit 312. The DAC 318 converts the data bits into an analog voltage value. The analog memory element(s) 322 stores the analog voltage value for a certain period of time until the data bits are programmed into the memory array 302. In one embodiment, the data bits belong to a page of data to be stored in the memory array 302. For example, after the specified time period, the ADC 316 can convert the analog voltage value into the data bits, so that the SA 308 can then program the data bits into the memory array 302.

[0044] In some embodiments, the SA 308 retrieves data bits from the memory array 302 in response to a memory operation. The DAC 318 converts the data bits into an analog voltage value. The analog memory element(s) 322 stores the analog voltage value for a certain period of time until the data bits are transferred to the I / O data line 314, for example, using the I / O sub-circuit 312. In one embodiment, the data bits belong to a page of data that was previously stored in the memory array 302. For example, after the specified time period, the ADC 316 can convert the analog voltage value into the data bits so that the SA 308 can transfer the data bits via the I / O data line 314.

[0045] Fig. 3B is an exemplary measuring amplifier (SA) 308 of the side buffer circuit 338 from Fig. 3A according to some embodiments. The SA 308 can detect weak current signals from a bit line representing a data bit (1 or 0) stored in a memory cell of the memory array 302 and amplify the small voltage swing to detectable levels so that the data can be correctly interpreted by the logic outside the memory. The SA 308 can also perform this operation in reverse for data bits received via the I / O data line 314 in order to program the data bits into a memory cell of the memory array 302.

[0046] In this embodiment, the I / O sub-circuit 312 can be integrated into the SA 308. The I / O sub-circuit 312 can, for example, contain a gate-connected pair of transistors (DL and DLN) coupled to the I / O data line 314, e.g., via a common measuring line (CSL). The sources of these gate-connected transistors can be coupled to a latch 332 of the SA 308. The latch (intermediate storage) 332 can capture and hold the incoming bits (e.g., digital values) between two measuring amplifier connections (SAB and SA).

[0047] The Latch 332 can be, for example, a set / reset latch, an SR latch, or a bistable multivibrator capable of holding two states, e.g., one state equivalent to a zero ("0") and another equivalent to a one ("1"). The Latch 332 can, for example, comprise a pair of coupled transistors Sa_R and Sa_S. In one embodiment, the Latch 332 outputs a high voltage to a digital data line 336 of the SA 308 when the gate of the Sa_S gate goes high. Conversely, the Latch 332 outputs a low voltage to the digital data line 336 when the gate of the Sa_R gate goes high.

[0048] A reset transistor (RST1), coupled to the sources of the interconnected transistors, can be selectively activated to discharge the voltage on the digital data line 336. Unless otherwise specified, the transistors mentioned here are n-type metal-oxide-semiconductor devices (NMOS devices). The SA 308 may also include a measuring amplifier capacitor (Csa) in which each data bit is stored when the bit is programmed into the memory array 302 or read from the memory 302 along a bit line (BL) coupled to the digital data line 336. The other transistors in the SA 308 are Fig. The 3B shown support the storage, power supply and programming of the bits for the 302 memory field.

[0049] For example, a bitline capacitor transistor (BLC1) can be placed between the digital data line 336 and the Csa, together with a second set of enable transistors 342, to forward the data bits from the digital data line 336 to be stored on the Csa for programming. A first set of enable transistors 346 can work together with a Tc_iso transistor to forward the bits from the Csa to the bitline.

[0050] Fig. 3C is an example of the analog storage element 322 and the transistor logic 328 of the side buffer circuit 338 from Fig. 3A according to some embodiments. In one embodiment, the analog storage element 322 is, for example, a first capacitor (C1) with a higher capacitance, such as between 7 and 9 femtofarads (fF), e.g., 8 ff. The first capacitor C1 can be a discrete component, for example, mounted on a printed circuit board (PCB), or an integrated component formed within (e.g., arranged in) the substrate of an integrated circuit device, which in various embodiments forms the basis of the side buffer circuit 338.

[0051] The ADC 316 and the DAC 318 can be coupled to C1 via an analog DC line (A_DC). Furthermore, a pre-charge transistor (PRE1) can be coupled to a voltage supply and the first capacitor, with the pre-charge transistor charging the first capacitor to an initial voltage level. The analog storage elements 322 can also include a second capacitor (C2) connected in parallel to the first capacitor (C1), which is approximately 4 to 20 times smaller than the first capacitor. In one embodiment, the second capacitor is, for example, between 0.5 and 2 fF, e.g., 1 fF.

[0052] In some embodiments, the side buffer circuit 338 includes the transistor logic 328, which is connected between the first capacitor (C1) and the second capacitor (C2). The transistor logic 328 is intended to selectively activate the second capacitor (C2) to consume charge from the first capacitor (C1) until the first capacitor stores the analog voltage value representing the digital bits detected by the measuring amplifier. This process is described with reference to Fig. 4 discussed in more detail.

[0053] In one embodiment, the transistor logic 328 comprises a clock-controlled transistor (CLK1) and an SA-controlled transistor (SA). When these transistors are switched ON, the charge on C1 is balanced by C2, thereby reducing the voltage across C1 by a charge quantity (Q_DC), e.g., the consumed charge. The transistor logic 328 can further include a discharge transistor (RST2) coupled to the second capacitor (C2) to discharge the second capacitor by the consumed charge from the first capacitor.

[0054] In some embodiments, the transistor logic 328 also includes a boost device 350, which is coupled to and configured with the first capacitor (C1) to supply a boost voltage to the charge stored on C1. The boost device 350 can be a p-type MOS device (PMOS), a diode, or a similar device capable of supplying a significant amount of voltage charge to C1. The voltage charge supplied by the boost device 350 makes it possible to increase the analog voltage value stored on the first capacitor (C1) by a certain amount, depending on the voltage level (L0-L7), when the analog voltage value is sent to the SA 308, so that it can be correctly interpreted by the SA 308. For example, the boost to C1 can compensate for a limit voltage (Vth) of a main transistor of the ADC 316 (see Fig. 6) The voltage levels, such as L0-L7, can be understood to correspond to one or more logical states of the memory cells.

[0055] Fig. Figure 4 shows a set of corresponding timing diagrams, which, according to some embodiments, map SA signals at the transistor logic to clock signals and analog signal values ​​within the side buffer circuit of the Fig. 3A-3C correlate. The upper part of the diagram illustrates how the analog voltage value (A_DC) for different voltage levels (L0 to L7) can be stored, for example, in a multi-level cell (MLC). As discussed, this analog voltage value occupies the space of three bits in this example, thus replacing three digital registers and consequently a significant side buffer area. In one embodiment, a charge quantity (e.g., 1Q) is specified as 0.2 V, which may correspond to the charge that C2 can consume. Thus, a supply voltage of 2.2 V may correspond to the highest analog voltage value (A_DC_7), the next lowest voltage value (A_DC_6) is 2.0 V, or 0.2 V lower than the highest analog voltage value, and so on over each of the eight analog voltage values ​​(A_DC_7 to A_DC_0) that are related to the limit voltage values ​​L0 to L7.The digital values ​​(SA_7 to SA_0) listed below the analog voltage values ​​illustrate corresponding values ​​acquired by the SA 308 for the corresponding analog voltage value stored in the first capacitor (C1).

[0056] With further reference to Fig. Figure 4 illustrates the waveforms in the lower part of the diagram, representing various signal values ​​within the SA 308 and the transistor logic 328 of the side buffer circuit 338, including those at CLK1, RST2, PRE1, RST1, SA_R, and CSL, which were introduced previously. In one embodiment, after data has been received on the CSL line, the PRE1 signal can precharge C1 to an initial voltage value (e.g., 2.2 V), and RST1 can predischarge the latch 332. This puts the side buffer circuit 338 into an initial set of states and makes it operational. The RST2 signal can then discharge C2 during an off-clock cycle (e.g., before CLK1 goes high), while C2 is operating, to discharge C1 incrementally by the amount of charge, in this example 0.2 V, although other charge increments are conceivable.

[0057] Fig. Figure 5 shows a timing diagram and a corresponding set of digital and analog values ​​illustrating an exemplary refresh operation for a limit voltage level of five (L5) stored in the analog memory component, according to one embodiment. The analog voltage value stored in the first capacitor (C1) can be refreshed once in each time period, for example, every 100 microseconds (µs), to ensure that the capacitor charge does not fall below a variance limit, which would cause the analog voltage value to now correspond to the wrong digital value or state. In some embodiments, the refresh interval can change with temperature, for example, closer to 30 µs at 130°F compared to 100 µs at 90°F. These values ​​and intervals can be adjusted to different levels.

[0058] In one embodiment, the refresh operation is performed by converting the analog voltage value back into the digital value or state held in the SA 308, and then back again into the analog voltage value, which is then fed back into the first capacitor C1. Although Fig. If 5 shows a refresh of an analog voltage value that is related to L5, the transistor logic 228 can cause a refresh of any of the analog voltage values ​​that are related to the limit voltage values ​​(L1-L7) in order to in turn cause a refresh of UP and XP of the memory cell.

[0059] Fig. Figure 6 shows a timing diagram and a corresponding set of digital and analog values ​​illustrating an exemplary analog-to-digital (A2D) conversion of a value stored in the analog memory component according to several embodiments. From left to right, the analog voltage values ​​(A_DC) at time zero (Time_0), corresponding to voltage values ​​L0-L7, are shown first. Further along the timing diagram, the SA 308 can be reset by activating the RST1 and SA_R signals, followed by successive boosts of the analog voltage value at C1 to update the corresponding digital value or state of the bit in the SA 308. The timing diagram illustrates the boost values ​​up to the fifth limit voltage value (L5) of the several possible digital states.

[0060] The voltage charge supplied by the Boost Device 350 can, as referenced in Fig. Section 3C discusses how to boost the analog voltage value stored in the first capacitor (C1) by a specific amount, dependent on the voltage level (L0-L7), when the analog voltage value is sent to the SA 308, in order for it to be interpreted correctly by the SA 308. For example, boosting C1 can compensate for a threshold voltage (Vth) of a main transistor of the ADC 316, which in one embodiment might be 2.3 V. Therefore, the boost values ​​can be calculated by subtracting a specific voltage, related to the threshold voltage value (L5 in this example), from 2.3 V at each boost step. Table 1 is an example set of boost values ​​for steps Boost_1 and Boost_2 according to one embodiment. Other boost values ​​for different Vth and other designs are conceivable. Table 1 Pegel Boost_1 Boost_2 L7 0.2 0 L6 0.4 0.2 L5 0.6 0.4 L4 0.8 0.6 L3 1.0 0.8 L2 1.2 1.0 L1 1.4 1.2 L0 1.6 1.4

[0061] Fig. Figure 7A shows a timing diagram and a corresponding set of digital and analog values ​​that illustrate the steps for performing a read operation by the side buffer circuit 338. Fig. 3A-3C according to an exemplary embodiment. The set of values ​​illustrates how the values ​​A_DC and those of the measuring amplifier (SA) behave with respect to the possible logic states (e.g., L0 to L7). An example is provided showing limit voltage read levels (both digital and analog values) with respect to the read level valleys, e.g., boundaries between logic states L0 and L1 (@R2), between logic states L3 and L4 (@R4), and between logic states L5 and L6 (@R6), as in the inserted group of logic states of Fig. Figure 7A shows this. Depending on the logical state of the cell coupled to the side buffer circuit 338, a data value of "1" can be interpreted from an A_DC value of Vcc and a data value of "0" from an A_DC value of ground (GND). These values ​​can be swapped depending on whether SA_R or SA_S of latch 332 is activated (see SA 308 in Figure 7A). Fig. 3B).

[0062] The time diagram in Fig. Figure 7A shows possible logical states of the memory cell (e.g., L0 to L7) and includes tracking of the pre-charge signal (PRE1) and the discharge signal (RST2) with respect to the reset signal (SA_R) and the set signal (SA_S) of latch 332 of SA 308. When these signals are activated, as shown, the bits read from the memory array 302 are converted into an analog voltage value (A_DC), which is stored in the first capacitor C1. The waveforms of the analog voltage values ​​for three read levels (R2, R4, R6) are shown only as examples. The analog voltage values ​​can, in turn, be stored in the first capacitor C1 for a certain period of time until the data bits are transferred to the I / O data line 314.

[0063] Fig. Figure 7B, for example, is a diagram illustrating various analog voltage read levels that are read from the memory array 302 to be copied by the first capacitor (C1) to the measuring amplifier (SA) 308 of the side buffer circuit 338 to be sent on an I / O data line 314, according to one embodiment. In this way, C1 serves to temporarily buffer the digital bits (but as an analog voltage value) during a read operation while waiting to transmit the digital bits, e.g., to the local media controller 135 and / or to the host system 120.

[0064] Fig. Figure 8A is a flowchart of an exemplary method 800A for the operation of a side buffer circuit according to an embodiment. The side buffer circuit can be the side buffer circuit 338 from Fig. 3A, comprising a measuring amplifier (SA) coupled to a memory array and an input / output data line (I / O data line), a digital / analog converter (DAC) coupled to the SA, and an analog storage element coupled to the DAC.

[0065] In Operation 810, the operation of the side buffer circuit includes capturing data bits. For example, Operation 810 can include capturing data bits received over the I / O data line by the SA. The SA can be the SA 308. Fig. 2A-2C, and the bits can be received by the local media controller 135 or the host system 120 via the I / O data line 314.

[0066] In Operation 820, the operation of the side buffer circuit includes a digital-to-analog conversion. For example, Operation 820 can convert data bits into an analog voltage value using the DAC. The DAC can be the DAC 318. Fig. 3A and Fig. It should be 3B.

[0067] In Operation 830, the operation of the side buffer circuit includes storing the analog voltage value. For example, Operation 830 may include storing, by means of the analog memory element, the analog voltage value for a period of time until the data bits are programmed into the memory array. The analog memory element may be the analog memory element(s) 322, and the memory array may be the memory array 302, which, with reference to the Fig. 3A-3C was discussed.

[0068] In further embodiments, the side buffer circuit also includes an analog-to-digital converter (ADC) connected between the analog memory element and the SA. Furthermore, the operation of the side buffer circuit can also include the conversion of the analog voltage value into data bits by the ADC and the programming of the data bits into the memory array by the SA after a specified time interval.

[0069] Fig. Figure 8B is a flowchart of another exemplary method 800B for operating a side buffer circuit according to an embodiment. The side buffer circuit can be the side buffer circuit 338 from Fig. 3A, comprising a measuring amplifier (SA) coupled to a storage array and an input / output data line (I / O data line), a digital / analog converter (DAC) coupled to the SA, and an analog storage element coupled to the DAC.

[0070] In Operation 850, the operation of the side buffer circuit involves retrieving data bits. For example, Operation 850 might involve the SA retrieving data bits from the memory array in response to a read operation. The SA could be SA 308, and the memory array could be memory array 302. Fig. 3A-3C.

[0071] In Operation 860, the operation of the side buffer circuit includes a digital-to-analog conversion. For example, Operation 860 can involve converting the data bits into an analog voltage value using a digital-to-analog converter (DAC). The DAC can be the DAC 318. Fig. 3A and Fig. It should be 3B.

[0072] In Operation 870, the operation of the side buffer circuit includes storing the analog voltage value. For example, Operation 870 may involve storing the analog voltage value in the analog memory element for a period of time until the data bits are transferred to the I / O data line. The analog memory element may be analog memory element(s) 322, and the I / O data line may be I / O data line 314. Fig. 3A-3C.

[0073] In further embodiments, the side buffer circuit also includes an analog-to-digital converter (ADC) coupled between the analog storage element and the SA. Furthermore, the operation of the side buffer circuit can also include the conversion of the analog voltage value into data bits by the ADC and the transfer of the data bits to the I / O data line by the SA after a certain time interval.

[0074] Fig. Figure 9 shows an exemplary machine of a computer system 900 in which a set of instructions can be executed to cause the machine to perform one or more of the methods discussed here. In some embodiments, the computer system 900 can correspond to a host system (e.g., the host system 120 from Fig. 1), which is a memory subsystem (e.g., memory subsystem 110 of Fig. 1) contains, is coupled to, or uses, or can be used to perform the operations of a controller (e.g., to run an operating system, to perform operations that are part of the functionality of the memory subsystem controller 115 from Fig. 1). In alternative embodiments, the machine can be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine can function as a server or client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0075] The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile phone, a web application, a server, a network router, a switch or bridge, or any machine capable of executing a set of instructions (sequentially or otherwise) that specify the actions to be performed by that machine. Even if a single machine is depicted, the term "machine" is intended to encompass any type of machine that, individually or collectively, executes a set (or multiple sets) of instructions to perform one or more of the methods discussed herein.

[0076] The exemplary computer system 900 comprises a processing device 902, a main memory 904 (e.g. read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 910 (e.g. flash memory, static random access memory (SRAM), etc.) and a data storage system 918, which communicate with each other via a bus 930.

[0077] The processing device 902 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. Specifically, the processing device may be a CISC (Complex Instruction Set Computing) microprocessor, a RISC (Reduced Instruction Set Computing) microprocessor, a VLIW (Very Long Instruction Word) microprocessor, or a processor implementing other instruction sets, or processors implementing a combination of instruction sets. The processing device 902 may also be one or more specialized processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like.The processing device 902 is configured to execute instructions 928 for performing the operations and steps discussed herein. The computer system 900 may also include a network interface device 912 for communication over the network 920.

[0078] The data storage system 918 may include a machine-readable storage medium 924 (also known as a computer-readable medium) on which one or more sets of instructions 928 or software embodying one or more of the methods or functions described herein are stored. The instructions 928 may also reside wholly or at least partially in the main memory 904 and / or the processing device 902 while being executed by the computer system 900, the main memory 904 and the processing device 902 also being machine-readable storage media. The machine-readable storage medium 924, the data storage system 918, and / or the main memory 904 may be connected to the storage subsystem 110. Fig. 1 corresponds.

[0079] Although the machine-readable storage medium 924 is shown as a single medium in one embodiment, the term "machine-readable storage medium" is to be understood as encompassing a single medium or multiple media that store one or more sets of instructions. The term "machine-readable storage medium" is also to encompass any medium capable of storing or encoding a set of instructions for execution by the machine, causing the machine to perform one or more of the methods of the present invention. Accordingly, the term "machine-readable storage medium" includes, but is not limited to, solid-state storage media, optical media, and magnetic media.

[0080] Some parts of the preceding detailed descriptions have been presented in the form of algorithms and symbolic representations of operations concerning data bits in a computer memory. These algorithmic descriptions and representations are used by those skilled in the art of data processing to communicate the content of their work most effectively to other skilled workers. An algorithm is understood here, and generally, as a consistent sequence of operations that leads to a desired result. The operations are those that require physical manipulations of physical quantities. Usually, though not necessarily, these quantities are in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated.Sometimes it has proven useful, mainly for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, concepts, numbers or the like.

[0081] It should be borne in mind, however, that all these and similar terms must be associated with the corresponding physical quantities and are merely practical designations for these quantities. The present invention may relate to the actions and processes of a computer system or similar electronic computing device that manipulates data represented as physical (electronic) quantities in the registers and memories of the computer system and converts it into other data represented in a similar manner as physical quantities in the memories or registers of the computer system or other such information storage systems.

[0082] The present invention also relates to a device for performing the operations described herein. This device may be specifically designed for the intended purposes, or it may comprise a general-purpose computer that is selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of floppy disk, including floppy disks, optical disks, CD-ROMs and magnetic-optical disks, read-only memory (ROMs), random-access memory (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each connected to a computer system bus.

[0083] The algorithms and representations presented here are not inherently tied to a specific computer or other device. Various general-purpose systems can be used with programs according to the teachings contained herein, or it may prove advantageous to construct a more specialized device for carrying out the method. The structure for a multitude of such systems is presented in the following description. Furthermore, the present invention is not described with reference to any particular programming language. It is evident that a multitude of programming languages ​​can be used to implement the teachings of the disclosure as described herein.

[0084] The present invention can be provided as a computer program product or in the form of software, which may include a machine-readable medium containing instructions stored thereon that can be used to program a computer system (or other electronic devices) to carry out a method according to the present invention. A machine-readable medium comprises any mechanism for storing information in a form that can be read by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium comprises a machine-readable (e.g., computer-readable) storage medium, such as read-only memory (“ROM”), random-access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory devices, etc.

[0085] In the preceding description, embodiments of the invention have been described with reference to specific embodiments. It is obvious that various modifications can be made to these embodiments without deviating from the basic concept and scope of the embodiments of the invention as set forth in the following claims. Accordingly, the description and the drawings are to be understood in an illustrative rather than a limiting sense.

Claims

[1] Device comprising: a storage array; a measuring amplifier (SA) coupled to the memory array and to an input / output data line (I / O data line), wherein the SA is configured to receive data bits via the I / O data line in conjunction with a program operation; a digital-to-analog converter (DAC) coupled to the SA, wherein the DAC is designed to convert the data bits into an analog voltage value; and an analog storage element coupled to the DAC, wherein the analog storage element is designed to store the analog voltage value for a period of time until the data bits are programmed into the memory array. [2] Device according to claim 1, wherein the data bits comprise a page of data to be stored in the memory array. [3] Device according to claim 1, further comprising an analog-to-digital converter (ADC) connected between the analog storage element and the SA, wherein the ADC is configured to convert the analog voltage value into the data bits after the time interval, and wherein the SA is configured to program the data bits into the storage array. [4] Device according to claim 1, wherein the analog storage element is a capacitor. [5] Device according to claim 4, wherein the device is an integrated circuit device, and wherein the capacitor is arranged within a substrate of the integrated circuit device. [6] Device according to claim 4, wherein the capacitor has a size between 7 and 9 femtofarads. [7] Device according to claim 4, wherein the capacitor is a first capacitor, further comprising: a pre-charge transistor coupled to a voltage supply and the first capacitor, wherein the pre-charge transistor is designed to charge the first capacitor to an initial voltage level; a second capacitor connected in parallel to the first capacitor, which is 4 to 20 times smaller than the first capacitor; and a transistor logic circuit connected between the first capacitor and the second capacitor, wherein the transistor logic selectively enables the second capacitor to consume charge from the first capacitor until the first capacitor stores the analog voltage value. [8] Device according to claim 7, wherein the transistor logic comprises a clock-controlled transistor and an SA-controlled transistor. [9] Device according to claim 7, wherein the transistor logic comprises a discharge transistor coupled to the second capacitor to discharge the second capacitor with the consumed charge from the first capacitor. [10] Device comprising: a storage array; a measuring amplifier (SA) coupled to the memory array and to an input / output data line (I / O data line), wherein the SA is configured to retrieve data bits from the memory array in response to a read operation; a digital-to-analog converter (DAC) coupled to the SA, wherein the DAC is designed to convert the data bits into an analog voltage value; and an analog storage element coupled to the DAC, wherein the analog storage element is designed to store the analog voltage value for a period of time until the data bits are transferred to the I / O data line. [11] Device according to claim 10, wherein the data bits comprise a page of data that is stored in the memory array. [12] Device according to claim 10, further comprising an analog-to-digital converter (ADC) connected between the analog storage element and the SA, wherein the ADC is configured to convert the analog voltage value into the data bits after the time interval, and wherein the SA is configured to transmit the data bits via the I / O data line. [13] Device according to claim 10, wherein the analog storage element is a capacitor. [14] Device according to claim 13, wherein the device is an integrated circuit device, and wherein the capacitor is arranged within a substrate of the integrated circuit device. [15] Device according to claim 13, wherein the capacitor has a size between 7 and 9 femtofarads. [16] Device according to claim 13, wherein the capacitor is a first capacitor, further comprising: a pre-charge transistor coupled to a voltage supply and the first capacitor, wherein the pre-charge transistor is designed to charge the first capacitor to an initial voltage level; a second capacitor connected in parallel to the first capacitor, which is 4 to 20 times smaller than the first capacitor; and a transistor logic circuit connected between the first capacitor and the second capacitor, wherein the transistor logic selectively enables the second capacitor to consume charge from the first capacitor until the first capacitor stores the analog voltage value. [17] Device according to claim 16, wherein the transistor logic comprises a clock-controlled transistor and an SA-controlled transistor. [18] Device according to claim 16, wherein the transistor logic comprises a discharge transistor coupled to the second capacitor to discharge the second capacitor with the consumed charge from the first capacitor. [19] Procedures, including: Operating a side buffer circuit comprising a measuring amplifier (SA) coupled to a memory array and an input / output data line (I / O data line), a digital-to-analog converter (DAC) coupled to the SA, and an analog storage element coupled to the DAC, wherein operating the side buffer circuit comprises: Capture, by the SA, of data bits received via the I / O data line; Converting, by the DAC, the data bits into an analog voltage value; and Store, in the analog storage element, the analog voltage value for a period of time until the data bits are programmed into the memory array. [20] Method according to claim 19, wherein the side buffer circuit further comprises an analog-to-digital converter (ADC) coupled between the analog storage element and the SA, and wherein the operation of the side buffer circuit further comprises: Converting the analog voltage value into data bits using the ADC; and Programming, by means of the SA according to the time span, the data bits into the memory array.

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