DISPLAY PANEL AND MANUFACTURING METHOD FOR IT

Abstract

A manufacturing process for a display panel (50) comprising a light source (LD) and a pixel circuit configured to operate the light source (LD), comprising the manufacturing process of: forming the pixel circuit on a substrate (SUB); and forming the light source (LD) on the pixel circuit, wherein forming the pixel circuit comprises: forming a first electrode layer on the substrate (SUB); forming a buffer layer (BUF) on the first electrode layer; and forming an active layer on the buffer layer (BUF), wherein forming the active layer comprises: depositing a first active layer (ACT1) and depositing a second active layer (ACT2) on the first active layer (ACT1);a first structuring step in which a photoresist (PR) material is applied to the second active layer (ACT2), a photoresist (PR) pattern is formed by a halftone mask, and the second active layer (ACT2) is etched to expose part of the first active layer (ACT1); a halftone ashing step of the photoresist (PR) pattern to expose part of the structured second active layer (ACT2); and a second structuring step in which the exposed part of the first active layer (ACT1) is etched using the structured second active layer (ACT2) as a mask.

Description

BACKGROUND Area The present disclosure relates to a display panel and a manufacturing process thereof. Description of the related technology An organic light-emitting device (hereinafter referred to as the light-emitting device), which forms an organic light-emitting display device, emits light itself and does not require a separate light source. Therefore, the thickness and weight of the display device can be reduced. The organic light-emitting display device also exhibits high-quality properties including low energy consumption, high luminance, high response speed, etc. In general, the lighting device has a structure in which an anode electrode, a bank surrounding the edge areas of the anode electrode, an emission material layer formed on the anode electrode within the bank, and a cathode electrode covering the emission material layer and the bank are stacked. The organic light-emitting display device features two types of light-emitting methods, such as a front-side and a back-side design. In the back-side design, the display faces the anode electrode, which is located towards the cathode electrode. The back-side design has a structure in which a pixel circuit, controlling the light-emitting device, is positioned in front of the anode electrode, i.e., a light-emitting part, and blocks light from the light-emitting part. For this reason, ensuring a specific aperture ratio is particularly important. US 2016 / 0071888A1 describes an organic light-emitting display panel comprising a light-shielding layer electrically connected to a drive current line on a substrate and storage capacitors formed in parallel on an oxide semiconductor, from which oxide semiconductors are insulated and overlap a gate. DE 10 2012 108 165 A1 describes a stray field circuit mode liquid crystal display device comprising a gate line, a data line, a thin-film transistor, an insulating layer with an opening area, a pixel electrode, a passivation layer and a plurality of common electrodes. BRIEF DESCRIPTION OF THE INVENTION The purpose of this disclosure is to provide a display panel with an improved aperture ratio. To this end, according to one aspect of this disclosure, a manufacturing method for a display panel and a display panel according to the independent claims are provided. Further embodiments are described in the dependent claims. The present disclosure includes the following embodiments. One embodiment is a manufacturing method for a display panel including a light source and a pixel circuit that controls the light source. The manufacturing method comprises: forming the pixel circuit on a substrate; and forming the light source on the pixel circuit. The formation of the pixel circuit comprises: forming a first electrode layer on the substrate; forming a buffer layer on the first electrode layer; and forming an active layer on the buffer layer.The formation of the active layer involves: deposition of a first active layer and deposition of a second active layer on top of the first active layer; a first structuring step in which a photoresist material is applied to the second active layer, a photoresist pattern is formed by a halftone mask, and the second active layer is etched; a halftone ashing step of the photoresist pattern to expose part of the structured second active layer; and a second structuring step in which the exposed part of the first active layer is etched using the structured second active layer as a mask. In the second structuring step, the etching can be carried out excessively, so that part of the buffer layer located under the first active layer is etched along with the first active layer. The formation of the active layer can further include a third structuring step, in which an additional etching of the second active layer is performed. The third structuring step can be carried out after the second structuring step. The third structuring step may exhibit wet etching. In other words, the etching of the second active layer in the third structuring step may exhibit wet etching. The first structuring step may involve dry etching. In other words, the etching of the second active layer in the first structuring step may involve dry etching. The second structuring step may exhibit wet etching. In other words, the etching of the first active layer in the second structuring step may exhibit wet etching. The first active layer can be made of indium gallium zinc oxide (IGZO), and the second active layer can be made of molybdenum titanium (MoTi). Another embodiment is a display panel in which a plurality of sub-pixels are arranged in a matrix. Each sub-pixel has a light source, a driver transistor that supplies a drive current to the light source, and a storage capacitor that maintains a voltage for a specific period of time, which controls the magnitude of the drive current. The storage capacitor has a bottom electrode, a buffer layer arranged on the bottom electrode, a middle electrode that covers part of the buffer layer, a gate insulating layer that covers the middle electrode and the buffer layer, and an upper electrode that covers part of the gate insulating layer. In the buffer layer, the thickness of a first region covered by the middle electrode is greater than the thickness of a second region that is in contact with the gate insulating layer. The middle electrode is formed by a double layer. The middle electrode can have: a first active layer formed from indium gallium zinc oxide (IGZO); and a second active layer formed from molybdenum titanium (MoTi). The middle electrode can be connected to a gate electrode of the driver transistor, and the lower electrode and the upper electrode can be connected to an anode electrode of the lighting device. BRIEF DESCRIPTION OF THE FIGURES The accompanying figures, which are included to provide a more comprehensive understanding of the invention and form part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the figures: Fig. 1 is a block diagram showing a configuration of a display device according to an embodiment; Fig. 2 is a circuit diagram showing an embodiment of a pixel shown in Fig. 1; Figs. 3a and 3b show a plan view of the pixel according to the embodiment; Fig. 4 is a cross-sectional view of the pixel according to the embodiment, and in particular a cross-sectional view along line II' from Fig. 3b; Fig. 5 is a flowchart showing a manufacturing process of a display panel according to the embodiment; Fig.Figure 6 shows a cross-section of a storage capacitor Cst from Figure 4 according to the embodiment; Figure 7 shows the storage capacitor Cst by means of a circuit symbol; Figures 8, 9, 10, 11 to 12 are views to describe a detailed process for the steps of forming an active layer; and Figure 13 shows a further embodiment from Figure 6 and shows a cross-section of the storage capacitor Cst formed by a manufacturing process from Figures 7, 8, 9, 10, 11 to 12. DETAILED DESCRIPTION The features, advantages, and methods for implementing the present invention will be more readily apparent with reference to the following detailed embodiments and the accompanying figures. However, the present invention is not limited to the embodiment disclosed below and is implemented in various and variable ways. The embodiments achieve the complete disclosure of the present invention and are provided only to enable those skilled in the art to fully understand the scope of the present invention. Since the shapes, sizes, proportions, angles, numbers, etc., illustrated in the figures to describe embodiments of the present invention, the present invention is not limited to the details shown. The same reference numerals correspond to the same elements throughout the entire disclosure. Furthermore, detailed descriptions of known technologies used herein are consistently omitted from the description of the present invention if they could render the subject matter of the present invention unclear. When terms such as "exhibits," "has," "formed," etc., are used in the present disclosure, other parts may be added unless the term "only" is used. A component represented in the singular form includes the expression of its plural form unless expressly stated otherwise. When designing components, error areas are considered to be included unless explicitly stated otherwise. When describing positional relationships, if the positional relationship of two parts is described as "on", "above", "below", "next to", etc., one or more other parts may be arranged between the two parts, as long as no term such as "direct" or "immediately" is used. Although terms such as the first and the second, etc., can be used to describe different components, the components are not limited by the terms mentioned above. The terms are only used to distinguish between one component and other components. Therefore, the first component described below could be the second component according to the spirit of the present invention. The same reference numbers correspond to the same elements throughout the disclosure.In an embodiment of the present invention, a pixel circuit formed on a display panel substrate can be configured as a thin-film transistor (TFT) having an n-type or p-type metal-oxide-semiconductor field-effect transistor (MOSFET) structure. The TFT is a three-electrode device comprising a gate, a source, and a drain. The source is an electrode that provides a charge carrier to the transistor. Within the TFT, charge carriers begin to flow from the source. The drain is an electrode through which charge carriers leave the TFT. That is, in the MOSFET, the charge carriers flow from the source to the drain. In the case of an n-type TFT (NMOS), since the charge carrier is an electron, the source voltage is lower than the drain voltage, allowing electrons to flow from the source to the drain.In an n-type TFT, since electrons flow from the source to the drain, the current flows from the drain to the source. In the case of a p-type TFT (PMOS), since the charge carrier is a hole, the source voltage is higher than the drain voltage, allowing holes to flow from the source to the drain. In a p-type TFT, since the holes flow from the source to the drain, the current flows from the source to the drain. It should be noted that the source and drain of a MOSFET are not fixed. For example, the source and drain of a MOSFET can be changed depending on an applied voltage. In the following, a gate-on voltage is the voltage of a gate signal at which the TFT can be switched on. A gate-off voltage is the voltage at which the TFT can be switched off. In PMOS, the gate-on voltage is a low gate voltage (VGL), and the gate-off voltage is a high gate voltage (VGH). In NMOS, the gate-on voltage is VGH, and the gate-off voltage is VGL. Various embodiments of the present invention are described in detail below with reference to the accompanying figures. The names of components used in the following description have been chosen to facilitate the writing of the specification and may differ from the names of components in an actual product. Fig. 1 is a block diagram showing a configuration of a display device according to an exemplary embodiment. Referring to Fig. 1, the display device 1 comprises a time control 10, a gate driver 20, a data driver 30, a power supply 40 and a display panel 50. The timing controller 10 can receive an RGB image signal and a CS control signal from an external source. The RGB image signal can contain multiple gradation data. The CS control signal can, for example, contain a horizontal synchronization signal, a vertical synchronization signal, and a master time signal. The timer 10 can appropriately process the RGB image signal and the CS control signal for the operating conditions of the display panel 50, in order to generate and output image data DATA, a gate driving control signal CONT1, a data driving control signal CONT2 and a power supply control signal CONT3. The gate driver 20 can be connected to pixels (or sub-pixels, PX) of the display panel 50 via a plurality of first gate lines GL11 to GL1n. The gate driver 20 can generate the gate signals based on the gate-driving control signal CONT1, which is output by the timer 10. The gate driver 20 can provide the generated gate signals to the pixels PX via the plurality of first gate lines GL11 to GL1n. In various embodiments, the gate driver 20 can further be connected to the pixel PX of the display panel 50 via a plurality of second gate lines GL21 to GL2n. The gate driver 20 can provide a measurement signal to the pixel PX via the plurality of second gate lines GL21 to GL2n. The measurement signal can be provided to measure characteristics of a driving transistor and / or a light source located within the pixel PX. The data driver 30 can be connected to the pixels PX of the display panel 50 via a plurality of data lines DL1 to Dlm. The data driver 30 can generate data signals based on the data-driving control signal CONT2 and the image data DATA output by the timer 10. The data driver 30 can provide the generated data signals to the pixels PX via the plurality of data lines DL1 to Dlm. In various embodiments, the data driver 30 can further be connected to the pixel PX of the display panel 50 by a plurality of measuring lines (or reference lines) SL1 to SLm. The data driver 30 can provide a reference voltage (or a measuring voltage, an initialization voltage) to the pixel PX by the plurality of measuring lines SL1 to SLm, or it can measure the states of the pixels PX based on an electrical signal fed back from the pixels PX. The power supply 40 can be connected to the pixels PX of the display panel 50 via multiple supply lines PL1 and PL2. The power supply 40 can generate a driver voltage for delivery to the display panel 50 based on the power supply control signal CONT3. This driver voltage can, for example, have a high-potential driver voltage ELVDD and a low-potential driver voltage ELVSS. The power supply 40 can deliver the generated driver voltages ELVDD and ELVSS to the pixels PX via the corresponding supply lines PL1 and PL2. A plurality of pixels PX (or sub-pixels) are arranged in the display panel 50. The pixels PX can be arranged, for example, in the form of a matrix on the display panel 50. Each pixel PX can be electrically connected to its assigned gate line and data line. Such pixel PX can emit light with a luminance corresponding to the gate signal and data signal provided by the first gate lines GL11 to GL1n and the data lines DL1 to DLM. Each pixel PX can represent one of the first three colors. In the example embodiment, each pixel PX can represent red, green, and blue. In another embodiment, each pixel PX can represent cyan, magenta, and yellow. In various embodiments, the pixels PX can represent one of four or more colors. For example, each pixel PX can represent red, green, blue, and white. The timer 10, the gate driver 20, the data driver 30, and the power supply 40 can each be implemented as a separate integrated circuit (IC), or they can be implemented as a single IC in which at least some of them are integrated. For example, at least one of the data driver 30 and the power supply 40 can be implemented as an IC integrated with the timer 10. Furthermore, although the gate driver 20 and the data driver 30 are shown in Fig. 1 as components separate from the display panel 50, at least one of the gate driver 20 and the data driver 30 can be formed in an in-panel method in which it is integrally formed with the display panel 50. For example, the gate driver 20 can be integrally formed with the display panel 50 in a gate-in-panel (GIP) method. Fig. 2 is a circuit diagram showing an embodiment of a pixel depicted in Fig. 1. Fig. 2 shows a pixel PXij, which is connected by way of example to an i-th first gate line GL1i and a j-th data line DLj. Referring to Fig. 2, the Pixel PX has a switching transistor ST, a driver transistor DT, a measuring transistor SST, a storage capacitor Cst, and a lighting device LD. A first electrode (e.g., a source electrode) of the switching transistor ST is electrically connected to a j-th data line DLj, and a second electrode (e.g., a drain electrode) of the switching transistor ST is electrically connected to a first node N1. A gate electrode of the switching transistor ST is electrically connected to the i-th first gate line GL1i. When a gate-on signal of a gate-on level is applied to the i-th first gate line GL1i, the switching transistor ST is turned on and transmits the data signal applied to the j-th data line DLj to the first node N1. A first electrode of the storage capacitor Cst is electrically connected to the first node N1, and a second electrode of the storage capacitor Cst is electrically connected to a second node N2. The storage capacitor Cst can charge a voltage corresponding to the difference between a voltage applied to the first node N1 and a voltage applied to the second node N2. A first electrode (e.g., a drain electrode) of the driver transistor DT is configured to receive the high-potential driver voltage ELVDD, and a second electrode (e.g., a source electrode) of the driver transistor DT is electrically connected to a first electrode (e.g., an anode electrode) of the lighting device LD. The gate electrode of the driver transistor DT is electrically connected to the first node N1. When a gate-level voltage is applied through the first node N1, the driver transistor DT can be switched on and can control the amount of driver current flowing through the lighting device LD according to a voltage supplied to the gate electrode, that is, a voltage stored in the storage capacitor Cst. A first electrode (e.g., a drain electrode) of the measuring transistor SST is electrically connected to a j-th measuring line SLj, and a second electrode (e.g., the source electrode) of the measuring transistor SST is electrically connected to the first electrode (e.g., an anode electrode) of the lighting device LD. A gate electrode of the measuring transistor SST is electrically connected to an i-th second gate line GL2i. When a gate-on level measurement signal is applied to the i-th second gate line GL2i, the measuring transistor SST is switched on and transmits the reference voltage applied to the j-th measuring line SLj to the anode electrode of the lighting device LD. The light source LD emits light according to the driver current. The light source LD can emit light in any red, green, or blue color. The light source LD can be an organic light-emitting diode (OLED) or a micro-inorganic light-emitting diode with a size ranging from microscale to nanoscale. However, the present invention is not limited to this. Exemplary embodiments in which the light source LD is formed by the organic light-emitting diode are described below. In the present invention, the structure of the pixel PX is not limited to what is shown in Fig. 2. According to the exemplary embodiment, the pixel PX can further comprise at least one element for compensating a threshold voltage of the driver transistor DT or for initializing the voltage of the gate electrode of the driver transistor DT and / or the voltage of the anode electrode of the lighting device LD. Fig. 2 shows an example in which the switching transistor ST, the driver transistor DT, and the measuring transistor SST are NMOS transistors. However, the present invention is not limited to this. For example, at least some or all of the transistors that form each pixel PX can be formed from a PMOS transistor. In the NMOS transistor and the PMOS transistor in the circuit symbol, the source electrode and the drain electrode are arranged opposite each other. In various embodiments, the switching transistor ST, the driver transistor DT and the measuring transistor SST are each designed as a low-temperature polysilicon (LTPS) thin-film transistor, an oxide thin-film transistor or a low-temperature polycrystalline oxide (LTPO) thin-film transistor. Fig. 3a and Fig. 3b show a plan view of the pixel according to the embodiment. Referring to Figures 2, 3a, and 3b together, the display panel has 50 pixel areas PXA defined in an intersection of the data lines DL, which extend in a first direction (e.g., a pixel column direction DR1), and the first and second gate lines GL1 and GL2, which extend in a second direction (e.g., a pixel row direction DR2). The pixels PX are arranged within the pixel areas PXA. Each pixel area PXA can have a light-emitting area EA, in which the light-emitting device LD of pixel PX is located, and a non-emission area NEA, in which circuit elements (e.g., a switching transistor ST, the driver transistor DT, the measuring transistor SST, and the storage capacitor Cst) are located to drive the light-emitting device LD. The light-emitting device LD can be operated by means of the circuit elements located in the non-emission area NEA and can emit light of a specific color. The pixel area PXA can have an aperture area that allows light from the light-emitting device LD to pass through it and display an image. The aperture area can be configured to correspond to pixel PX, which represents one of the colors red, green, blue, and white. Wiring areas WA can be defined between pixel columns. The data line DL and the measuring line SL, which extend in the first direction DR1, are located in each wiring area WA. The data line DL can receive a data signal from the data driver 30. The measuring line SL can receive a reference voltage from the data driver 30 or can transmit an electrical signal output by the corresponding pixel PX to the data driver 30. In the exemplary embodiment, a first supply line PL1 for applying the high-potential driver voltage ELVDD to the pixels PX can furthermore be formed in a part of the wiring areas WA. The first supply line PL1 can generally extend in the first direction DR1 parallel to the data line DL and the measuring line SL. The first gate line GL1 and the second gate line GL2 extend across the non-emission zone NEA in the second direction DR2. In this case, the first gate line GL1 and the second gate line GL2 can be arranged at regular intervals along the first direction DR1. The data line DL, the measurement line SL, the first supply line PL1, the first gate line GL1, and the second gate line GL2 are electrically connected to the circuit elements via contact holes. Specifically, the data line DL can be electrically connected to an electrode (e.g., a drain electrode) of the switching transistor ST, and the measurement line SL can be electrically connected to an electrode (e.g., a drain electrode) of the measurement transistor SST. The first gate line GL1 is electrically connected to the gate electrodes of the switching transistor ST, and the second gate line GL2 is electrically connected to the gate electrode of the measurement transistor SST. As described with reference to Fig. 2, the pixel PX can include the switching transistor ST, the driver transistor DT, the measuring transistor SST, the storage capacitor Cst, and the lighting device LD. The switching transistor ST can have a first gate electrode GE1, a first source electrode SE1 and a first drain electrode DE1. The first gate electrode GE1 can be arranged to overlap a first channel CH1 formed in an active layer. The first channel CH1 can be a semiconductor pattern in which foreign atoms are not doped into the active layer. The first gate electrode GE1 can be electrically connected to the first gate line GL1. For example, the first gate electrode GE1 can be a region that overlaps the first channel CH1 on the first gate line GL1. The first source electrode SE1 can be connected to a first source area SA1, which is formed on one side of the first channel CH1 of the active layer. The first source electrode SE1 can further be connected to the data line DL through a first contact hole CT1. The first drain electrode DE1 can be connected to a first drain region DA1, which is formed on the other side of the first channel CH1 of the active layer. The first drain electrode DE1 can be electrically connected to a lower electrode BE of the storage capacitor Cst through a second contact hole CT2. The driver transistor DT can have a second gate electrode GE2, a second source electrode SE2 and a second drain electrode DE2. The second gate electrode GE2 can be arranged to overlap a second channel CH2 formed in the active layer. The second gate electrode GE2 can be electrically connected to the lower electrode BE of the storage capacitor Cst via a third contact hole CT3. The second source electrode SE2 can be connected to a second source area SA2 formed on one side of the second channel CH2 of the active layer. The second source electrode SE2 can be electrically connected via a fourth contact hole CT4 to the first supply line PL1, to which the high-potential driver voltage ELVDD is applied. In the exemplary embodiment, the second source electrode SE2 can be formed by a conductive pattern provided substantially in the wiring area WA. The second source electrode SE2 can be electrically connected to an upper electrode UE of the storage capacitor Cst. For example, the second source electrode SE2 can be integrally formed with the upper electrode UE of the storage capacitor Cst to form a pattern.As will be described later, since the upper electrode UE of the storage capacitor Cst is connected to the anode electrode AE ​​of the lighting device LD through a first via hole VIA1, the second source electrode SE2 of the driver transistor DT is electrically connected to the anode electrode AE ​​of the lighting device LD through the upper electrode UE of the storage capacitor Cst. The second drain electrode DE2 can be connected to a second drain area DA2, which is formed on the other side of the second channel CH2 of the active layer. Furthermore, the second drain electrode DE2 can be connected to a light-shielding layer LS via a fifth contact hole CT5. This allows, when defects in pixel PX are repaired using a repair pattern RP, the repair pattern RP and the light-shielding layer LS to be joined by laser welding, so that the anode electrode AE ​​of an adjacent pixel PX (i+1)j and the second drain electrode DE2 of the driver transistor DT can be electrically connected. The measuring transistor SST can have a third gate electrode GE3, a third source electrode SE3, and a third drain electrode DE3. The third gate electrode GE3 can be arranged to overlap a third channel CH3 formed in the active layer. The third gate electrode GE3 can be electrically connected to the second gate line GL2. For example, the third gate electrode GE3 can be a region that overlaps the third channel CH3 on the second gate line GL2. The third source electrode SE3 can be connected to a third source area SA3, which is formed on the other side of the third channel CH3 of the active layer. The third source electrode SE3 can be electrically connected to a bridge pattern BRP through a sixth contact hole CT6. The bridge pattern BRP is electrically connected to the measuring lead SL through an eighth contact hole CT8. Accordingly, the third source electrode SE3 can be electrically connected to the measuring lead SL through the bridge pattern BRP. The third drain electrode DE3 can be connected to a third drain region DA3, which is formed on the other side of the third channel CH3 of the active layer. Furthermore, the third drain electrode DE3 can be connected to the light-shielding layer LS through a seventh contact hole CT7. In the exemplary embodiment, since the light-shielding layer LS is connected to the second drain electrode DE2 of the driver transistor DT through the fifth contact hole CT5, the third drain electrode DE3 can be electrically connected to the second drain electrode DE2 of the driver transistor DT through the light-shielding layer LS. The storage capacitor Cst can have the lower electrode BE and the upper electrode UE. The lower electrode BE can be electrically connected to the first drain electrode DE1 of the switching transistor ST via the second contact hole CT2. Furthermore, the lower electrode BE can be electrically connected to the second gate electrode GE2 of the driver transistor DT via the third contact hole CT3. In the exemplary embodiment, the lower electrode BE can have an extension section EXT for the lower electrode BE in order to be connected to the second gate electrode GE2 of the driver transistor DT. In a region of the extension section EXT, the lower electrode BE overlaps the second gate electrode GE2 and is electrically connected to the second gate electrode GE2 through the third contact hole CT3. The upper electrode UE is configured such that at least a region of the upper electrode UE covers the lower electrode BE. Since charges corresponding to a potential difference between the upper electrode UE and the lower electrode BE are stored in the two electrodes, the upper electrode UE and the lower electrode BE can function as the storage capacitor Cst. The capacitance of the storage capacitor Cst can be determined as a function of the area where the upper electrode UE and the lower electrode BE overlap. Accordingly, the upper electrode UE and the lower electrode BE can each have a region (size) that fulfills the required capacitance of the storage capacitor Cst. The upper electrode UE can be electrically connected to the second drain electrode DE2 of the driver transistor DT via the fifth contact hole CT5. Furthermore, the upper electrode UE can be electrically connected to the anode electrode AE ​​of the lighting device LD via the first via hole VIA1. The aforementioned storage capacitor Cst is connected to the second gate electrode GE2 of the driver transistor DT via its lower electrode BE. A cathode electrode CE of the lighting device LD, as described below, can be located on the driver transistor DT. In this case, an electric field can be formed between the cathode electrode CE and the second gate electrode GE2 of the driver transistor DT. This can reduce the charging rate of the storage capacitor Cst, which is electrically connected to the second gate electrode GE2. In other words, a parasitic capacitor can be formed, which has the second gate electrode GE2 as one of its electrodes and the cathode electrode CE as its other electrode.As described in the exemplary embodiment, if the second gate electrode GE2 is electrically connected to the lower electrode BE instead of the upper electrode UE of the storage capacitor Cst, the electrical path from the parasitic capacitor to the storage capacitor Cst can become relatively longer, thus reducing the effect of the parasitic capacitor. Furthermore, since the lower electrode BE of the storage capacitor Cst is formed on the substrate of the display panel 50, an electric field between the second gate electrode GE2 and the cathode electrode CE is prevented from forming, thereby eliminating the parasitic capacitor. The luminaire LD can comprise the anode electrode AE, the cathode electrode CE, and an emissive material layer EML arranged between the anode electrode AE ​​and the cathode electrode CE. In the exemplary embodiment, the anode electrode AE, the emissive material layer EML, and the cathode electrode CE can be arranged in direct contact within the light emission region EA. The anode electrode AE ​​can be connected to the upper electrode UE of the storage capacitor Cst through the first via hole VIA1. A bank layer BNK, the emission material layer EML, and the cathode electrode CE can be arranged on the anode electrode AE ​​in the non-emission region NEA described below. The anode electrode AE ​​is generally formed in the light emission region EA. However, at least a portion of the anode electrode AE ​​can extend to the non-emission region NEA so that the anode electrode AE ​​contacts the upper electrode UE of the storage capacitor Cst. The emission material layer (EML) and the cathode electrode (CE) are broadly formed in the light emission region (EA) and the non-emission region (NEA). Here, the emission material layer (EML) covers the anode electrode (AE). In the exemplary embodiment, the pixel PX can further comprise the repair pattern RP. A region of the repair pattern RP is arranged such that it does not overlap the anode electrode AE ​​of an adjacent pixel PX(i+1)j and does not overlap the light-shielding layer LS. In this case, the repair pattern RP is electrically connected to the anode electrode AE ​​of the neighboring pixel PX(i+1)j via a second via hole VIA2 in a different region than the first. To be electrically connected to the anode electrode AE ​​of the neighboring pixel PX(i+1)j, the repair pattern RP can be located near the anode electrode AE ​​of the neighboring pixel PX(i+1)j in the non-emission region NEA. Since the repair pattern RP is located near the anode electrode AE ​​of the adjacent pixel PX(i+1)j in the non-emission region NEA, the light-shielding layer LS, which is arranged to overlap the repair pattern RP in one region, can have a wide area extending from a part overlapping the driver transistor DT to that one region. The repair pattern RP can be an island-shaped electrode with a bar shape, generally extending in the second direction DR2. However, the shape of the repair pattern RP is not limited to this and can be modified in many ways according to the relative arrangement of other components, including the light shielding layer LS and the anode electrode AE. Figures 3a and 3b show, as an example, that the display device 1 has a WRGB structure including a white pixel W. However, the above embodiments are not only applied to the display device 1 which has the WRGB structure. That is, various features that do not relate to the white pixel W in the above embodiment can be applied to display devices which have an RGB structure or an RGBG structure that do not have the white pixel W. Furthermore, various features that relate to the white pixel W in the above embodiment can be applied not only to the display device 1 which has a WRGB structure, but also to display devices which have various structures including the white pixel W. The following describes in more detail a stacked structure (cross-sectional structure) of the pixel PX according to the exemplary embodiment with reference to the drawings. Fig. 4 is a cross-sectional view of the pixel according to the embodiment, and in particular it is a cross-sectional view along line II' from Fig. 3b . Referring to Fig. 4 together with Fig. 3a and Fig. 3b, the display panel 50 can comprise a substrate SUB, a pixel circuit layer and a light device layer. The substrate SUB is a base material of the 50-inch display panel and can be a translucent substrate. The substrate SUB can be rigid, including glass or tempered glass, or flexible, made of plastic. For example, the substrate SUB can be made of a plastic material such as polyimide, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or polycarbonate (PC), etc. However, the substrate SUB material is not limited to these. The pixel area PXA is defined on the substrate SUB. The pixel area PXA can be defined as an area comprising at least one circuit element located on the pixel circuit layer and the light-emitting device LD located on the light-emitting device layer. The at least one circuit element and the light-emitting element LD can form a pixel PX. The pixel circuit layer is formed on the substrate SUB and can include circuit elements that form the pixel PX (e.g. the switching transistor ST, the driver transistor DT, the measuring transistor SST and the storage capacitor Cst, etc.) and wiring. First, a first electrode layer can be arranged on the substrate SUB. The first electrode layer can include the light shielding layer LS and the lower electrode BE of the storage capacitor Cst. The light-shielding layer LS can be arranged to overlap a semiconductor pattern of the driver transistor DT, in particular the second channel CH2, on one plane, and can protect the oxide semiconductor device from external light. In the exemplary embodiment, the light-shielding layer LS can further be connected to the second drain electrode DE2 of the driver transistor DT through the fifth contact hole CT5. Thus, when defects in pixel PX are repaired using a repair pattern RP, the repair pattern RP and the light-shielding layer LS are connected by laser welding, so that the anode electrode AE ​​of an adjacent pixel PX (i+1)j and the second drain electrode DE2 of the driver transistor DT can be electrically connected. The lower electrode BE can be electrically connected to the first drain electrode DE1 of the switching transistor ST via the second contact hole CT2. Furthermore, the lower electrode BE can be electrically connected to the second gate electrode GE2 of the driver transistor DT via the third contact hole CT3. In the exemplary embodiment, the lower electrode BE can have the extension section EXT for connecting the lower electrode BE to the second gate electrode GE2 of the driver transistor DT. In one region of the extension section EXT, the lower electrode BE overlaps the second gate electrode GE2 and is electrically connected to it via the third contact hole CT3. Another region of the extension section EXT is arranged so as not to overlap other electrodes of the circuit elements and the anode electrode AE ​​of the light-emitting element LD. This makes it possible to prevent an electrical short circuit between other electrodes and / or between the anode electrode AE ​​and the cathode electrode CE of the light-emitting device LD when the second gate electrode GE2 and the anode electrode AE ​​are electrically isolated by cutting the extension section EXT with a laser and defects in the pixel PX are repaired. In the wiring area WA, the first electrode layer can further include the data line DL, the measuring line SL, and the first supply line PL1. The data line DLj is connected to the first source electrode SE1 of the switching transistor ST via the first contact hole CT1. The measuring line SL is connected to the third source electrode SE3 of the measuring transistor SST via the bridge pattern BRP. The first supply line PL1 is connected to the second source electrode SE2 of the driver transistor DT via the fourth contact hole CT4. In various embodiments, additional wiring and / or electrodes, not shown, such as a second supply line PL2 which applies the low-potential driver voltage ELVSS, and an additional electrode on the substrate SUB, may also be provided. A buffer layer BUF is arranged on the substrate SUB and covers the light shielding layer LS, the lower electrode BE of the storage capacitor Cst, and the wiring. The buffer layer BUF prevents ions or foreign atoms from diffusing out of the substrate SUB and prevents moisture from penetrating. Furthermore, the buffer layer BUF improves the surface flatness of the substrate SUB. The buffer layer BUF can consist of inorganic material, such as oxides, nitrides, etc., organic material, or an organic / inorganic composite, and can be formed as a single layer or as multiple layers. For example, the buffer layer BUF can have a structure of three or more layers formed from silicon dioxide, silicon nitride, and silicon oxide. In another embodiment, the buffer layer BUF can be omitted. The active layer (not shown) can be formed on the buffer layer BUF. The active layer can be made of a silicon-based semiconductor material or an oxide-based semiconductor material. Amorphous silicon or polycrystalline silicon can be used as the silicon-based semiconductor material.The oxide-based semiconductor material can be a quaternary metal oxide such as indium tin gallium zinc oxide (InSnGaZnO), a ternary metal oxide such as indium gallium zinc oxide (InGaZnO), indium tin zinc oxide (InSnZnO), indium aluminum zinc oxide (InAlZnO), tin gallium zinc oxide (SnGaZnO), aluminum gallium zinc oxide (AlGaZnO), tin aluminum zinc oxide (SnAlZnO), a binary metal oxide such as indium zinc oxide (InZnO), tin zinc oxide (SnZnO), aluminum zinc oxide (AlZnO), zinc magnesium oxide (ZnMgO), tin magnesium oxide (SnMgO), indium magnesium oxide (InMgO), indium gallium oxide (InGaO), They contain indium oxide (InO), tin oxide (SnO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), and similar materials. The active layer may consist of a bilayer including molybdenum-titanium (MoTi). The active layer has the first to third drain region DA1 to DA3, the first to third source region SA1 to SA3, which contain foreign atoms of the p-type or n-type, and the first to third channel CH1 to CH3, which are each formed between the first to third source region SA1 to SA3 and the first to third drain region DA1 to DA3. A second electrode layer is arranged on top of the active layer. A gate insulating layer (GI) can be inserted between the active layer and the second source electrode layer. The gate insulating layer (GI) can be made of silicon dioxide (SiOx), silicon nitride (SiNx), or multiple layers thereof. The second electrode layer can include gate electrodes GE1, GE2, and GE3, source electrodes SE1, SE2, and SE3, and drain electrodes DE1, DE2, and DE3. Gate electrodes GE1, GE2, and GE3 can be arranged to overlap the corresponding channels CH1, CH2, and CH3 of the active layer. At least some (GE1, GE3) of the gate electrodes GE1, GE2, and GE3 can be integrally formed with wires GL1 and GL2, which are electrically connected to the corresponding gate electrodes GE1 and GE3, forming a pattern. The second electrode layer can further comprise the upper electrode UE of the storage capacitor Cst. The upper electrode UE is configured such that at least a portion of it covers the lower electrode BE. Since charges corresponding to a potential difference between the upper electrode UE and the lower electrode BE are stored in the two electrodes, the upper electrode UE and the lower electrode BE can function as the storage capacitor Cst. In various embodiments, the storage capacitor Cst can also comprise a middle electrode (not shown). If the storage capacitor Cst is configured to have a middle electrode, it is possible to further increase the capacitor capacitance in a limited area. The upper electrode UE and the middle electrode form a first capacitor, and the lower electrode BE and the middle electrode form a second capacitor.The first and second capacitors are connected in parallel. Therefore, the storage capacitor Cst has a value obtained by summing the capacitance of the first capacitor and the capacitance of the second capacitor, and consequently, the capacitance of the storage capacitor Cst can be increased. Details on this will be described later. The upper electrode UE can be electrically connected to the second source electrode SE2 of the driver transistor DT through the fifth contact hole CT5. Furthermore, the upper electrode UE can be electrically connected to the anode electrode AE ​​of the lighting device LD via the first via hole VIA1. The storage capacitor Cst described above is connected to the second gate electrode GE2 of the driver transistor DT via its lower electrode BE. The cathode electrode CE of the lighting device LD can be located on the driver transistor DT. In this case, an electric field can be formed between the cathode electrode CE and the second gate electrode GE2 of the driver transistor DT. This can reduce the charging rate of the storage capacitor Cst, which is electrically connected to the second gate electrode GE2. In other words, a parasitic capacitor can be formed, which has the second gate electrode GE2 as one of its electrodes and the cathode electrode CE as the other.As described in the exemplary embodiment, if the second gate electrode GE2 is electrically connected to the lower electrode BE instead of the upper electrode UE of the storage capacitor Cst, the electrical path from the parasitic capacitor to the storage capacitor Cst becomes relatively longer, thus reducing the effect of the parasitic capacitor. Furthermore, since the lower electrode BE of the storage capacitor Cst is formed on the substrate of the display panel 50, an electric field between the second gate electrode GE2 and the cathode electrode CE is prevented from forming, thereby eliminating the parasitic capacitor. The second electrode layer can also feature the BRP bridge pattern. The BRP bridge pattern can electrically connect the third source electrode SE3 of the measuring transistor SST and the measuring line SL. The second electrode layer can also feature the RP repair pattern. The first and second electrode layers can be formed from any one element selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. Furthermore, the first and second electrode layers can be formed as multiple layers, each composed of any one element selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. For example, the first and second electrode layers can be a double layer of molybdenum / aluminum-neodymium or molybdenum / aluminum. The pixel circuit layer can be covered by a passivation layer (PAS). The PAS can cover the second electrode layer and any exposed areas of the buffer layer (BUF) and the active layer that are not covered by the second electrode layer. The PAS is an insulating layer for protecting the underlying devices and can be made of silicon oxide (SiOx), silicon nitride (SiNx), or multiple layers thereof. In various embodiments, the PAS can be omitted. An OC coating layer can be formed on the PAS passivation layer. The OC coating layer can be a planarizing layer to reduce step differences in the underlying structure and can be made of organic material, such as polyimide, a resin from the benzocyclobutene group, acrylate, etc. In the exemplary embodiment, a color filter (not shown) can be formed between the passivation layer PAS and the coating layer OC. The color filter can be located in the light emission region EA. The color filter is a wavelength-selective optical filter that transmits light in one specific wavelength band and blocks light in another specific wavelength band, thus selectively transmitting incident light only in a partial wavelength band. The color filter can be formed from a photosensitive resin containing a colorant such as a pigment, dye, etc. Light passing through the color filter in the light emission region EA can be any color of red, green, or blue. If pixel PX represents white, the color filter for the corresponding pixel PX can be omitted. Although it was described above that the color filter is formed between the passivation layer PAS and the coating layer OC, the present embodiment is not limited to this. That is, if the illuminating device LD is a top-emission type, the color filter can be formed on a top layer of the illuminating device layer as described below. The luminescent layer is formed on the coating layer OC and comprises the luminescent devices LD. The luminescent device LD comprises the anode electrode AE, the emissive material layer EML, and the cathode electrode CE. At least one of the anode electrode AE ​​and the cathode electrode CE can be a transmissive electrode, and at least the other can be a reflective electrode. For example, if the illuminating device LD is a back-emission type, the anode electrode AE ​​can be a transmissive electrode, and the cathode electrode CE can be a reflective electrode. Conversely, if the illuminating device LD is a top-emission type, the anode electrode AE ​​can be a reflective electrode, and the cathode electrode CE can be a transmissive electrode. In another embodiment, if the illuminating device LD is a double-sided emission type, both the anode electrode AE ​​and the cathode electrode CE can be transmissive electrodes. A detailed configuration of the illuminating device LD is described below using an example where the illuminating device LD is a back-emission type. The anode electrode AE ​​is formed on the coating layer OC. The anode electrode AE ​​is electrically connected to the upper electrode UE of the storage capacitor Cst via the first via hole VIA1, which passes through the coating layer OC and the passivation layer PAS. The anode electrode AE ​​can also be electrically connected to the second drain electrode DE2 of the driver transistor DT via the storage capacitor Cst. As described above, when the first via hole VIA1 is formed, the upper electrode UE of the storage capacitor Cst, which has a relatively larger area than the electrodes, can be contacted, but the effect may be reduced due to the step difference around the first via hole VIA1. The anode electrode AE ​​can be made of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), or zinc oxide (ZnO). If the anode electrode AE ​​is a reflective electrode, it can have a reflective layer. The reflective layer can be made of aluminum (Al), copper (Cu), silver (Ag), nickel (Ni), or an alloy thereof. In the exemplary embodiment, the reflective layer can be made of a silver / palladium / copper alloy (APC). The bank layer BNK is formed on the anode electrode AE ​​in the non-emission region NEA. However, the emission material layer EML is formed on the anode electrode AE ​​in direct contact with the anode electrode AE ​​in the light emission region EA. This means that the bank layer BNK has a half-bank structure, covering the non-emission region NEA but not the light emission region EA. For example, according to a structure in which the bank layer BNK is arranged over the entire area of ​​the substrate SUB, which has the light emission area EA and the non-emission area NEA, manufacturing costs are increased and the overall aperture ratio of the display panel 50 is reduced. Conversely, according to a completely bankless structure, color mixing can occur in which light of different colors emitted by one pixel PX or another adjacent pixel PX is mixed together and emitted in the light emission area EA. Accordingly, the present invention is characterized in that the bank layer BNK has a half-bank structure that covers the non-emission area NEA but does not cover the light emission area EA. In particular, the bank layer BNK is not arranged in the pixel-column direction of the light emission area EA, in which a plurality of pixels PX are arranged row by row, and the bank layer BNK is arranged in a lower section of the light emission area EA in a column direction of the non-emission area NEA, in which the pixel circuit layer is arranged. Repeatedly, the bank layer BNK is not arranged in the pixel-column direction of the light emission area EA below the non-emission area NEA, and the bank layer BNK is arranged at the lower section of the light emission area EA in a column direction of the non-emission area NEA, in which the pixel circuit layer is arranged. Therefore, the bank layer BNK can be implemented in the form of a strip on the display device 1. The emissive material layer (EML) is broadly shaped in the light-emitting region (EA) and the non-emissive region (NEA). In the light-emitting region (EA), the EML is formed to cover the anode electrode (AE). In this embodiment, the EML can have a multilayer thin-film structure, including a light-generating layer. The color of the light generated in the light-generating layer can be white, red, blue, green, etc., but is not limited to these colors. The light-emitting layer (EML) can, for example, include a hole transport layer (HTL), an organic emission layer (OEL), and an electron transport layer (ETL). The hole transport layer facilitates the transfer of holes injected from the anode electrode (AE) into the OEL. The OEL can be composed of an organic material, including a phosphorescent or fluorescent material. The electron transport layer facilitates the transfer of electrons injected from the cathode electrode (CE) to the OEL. In addition to the hole transport layer, OEL, and electron transport layer, the OEL can also include a hole injection layer (HIL), a hole blocking layer (HBL), an electron injection layer (EIL), and an electron blocking layer (EBL). The emission material layer (EML) can be formed as a tandem structure of two or more stacks. In this case, each stack can contain a hole transport layer, an organic light emission layer, and an electron transport layer. When the EML is formed as a tandem structure of two or more stacks, a charge generation layer can be formed between the stacks. The charge generation layer can include an n-type charge generation layer adjacent to the lower stack and a p-type charge generation layer formed on top of the n-type charge generation layer and adjacent to the upper stack. The n-type charge generation layer injects electrons into the lower stack, and the p-type charge generation layer injects holes into the upper stack.The n-type charge-generating layer can be an organic layer obtained by doping an organic host material, which exhibits electron transport capability, with an alkali metal such as lithium (Li), sodium (Na), potassium (K), or cesium (Cs), or an alkaline earth metal such as magnesium (Mg), strontium (Sr), barium (Ba), or radium (Ra). The p-type charge-generating layer can be an organic layer obtained by doping an organic host material, which exhibits hole transport capability, with a dopant. The cathode electrode CE is formed on the emissive material layer EML. The cathode electrode CE can be broadly shaped in the light emission region EA and the non-emissive region NEA. The cathode electrode (CE) can be made of a transparent conductive material (TCO) or a semi-transparent conductive material such as molybdenum (Mo), tungsten (W), silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), and alloys thereof. If the cathode electrode (CAT) is made of a semi-transparent conductive material, light emission efficiency can be increased by microcavities. Referring to Fig. 3a, Fig. 3b and Fig. 4, in the present embodiment at least one section of the anode electrode AE ​​extends to the non-emission area NEA in order to contact the circuit element. In the exemplary embodiment, a light-absorbing layer LA can further be present between the passivation layer PAS and the coating layer OC. The light-absorbing layer LA can contain a colorant such as a pigment, dye, etc., which transmits light in one specific wavelength band and blocks light in another specific wavelength band, and consequently selectively transmits incident light only in a partial wavelength band. The light-absorbing layer LA can have a structure in which at least two pigment layers are stacked so that the light-absorbing layer absorbs light generated by the lighting device LD.For example, the light-absorbing layer LA can have a first absorbing layer LA1, which contains a pigment of a first color, and a second absorbing layer LA2, which contains a pigment of a second color that is different from the first color. In the exemplary embodiment, the first color can be red and the second color can be blue, but they are not limited to these. If the absorbing layers containing pigments of different colors are overlapped, a light leakage phenomenon can be effectively blocked by a luminescent reflection effect (e.g., a black luminescent effect). The light-absorbing layer LA is made of the same material as the color filter and can be formed by the same process. That is, the color filter, which contains the pigment of the same color, and the light-absorbing layer LA can be formed together through a single masking process. For example, when the color filter containing the pigment of the first color is formed, the first absorbing layer LA1 of the light-absorbing layer LA can be formed together with it, and when the color filter containing the pigment of the second color is formed, the second absorbing layer LA2 of the light-absorbing layer LA can be formed together with it. Accordingly, according to the present embodiment, a light leakage phenomenon in the non-emission region NEA can be more completely blocked without the need for a separate additional process to create the light-absorbing layer LA. The light-absorbing layer LA can be formed over the entire non-emission region NEA. However, the present embodiment is not limited to this, and depending on the implementation, the light-absorbing layer LA can be formed on the anode electrode AE ​​within the non-emission region NEA. In the exemplary embodiment, if pixel PX represents a white color, the light-absorbing layer LA may not be formed in pixel PX. If the light-absorbing layer LA is formed over the entire non-emission region NEA, the first viahole VIA1 and the second viahole VIA2 can be formed, allowing light to pass through the light-absorbing layer LA. Alternatively, the light-absorbing layer LA may not be formed around the first viahole VIA1 and the second viahole VIA2. Fig. 5 is a flowchart showing a manufacturing process for the display panel according to the exemplary embodiment. Fig. 5 is described with reference to Figs. 3 to 4. First, the pixel circuit layer can be formed on the substrate SUB. In particular, the first electrode layer can be formed on the substrate SUB (1501). The first electrode layer can be formed by forming a conductive layer on the substrate SUB using a printing process, a sputtering process, a chemical vapor deposition process, a pulsed laser deposition (PLD) process, a vacuum deposition process, an atomic layer lamination process, etc., and by structuring using an etching process with a mask. Here, a first mask is used. Then the buffer layer BUF can be formed on the first electrode layer (1502). The buffer layer BUF can be formed by a chemical vapor deposition process, a spin coating process, a plasma-enhanced chemical vapor deposition process, a sputtering process, a vacuum deposition process, a high-density plasma chemical vapor deposition process, a pressure process, or similar processes. The active layer can be formed on the buffer layer BUF (1503). For example, an amorphous silicon layer can be formed on the buffer layer BUF, and a polysilicon layer can be formed by crystallizing the amorphous silicon layer. The active layer can then be formed by structuring the polysilicon layer using a photolithography process or similar method. A second mask can be used for the photolithography process. The source regions SA1, SA2, and SA3, the drain regions DA1, DA2, and DA3, and the channels CH1, CH2, and CH3 can be formed by implanting foreign atoms into the polysilicon layer that forms the active layer. Contact holes for contacting the first electrode layer and the top layer can also be formed in the buffer layer BUF. The gate insulating layer GI can be formed on the active layer (1504). The gate insulating layer GI can be selectively formed in a region described below, where the second electrode layer is to be formed. In particular, the gate insulating layer GI can be formed by a photolithography process, which exposes and develops the gate insulating layer GI using a mask. A third mask can be used here. The active layer can be formed from a molybdenum-titanium (MoTi) bilayer. The second electrode layer can be formed on the gate insulating layer GI (1505). The second electrode layer can be formed by creating a conductive layer on the substrate SUB using a printing process, a sputtering process, a chemical vapor deposition process, a pulsed laser deposition (PLD) process, a vacuum deposition process, an atomic layer lamination process, etc., and by structuring using an etching process with a mask. Here, a fourth mask is used. Then the passivation layer PAS can be formed to cover the second electrode layer (1506). The color filter can be formed on the passivation layer PAS (1507). For the color filter, for example, the color filter for the first color can be structured using the first mask, the color filter for the second color can be structured using the second mask, and the color filter for the third color can be structured using the third mask. While the color filter is being formed, the light-absorbing layer LA can be formed simultaneously. To form the color filter and the light-absorbing layer LA, three masks corresponding to the respective colors, that is, the fifth to seventh masks, can be used. Then the coating layer OC is formed to cover the color filter and the light-absorbing layer LA (1508). The coating layer OC can be exposed and developed on the passivation layer PAS by using the mask. The mask may have openings corresponding to the via holes VIA1 and VIA2. Here, an eighth mask may be used. Then the luminescent device can be formed on the coating layer OC. In particular, the anode electrode AE ​​is structured on the coating layer OC by using a ninth mask having openings corresponding to the emission regions EA (1509). After the anode electrode AE ​​is formed, the emissive material layer EML and the cathode electrode CE are broadly formed to cover the entire area of ​​the display panel 50 (1511). Fig. 6 shows a cross-section of the storage capacitor Cst from Fig. 4 according to the exemplary embodiment. Fig. 7 shows the storage capacitor Cst as a circuit symbol. In the exemplary embodiment, the storage capacitor Cst can have the upper electrode UE, the lower electrode BE and the middle electrode ME. The buffer layer BUF is placed between the lower electrode BE and the middle electrode ME. The gate insulating layer is placed between the middle electrode ME and the upper electrode UE. Since the buffer layer BUF and the gate insulating layer are insulators, both the upper electrode UE and the middle electrode ME, and the middle electrode ME and the lower electrode BE, can act as capacitors for storing charges. The upper electrode UE and the middle electrode ME form a first capacitor C1, and the middle electrode ME and the lower electrode BE form a second capacitor C2. The middle electrode ME is connected to the gate electrode of the driver transistor and is then connected to the first node N1 in Fig. 2. The upper electrode UE and the lower electrode BE are electrically connected to the source node of the driver transistor and are then connected to the second node N2.Since the first capacitor C1 and the second capacitor C2 are connected in parallel, the capacitance of the storage capacitor Cst is the sum of the capacitances of the first and second capacitors C2. Accordingly, if the storage capacitor Cst is formed using three electrodes, the capacitance can be further increased in a limited range, thereby improving the opening ratio. The first electrode layer, arranged on the substrate SUB, can form the lower electrode BE of the storage capacitor Cst. This first electrode layer can also include a light-shielding layer. The buffer layer BUF is positioned on the lower electrode BE to cover the first electrode layer. The buffer layer BUF prevents ions or foreign atoms from diffusing out of the substrate SUB and prevents moisture penetration. Furthermore, the buffer layer BUF improves the surface flatness of the substrate SUB. The buffer layer BUF can consist of inorganic material such as oxide, nitride, etc., organic material, or organic / inorganic composites. The middle electrode ME is arranged on the buffer layer BUF. The middle electrode ME can be formed in the same layer as a layer containing the active layer CH2 from Fig. 4. As described above, the active layer can be formed from a molybdenum-titanium (MoTi) bilayer. The middle electrode ME, which forms the storage capacitor Cst, can also be formed from a molybdenum-titanium (MoTi) bilayer. A first active layer ACT1 can be formed from indium gallium zinc oxide (IGZO). A second active layer, ACT2, can be formed from molybdenum titanium (MoTi). This second active layer, ACT2, has a low contact resistance compared to the first active layer, ACT1, which is formed from amorphous zinc oxide. Furthermore, the second active layer, ACT2, exhibits wet set selectivity. The middle electrode, ME, is connected to the gate electrode of the driver transistor (see GE2 in Fig. 4). The gate electrode of the driver transistor has a top-gate structure and is formed on the same layer as the top electrode, UE. The middle electrode, ME, is connected to the gate electrode of the driver transistor, and the top electrode, UE, and the middle electrode, ME, which together form the gate electrode, represent distinct layers.Therefore, a contact hole is required to electrically connect the gate electrode and the middle electrode in the driver transistor area. The second active layer, ACT2, which is made of molybdenum-titanium (MoTi), has a low contact resistance compared to the first active layer, ACT1, which is made of amorphous zinc oxide. Therefore, even if the contact hole connecting the gate electrode and the middle electrode (ME) is small, there should be no reliability issues if the middle electrode (ME) is formed from a Molybdenum-titanium (MoTi) bilayer. The opening ratio can be increased if the contact hole is small. If the middle electrode (ME) is formed from a Molybdenum-titanium (MoTi) bilayer, the opening ratio can be improved. Furthermore, the second active layer, ACT2, which is made of molybdenum titanium (MoTi), serves to protect the first active layer, ACT1, which is made of indium gallium zinc oxide (IGZO). Hydrogen remaining in the passivation layer can diffuse into the first active layer, ACT1. The middle electrode, ME, forms a channel in the driver transistor area, and if hydrogen diffuses into this channel, it can change the threshold voltage of the driver transistor. The second active layer, ACT2, which is made of molybdenum titanium (MoTi), blocks the diffusion of hydrogen into the first active layer, ACT1. That is, the second active layer, ACT2, acts as a hydrogen-blocking layer for the first active layer, ACT1. The gate insulating layer GI is placed on the central electrode ME. The gate insulating layer GI can be formed using a photolithography process, which develops and exposes the gate insulating layer GI using a mask. Here, a third mask is used. The upper electrode UE is formed on the gate insulating layer GI. The upper electrode UE is formed by structuring the second electrode layer through an etching process using a mask. The second electrode layer is formed from a conductive film on the gate insulating layer GI using a printing process, a sputtering process, a chemical vapor deposition process, a pulsed laser deposition (PLD) process, a vacuum deposition process, an atomic layer lamination process, or a similar process. The passivation layer is placed on the upper electrode UE to cover the upper electrode UE. As described above, in order to increase the opening ratio, the middle electrode ME is formed by a double layer which has the first active layer ACT1, which is formed from indium gallium zinc oxide (IGZO), and the second active layer ACT2, which is formed from molybdenum titanium (MoTi). The inventors of the present disclosure discovered the following problems with this structure. It has been confirmed that a TAIL pattern is formed in the first active layer ACT1 when the middle electrode ME is formed by a double layer. If a TAIL-shaped pattern (hereinafter referred to as the TAIL pattern) is formed in a channel region of the driver transistor at the end of the first active layer ACT1, as indicated by a dotted circle in Fig. 6, a HUMP phenomenon can occur, which degrades the device characteristics of the driver transistor. The HUMP phenomenon means that in a section where the magnitude of a drain current increases linearly proportional to the magnitude of a gate voltage of the driver transistor, the drain current increases linearly and then jumps abnormally. Furthermore, the TAIL pattern of the first active layer ACT1 enlarges the area in which a pixel circuit element layer is formed, thereby reducing the aperture ratio. Additionally, the TAIL pattern of the first active layer ACT1 reduces the success rate of a repair attempt to separate the cells within the pixel. The inventors of the present disclosure have invented a new process for preventing the formation of the TAIL pattern of the first active layer ACT1. The process for preventing the formation of the TAIL pattern is described below with reference to Figures 8, 9, 10, 11 to 12. Figures 8, 9, 10, 11 to 12 are views illustrating a detailed process for the steps of active layer formation. "Cst" denotes an area where the storage capacitor Cst is formed, and "DT" denotes an area where the driver transistor is formed. Fig. 8 shows that the first active layer ACT1 is deposited, the second active layer ACT2 is deposited on top of the first active layer ACT1, a photoresist PR material is applied to the active layer in which the first active layer ACT1 and the second active layer ACT2 are deposited sequentially, and a photoresist PR pattern is formed using a halftone mask. The photoresist PR pattern is formed using a halftone H / T at a position corresponding to the region where the channel (CH) of the driver transistor is formed. Fig. 9 shows a first structuring step and the first structuring step of the second active layer ACT2. The second active layer ACT2 is first structured to match the photoresist PR pattern. It is preferred that the first structuring step of the second active layer ACT2 be performed using a dry etching process. This is because, in the first structuring step of the second active layer ACT2, the first active layer ACT1, which is located beneath the second active layer ACT2, should not be etched. Therefore, it is desirable to use the dry etching process, which is capable of etching only a desired section, exhibits good accuracy, and allows for fine structuring. Dry etching has anisotropic properties, which result in different etch rates in the horizontal and vertical directions. Fig. 10 shows a halftone H / T ashing step of removing a portion of the photoresist PR. Halftone H / T ashing removes a portion of the photoresist PR and reduces its thickness. It is desirable to remove a portion of the photoresist PR to such an extent that the photoresist PR pattern formed by the halftone H / T ashing is removed, exposing the area where the CH of the driver transistor is formed. The side width of the photoresist PR covering the second active layer ACT2 is reduced by the halftone H / T ashing, and consequently, a portion of the second active layer ACT2 of the storage capacitor Cst region is exposed by an amount equal to D. Fig. 11 shows a second structuring step and an etching step of the first active layer ACT1. Wet etching is preferred on the first active layer ACT1. It is preferred to select an etching solution that selectively dissolves not only non-metallic materials. Wet etching has a high etch rate and isotropic properties, exhibiting the same etch rate in both the horizontal and vertical directions. Therefore, even the base of the photoresist PR can be etched. When the first active layer ACT1 is structured using a wet etching process, both the base of the photoresist PR and the second active layer ACT2 can be etched, as shown in Fig. 11. Consequently, the buffer layer BUF has a thickness difference TD. Specifically, in the buffer layer BUF, the thickness of the area covered by the first active layer ACT1 is greater than the thickness of the exposed area.The channel CH region of the driver transistor is not etched because the etching solution is blocked by the second active layer ACT2. Figure 12 shows a third structuring step and an additional etching step of the second active layer ACT2. In the third structuring step, the end of the second active layer ACT2 is removed. Wet etching is preferred for the third structuring step of the additional etching of the second active layer ACT2. This is because, unlike the first structuring step, the third structuring step requires isotropic etching with a high etch rate. In the third structuring step, it is preferred to select an etching solution that dissolves both a metallic material, such as molybdenum titanium (MoTi), and a non-metallic material. When the active layer is formed using the process described above, it is possible to prevent the problem described with reference to Fig. 6, namely the formation of the tail pattern of the first active layer ACT1. As a result of forming the active layer using the described process, it was confirmed that the critical dimension (CD) value of the tail pattern of the first active layer ACT1 is improved from 1.6 micrometers to 0 micrometers. Fig. 13 shows a further embodiment from Fig. 6 and shows a cross-section of the storage capacitor Cst, which is formed by means of the manufacturing process from Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11 to Fig. 12. The storage capacitor Cst has the lower electrode BE on the substrate SUB, the buffer layer BUF, which is arranged on the lower electrode, the middle electrode ME, which covers part of the buffer layer BUF, the gate insulating layer GI, which covers the middle electrode ME and the buffer layer BUF, and the upper electrode UE, which covers part of the gate insulating layer GI. The middle electrode ME can be formed from a double layer. The middle electrode ME can have the first active layer ACT1, which is formed from indium gallium zinc oxide (IGZO), and the second active layer ACT2, which is formed from molybdenum titanium (MoTi). The buffer layer BUF can be divided into a first region 1A and a second region 2A. The first region 1A is covered by the middle electrode ME, and the second region 2A is exposed and in contact with the gate insulating layer GI. The thickness T1 of the first region 1A is greater than the thickness T2 of the second region 2A. The buffer layer BUF, which has this shape, is a result of the second structuring step, described with reference to Fig. 11. As described in Fig. 7, the lower electrode BE and the upper electrode UE are connected to each other at the second node N2 and are connected to the anode electrode of the light source. To connect the lower electrode BE and the upper electrode UE, a hole must be formed in the buffer layer BUF. In the display panel according to the embodiment shown in Fig. 13, the thickness of the second region 2A, in which the hole is formed, is as thin as T2.This makes it easier to form the hole for connecting the lower electrode BE and the upper electrode UE to each other in the buffer layer BUF in a subsequent process. As described above, the display panel and the method for its fabrication according to the exemplary embodiment propose a storage capacitor structure capable of increasing the storage capacitor's capacitance relative to the area occupied by the pixel circuit layer, thus improving the open-axis response. Furthermore, any electrode belonging to the storage capacitor is formed from a bilayer comprising indium gallium zinc oxide (IGZO) and molybdenum titanium (MoTi), thereby increasing the open-axis response. It is also possible to further improve the open-axis response by preventing the formation of the TAIL pattern of indium gallium zinc oxide (IGZO), which reduces the open-axis response in the electrode formed from a bilayer comprising indium gallium zinc oxide (IGZO) and molybdenum titanium (MoTi).Furthermore, by preventing the formation of the TAIL pattern of indium gallium zinc oxide (IGZO), it is possible to increase the success rate of repairs resulting from cell cutting within the pixel. Simultaneously, it is possible to eliminate the influence of the HUMP phenomenon, which degrades the device characteristics of the driver transistor.

Claims

A manufacturing process for a display panel (50) comprising a light source (LD) and a pixel circuit configured to operate the light source (LD), comprising the manufacturing process of: forming the pixel circuit on a substrate (SUB); and forming the light source (LD) on the pixel circuit, wherein forming the pixel circuit comprises: forming a first electrode layer on the substrate (SUB); forming a buffer layer (BUF) on the first electrode layer; and forming an active layer on the buffer layer (BUF), wherein forming the active layer comprises: depositing a first active layer (ACT1) and depositing a second active layer (ACT2) on the first active layer (ACT1);a first structuring step in which a photoresist (PR) material is applied to the second active layer (ACT2), a photoresist (PR) pattern is formed by a halftone mask, and the second active layer (ACT2) is etched to expose part of the first active layer (ACT1); a halftone ashing step of the photoresist (PR) pattern to expose part of the structured second active layer (ACT2); and a second structuring step in which the exposed part of the first active layer (ACT1) is etched using the structured second active layer (ACT2) as a mask. The manufacturing process according to claim 1, wherein in the second structuring step the etching is carried out excessively, such that a part of the buffer layer (BUF) arranged under the first active layer (ACT1) is etched together with the first active layer (ACT1). The manufacturing process according to claim 1 or 2, wherein the formation of the active layer further comprises a third structuring step in which an additional etching of the second active layer (ACT2) is carried out. The manufacturing process according to claim 3, wherein the etching of the second active layer (ACT2) in the third structuring step comprises wet etching. The manufacturing process according to one of claims 1 to 4, wherein the etching of the second active layer (ACT2) in the first structuring step comprises dry etching. The manufacturing process according to one of claims 1 to 5, wherein the etching of the first active layer (ACT1) in the second structuring step comprises wet etching. The manufacturing process according to any one of claims 1 to 6, wherein the first active layer (ACT1) is formed from indium gallium zinc oxide, and wherein the second active layer (ACT2) is formed from molybdenum titanium. A display panel (50) in which a plurality of sub-pixels (PX) are arranged in the form of a matrix, each of the sub-pixels (PX) comprising a light source (LD), a driver transistor (DT) configured to supply a driver current to the light source (LD), and a storage capacitor (Cst) configured to maintain a voltage controlling the magnitude of the driver current for a specific duration, the storage capacitor (Cst) comprising a lower electrode (BE), a buffer layer (BUF) arranged on the lower electrode (BE), a middle electrode (ME) covering part of the buffer layer (BUF), a gate insulating layer (GI) covering the middle electrode (ME) and the buffer layer (BUF), and an upper electrode (UE) covering part of the gate insulating layer (GI), wherein the buffer layer (BUF) has a thickness (T1) of a first region (1A),which is covered by the middle electrode (ME), is greater than a thickness (T2) of a second region (2A) which is in contact with the gate insulating layer (GI), and wherein the middle electrode (ME) is formed by a double layer. The display panel (50) according to claim 8, wherein the middle electrode (ME) comprises: a first active layer (ACT1) formed from indium gallium zinc oxide; and a second active layer (ACT2) formed from molybdenum titanium. The display panel (50) according to one of claims 8 to 9, wherein the middle electrode (ME) is connected to a gate electrode (GE2) of the driver transistor (DT), and wherein the lower electrode (BE) and the upper electrode (UE) are connected to an anode electrode (AE) of the light device (LD).

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