CONTACTS FOR SEMICONDUCTOR DEVICES AND METHODS FOR THEIR MANUFACTURE

Abstract

Semiconductor device comprising: a first transistor comprising: a first gate stack (80, 104, 106) over a semiconductor substrate (50), the first gate stack having a first height, a first source / drain region (90B) adjacent to the first gate stack (80, 104, 106), a first gate contact (130) electrically connected to the first gate stack (80, 104, 106), wherein a top surface of the first gate contact has a first width (W3), and a first source / drain contact (128) electrically connected to the first source / drain region (90B), wherein a top surface of the first source / drain contact has a second width (W2) that is greater than the first width (W3); and a second transistor having: a second gate stack (104, 106) above the semiconductor substrate (50), the second gate stack having a second height that is smaller than the first height, a second source / drain region (90A) adjacent to the second gate stack (104, 106), and a second source / drain contact (126) electrically connected to the second source / drain region (90A), wherein a top surface of the second source / drain contact has a third width (W1) that is smaller than the second width (W2); wherein the first transistor has a first channel region (87); wherein the second transistor has a second channel region (87); wherein the second gate stack (104, 106) comprises a dielectric material (104) in contact with the second channel region (87); wherein the first gate stack (80, 104, 106) comprises the dielectric material (104) separated from the first channel region (87) by a deposited gate oxide layer (80); wherein an upper surface of the second channel region (87) is arranged at a first distance (H1) above an upper surface of the first channel region (87) in a direction perpendicular to a main surface of the semiconductor substrate (50); and wherein a thickness of the deposited gate oxide layer (80) is equal to the first distance (H1).

Description

background

[0001] Semiconductor devices are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric material layers, conductive material layers, and semiconductor material layers over a semiconductor substrate. The various material layers are patterned by lithography to create circuit components and elements on the substrate.

[0002] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size so that more components can be integrated in a given area.

[0003] US 2011 / 0018068 A1 describes an integrated circuit having a low-voltage region and a high-voltage region, wherein in both regions source / drain regions and gate stacks are contacted through an interlayer dielectric, heights of the source / drain contacts in the high-voltage region are greater than heights of the source / drain contacts in the low-voltage region, and in both regions heights of the source / drain contacts are greater than heights of the gate contacts.

[0004] US 2020 / 0303508 A1 describes an integrated circuit comprising a first and a second transistor, an interlayer dielectric over the two transistors, and source / drain contacts through the interlayer dielectric, wherein a height of the source / drain contact of the second transistor is greater than a height of the source / drain contact of the first transistor, and wherein a width of the source / drain contact of the second transistor is greater than a width of the source / drain contact of the first transistor.

[0005] US 2020 / 0043939 A1 describes a semiconductor device having a first and a second transistor, wherein surfaces of the channel regions of the two transistors are not coplanar and the gate dielectric layer of the second transistor is thinner than the gate dielectric layer of the first transistor. Short description of the drawings

[0006] Aspects of the present disclosure are best understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Rather, the dimensions of various features may be arbitrarily exaggerated or reduced for clarity of illustration. The Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19A, Fig. 19B, Fig. 19C, Fig. 19D, Fig. 19E, Fig. 20A, Fig. 20B, Fig. 20C, Fig. 21A, Fig. 21B and Fig. 21C are cross-sectional and top-down views of intermediate stages in the fabrication of field-effect transistors (FETs) according to some embodiments. Fig. 21D shows a graphical representation of material properties of a contact according to some embodiments. Detailed description

[0007] The following description provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to facilitate the present invention. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and may also include embodiments in which additional elements may be fabricated between the first and second elements such that the first and second elements are not in direct contact. Furthermore, in the present invention, reference numerals and / or letters may be repeated in the various examples.This repetition is for simplicity and clarity and does not, in itself, prescribe any relationship between the various embodiments and / or configurations discussed.

[0008] Furthermore, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein to conveniently describe the relationship of one element or structure to one or more other elements or structures illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation, in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relative descriptors used herein may be interpreted accordingly.

[0009] In various embodiments, methods for fabricating contacts for low-voltage semiconductor devices and high-voltage semiconductor devices, as well as semiconductor devices fabricated using these methods, are provided. One method comprises fabricating low-voltage semiconductor devices in a first region of a substrate and fabricating high-voltage semiconductor devices in a second region of the substrate. The second region of the substrate is recessed beneath the first region of the substrate. Gates are fabricated in the first and second regions, wherein the gates in the second region have heights greater than those of the gates in the first region. One or more interlayer gate dielectrics are fabricated over the first and second regions.A patterned photoresist is formed over the interlayer gate dielectrics and is used to create openings that expose first source / drain regions in the first region, second source / drain regions in the second region, and the gates in the first and second regions.

[0010] The photoresist is patterned to include first openings over the first source / drain regions, second openings over the second source / drain regions, and third openings over the gates. The second openings may have widths larger than the first and third openings, and the first openings may have widths equal to or larger than the third openings. As the width of the openings increases, the etch rate of the underlying interlayer dielectrics may also increase. This allows the different opening widths to be used to expose the first and second source / drain regions and the gates arranged at different heights without overetching the first and second source / drain regions or the gates. This reduces device defects and improves device performance. It also eliminates masking steps, thereby reducing costs.

[0011] Some embodiments described herein are discussed in the context of planar FETs fabricated using a gate-last process. In other embodiments, a gate-first process may be used. Additionally, some embodiments contemplate aspects used in fin field-effect transistors (FinFETs), nanostructured field-effect transistors (e.g., nanolayer, nanowire, gate-all-around, or similar FETs) (NSFETs), or the like.

[0012] In Fig. 1, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Generally, an SOI substrate comprises a layer of a semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer may be formed on a substrate, typically a silicon or glass substrate. Other substrates, such as a multilayer or gradient substrate, may also be used.In some embodiments, the semiconductor material of substrate 50 may include: silicon; germanium; a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor such as silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof.

[0013] The substrate 50 has a low-voltage device (LV) region 100 and a high-voltage device (HV) region 200. The LV device region 100 is a region where a low-voltage device, such as a low-voltage MOS (metal oxide semiconductor) device, is to be fabricated. The HV device region 200 is a region where a high-voltage device, such as a high-voltage MOS device, is to be fabricated. The LV device is configured to operate at operating voltages and supply voltages that are lower than the respective voltages of the HV device. It should be understood that the principles of HV and LV devices are related. The maximum voltages that the LV device can withstand without damage are lower than the maximum voltages that the HV device can withstand without damage.In some embodiments, the operating and supply voltages of the HV device are about 2.5 V to about 15 V, and the operating and supply voltages of the LV device are about 0.5 V to about 1 V. The LV device region 100 may be physically separated from the HV device region 200 (as represented by a divider 51), and a number of device elements (e.g., other active devices, doped regions, isolation structures, or the like) may be disposed between the LV device region 100 and the HV device region 200.

[0014] In addition, Fig. 1, a pad layer 52 and a mask layer 54 are formed on the substrate 50. The pad layer 52 may be a thin layer of silicon oxide or the like, which may be formed using a thermal oxidation process or the like. In some embodiments, the pad layer 52 may comprise silicon nitride, silicon oxynitride, combinations or multilayers thereof, or the like. The pad layer 52 may function as an adhesion layer between the substrate 50 and the mask layer 54. The pad layer 52 may also function as an etch stop layer for etching the mask layer 54. In some embodiments, the mask layer 54 is formed from silicon nitride or the like. In some embodiments, the mask layer 54 may comprise silicon oxynitride, polysilicon, combinations or multilayers thereof, or the like. The mask layer 54 may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like.The mask layer 54 can be used as a hard mask during a later photolithography process.

[0015] In Fig. 2, the mask layer 54, the pad layer 52, and the substrate 50 are etched to create trenches 56. A first patterned mask (not individually shown), such as a patterned photoresist, may be formed over the mask layer 54. The first patterned mask may be formed by depositing a first photosensitive layer over the mask layer 54 using spin coating or the like. Subsequently, the first photosensitive layer may be patterned by exposing it to a patterned energy source (e.g., a patterned light source) and developing the first photosensitive layer to remove an exposed or unexposed portion of the first photosensitive layer, thereby forming the first patterned mask.The mask layer 54, the pad layer 52, and the substrate 50 may be etched using a suitable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or the like, or a combination thereof, to transfer the pattern of the first patterned mask to the mask layer 54, the pad layer 52, and the substrate 50, thereby forming the trenches 56. In some embodiments, the etching process may be anisotropic. The first patterned mask may then be removed using a suitable method, such as a detachment process, a stripping process, or the like, or a combination thereof.

[0016] In Fig. 3, shallow trench isolation (STI) regions 58 are formed in the trenches 56 adjacent to the mask layer 54, the pad layer 52, and the substrate 50. The STI regions 58 may be formed by depositing an insulating material (not individually shown) to fill the trenches 56 and extend along top and side surfaces of the substrate 50, side surfaces of the pad layer 52, and top and side surfaces of the mask layer 54. The insulating material may be an oxide, such as silicon oxide, a nitride, or the like, or a combination thereof, and may be deposited by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system with post-cure to convert the deposited material into another material, such as an oxide), or the like, or a combination thereof.Other insulating materials deposited using a suitable method may also be used. In the illustrated embodiment, the insulating material is silicon oxide deposited using an FCVD process. After deposition of the insulating material, an annealing process may be performed. In some embodiments, the insulating material is deposited such that excess insulating material covers the mask layer 54. The insulating material may be a single layer or may comprise multiple layers. For example, in some embodiments, an overlay (not individually shown) may first be formed along surfaces of the substrate 50, the pad layer 52, and the mask layer 54. Subsequently, a fill material, such as one of the aforementioned fill materials, may be deposited over the overlay.

[0017] A removal process is then performed on the insulating material to remove excess insulating material over the mask layer 54. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, or the like, may be used. The removal process may planarize the insulating material and the mask layer 54 to form the STI regions 58. The removal process exposes the mask layer 54 so that the top surfaces of the mask layer 54 and the STI regions 58 are at the same height after the planarization process is complete.

[0018] In Fig. 4, a second patterned mask 60 is formed over the LV device region 100, and the STI regions 58, the mask layer 54, the pad layer 52, and the substrate 50 are etched in the HV device region 200. The second patterned mask 60 may be a patterned photoresist. The second patterned mask 60 may be formed by depositing a second photosensitive layer over the mask layer 54 and the STI regions 58 using spin coating or the like. Subsequently, the second photosensitive layer may be patterned by exposing it to a patterned energy source (e.g., a patterned light source) and developing it to remove an exposed or unexposed portion of the second photosensitive layer, thereby forming the second patterned mask 60 covering the LV device region 100 and leaving the HV device region 200 uncovered.The mask layer 54, the pad layer 52, the substrate 50, and the STI regions 58 in the HV device region 200 may then be etched using a suitable etching process. The etching process may be a wet etching process, a dry etching process, or the like. In some embodiments, the etching process may be a reactive ion etch (RIE), a neutral beam etch (NBE), or the like, or a combination thereof. In some embodiments, the etching process may be anisotropic. In some embodiments, the mask layer 54, the pad layer 52, and the substrate 50 may be etched separately from the STI regions 58. The mask layer 54, the pad layer 52, and the substrate 50 may be etched before or after the STI regions 58.

[0019] As also in Fig. 4, top surfaces of the mask layer 54 and the STI regions 58 in the LV device region 100 may be located above top surfaces of the substrate 50 and the STI regions 58 in the HV device region 200 in a direction perpendicular to a major surface of the substrate 50. The top surfaces of the mask layer 54 and the STI regions 58 in the LV device region 100 may be located at a height H1 of about 50 nm to about 350 nm above the top surfaces of the substrate 50 and the STI regions 58 in the HV device region 200. Gate structures later formed in the HV device region 200 may have heights greater than those of gate structures later formed in the LV device region 100. By excluding the substrate 50 and the STI regions 58 in the HV device region 200, gate structures to be fabricated later in the LV device region 100 and the HV device region 200 can be fabricated simultaneously.

[0020] In Fig. 5, the second patterned mask 60, the mask layer 54, and the pad layer 52 are removed from the LV device region 100. The second patterned mask 60 may be removed using any suitable method, such as a stripping process, a stripping process, or the like, or a combination thereof. In embodiments where the mask layer 54 comprises silicon nitride and the pad layer 52 comprises silicon oxide, the mask layer 54 may be removed using a wet cleaning process using phosphoric acid (H3PO4) or the like, and the pad layer 52 may be removed using a wet etching process using dilute hydrofluoric acid (dHF) or the like. The STI regions 58 may also be recessed such that top surfaces of the STI regions 58 are substantially coplanar with the top surface of the substrate 50.In some embodiments, a planarization process, such as a CMP process, may be performed to bring the top surfaces of the STI regions 58 in the LV device region 100 level with the top surface of the substrate 50. In some embodiments, the HV device region 200 may be masked while performing the planarization process in the LV device region 100.

[0021] In Fig. 6, a first well 62 is formed in the substrate 50 in the LV device region 100, and a second well 64 is formed in the substrate 50 in the HV device region 200. In some embodiments, the first well 62 and the second well 64 may be doped with the same or different dopants and with the same or different doping concentrations. Furthermore, the first well 62 and the second well 64 may each be doped with n-type or p-type dopants. In the embodiments with different dopants or doping concentrations, the different implantation steps for the LV device region 100 and the HV device region 200 may be realized using a photoresist or other masks (not individually shown). For example, a photoresist may be formed over the substrate 50 and the STI regions 58 in the LV device region 100.The photoresist is patterned to expose the HV device region 200 of the substrate 50. The photoresist may be spin-coated and patterned using suitable photolithography techniques. After the photoresist has been patterned, dopants are implanted into the HV device region 200, where the photoresist may act as a mask to prevent the dopants from being implanted into the LV device region 100. The dopants may be phosphorus, arsenic, antimony, boron, boron fluoride, indium, or the like, present in the region at a concentration equal to or less than 1 × 10 18 atoms / cm 3 , e.g. of about 1 × 10 16 atoms / cm 3 up to about 1 × 10 18 atoms / cm 3 , are implanted. After implantation, the photoresist is removed, for example, using a suitable stripping process.

[0022] After implanting the HV device region 200, a photoresist is formed over the substrate 50 and the STI regions 58 in the HV device region 200. The photoresist is patterned to expose the LV device region 100 of the substrate 50. The photoresist may be formed by spin-coating and patterned using suitable photolithography techniques. After the photoresist has been patterned, dopants may be implanted in the LV device region 100, where the photoresist may act as a mask to prevent the dopants from being implanted into the HV device region 200. The dopants may be phosphorus, arsenic, antimony, boron, boron fluoride, indium, or the like, present in the region at a concentration equal to or less than 1 × 10 18 atoms / cm 3 , e.g. of about 1 × 10 16 atoms / cm 3 up to about 1 × 10 18atoms / cm 3 , implanted. After implantation, the photoresist may be removed, for example, using a suitable stripping process. Following the implantations of the LV device region 100 and the HV device region 200, an annealing process may be performed to repair implantation damage and activate the implanted dopants. The first well 62 and the second well 64 are shown with bottom surfaces located below bottom surfaces of the STI regions 58 and extending below the STI regions 58. In some embodiments, the first well 62 and the second well 64 do not extend below the STI regions 58. In some embodiments, the bottom surfaces of the STI regions 58 are located below the bottom surfaces of the first well 62 and / or the second well 64.

[0023] In Fig. 7, a first gate dielectric layer 66 is formed over the STI regions 58, the first well 62, and the second well 64. The first gate dielectric layer 66 may be a dielectric material, for example, an oxide such as silicon oxide; a nitride such as silicon nitride; a composite structure such as oxide / nitride / oxide; a combination or multilayers thereof; or the like. The first gate dielectric layer 66 may be formed using a deposition process such as CVD, ALD, or the like. In some embodiments, the first gate dielectric layer 66 forms a gate oxide for a high-voltage transistor to be fabricated later. The first gate dielectric layer 66 may have a thickness of about 10 nm to about 100 nm.

[0024] In Fig. 8, the first gate dielectric layer 66 is removed from the LV device region 100. The first gate dielectric layer 66 may be removed using suitable photolithography and etching techniques. As shown in Fig. 8, a top surface of the first gate dielectric layer 66 in the HV device region 200 may be coplanar with top surfaces of the first well 62 and the STI regions 58 in the LV device region 100. After removing the first gate dielectric layer 66 from the LV device region 100, the top surfaces of the first well 62 and the STI regions 58 may be exposed. In some embodiments, the top surface of the first gate dielectric layer 66 in the HV device region 200 may be located above or below the top surfaces of the first well 62 and the STI regions 58 in the LV device region 100.

[0025] In Fig. 9, a second gate dielectric layer 70 is formed over the STI regions 58, the first well 62, and the first gate dielectric layer 66. The second gate dielectric layer 70 may be, for example, silicon oxide, silicon nitride, or a combination thereof, or the like, and may be deposited using suitable techniques or thermally grown. A gate layer 72 is formed over the second gate dielectric layer 70, and a mask layer 74 is formed over the gate layer 72. The gate layer 72 may be deposited over the second gate dielectric layer 70 and then planarized, for example, using a CMP. The mask layer 74 may be deposited over the gate layer 72.The gate layer 72 may be a conductive or non-conductive material selected from the group consisting of amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, and metals. The gate layer 72 may be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other suitable methods for depositing the selected material. The gate layer 72 may also be formed from other materials that have high etch selectivity toward etching isolation regions, e.g., the STI regions 58, the first gate dielectric layer 66, and / or the second gate dielectric layer 70. The mask layer 74 may comprise one or more layers, for example, silicon nitride, silicon oxynitride, or the like. In the embodiment shown in FIG. Fig. 9, a single gate layer 72 and a single mask layer 74 are formed across the LV device region 100 and the HV device region 200. Note that for illustrative purposes, the second gate dielectric layer 70 is shown covering the first well 62 and the STI regions 58. In some embodiments, the second gate dielectric layer 70 may be deposited to cover only the first well 62 and the first gate dielectric layer 66.

[0026] In Fig. 10, the mask layer 74 (see Fig. 7) may be patterned using suitable photolithography and etching techniques to form masks 86. The pattern of masks 86 may then be transferred to gate layer 72 to form gates 84. In some embodiments, the pattern of masks 86 may also be transferred to second gate dielectric layer 70 in LV device region 100 and HV device region 200 to form second gate dielectrics 82, and may be transferred to first gate dielectric layer 66 in HV device region 200 to form a first gate dielectric 80. The pattern of masks 86 may be transferred using suitable etching techniques. Gates 84 cover respective channel regions 87 of first well 62 and second well 64. The pattern of masks 86 physically separates each of gates 84 from adjacent gates.

[0027] After the mask layer 74, the gate layer 72, the second gate dielectric layer 70, and the first gate dielectric layer 66 have been patterned to form the masks 86, the gates 84, the second gate dielectrics 82, and the first gate dielectric 80, respectively, implantations for lightly doped source / drain regions (LDD regions; not individually shown) may be performed. In embodiments where the LV device region 100 and the HV device region 200 comprise different device types, similar to the embodiments described above with reference to Fig. 6, a mask, such as a photoresist, may be formed over the HV device region 200 while the LV device region 100 is exposed, and dopants of a corresponding type (e.g., n-type or p-type) may be implanted into the exposed first well 62 in the LV device region 100. The mask may then be removed. The aforementioned n-type dopants may be used as the n-type dopants, and the aforementioned p-type dopants may be used as the p-type dopants. The lightly doped source / drain regions may have a dopant concentration of approximately 10 15 atoms / cm 3 up to about 10 19 atoms / cm 3 An annealing process can repair implantation damage and activate the implanted dopants.

[0028] It should be noted that a method for forming spacers and LDD regions has been generally described above. Other methods and orders may also be used. For example, fewer or more spacers may be used. In some embodiments, gate seal spacers (not individually shown) may be formed along sidewalls of the masks 86, the gates 84, the second gate dielectrics 82, and the first gate dielectric 80, and after the gate seal spacers are formed, the LDD regions may be formed. Furthermore, n- and p-type devices may be formed using different structures and steps. For example, LDD regions for n-type devices may be formed before the gate seal spacers are formed, while the LDD regions for p-type devices may be formed after the gate seal spacers.

[0029] In Fig. 11, gate spacers 88 are formed along the sidewalls of the masks 86, the gates 84, the second gate dielectrics 82, and the first gate dielectric 80. The gate spacers 88 may be formed by conformally depositing an insulating material and subsequently anisotropically etching the insulating material. The insulating material for the gate spacers 88 may be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, a combination thereof, or the like.

[0030] In Fig. 12, source / drain regions 90A and 90B are formed in the first well 62 and the second well 64, respectively. The source / drain regions 90A and 90B may be formed using an implantation process, an etching process followed by an epitaxial growth process, or the like. The source / drain regions 90A are formed in the first well 62 such that the gate 84 in the LV device region 100 is located between respective adjacent pairs of the source / drain regions 90A. Similarly, the source / drain regions 90B are formed in the second well 64 such that the gate 84 in the HV device region 200 is located between respective adjacent pairs of the source / drain regions 90B.In some embodiments, the gate spacers 88 are used to separate the source / drain regions 90A and 90B from the gates 84 by an appropriate lateral distance such that the source / drain regions 90A and 90B do not short-circuit later-fabricated gates of the resulting FETs.

[0031] In embodiments where source / drain regions 90A and 90B are formed using an epitaxial growth process, source / drain regions 90A may be formed in LV device region 100 by masking HV device region 200 and etching the source / drain regions of first well 62 in LV device region 100 to create recesses in first well 62. Then, source / drain regions 90A are epitaxially grown in the recesses in LV device region 100. Source / drain regions 90A may comprise a suitable material such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, silicon germanium, boron-doped silicon germanium, germanium, germanium-tin, or the like. The materials for the source / drain regions 90A can be selected to introduce stress into the respective channel regions 87 to improve performance.In some embodiments, the source / drain regions 90A in the LV device region 100 may have surfaces that are raised from respective surfaces of the first well 62 and may have chamfers.

[0032] The source / drain regions 90B in the HV device region 200 may be created by masking the LV device region 100 and etching the source / drain regions of the second well 64 in the HV device region 200 to create recesses in the second well 64. Then, the source / drain regions 90B in the HV device region 200 are epitaxially grown in the recesses. The source / drain regions 90B may comprise a suitable material such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, silicon germanium, boron-doped silicon germanium, germanium, germanium-tin, or the like. The materials for the source / drain regions 90B may be selected to introduce stress into the respective channel regions 87 to improve performance.In some embodiments, the source / drain regions 90B in the HV device region 200 may have surfaces that are raised from respective surfaces of the second well 64 and may have chamfers.

[0033] In embodiments where the source / drain regions 90A and 90B are formed by implantation or epitaxial growth, the source / drain regions 90A and 90B, the first well 62, and / or the second well 64 may be implanted with dopants to form the source / drain regions, similar to the method discussed above for forming lightly doped source / drain regions, and then an annealing process may be performed. The source / drain regions 90A and 90B may have a doping concentration of about 10 19 atoms / cm 3 up to about 10 21 atoms / cm 3The aforementioned dopants can be used as the n- and / or p-type dopants for the source / drain regions 90A and 90B. In some embodiments, the source / drain regions 90A and 90B can be doped in situ during growth.

[0034] In addition, Fig. 12 silicide regions 92A and 92B are formed in the LV device region 100 and the HV device region 200, respectively. The silicide regions 92A and 92B may be formed by forming a metal layer (not individually shown) over the source / drain regions 90A and 90B, performing an annealing process to form the silicide regions 92A and 92B, and removing unreacted portions of the metal layer.

[0035] In Fig. 13, the masks 86 are removed, and the gate spacers 88 are etched. In some embodiments, a planarization process, such as CMP, may be performed to bring top surfaces of the gates 84 level with top surfaces of the gate spacers 88. In some embodiments, one or more suitable etch processes, which may be isotropic or anisotropic, may be used for removing the masks 86 and etching the gate spacers 88. In some embodiments, the masks 86 and the gate spacers 88 may be etched using a dry etch process that has a higher etch selectivity for the materials of the masks 86 and the gate spacers 88 than for the materials of the gates 84, the STI regions 58, and the silicide regions 92A and 92B. Top surfaces of the gate spacers 88 may be located above or below top surfaces of the gates 84.By etching the masks 86 and the gate spacers 88, an aspect ratio (i.e., a height to width ratio) of openings between adjacent gate stacks may be reduced, which may facilitate later deposition of an interlayer dielectric (such as a first interlayer dielectric 96 described below with reference to FIG. Fig. 14). This reduces device defects and improves device performance.

[0036] In Fig. 14, a first interlayer dielectric (ILD) 96 is formed over the Fig. 13. The first ILD 96 may be made of a dielectric material and may be deposited using a suitable process such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Phosphorus silicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), or the like may be used for the dielectric material. Other insulating materials deposited using a suitable process may also be used. In some embodiments, a contact etch stop layer (CESL) 94 is formed between the first ILD 96 and the silicide regions 92A and 92B, the STI regions 58, the gate spacers 88, and the gates 84. The CESL 94 may comprise a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, or the like that has a lower etch rate than the material of the overlying first ILD 96.

[0037] In Fig. 15, a planarization process, such as CMP, is performed to bring a top surface of the first ILD 96 level with the top surfaces of the gates 84. After the planarization process, the top surfaces of the gates 84, the gate spacer 88, the first ILD 96, and the CESL 94 are level. Accordingly, the top surfaces of the gates 84 are exposed through the first ILD 96 and the CESL 94.

[0038] In Fig. 16, the gates 84 are removed using a suitable etching process to create recesses 102. Portions of the second gate dielectrics 82 in the recesses 102 may also be removed. In some embodiments, only the gates 84 are removed, while the second gate dielectrics 82 remain in and are exposed from the recesses 102. The first gate dielectric 80 in the HV device region 200 may remain relatively unetched. In some embodiments, the gates 84 are removed using an anisotropic dry etch process. For example, the etch process may be a dry etch process using reactive gases in which the gates 84 are selectively etched while the first ILD 96, the gate spacers 88, or the CESL 94 are little or not etched. The recess 102 in the LV device region 100 exposes and / or is disposed over the channel region 87 of the first tray 62.The recess 102 in the HV device region 200 exposes and / or is disposed over the first gate dielectric 80. During removal, the second gate dielectrics 82 may be used as etch stop layers when the gates 84 are etched. After the gates 84 are removed, the second gate dielectrics 82 may optionally also be removed.

[0039] In Fig. 17, gate dielectric layers 104 and gate electrodes 106 for replacement gates are formed. The gate dielectric layers 104 may include one or more layers deposited in the recesses 102, for example, on a top surface of the first well 62, a top surface of the first gate dielectric 80, and on sidewalls of the gate spacers 88. The gate dielectric layers 104 may also be formed to extend along the top surfaces of the first ILD 96, the CESL 94, and the gate spacers 88. In some embodiments, the gate dielectric layers 104 include one or more dielectric layers, such as one or more layers of silicon oxide, silicon nitride, metal oxide, metal silicate, or the like.For example, in some embodiments, the gate dielectric layers 104 comprise an interfacial layer of silicon oxide formed by thermal or chemical oxidation and an overlying high-k dielectric material, such as a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The gate dielectric layers 104 may comprise a dielectric layer having a k value greater than about 7.0. Molecular beam deposition (MBD), ALD, PECVD, and the like may be used as the fabrication method for the gate dielectric layers 104. In embodiments where portions of the second gate dielectrics 82 remain in the recesses 102, the gate dielectric layers 104 may comprise materials of the second gate dielectrics 82 (e.g., SiO2).

[0040] The gate electrodes 106 are deposited over the gate dielectric layers 104 and fill the remaining portions of the recesses 102. The gate electrodes 106 may comprise a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multilayers thereof. Fig. 17, single-layer gate electrodes 106 are illustrated, but the gate electrodes 106 may include any number of cap layers, work function adjustment layers, and fill materials. After filling the recesses 102, a planarization process, such as CMP, may be performed to remove excess portions of the gate dielectric layers 104 and the gate electrodes 106 located above the top surface of the first ILD 96. The remaining portions of the gate electrodes 106 and the gate dielectric layers 104 form replacement gates of the resulting FETs. The gate electrodes 106 and the gate dielectric layers 104 in the LV device region 100, as well as the gate electrodes 106, the gate dielectric layers 104, and the first gate dielectric 80 in the HV device region 200, may be collectively referred to as a "gate stack." The gate stacks may extend along the top surfaces of the channel regions 87 of the first well 62 and the second well 64.

[0041] The gate dielectric layers 104 may be formed simultaneously in the LV device region 100 and the HV device region 200, such that the gate dielectric layers 104 in each region are made of the same materials, and the gate electrodes 106 may also be formed simultaneously, such that the gate electrodes 106 in each region are also made of the same materials. In some embodiments, the gate dielectric layers 104 in each region may be formed using different processes, such that the gate dielectric layers 104 may be different materials, and / or the gate electrodes 106 in each region may be formed using different processes, such that the gate electrodes 106 may be different materials. Different masking steps may mask and expose corresponding regions when different processes are used.

[0042] In Fig. 18, gate masks 110 are formed over the gate stacks. The gate masks 110 may be disposed between opposing portions of the gate spacers 88. In some embodiments, the gate masks 110 may be formed by recessing the gate dielectric layers 104 and the gate electrodes 106 of the gate stacks, forming recesses directly above the remaining portions of the gate stacks and between opposing portions of the gate spacers 88. The gate masks 110, comprising one or more layers of a dielectric material such as silicon nitride, silicon oxynitride, or the like, are then filled into the recesses, and subsequently, a planarization process is performed to remove excess portions of the dielectric material extending above the first ILD 96.

[0043] In addition, Fig. 18, a second ILD 108 is deposited over the first ILD 96. In some embodiments, the second ILD 108 is a flowable layer formed by flowable CVD. In some embodiments, the second ILD 108 is formed from a dielectric material such as PSG, BSG, BPSG, USG, or the like, which may be deposited using a suitable process such as CVD, PECVD, or the like. Later-formed gate contacts (such as gate contacts 130, which will be described later with reference to FIG. Fig. 21A to 21C) may penetrate the second ILD 108 and the gate masks 110 to contact top surfaces of the recessed gate electrodes 106.

[0044] In the Fig. 19A to 19C, a patterned photoresist 112 having openings 114, 116, and 118 is formed over the second ILD 108. Fig. Figure 19C shows a top-down view and reference cross-sections included in the Fig. 19A and Fig. 19B. A cross section A - A' passes through the openings 114 and 116 in a direction perpendicular to the longitudinal axes of the gate stacks, and the sectional views shown in the Fig. 1 to 19A, 20A and 21A are shown along the cross section A - A'. A cross section B - B' is parallel to the cross section A - A' and passes through the openings 118, and the sectional views shown in the Fig. 19B, Fig. 20B and Fig. 21B are shown along the cross section B - B'. As shown in Fig. 19B, the gate stack may extend beyond the STI regions 58 beyond side surfaces of the first well 62 and the second well 64.

[0045] The patterned photoresist 112 may be formed by depositing a photosensitive layer over the second ILD 108 by spin coating or the like. Subsequently, the photosensitive layer may be patterned by exposure to a patterned energy source (e.g., a patterned light source) and development to remove an exposed or unexposed portion of the photosensitive layer, thereby forming the patterned photoresist 112. Openings 114, 116, and 118 are created through the patterned photoresist 112, exposing the second ILD 108. The pattern of the patterned photoresist 112 corresponds to contacts to be formed in the second ILD 108, the first ILD 96, the CESL 94, and the gate masks 110, as described later with reference to FIG. Fig. 21A to 21C.

[0046] The Fig. 19D and Fig. 19E show an etch charging effect that can later be used to etch the second ILD 108, the first ILD 96, the CESL 94, and the gate masks 110 using the patterned photoresists 112 as a mask without overetching and damaging the silicide regions 92A, the source / drain regions 90A, and the gate electrodes 106. In Fig. 19D, a substrate 202 is provided, and a patterned photoresist 204 with openings 206 is formed over the substrate 202. Materials for the substrate 202 may be the same or similar to the materials of the second ILD 108, the first ILD 96, and / or the gate masks 110. In some embodiments, the substrate may be formed from an oxide, such as silicon oxide and the like. The patterned photoresist 204 may be formed from the same or similar materials and using the same methods as those for the patterned photoresist 112. In Fig. 19E, the openings 206 are extended into the substrate 202 while simultaneously using the patterned photoresist 204 as a mask. As in Fig. 19E, as the width of the openings 206 in the patterned photoresist 204 increases, the depth to which the openings 206 extend into the substrate 202 increases. For example, a ratio of a width of each of the openings 206 to a respective depth of the opening 206 may be about 0.02 to about 1. The widths of the openings 114, 116, and 118 may be selected such that the depths of openings (such as openings 120, 122, and 124, which will be described later with reference to FIG. Fig. 20A to 20C) patterned by openings 114, 116, and 118 can be controlled to prevent over-etching of silicide regions 92A, source / drain regions 90A, and gate electrodes 106.

[0047] Let us come to the Fig. 19A to 19C. Openings 114 may be formed with widths W1, openings 116 may be formed with widths W2, and openings 118 may be formed with widths W3. Widths W2 may be greater than widths W1 and W3. In some embodiments, a ratio of widths W2 to widths W1 may be about 1.5 to about 50 or about 1.5 to about 15, and a ratio of widths W2 to widths W3 may also be about 1.5 to about 50 or about 1.5 to about 15. In some embodiments, widths W1 may be equal to or greater than widths W3. In some embodiments, the widths W1 may be about 10 nm to about 100 nm, the widths W2 may be about 15 nm to about 500 nm, and the widths W3 may be about 10 nm to about 100 nm. As described later with reference to the Fig. 20A to 20C, the patterned photoresist 112 can be used as a mask to extend the openings 114, 116, and 118 to expose the silicide regions 92A, the silicide regions 92B, and the gate electrodes 106, respectively. When the openings 114, 116, and 118 are formed with the predetermined widths and relationships, they can be used to control the depth to which the openings 114, 116, and 118 are extended, thereby preventing over-etching of the silicide regions 92A, the source / drain regions 90A, and the gate electrodes 106 while allowing the silicide regions 92B to be exposed. If the openings 116 are formed with widths W2 that are larger than the specified values, an undesirable area penalty may arise, so that larger source / drain regions 90B and silicide regions 92B must be formed, which may reduce the device density.On the other hand, if the openings 116 are formed with widths W2 smaller than the predetermined values, they may not be large enough to prevent over-etching of the silicide regions 92A, the source / drain regions 90A, and the gate electrodes 106, and the device performance may decrease.

[0048] In the Fig. 20A to 20C, the patterned photoresist 112 is used as a mask for etching the second ILD 108, the first ILD 96, the CESL 94, and the gate masks 110, thereby extending the openings 114, 116, and 118 to create openings 120, 122, and 124, respectively. The openings 120 may be etched through the second ILD 108, the first ILD 96, and the CESL 94 in the LV device region 100, and expose the silicide regions 92A. The openings 122 may be etched through the second ILD 108, the first ILD 96, and the CESL 94 in the HV device region 200, and expose the silicide regions 92B. The openings 124 may be etched through the second ILD 108 and the gate masks 110 in the LV device region 100 and the HV device region 200, and expose the gate electrodes 106 in the LV device region 100 and the HV device region 200.The second ILD 108, the first ILD 96, the CESL 94, and the gate masks 110 may be etched using any suitable etching technique, such as reactive ion etching (RIE), neutral beam etching (NBE), or the like, or a combination thereof. The etching processes may be anisotropic.

[0049] Openings 120, 122, and 124 can be etched simultaneously. Because openings 114, 116, and 118 are created in patterned photoresist 112 with predetermined widths W1, W2, and W3, respectively, openings 120, 122, and 124 can be etched simultaneously and can extend to different depths. This allows the silicide regions 92A, silicide regions 92B, and gate electrodes 106 to be exposed without over-etching the silicide regions 92A and gate electrodes 106. This improves device performance and reduces device defects. Furthermore, no further masking processes are required to create openings 120, 122, and 124 with different heights, thus reducing costs.

[0050] The openings 120 may have upper widths W1 that are level with top surfaces of the second ILD 108 and equal to the widths W1 of the openings 114 in the patterned photoresist 112. The openings 120 may have heights H2 of about 50 nm to about 1000 nm and lower widths W1' that are level with the bottom surface of the CESL 94 and are about 10 nm to about 100 nm. The openings 122 may have upper widths W2 that are level with the top surface of the second ILD 108 and equal to the widths W2 of the openings 116 in the patterned photoresist 112. The openings 122 may have heights H3 of about 100 nm to about 1500 nm and bottom widths W2' that are level with the bottom of the CESL 94 and are about 15 nm to about 500 nm. The openings 124 may have top widths W3 that are level with the top of the second ILD 108 and equal to the widths W3 of the openings 118 in the patterned photoresist 112.The openings 124 may have heights H4 of about 50 nm to about 1000 nm and bottom widths W3' that are level with the bottom surfaces of the gate masks 110 and are about 10 nm to about 100 nm. The heights H3 may be greater than the heights H2, and the heights H2 may be greater than the heights H4. In some embodiments, a ratio of the heights H3 to the heights H2 (H3 / H2) may be about 1.5 to about 50, and a ratio of the heights H3 to the heights H4 (H3 / H4) may also be about 1.5 to about 50. In some embodiments, the widths W2' may be equal to or greater than the widths W1'. If the openings 122 are formed with widths W2' that are larger than the widths W1', contact resistances of contacts later formed in the openings 122 can be reduced, thereby improving device performance.

[0051] In the Fig. 21A to 21C, the patterned photoresist 112 is removed, and LV contacts 126, HV contacts 128, and gate contacts 130 are formed in openings 120, 122, and 124, respectively. Fig. Figure 21C shows a top-down view in which the second ILD 108 and the first ILD 96 have been omitted to show the underlying structures. The patterned photoresist 112 may be removed using a suitable stripping process, such as using an oxygen plasma or the like. The LV contacts 126, the HV contacts 128, and the gate contacts 130 are formed by depositing a coating (not individually shown), such as a diffusion barrier layer, an adhesion layer, or the like, in the openings 120, 122, and 124 and then depositing a conductive material over the coating to fill the openings 120, 122, and 124. The coating may comprise titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material can be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel or the like.A planarization process, such as CMP, may be performed to remove excess material from a surface of the second ILD 108. The remaining deposit and conductive material form the LV contacts 126, the HV contacts 128, and the gate contacts 130. The LV contacts 126 are physically and electrically connected to the source / drain regions 90A via the silicide regions 92A. The HV contacts 128 are physically and electrically connected to the source / drain regions 90B via the silicide regions 92B. The gate contacts 130 are physically and electrically connected to the gate electrodes 106. The LV contacts 126, the HV contacts 128, and the gate contacts 130 may be formed in different processes or in the same process.

[0052] The LV contacts 126, the HV contacts 128, and the gate contacts 130 may have the same dimensions as the openings 120, 122, and 124, respectively. For example, the LV contacts 126 may have widths W1, widths W1', and heights H2; the HV contacts 128 may have widths W2, widths W2', and heights H3; and the gate contacts 130 may have widths W3, widths W3', and heights H4. The widths W3 and heights H4 of the gate contacts 130 may be the same in the LV device region 100 and the HV device region 200. Ratios of the widths W1 to the heights H2 may be about 0.01 to about 0.2; Ratios of the widths W2 to the heights H3 may be about 0.01 to about 0.2; and ratios of the widths W3 to the heights H4 may also be about 0.01 to about 0.2.

[0053] Fig. Figure 21D shows the cumulative probability as a function of the contact resistance (Rc) between the HV contacts 128 and the silicide regions 92B. A curve 300 shows an embodiment in which the HV contacts 128 are manufactured with greater widths than the LV contacts 126. A curve 302 shows an embodiment in which the HV contacts 128 are manufactured with widths equal to the widths of the LV contacts 126. As in Fig. As shown in Figure 21D, by fabricating the HV contacts 128 with larger widths, the contact resistance of the HV contacts 128 and the variance of the contact resistance of the HV contacts 128 are reduced. Specifically, the contact resistance for the embodiment represented by curve 300 is at least 15% lower than the contact resistance for the embodiment represented by curve 302. This improves device performance and reduces device defects.

[0054] Embodiments may achieve various benefits. For example, by creating openings 114, 116, and 118 in patterned photoresist 112 with different widths, openings 120, 122, and 124 may be created simultaneously without over-etching silicide regions 92A, source / drain regions 90A, and gate electrodes 106 disposed over silicide regions 92B. This avoids device defects, improves device performance, and reduces the number of masks required to pattern openings 114, 116, and 118, thus lowering costs. In addition, HV contacts 128 may be fabricated with larger widths, reducing contact resistance and further improving device performance.

[0055] The invention is defined by the main claim and the subordinate claim. The subclaims describe further embodiments of the invention.

Claims

[1] Semiconductor device comprising: a first transistor comprising: a first gate stack (80, 104, 106) over a semiconductor substrate (50), the first gate stack having a first height, a first source / drain region (90B) adjacent to the first gate stack (80, 104, 106), a first gate contact (130) electrically connected to the first gate stack (80, 104, 106), wherein a top surface of the first gate contact has a first width (W3), and a first source / drain contact (128) electrically connected to the first source / drain region (90B), wherein a top surface of the first source / drain contact has a second width (W2) that is greater than the first width (W3); and a second transistor having: a second gate stack (104, 106) above the semiconductor substrate (50), the second gate stack having a second height that is smaller than the first height, a second source / drain region (90A) adjacent to the second gate stack (104, 106), and a second source / drain contact (126) electrically connected to the second source / drain region (90A), wherein a top surface of the second source / drain contact has a third width (W1) that is smaller than the second width (W2); wherein the first transistor has a first channel region (87); wherein the second transistor has a second channel region (87); wherein the second gate stack (104, 106) comprises a dielectric material (104) in contact with the second channel region (87); wherein the first gate stack (80, 104, 106) comprises the dielectric material (104) separated from the first channel region (87) by a deposited gate oxide layer (80); wherein an upper surface of the second channel region (87) is arranged at a first distance (H1) above an upper surface of the first channel region (87) in a direction perpendicular to a main surface of the semiconductor substrate (50); and wherein a thickness of the deposited gate oxide layer (80) is equal to the first distance (H1). [2] The semiconductor device according to claim 1, wherein a ratio of the second width (W2) to the first width (W3) is 1.5 to 50 and a ratio of the second width to the third width (W1) is 1.5 to 50. [3] A semiconductor device according to any one of claims 1 or 2, wherein the first width (W3) is equal to the third width (W1). [4] The semiconductor device according to any one of claims 1 to 3, further comprising a second gate contact (130) electrically connected to the second gate stack (104, 106), wherein a width of a top surface of the second gate contact is equal to the first width (W3). [5] A semiconductor device according to any one of claims 1 to 4, wherein a top surface of the first gate stack (80, 104, 106) is level with a top surface of the second gate stack (104, 106). [6] The semiconductor device according to any one of claims 1 to 5, wherein a bottom surface of the first source / drain contact (128) has a fourth width (W2') that is greater than a fifth width (W1') of a bottom surface of the second source / drain contact (126). [7] A semiconductor device according to any one of claims 1 to 6, wherein the top side of the first source / drain contact (128), the top side of the second source / drain contact (126) and the top side of the first gate contact (130) are at the same height, and the first source / drain contact (128) has a first height (H3) that is greater than a second height (H2) of the second source / drain contact (126), the second height being greater than a third height (H4) of the first gate contact (130). [8] Procedure with the following steps: Fabricating a first transistor and a second transistor over a semiconductor substrate (50), the first transistor having a first gate stack (80, 104, 106) and a first source / drain region (90B) adjacent to the first gate stack and the second transistor having a second gate stack (104, 106) and a second source / drain region (90A) adjacent to the second gate stack; forming an interlayer dielectric (96, 108) over the first transistor and the second transistor; depositing a photoresist (112) over the interlayer dielectric (96, 108); Patterning the photoresist (112) to produce a patterned photoresist (112) having a first opening (116) directly above the first source / drain region (90B), a second opening (114) directly above the second source / drain region (90A), and a third opening (118) directly above the first gate stack (80, 104, 106), the first opening having a first width (W2), the second opening having a second width (W1), and the third opening having a third width (W3), the first width (W2) being greater than each of the second width (W1) and the third width (W3); etching the interlayer dielectric (96, 108) using the patterned photoresist (112) as a mask; and Producing a first contact (128) such that it is electrically connected to the first source / drain region (90B), producing a second contact (126) such that it is electrically connected to the second source / drain region (90A), and producing a third contact (130) such that it is electrically connected to the first gate stack (80, 104, 106), wherein the first contact (128) has a first height (H3) which is greater than a second height (H2) of the second contact (126) and a third height (H4) of the third contact (130), respectively; wherein the fabrication of the first transistor and the second transistor comprises recessing a first region (200) of the semiconductor substrate (50) with respect to a second region (100) of the semiconductor substrate, wherein the first transistor is fabricated in the first region and the second transistor is fabricated in the second region; wherein fabricating the first transistor and the second transistor further comprises: forming a gate oxide layer (66) over the first region (200) and the second region (100); Removing the gate oxide layer (66) from the second region (100), wherein the first gate stack (80, 104, 106) has a remaining portion (80) of the gate oxide layer; and wherein a top surface of the remaining portion (80) of the gate oxide layer (66) in the first region (200) is coplanar with a top surface of a channel region (87) of the second transistor. [9] The method of claim 8, further comprising planarizing top surfaces of the first gate stack (80, 104, 106), the second gate stack (104, 106) and the interlayer dielectric (96). [10] The method of claim 8 or 9, wherein forming the first contact (128), the second contact (126), and the third contact (130) further comprises planarizing top surfaces of the first contact, the second contact, the third contact, and the interlayer dielectric (108). [11] Method according to one of claims 8 to 10, wherein the third width (W3) is equal to the second width (W1).

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