METHOD FOR MANUFACTURING A SEMICONDUCER PACKAGE AND SEMICONDUCER PACKAGE

Abstract

A method for producing a semiconductor package (300), comprising: singulating a wafer (101) having a plurality of dies (101D) attached to an auxiliary support (102) to produce dies (101D) having exposed side faces (410); subsequently covering at least the side faces of the dies (101D) with a passivation layer (122) by means of a deposition process at a temperature below the melting temperature of the auxiliary support (102), wherein a gap is maintained between the passivation layer (122) on the side faces of adjacent dies (101D) of the plurality of dies (101D) (420); removing the dies (100) from the auxiliary support (102); and performing at least one backend process penetrating through the passivation layer (122) on the dies (100).

Description

Technical field Several embodiments relate generally to a method for manufacturing a semiconductor package and a die. background Semiconductor power modules are designed to protect semiconductors from electrical, thermal, mechanical, chemical, and environmental influences. Conversely, all components of the power module assemblies are intended to match the semiconductor devices in terms of these influences. Typically, the front-end process chain ends with chips (also called dies) that are mounted on an adhesive tape after a wafer singulation process, such as a separation process. The semiconductor material from the separated semiconductor wafers, e.g., bare silicon, and the front (FSM) and back (BSM) metallization are typically exposed on the chip sidewalls. In a backend assembly process, the chips are removed from the adhesive tape and transferred to a die application process such as sintering or soldering. The unprotected sidewall structure of the chips with defects in the layered structure created by the singulation process can be susceptible to various interactions with backend materials used in subsequent assembly processes. The interactions can include, for example, an effect of (ionic) impurities of package materials on the electrical properties of the chip, chemical reactions of solder components with the silicon of the chip, of potting / mold components with the chip silicon, of housing / potting / mold components with the FSM / BSM (e.g. corrosion), and of course of moisture and / or harmful gases with the FSM / BSM (e.g. corrosion), all of which can lead to chip failure. Furthermore, given the interactions mentioned above, it may be necessary to limit a module temperature, for example activation temperatures in processes / tests. Currently, the problems mentioned above are avoided by using package materials and manufacturing processes that are able to cope with the unprotected chip sidewalls. This means that options for finding the right combination of cost and performance requirements are limited. Furthermore, there is no catalog of known chip-material interactions and determined material specifications. Materials from a second source, particularly regarding potting / mold connections and housings, often contain various, frequently unknown ingredients that may only be known to the supplier, and can therefore pose a high risk of unknown or unexpected chip interactions. Furthermore, some die deposition technologies may not meet limitations on unprotected chip sidewalls; for example, certain solder alloys and corresponding processes may be cost-effective die deposition technologies for high-performance requirements, but pose a risk of chemical reactions with the bare silicon exposed on the chip sidewalls, and solder and sinter pastes may create harmful (e.g., corrosive) environments for unprotected chip sidewalls during processing. There is currently a general trend toward increasing module operating temperatures. This may necessitate new and more complex materials and assembly processes, which currently pose a high risk of negatively impacting chip performance. Studying these interactions can entail a significant development and qualification effort, with substantial implications for the cost and duration of the affected package development projects. DE 10 2016 118 709 B3 discloses a protective device against electrostatic discharge, comprising: a first vertically integrated protective structure against electrostatic discharge, comprising a first semiconductor section, a first contact area arranged on a first side of the first semiconductor section, a first terminal exposed on a second side of the first semiconductor section opposite the first side of the first semiconductor section, and at least two protective structure elements against electrostatic discharge in an antiparallel arrangement; a second vertically integrated protective structure against electrostatic discharge, comprising a second semiconductor section, a second contact area arranged on a first side of the second semiconductor section, a second terminal exposed on a second side of the second semiconductor section opposite the first side of the second semiconductor section.exposed, and has at least two protective structural elements against electrostatic discharge in an antiparallel arrangement, a layer for electrical connection, wherein the first vertically integrated protective structure against electrostatic discharge and the second vertically integrated protective structure against electrostatic discharge are arranged laterally separated from each other on the layer for electrical connection and are electrically connected to each other in an anti-series manner via the layer for electrical connection, wherein the layer for electrical connection is mounted to a support carrier via at least one adhesive layer. US 2014 / 0175623 A1 discloses a semiconductor wafer containing a plurality of semiconductor chips separated by a sawing line. The wafer is mounted on dicing tape. The wafer is singulated by the sawing line to expose side faces of the semiconductor chip. An ESD protection layer is formed over the semiconductor chip and around the exposed side faces of the semiconductor chip. The ESD protection layer can be a metal layer, an encapsulation film, a conductive polymer, a conductive ink, or an insulating layer covered by a metal layer. The ESD protection layer is singulated between the semiconductor chips. US 2005 / 167799 A1 discloses a method for manufacturing a chip- or wafer-based package with passivation layers on virtually all surfaces. The package can be formed by applying a first passivation layer to the passive or back-side surface of a semiconductor wafer.The semiconductor wafer can be attached to a flexible membrane and separated using a wafer saw. After separation, the flexible membrane can be stretched so that the individual semiconductor devices are laterally displaced, largely exposing their side edges. Once the side edges of the semiconductor devices are exposed, a passivation layer can form on the side edges and active surfaces of the devices. A portion of the passivation layer over the active surface of each semiconductor device can be removed to expose the underlying conductive elements. US 2017 / 040272A1 discloses integrated circuits with copper bonding structures and silicon carbon nitride passivation layers, comprising a substrate and a copper bonding structure with a contact surface. The copper bonding structure is located above the substrate. A silicon carbon nitride passivation layer is located on the contact surface. Brief description A method for fabricating a semiconductor package according to claim 1 and a die according to claim 13 are provided. Further embodiments are described in the dependent claims. A method for manufacturing a semiconductor package is provided. The method may include singulating a wafer having a plurality of dies attached to a support to produce dies with exposed side faces, and covering at least the side faces of the dies with a passivation layer by means of a deposition process at a temperature below the melting temperature of the support, leaving a gap between the passivation layers on the side faces of adjacent dies of the plurality of dies. Brief description of the characters In the figures, identical reference numerals generally refer to the same parts across the different views. The figures are not necessarily to scale, with the emphasis instead generally placed on illustrating the principles of the invention. In the following description, various embodiments of the invention are described with reference to the following figures, wherein: Figures 1A to 1C illustrate a method for fabricating a semiconductor package according to various embodiments; Figure 2 shows a schematic cross-sectional view of a die according to various embodiments; Figure 3 shows a schematic cross-sectional view of a die package according to various embodiments; and Figure 4 shows a flowchart of a method for fabricating a semiconductor package according to various embodiments. Description The following detailed description refers to the attached figures, which illustrate specific details and embodiments in which the invention can be practiced. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" is not necessarily to be understood as preferable or advantageous over other embodiments or designs. The word "over" in reference to a deposited material formed "over" a side or surface can be used here to mean that the deposited material may be formed "directly on," e.g., in direct contact with, the side or surface in question. The word "over" in reference to a deposited material formed "over" a side or surface can also be used here to mean that the deposited material may be formed "indirectly on" the indicated side or surface, with one or more additional layers arranged between the side or surface in question and the deposited material. Various aspects of the disclosure relate to devices, and various aspects of the disclosure relate to processes. It is understood that fundamental properties of the devices also apply to the processes and vice versa. For the sake of brevity, a duplicate description of such properties may therefore have been omitted. According to various embodiments, a method for manufacturing a semiconductor package, e.g., a die package, is provided, which makes it possible to protect the semiconductor (the die) on a wafer level directly after singulation into individual units (dies), and accordingly before a redistribution process (a pick-and-place, for example, onto a leadframe), in particular its sidewalls. The protection can be provided in such a way that the die remains bondable and solderable. According to various embodiments, surface passivation and die sidewall protection are provided by applying a surface coating after wafer singulation (e.g., cutting) without reconstitution (i.e., changing the arrangement of chips on the tape or transferring them to another tape). In other words, passivation can be performed at a transition between front-end and back-end processing of the die. The passivation layer can be designed so that it does not add any electrical function to the wafer, but rather provides protection against chemical interactions with backend materials and environmental influences. Depending on the specific embodiment, coated die sidewalls can offer various improvements with respect to die material (e.g., die package material) and / or die-environment interactions. For example, coated die sidewalls can enable the use of new materials and processes (diffusion brazing, new brazing alloys, and insulating materials), simplify the introduction of materials from a secondary source, and increase resistance to moisture and harmful gases (e.g., H₂S). Additionally, protecting large areas of the front-side metallization can be advantageous for applications in harsh environments (high humidity, harmful gases). Figures 1A to 1C illustrate a method for fabricating a semiconductor package 300, e.g., a die package, according to various embodiments. Figure 2 shows a schematic cross-sectional view of a die 100 according to various embodiments, and Figure 3 shows a schematic cross-sectional view of a die package 300 according to various embodiments. The last die 100 has a passivation layer 122. Parts of the wafer 101 that form the base of one of these last dies 100 are designated as dies 101D. A starting point for forming the semiconductor, e.g., the die 100 according to various embodiments, can be a semiconductor wafer 101, which can have a plurality of dies 101D, each of which can have at least one semiconductor device, integrated circuit, or the like. The semiconductor wafer 101 can have a semiconductor material 112, for example, silicon, gallium arsenide, silicon carbide, or any other suitable semiconductor material. According to various embodiments of the semiconductor wafer 101, a front face metallization 104 can further be formed on a first main surface of the semiconductor material 112 of the semiconductor wafer 101, and / or a back face metallization 110, formed on a second main surface of the semiconductor material opposite the first main surface. The semiconductor wafer 101 can be attached to an auxiliary support 102 with its first main surface or with its second main surface, e.g. to an adhesive strip, for example to a polymer adhesive strip. The auxiliary support 102 can have a melting temperature of approximately 150°C, for example of at least 150°C. The semiconductor wafer 101 can be divided according to various embodiments, e.g. by forming trenches 109 between adjacent dies 101D, into a plurality of dies 101D, thereby exposing side surfaces 106 of the dies 101D. According to various embodiments, the grooves 109 can extend completely through the wafer 101 to the support carrier 102. According to other embodiments, the grooves 109 can extend only partially through the wafer 101, for example, through the front-side metallization 104 or the back-side metallization 110, if present, which may be arranged to point away from the support carrier 102, and, at least predominantly, through the semiconductor material 112. Optionally, the grooves 109 can also extend through the other side of the front-side metallization 104 and the back-side metallization 110, if present, which may be attached to the support carrier 102. In other words, prior to passivation, a complete separation (on a stretched film and on an unstretched film as the support 102) or a partial separation of the back or front of adjacent dies 101D or any combination of the separation processes can be applied. According to various embodiments, the trenches 109 can be deep enough to ensure that, after the protective treatment described in more detail below and subsequent final singulation of the dies 100, no vulnerable area remains unprotected on the chip side faces 106. For example, only the front face metallization 104 or the back face metallization 110, which may have remained at least partially intact after dicing, may be partially exposed on the side face 106 of each die 100, but no area of ​​the semiconductor material 112 may be exposed. According to another example, only the first face face of the wafer 101 may have formed the front face metallization 104 on it, and the semiconductor material 112 may be attached to the support carrier 102. The singulation can be performed as a dice-before-grind process.In other words, singulation and the protective treatment yet to be described can be applied, and the final separation of the individual Dies 100 can be achieved by rearranging them on a second support and subsequent grinding until the trenches 109 are exposed. According to various embodiments, the Dies 101D can be completely separated from their neighboring Dies 101D before the protective treatment is carried out. Any method used in engineering to form the trenches 109, which have a width of at least 10 µm, can be suitable for singulation, for example such that a distance between all adjacent generated dies 101D of the majority of dies 101D is in a range of about 10 µm to about 50 µm, for example separation methods such as sawing, laser cutting, or (e.g. plasma) etching. According to various embodiments, a singulation process can be used which involves forming a singulation area and subsequently stretching (optionally bending) the auxiliary carrier 102, which can increase the distance between adjacent dies 101D, for example stealth dicing using a laser, as long as the stretching makes it possible to space the adjacent dies apart by at least about 10 µm. After the singulation process, the dies 101D may still be attached to the support carrier 102. On their side surfaces 106, one or more materials may be exposed, for example, the semiconductor material 112, and optionally the first metallization 104, the second metallization 110, one or more layers of additional semiconductor material that may have been placed on the wafer 101, layers of insulating material, etc. According to various embodiments, the method can further include covering at least the side faces 106 of the dies 1101D with a passivation layer 122 using a deposition process. The region of the passivation layer 122 formed on the chip side faces 106 is referred to as the passivation layer 108, and an optional region of the passivation layer 122 formed on the main face of the dies 101D, facing away from the support carrier 102, can be referred to as the passivation layer 120. According to various embodiments, once the passivation layer 122 is formed, it can be formed together with the passivation layer 108, in other words, in a common process. The passivation layer 122 can be formed at a temperature below the melting temperature of the auxiliary support 102. Furthermore, the passivation layer 122 can be formed such that a gap with a width G is maintained between the passivation layers 108 on the side surfaces of the majority of dies 100. According to various embodiments, the thickness of the passivation layer 122 can be selected such that it allows the at least one backend process to penetrate the passivation layer 122. The thickness of the passivation layer 122 can, for example, be in a range of approximately 1 nm to approximately 50 nm, approximately 5 nm to approximately 30 nm, approximately 5 nm to approximately 20 nm, approximately 1 nm to 10 nm, or less than 10 nm. The deposition process can be carried out according to various embodiments at a temperature below approximately 150 °C. On the one hand, this can ensure that the deposition temperature is below the melting temperature of the auxiliary carrier 102 for many materials that can be used as the auxiliary carrier 102, e.g., a typical polymer adhesive tape. The deposition process may include or consist of atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), pulsed atomic layer deposition (pulsed ALD), pulsed atomic layer chemical vapor deposition (pulsed AL-CVD), and / or metal-organic chemical vapor deposition (MOCVD) to form the passivation layer.122 Atomic layer deposition (ALD) and plasma-enhanced chemical vapor deposition (PECVD) technology may be particularly suitable for realizing the low-temperature implementation examples, as these techniques can cope with process temperatures of less than 150°C. For example, a thin silicon dioxide (SiO2) sidewall coating 108 can be produced on the sidewalls 106 of the dies 101D (and optionally also the top surface coating 120 on the uppermost surface of the dies 101D) using hexamethyldisiloxane (HMDSO) in a PECVD coating process. By using an auxiliary carrier 102 with a thermal stability of at least approximately 150°C (e.g., a melting point above 150°C), thermal ALD processes are also possible, for example, for depositing an aluminum oxide (Al2O3) passivation layer 122. For passivation of a back side of the die 100 (e.g., wafers 101 mounted with their top side after back grinding and pre-sawing), a solderable passivation layer 122, formed by the low-temperature deposition of Al2O3, can be provided. According to various embodiments, different types of thin-film passivation layers 122 (oxides, fluorides, nitrides, metals and more) can be produced in an ALD process, depending on the precursor material. For low-voltage dies 100 (small, thin geometry), the more cost-effective and faster PECVD can be used. Low-voltage applications (<1.2 kV) tend to exhibit reduced chip-material interactions compared to high-voltage applications (>>1.2 kV). Accordingly, the reduced aspect ratio capabilities of PECVD may be sufficient for coating the relatively low sidewalls 106 (with a height of less than 100 µm), and although the passivation layer 122 formed by PECVD may have a higher defect density, this may still be sufficient to achieve the desired advantages in the low-voltage range. PEALD processes, in particular, can be suitable for providing low-temperature deposition of high-quality thin films (e.g., with a thickness of less than about 10 nm), which can be used as or for the passivation layer 122. Precursors for plasma-enhanced low-temperature ALD are available for most suitable materials, such as Al2O3, TiO2, SiO2, Ta2O5, ZrO2, and any combinations of these materials. According to various embodiments, the passivation layer 122 can be a stack of layers comprising a plurality of individual layers, which together can have a thickness in the range of about 1 nm to about 50 nm. The passivation layer 122 can, according to various embodiments, comprise or consist of an oxide, for example, aluminum oxide, titanium oxide, silicon oxide, tantalum oxide, and zirconium oxide, a fluoride, a nitride, and / or a metal. The metal can be used in designs where it is ensured that the metal passivation layer 122 does not create an electrically conductive path between the front-side metallization 104 and the back-side metallization 110. For example, the metal passivation layer 122 can be used when only one of the metallizations 104, 110 is formed in the die 100, or in a layer stack 122 that has an insulating layer beneath the metal layer. According to the invention, the method includes the execution of at least one backend process for the dies 100, which have the covered side surfaces 106. According to the invention, the passivation layer 122 is thin enough to allow the backend process to be carried out through it. For example, a bonding process with a thick wire can be performed on the front-side metallization 104 or on the back-side metallization 110 through a cutout in the passivation layer 122 created during the wire bonding process. For example, the wire 320 shown in Fig. 3 can be bonded to the front-side metallization 104 through the passivation layers 120, 122 without a special process for exposing the front-side metallization 104. The at least one backend process can include an adhesion process (e.g., an adhesive process), a sintering process, a soldering process, and / or a bonding process. The backend process itself can be carried out essentially as known in the prior art. According to the invention, the semiconductor package 300 comprises the die 100 according to various embodiments, which has a front-side metallization 104 and / or a back-side metallization 110. The semiconductor package 300 further comprises encapsulation material 322, which encapsulates the die 100, and at least one electrically conductive interconnect structure 320, which is attached to the front-side metallization 104 (this is shown in the exemplary embodiment in Fig. 3). Alternatively or additionally, the at least one electrically conductive interconnect structure 320 can be attached to the back-side metallization 110 of the die 100. The semiconductor package 300 can further comprise at least one carrier 330 (in Fig. 3, the carrier 330 can comprise a stack of four layers 324, 326, 328, 330) on which the die 100 can be mounted. The carrier 330 can be configured essentially as known in the art. According to various embodiments, the carrier 330 can be at least partially free of the encapsulation material 322. For example, electrical connection structures, such as the carrier layer 324, can be free of the electrically insulating encapsulation material 322. According to various embodiments, the passivation layer 122 can be formed over the front metallization 104 or over the back metallization 110. The other side of the front metallization 104 and the back metallization 110 can be free of the passivation layer 122. Or, more generally, only one of the main surfaces of the die 100 may be covered by the passivation layer 122. This can be a direct result of the formation of the passivation layer 122, which is carried out while the dies 101D are mounted on the auxiliary support 102, and accordingly a result of a simple manufacturing process. According to various embodiments, the at least one electrically conductive connection structure 320 can be attached to the front metallization 104 of the die 100 and / or to the back metallization 110 of the die 100 in an arrangement that penetrates the passivation layer 122. Fig. 4 shows a flowchart 400 of a method for manufacturing a semiconductor package according to various embodiments. The process may include singulating a wafer having a plurality of dies attached to an auxiliary support to produce dies having exposed side faces (410), and covering at least the side faces of the dies with a passivation layer by means of a deposition process at a temperature below the melting temperature of the auxiliary support, leaving a gap between the passivation layers on the side faces of adjacent dies of the plurality of dies (420). Several examples of implementation are illustrated below: Example 1 is a method for manufacturing a semiconductor package. The method may include singulating a wafer having a plurality of dies attached to a support to produce dies with exposed side faces, and covering at least the side faces of the dies with a passivation layer by means of a deposition process at a temperature below the melting temperature of the support, leaving a gap between the passivation layers on the side faces of adjacent dies of the plurality of dies. According to the invention, the subject matter according to Example 1 includes the execution of at least one backend process for the dies which have the covered side surfaces. According to Example 2, the object according to Example 1 or 2 may optionally have the auxiliary support being an adhesive tape. According to Example 4, the item according to one of Examples 1 to 3 may optionally have that the thickness of the passivation layer is chosen to allow the at least one backend process to penetrate the passivation layer. According to Example 5, the item according to one of Examples 1 to 4 may optionally have a passivation layer thickness in the range of about 1 nm to about 50 nm. According to Example 6, the item according to one of Examples 1 to 5 may optionally have the deposition process carried out at a temperature below about 150 °C. According to Example 7, the item according to any one of Examples 1 to 6 may optionally have the deposition process selected from a group of deposition processes consisting of atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), pulsed atomic layer deposition (pulsed ALD), pulsed atomic layer chemical vapor deposition (pulsed AL-CVD), and metal-organic chemical vapor deposition (MOCVD). According to Example 8, the object according to any of Examples 1 to 7 may optionally have the distance between all adjacent generated dies of the majority of dies in a range of about 10 µm to about 50 µm. According to Example 9, the item according to any of Examples 1 to 8 may optionally have that the at least one backend process includes a process selected from a group consisting of an adhesion process (e.g., an adhesive process), a sintering process, a soldering process, and a bonding process. According to Example 10, the article according to any one of Examples 1 to 9 may optionally have a passivation layer that includes or consists of an oxide, a fluoride, a nitride and / or a metal. According to Example 11, the article according to any of Examples 1 to 10 may optionally have a passivation layer comprising or consisting of at least one material selected from the group consisting of aluminium oxide, titanium oxide, silicon oxide, tantalum oxide and zirconium oxide. According to Example 12, the object according to one of Examples 1 to 11 may optionally also have an extension of the auxiliary supports, thereby increasing the distance between adjacent dies before covering the side surfaces of the dies. According to Example 13, the item according to any of Examples 1 to 12 may optionally include singulation by sawing, laser cutting, stealth dicing, dice-before-grinding and / or etching, for example plasma etching. Example 14 is a die. The die can have a die body having a front surface, a back surface and a plurality of side faces, and an atomic layer deposition passivation layer covering the front surface and all side faces, with the back side being free of the atomic layer deposition passivation layer. According to Example 15, the item according to Example 14 may optionally have a passivation layer thickness in the range of about 1 nm to about 50 nm. According to Example 16, the item according to Example 14 or 15 may optionally have a passivation layer that is a low-temperature deposit layer deposited at a temperature below about 150°C. According to Example 17, the article according to one of Examples 14 to 16 may optionally have the passivation layer formed by means of a deposition process selected from a group of deposition processes consisting of atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), pulsed atomic layer deposition (pulsed ALD), pulsed atomic layer chemical vapor deposition (pulsed AL-CVD), and metal-organic chemical vapor deposition (MOCVD). According to Example 18, the article according to any of Examples 14 to 17 may optionally have a passivation layer that includes or consists of an oxide, a fluoride, a nitride and / or a metal. According to Example 19, the article according to any of Examples 14 to 18 may optionally have the passivation layer comprising or consisting of at least one material selected from the group consisting of aluminium oxide, titanium oxide, silicon oxide, tantalum oxide and zirconium oxide. Example 20 is a die package. The die package may include a die according to any of Examples 14 to 19, comprising a front-side metallization and / or a back-side metallization, encapsulation material encapsulating the die, and at least one electrically conductive interconnect structure attached to the front-side metallization of the die and / or the back-side metallization of the die. According to Example 21, the item according to Example 20 may optionally have the passivation layer formed over the front-side metallization or over the back-side metallization. According to Example 22, the article according to Example 21 may optionally have at least one electrically conductive interconnect structure arranged on the front metallization of the die and / or on the back metallization of the die such that it penetrates the passivation layer. Although the invention has been shown and described, particularly with reference to specific embodiments, the person skilled in the art should understand that various modifications in form and detail can be made to it without departing from the spirit and scope of the invention as defined by the accompanying claims. The scope of the invention is therefore specified by the accompanying claims, and all modifications that fall within the meaning and equivalence of the claims are thus to be included.

Claims

A method for producing a semiconductor package (300), comprising: singulating a wafer (101) having a plurality of dies (101D) attached to an auxiliary support (102) to produce dies (101D) having exposed side faces (410); subsequently covering at least the side faces of the dies (101D) with a passivation layer (122) by means of a deposition process at a temperature below the melting temperature of the auxiliary support (102), wherein a gap is maintained between the passivation layer (122) on the side faces of adjacent dies (101D) of the plurality of dies (101D) (420); removing the dies (100) from the auxiliary support (102); and performing at least one backend process penetrating through the passivation layer (122) on the dies (100). The method according to claim 1, wherein the auxiliary carrier (102) is an adhesive tape. The method according to claim 1 or 2, wherein the layer thickness of the passivation layer (122) is selected to allow the at least one backend process to penetrate the passivation layer (122). The method according to one of claims 1 to 3, wherein the thickness of the passivation layer (122) is in the range of about 1 nm to about 50 nm. The method according to any one of claims 1 to 4, wherein the deposition process is carried out at a temperature below about 150 °C. The method according to any one of claims 1 to 5, wherein the deposition process is selected from a group of deposition processes consisting of: atomic layer deposition (ALD); plasma-enhanced atomic layer deposition (PEALD); pulsed atomic layer deposition (pulsed ALD); pulsed atomic layer chemical vapor deposition (pulsed AL-CVD); and metal-organic chemical vapor deposition (MOCVD). The method according to any one of claims 1 to 6, wherein the distance between all adjacent generated dies (101D) of the plurality of dies (101D) is in a range of about 10 µm to about 50 µm. The method according to any one of claims 1 to 7, wherein the at least one backend process comprises a process selected from a group consisting of: adhesion process, e.g., adhesive process; sintering process; soldering process; and bonding process. The method of one of claims 1 to 8, wherein the passivation layer (122) comprises or consists of an oxide, a fluoride, a nitride and / or a metal. The method of one of claims 1 to 9, wherein the passivation layer (122) comprises or consists of at least one material selected from the group consisting of: aluminum oxide; titanium oxide; silicon oxide; tantalum oxide; and zirconium oxide. The method of one of claims 1 to 10, further comprising: stretching the auxiliary carriers (102), thereby increasing the distance between adjacent dies (101D), before covering the side surfaces of the dies (101D). A semiconductor package (300) comprising: a die (100) comprising: a die body (112, 104, 110) comprising a front surface, a rear surface and a plurality of side faces (106); a passivation layer (122) completely covering the front surface and all side faces (106), the rear side being exposed and free of the passivation layer (122); a front metallization (104) or a rear metallization (110) beneath the passivation layer (122); at least one electrically conductive interconnect structure arranged at the front metallization (104) or the rear metallization (110) penetrating the passivation layer (122); and encapsulation material (322) encapsulating the die (100). The semiconductor package (300) according to claim 12, wherein the layer thickness of the passivation layer (122) is in the range of about 1 nm to about 50 nm. The semiconductor package (300) according to claim 12 or 13, wherein the passivation layer (122) is a low-temperature deposit layer deposited at a temperature below about 150°C. The semiconductor package (300) according to one of claims 12 to 14, wherein the passivation layer (122) is formed by means of a deposition process selected from a group of deposition processes consisting of: atomic layer deposition (ALD); plasma-enhanced atomic layer deposition (PEALD); pulsed atomic layer deposition (pulsed ALD); pulsed atomic layer chemical vapor deposition (pulsed AL-CVD); and metal-organic chemical vapor deposition (MOCVD). The semiconductor package (300) according to any one of claims 12 to 15, wherein the passivation layer (122) comprises or consists of an oxide, a fluoride, a nitride and / or a metal. The semiconductor package (300) according to any one of claims 12 to 16, wherein the passivation layer (122) comprises or consists of at least one material selected from the group consisting of: aluminum oxide; titanium oxide; silicon oxide; tantalum oxide; and zirconium oxide.

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