AVALANCHE PHOTODIODE

Abstract

Structure (10, 10a, 10b) comprising: a substrate material having a trench (16) with sidewalls and a bottom; a first semiconductor material (18, 18a) lining the sidewalls and bottom of the trench (16); a photosensitive semiconductor material (20) arranged on the first semiconductor material (18, 18a); and a second semiconductor material (22, 22a) forming a plug in the center of the photosensitive semiconductor material (20) and extending on an upper surface of the photosensitive semiconductor material (20).

Description

FIELD OF THE INVENTIONThe present disclosure relates to semiconductor structures, and more particularly to avalanche photodiodes and fabrication methods.BACKGROUNDAn avalanche photodiode (APD) is a highly sensitive semiconductor photodiode that utilizes the photoelectric effect to convert light into electricity. From a functional point of view, the avalanche photodiode can be considered as the semiconductor analog for photomultipliers. Typical applications for avalanche photodiodes are long range fiber optic communication and quantum sensing for control algorithms. More recent applications include positron emission tomography and particle physics.The applicability and usefulness of an avalanche photodiode depends on many parameters. Two factors are, for example, quantum efficiency and total leakage. Quantum efficiency indicates how well incident optical photons are absorbed and then used to generate primary charge carriers; while the total leakage current is the sum of dark current, photocurrent, and noise.The sensitivity of a photodiode is dependent on the length of the light path through the photosensitive material and the ability of carrier pairs produced to reach the electrode / contact / cathode. In conventional structures, the beams move in a two-dimensional path, e.g., vertically or laterally, resulting in a long path. Due to the longer lanes of conventional avalanche photodiodes, there is a high frequency of photon recombination within the photosensitive material, resulting in signal loss or attenuation of the signal itself. In addition, the photosensitive material itself must be very thick, which is expensive and time consuming to grow and which makes integration with other circuit elements increasingly challenging. US 2015 / 0 097 256 A1 discloses an avalanche photodiode comprising a substrate having a trench, a first semiconductor material in the trench, a photosensitive semiconductor material completely filling the trench and an overlying second semiconductor material.SHORT TEAR-OFFIn one aspect of the disclosure, a structure includes: a substrate material having a trench with sidewalls and a bottom; a first semiconductor material lining the sidewalls and the bottom of the trench; a photosensitive semiconductor material disposed on the first semiconductor material; and a second semiconductor material forming a plug at the center of the photosensitive semiconductor material and extending on an upper surface of the photosensitive semiconductor material.In one aspect of the disclosure, a structure includes: a semiconductor substrate; a trench formed in the semiconductor substrate, the trench having sidewalls and a bottom; a first semiconductor material having a first dopant type lining the sidewalls and the bottom of the trench; an intrinsic photosensitive semiconductor material contacting the first semiconductor material; a second semiconductor material having the first dopant type and being in the trench and contacting the intrinsic photosensitive semiconductor material, the second semiconductor material forming a plug at the center of the photosensitive semiconductor material; and an isolation structure including reflective material surrounding the trench and spaced apart from the intrinsic photosensitive semiconductor material.In one aspect of the disclosure, a method includes: forming a trench in a substrate; providing a liner of a first semiconductor material on sidewalls and a bottom of the trench; forming an undoped photosensitive material on the first semiconductor material within the trench; forming a second semiconductor material within a remaining trench portion at the center of the undoped photosensitive material and partially on a top surface of the photosensitive material, the second semiconductor material forming a plug at the center of the photosensitive semiconductor material; and forming trench structures with reflective material in the substrate adjacent the liner of the first semiconductor material and spaced apart from the photosensitive material.BRIEF DESCRIPTION OF THE DRAWINGSThe present disclosure will be described in the following detailed description with reference to the above-mentioned plurality of drawings by way of non-limiting examples of exemplary embodiments of the present disclosure. FIG. 1 illustrates a substrate having a trench, among other features, and respective fabrication processes, in accordance with aspects of the present disclosure. FIG. 2 illustrates a semiconductor material lining both a bottom surface and sidewalls of the trench, among other features, and respective fabrication processes in accordance with aspects of the present disclosure. FIG. 3 illustrates additional semiconductor materials in the trench used to form a photodiode and respective fabrication processes in accordance with aspects of the present disclosure. FIG. 4 illustrates a shallow trench isolation structure around the photodiode and respective fabrication processes, in accordance with aspects of the present disclosure. FIG. 5 illustrates a carrier path in the photodiode in accordance with aspects of the present disclosure. FIGS. 6A and 6B show various forms of the photodiode in accordance with aspects of the present disclosure. FIG. 7 illustrates contact formation to the photodiode, among other features, and respective fabrication processes, in accordance with aspects of the present disclosure. FIG. 8 illustrates a photodiode in accordance with additional aspects of the present disclosure. FIG. 9 illustrates a photodiode in accordance with still additional aspects of the present disclosure. FIGS. 10A and 10B show various arrays of photodiodes in accordance with aspects of the present disclosure. FIG. 11 is a comparison graph showing responsiveness of the photodiodes of the present disclosure and conventional systems in which the photon path is only two-dimensional, e.g., from top to bottom (vertical) or from one side to another side (lateral).DETAILED DESCRIPTIONThe present disclosure relates to semiconductor structures, and more particularly to avalanche photodiodes and fabrication methods. More particularly, the present disclosure is directed to structures and methods for forming concentrically shaped (or otherwise shaped) avalanche photodiodes. Advantageously, the avalanche photodiodes described herein have an increased sensitivity due to a particular shape factor, e.g. circular, in addition to a dense packing of cells and an improved reflection. In addition, the avalanche photodiodes may be integrated with other devices using established / existing processes.In more specific embodiments, the avalanche photodiodes are formed in a trench having sidewalls and a bottom composed of an exposed semiconductor material. A semiconductor material, such as silicon, is provided along the sidewalls and the bottom of the trench to increase the growth of a photosensitive material, e.g., a germanium (Ge) layer, compared to having oxide on the sidewalls that inhibits the growth of a Ge material on the sidewalls. That is, in the structures presented herein, a Ge layer is grown from both a bottom and sidewalls of the trench, rather than just from the bottom of the trench.In embodiments, by implementing the structures herein, layered epitaxial growth (versus a solid Ge mass) may be used to create a shorter three-dimensional (3D) path for generated carriers (versus a strictly linear path), thereby reducing the risk of carrier recombination prior to detection. In further embodiments, a poly film stack is grown inside the trench in layers from the bottom and the outside with a P+ plug in the center of the structure to provide biasing for the operation of the avalanche diode.The avalanche photodiodes of the present disclosure may be fabricated in a number of ways using a number of different tools. Generally, however, the methodologies and tools are used to form structures having dimensions on the micrometer and nanometer scale. The methodologies, i.e., technologies, used to fabricate the avalanche photodiodes of the present disclosure have been adopted from integrated circuit (IC) technology. For example, the structures are fabricated on wafers and realized in films of material that are patterned onto the top of a wafer by photolithography processes. In particular, the fabrication of avalanche photodiodes uses three basic building blocks: (i) deposition of thin films of material on a substrate, (ii) deposition of a patterned mask on top of the films by photolithography imaging, and (iii) etching the film selectively with respect to the mask.FIG. 1 illustrates a substrate having a trench, among other features, and respective fabrication processes, in accordance with aspects of the present disclosure. In particular, the structure 10 comprises a substrate 12. In embodiments, the substrate 12 is preferably a Si material, although other semiconductor materials are contemplated herein. For example, the substrate 12 may be composed of any suitable material including SiC, GaAs, InAs, InP, and other III / V or II / VI compound semiconductors. In preferred embodiments, the substrate 12 is an N-type substrate composed of a single semiconducting material, such as bulk silicon; although, as described with reference to FIG. 9, the substrate 12 may be, for example, a P-type substrate.A hard mask 14 is deposited on the substrate 12. In embodiments, the hard mask 14 may be a nitride or other hard mask material as is known in the art, so no further explanation is required for a complete understanding of the present disclosure. The hard mask 14 may be deposited by known deposition methods, such as, for example, a chemical vapor deposition (CVD) process. The hard mask 14 prevents epitaxial growth of a semiconductor material on a surface of the substrate 12 in subsequent processes.Referring still to FIG. 1, a trench 16 is formed in the substrate 12 using conventional lithography and etching processes known to those skilled in the art. In a non-limiting example, trench 16 may have a depth of about 2.5 μm (although other dimensions are contemplated herein). In forming the trench 16, a resist formed over the hard mask 14 is exposed to energy (light) to form a pattern (opening). A selective chemical etch process, e.g., reactive ion etching (RIE), is used to form one or more trenches 16 in the substrate 12 through the hard mask 14 and openings of the resist. As described with reference to FIGS. 6A and 6B, the trench 16 may have many different configurations, e.g., round, square, etc. HF (hydrofluoric acid) cleaning may follow the etching process to remove contaminants from the surfaces of the trench 16, thereby ensuring a clean surface of an exposed semiconductor material of the bottom surface and sidewalls of the trench 16. The resist may be removed by a conventional oxygen ashing process or other known stripping agents.Due to the selectivity of the chemicals during the etching process, the substrate 12 may be etched laterally under the hard mask 14, relative to the opening of the hard mask 14. By having the lateral recess, an overhang 16 aof the hard mask 14 is formed over the trench 16. The overhang 16a pints dislocations, maintains a separation between materials, avoids pinch-off (pinch-off), and improves epitaxial growth in subsequent processes.In FIG. 2, a semiconductor material 18 is grown on both the bottom surface and the sidewalls of the trench 16, under the overhang 16 a. In embodiments, the semiconductor material 18 is a liner formed by a selective epitaxial growth process that starts from the exposed semiconductor material on both the sidewalls and the bottom surface of the trench 16. The semiconductor material 18 may be grown in ring-shaped rings as an example. As should be understood by those of ordinary skill in the art, the hard mask 14 prevents growth of the semiconductor material on a surface of the substrate 12 outside of the trench 16. the semiconductor material 18 is a P-type semiconductor material that is preferably composed of the same material as the substrate 12, e.g., Si. In alternative embodiments, the semiconductor material 18 may be a different material, such as SiGe.As shown in FIG. 3, an additional semiconductor material 20 is selectively grown on the semiconductor material 18. In embodiments, the additional semiconductor material 20 is an intrinsic photosensitive semiconductor material (undoped) formed by an epitaxial growth process. The semiconductor material 20 is preferably a Ge material to provide excellent responsiveness, and is thicker than the liner composed of the semiconductor material 18. In alternative embodiments, the semiconductor material 20 may be Si, SiGe, etc. A semiconductor material 22 is then grown in the remaining portions of the trench 16, over the semiconductor material 20. The semiconductor material 22 also grows on the upper exposed surface of the semiconductor material 20. the semiconductor material 22 is preferably the same material as that of the semiconductor material 18.In embodiments, the semiconductor material 22 is a P+ plug at the center of the structure to provide biasing for the operation of the avalanche photodiode. In this way, an N-P-I-P photodiode 25 can be formed. In particular, the P+ material, e.g., semiconductor material 22, in the center of photodiode 25 and the P+ material (e.g., semiconductor material 18) on the sides and bottom of the SiGe material (e.g., semiconductor material 20) create an avalanche photodiode (APD) biased in three dimensions, which increases the likelihood of a signal being collected prior to carrier recombination.In FIG. 4, the hard mask is now removed by a selective etching process. In embodiments, the hard mask removal leaves a space "x" between the semiconductor material 22 and an edge of the trench 16 (e.g., photodiode 25). A shallow trench isolation structure or deep oxide filled / lined trench 24 is formed around the now filled trench 16 (e.g., photodiode 25). In embodiments, the shallow trench isolation structure or deep oxide filled / lined trench 24 should be spaced apart from the intrinsic material, e.g., Ge material 20, to avoid damage to these materials, and thus reduce any potential for trapping photons. Also, the shallow trench isolation structure or deep oxide filled / lined trench 24 may have different depths, including below the depth of the trench 16 (e.g., photodiode 25), depending on the performance parameters.The shallow trench isolation structure or deep oxide filled / lined trench 24 may be fabricated by conventional lithography, etching and deposition techniques. For example, a resist formed over the substrate 12 and the photodiode 25 is exposed to energy (light) to form a pattern (opening). An etching process with a selective chemical, e.g., RIE, is used to form one or more trenches in the substrate 12, on the side of the photodiode 25. Following removal of the resist, an insulator material (e.g., an oxide) may be deposited by any conventional deposition process, e.g., CVD processes. Any residual material on the surface of the substrate 12 may be removed by conventional chemical mechanical polishing (CMP) processes.As representatively shown in FIG. 5, photons enter photodiode 25 and create carriers in the intrinsic material that move through intrinsic semiconductor material 20 (e.g., Ge material) to semiconductor material 18 on all sides (e.g., as shown by the arrows). In this way, the photodiode 25 has a three-dimensional current flow. By having the three-dimensional current flow, the carrier path to the substrate 12 or, more specifically, through the semiconductor material (p-material) 18 to the substrate (N-type material) 12 is much shorter (compared to known photodiodes having a path from top to bottom), because the intrinsic semiconductor material 20 is surrounded at its sides and bottom by the semiconductor material 18. And by having a shorter path, the carriers are less likely to recombine, resulting in a loss of signal strength.Also, the shallow trench isolation structure or deep oxide filled / lined trench 24 acts as a reflector or mirror to prevent the light from entering the substrate 12 on the trench side; instead, they effectively push any light (photons) toward the liner 18 and into the substrate 12.FIGS. 6A and 6B show various cross-sectional shapes of the photodiode 25. for example, in FIG. 6A, the cross-sectional profile of the photodiode 25 is circular (columnar); whereas in FIG. 6B, the cross-sectional profile of the photodiode 25 is quadrilateral (e.g., square). However, it should be understood that other profiles are also contemplated herein, such as, but not limited to, rods, rectangle, oval, octagon, etc.FIG. 7 shows contact formation to the photodiode, among other features, and respective manufacturing processes. In FIG. 7, a semiconductor material 26, e.g., polysilicon, is formed on the top surface of photodiode 25. The semiconductor material 26 acts as a contact to the top of the semiconductor material 26 (e.g., P+ plugs of photodiode 25). In particular, the semiconductor material 26 provides a driving current to the photodiode 25 to bias the plug 22 and drive carriers from the center of the photodiode (e.g., semiconductor material 20) to the outside of the photodiode 25 (e.g., liner of the semiconductor material 18). In this way, the driving current effectively amplifies the signal.A film 28, e.g., a nitride or other hard mask material, covers or isolates the semiconductor material 26 to prevent a silicide from forming on the top surface of the photodiode 25. The un silicided top surface provides optimal performance under front side illumination of photodiode 25.A silicide contact 30 is formed on an exposed surface of the substrate 12, on one side of the photodiode 25. As should be appreciated by those skilled in the art, the silicide process begins by depositing a thin transition metal layer, e.g., nickel, cobalt, or titanium, over the semiconductor material of the substrate 12. Following the reaction, any remaining transition metal is removed by chemical etching, leaving silicide contacts 30.Still referring to FIG. 7, an inter-level dielectric material (e.g., an oxide) 32 is deposited over the structure. A trench is formed in the inter-level dielectric material (e.g., an oxide) 32 that aligns with and exposes a top surface of the silicide contact 30. The trench is formed by conventional lithography and etching processes as already described herein. The trench is filled with a metal material, e.g., tungsten, to form a contact 34. As should be apparent to those skilled in the art, contact 34 is used to detect the current generated by the photons striking photodiode 25 (e.g., a semiconductor material 20 of photodiode 25).FIG. 8 illustrates a photodiode in accordance with additional aspects of the disclosure. In particular, in the structure 10 aof FIG. 8, a silicide contact 30 is formed directly on an upper surface of the photodiode 25, e.g., a semiconductor material 22. This arrangement is suitable for backlighting. Thereafter, a contact 34 is formed to the silicide contacts 30, as described with reference to FIG. 7.FIG. 9 illustrates a photodiode in accordance with additional aspects of the disclosure. In structure 10b of Figure 9, photodiode 25 comprises a different film stack arrangement (e.g., P-I-P-N) compared to that described with reference to Figures 1-8. In particular, the substrate 12 a, the semiconductor material 18 a, and the semiconductor material 22 aare P-type semiconductor materials; whereas the semiconductor material 20 remains an intrinsic semiconductor material (undoped) formed on the semiconductor material 18 aby an epitaxial growth process.However, in this embodiment, the semiconductor material 22 adoes not completely fill the remaining portion of the trench. Instead, an N-type semiconductor material 36 is epitaxially grown on the semiconductor material 22a. Alternatively, the semiconductor material 22 amay be grown to completely fill the remaining portion of the trench, followed by a lithography and etching process to form a trench in a central portion thereof. The trench may then be filled with the N-type semiconductor material 36 by epitaxial growth on the semiconductor material 22 a. A silicide contact 30 is formed directly on an upper surface of photodiode 25, e.g., a semiconductor material 36, with a contact 34 formed to silicide contacts 30, as described with reference to FIG. 7. This arrangement is also suitable for backlighting. It should also be appreciated that front side illumination may also be practiced using this configuration (e.g., using a PolySi contact and without silicided over the detector).FIGS. 10A and 10B show different arrays of photodiodes in accordance with aspects of the present disclosure. In particular, FIG. 10A shows an array of quadrilateral (e.g., square or rectangular) photodiodes 25 and FIG. 10B shows an array of circular photodiodes 25. In addition, it is noted that the array of circular photodiodes 25 are more densely packed together than the quadrilateral (e.g., square or rectangular) photodiodes 25, e.g., 18 photodiodes versus 16 photodiodes.FIG. 11 is a comparative graph showing the responsiveness of the photodiodes of the present disclosure and conventional systems in which the photon path is only two-dimensional, e.g., from top to bottom (vertical) or from one side to another side (lateral). In the graph, the x-axis is the wavelength (μm) and the y-axis is the responsiveness (mA / W). Line "A" represents a photodiode having a Ge material and line "B" represents a photodiode having a Si material, both of which have a three-dimensional (3D) path according to aspects of the disclosure; whereas line "D" represents a photodiode having a Ge material with a trajectory only in the lateral direction and line "C" represents a photodiode having a Ge material with a trajectory only in the vertical direction. As clearly seen from the graph, the responsiveness is greatest for both the photodiode of the lines "A" and "B" at a wavelength of about 0.7 μm. In addition, the Ge implementation shown in line "A" is much better than any other implementation over a wavelength of about 1.5 μm.The avalanche photodiode can be used in a system on chip (SoC) technology. It should be understood by those skilled in the art that SoC is an integrated circuit (also known as a "chip") that integrates all of the components of an electronic system on a single chip or substrate. Since the components are integrated on a single substrate, SoCs consume much less power and take up much less space than multi-chip designs with equivalent functionality. For this reason, SoCs become the dominant force in mobile computing (such as in smartphones) and edge computing markets. SoC is also commonly used in embedded systems and in the Internet of Things.The method(s) described above is(are) used in the manufacture of integrated circuit chips. The resulting integrated circuit chips may be sold by the paver in raw wafer form (i.e., as a single wafer having multiple unpackaged chips), as a bare chip (bare die), or in a packaged form. In the latter case, the chip is mounted in a single chip package (such as a plastic carrier, with conductors attached to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier having one or both surface interconnections or buried interconnections). In either case, the chip is then integrated with other chips, discrete switching elements, and / or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The final product may be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, keyboard, or other input device, and a central processor.

Claims

A structure (10, 10a, 10b) comprising: a substrate material having a trench (16) with sidewalls and a bottom; a first semiconductor material (18, 18a) lining the sidewalls and the bottom of the trench (16); a photosensitive semiconductor material (20) disposed on the first semiconductor material (18, 18a); and a second semiconductor material (22, 22a) forming a plug at the center of the photosensitive semiconductor material (20) and extending on an upper surface of the photosensitive semiconductor material (20).The structure (10, 10a, 10b) of claim 1, further comprising isolation structures (24) extending into the substrate material and surrounding the trench (16) remote from the photosensitive semiconductor material (20).The structure (10, 10a 10b) of claim 2, wherein the isolation structures (24) comprise a reflective material configured to reflect photons into the first semiconductor material (18, 18a) lining the sidewalls and the bottom of the trench (16).The structure (10, 10a, 10b) of claim 1, wherein the photosensitive semiconductor material (20) is an intrinsic semiconductor material.The structure (10, 10a, 10b) of claim 4, wherein the intrinsic semiconductor material is an undoped germanium material.The structure (10, 10a, 10b) of claim 4, wherein the substrate material is an N-type semiconductor material, and the first semiconductor material (18, 18a) and the second semiconductor material (22, 22a) are each a P-type semiconductor material.The structure (10, 10a, 10b) of claim 6, wherein the plug is a P+ plug configured to bias operation of an avalanche photodiode.The structure (19, 10a, 10b) of claim 7, further comprising a fourth semiconductor material (26) on the P+ plug and a masking material (28) over the fourth semiconductor material (26) arranged to prevent silicide formation on the P+ plug.The structure (10, 10a, 10b) of claim 8, wherein the P+ plug comprises un silicided material and a contact (34) is formed on a side of the trench (16) and is configured to electrically contact the substrate (12) for detecting a signal.The structure (10, 10a, 10b) of claim 7, further comprising a silicide (30) and a contact (34) on the P+ plug.The structure (10, 10a, 10b) of claim 3, further comprising a third semiconductor material (36) on the second semiconductor material (22, 22a), all of which are within the trench (16), wherein the substrate material, the first semiconductor material (18, 18a), and the second semiconductor material (22, 22a) are P-type materials, and the third material (36) is an N-type semiconductor material.The structure of claim 11, further comprising a silicide contact (30) and a contact (34) in electrical communication with the N-type semiconductor material.A structure (10, 10a, 10b) comprising: a semiconductor substrate (12, 12a); a trench (16) formed in the semiconductor substrate (12, 12a), the trench (16) having sidewalls and a bottom; a first semiconductor material (18, 18a) having a first dopant type lining the sidewalls and the bottom of the trench (16); an intrinsic photosensitive semiconductor material (20) contacting the first semiconductor material (18, 18a); a second semiconductor material (22, 22a) having the first dopant type and being in the trench (16) and contacting the intrinsic photosensitive semiconductor material (20), the second semiconductor material (22, 22a) forming a plug at the center of the photosensitive semiconductor material (20); and an isolation structure (24) comprising reflective material surrounding the trench (16) and spaced apart from the intrinsic photosensitive semiconductor material (20).The structure (10, 10a, 10b) of claim 13, wherein the semiconductor substrate (12, 12a) comprises an N-type semiconductor material and the first dopant type is a P-type dopant, and further comprising a masking material (28) over the second semiconductor material (22, 22a) configured to prevent silicide formation on the second semiconductor material (22, 22a).The structure (10, 10a, 10b) of claim 13, wherein the semiconductor substrate (12, 12a) comprises an N-type semiconductor material and the first dopant type is a P-type dopant, and further comprising a silicide contact directly on the second semiconductor material (22, 22a).The structure (10, 10a, 10b) of claim 13, further comprising a third N-type semiconductor material (36) directly on the second semiconductor material (22, 22a) within the trench (16), wherein the semiconductor substrate material and the second semiconductor material (22, 22a) are P-type semiconductor materials and the intrinsic photosensitive semiconductor material (20) is an undoped germanium material.The structure (10, 10a, 10b) of claim 13, wherein the intrinsic photosensitive semiconductor material (20) is an undoped germanium material.The structure (10, 10a, 10b) of claim 13, further comprising a silicide contact (30) and a contact (34) in electrical communication with the semiconductor substrate (12).The structure (10, 10a, 10b) of claim 13, wherein the trench (16) is circular or quadrilateral in cross-section.A method comprising: forming a trench (16) in a substrate (12, 12a); providing a liner of a first semiconductor material (18, 18a) on sidewalls and a bottom of the trench (16); forming an undoped photosensitive material (20) on the first semiconductor material (18, 18a) within the trench (16); forming a second semiconductor material (22, 22a) within a remaining trench portion at the center of the undoped photosensitive material (20) and partially on a top surface of the undoped photosensitive material (20), wherein the second semiconductor material (22, 22a) forms a plug at the center of the undoped photosensitive semiconductor material (20); and forming trench structures (24) with reflective material in the substrate (12, 12a) adjacent to the liner of the first semiconductor material (18, 18a) and spaced apart from trench (16), wherein

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