TRANSISTOR GATE STRUCTURES AND METHODS FOR THEIR FORMATION

Abstract

Device comprising: a canal area (68); a dielectric gate layer (112) on the channel area (68); a first work function tuning layer (114A) on the dielectric gate layer (112), wherein the first work function tuning layer (114A) has a p-type work function metal; a barrier layer (114B) on the first output work tuning layer (114A), wherein the barrier layer (114B) comprises amorphous silicon; a second output work tuning layer (114C) on the barrier layer (114B), wherein the second output work tuning layer (114C) comprises an n-type output work metal, the n-type output work metal being different from the p-type output work metal; and a filler layer on the second outlet work adjustment layer (114C).

Description

BACKGROUND

[0001] Semiconductor devices are used in a wide variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a semiconductor substrate, and structuring the various material layers using lithography to create circuit components and elements.

[0002] The semiconductor industry is continuously improving the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, thus enabling the integration of more components within a given area. However, as the minimum sizes of structural elements are reduced, additional problems arise that should be addressed.

[0003] US 2016 / 0365347A1 describes CMOS FinFETs in which multiple gate stack sections are formed within a gate cavity by direct metal gate structuring to provide FinFETs with different threshold voltages. The different threshold voltages are achieved by selectively incorporating metal layers with different work functions in different gate stack sections.US 2014 / 0186030A1 describes a method for fabricating a semiconductor device comprehensively: forming a gate dielectric layer over a substrate; forming a metal-containing layer containing a species for adjusting an effective work function over the dielectric gate layer; forming an antireaction layer over the metal-containing layer; increasing an amount of the species for adjusting the effective work function contained in the metal-containing layer; and forming a gate stack on the substrate by etching the antireaction layer, the metal-containing layer, and the gate dielectric layer.

[0004] US 2020 / 0335602A1 discloses a metal gate (e.g., a replacement metal gate (RMG) for a field-effect transistor (FET)) and a method for fabricating the metal gate. The method includes depositing a conformal dielectric layer to line a gate opening and performing a series of unclustered and clustered conformal metal deposition and beveling processes to selectively adjust the heights of the conformal metal layers within the gate opening. By selectively controlling the heights of the conformal metal layers, the method provides improved overall control of gate height and gate quality, particularly when the metal gate has a small critical dimension (CD) and / or a high aspect ratio (AR).The procedure may also include the use of different etching techniques during the various beveling processes, particularly when different materials and / or different material interfaces are exposed to an etchant to ensure a substantially uniform etch rate of the conformal metal layer(s) concerned in a substantially vertical direction.

[0005] DE 10 2020 128 875 A1 describes a device comprising: a first nanostructure; a second nanostructure above the first nanostructure; a high-k-gate dielectric surrounding the first and second nanostructures, wherein the high-k-gate dielectric has a first section on an upper surface of the first nanostructure and a second section on a lower surface of the second nanostructure; and a gate electrode above the high-k-gate dielectric. The gate electrode comprises: a first work-effect metal surrounding the first and second nanostructures, wherein the first work-effect metal fills a zone between the first section of the high-k-gate dielectric and the second section of the high-k-gate dielectric; and a tungsten layer above the first work-effect metal, wherein the tungsten layer is fluorine-free.

[0006] US 2018 / 0151373 A1 discloses a semiconductor device and a method for its fabrication. In one embodiment, a metal layer is formed over a substrate using a fluorine-free deposition process, a seed layer is formed over the metal layer using a fluorine-containing deposition process, and a filler material is formed to fill an opening and form a gate stack. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of this disclosure are best understood from the detailed description below, which, in accordance with standard industry practices, includes various elements not drawn to scale. In fact, the dimensions of the various elements may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 illustrates an example of a nanostructured field-effect transistor (nano-FET) in a three-dimensional view according to some embodiments. Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7A, Fig. 7B, Fig. 8A, Fig. 8B, Fig. 9A, Fig. 9B, Fig. 9C, Fig. 9D, Fig. 10A, Fig. 10B, Fig. 11A, Fig. 11B, Fig. 12A, Fig. 12B, Fig. 13A, Fig. 13B, Fig. 14A, Fig. 14B, Fig. 15A, Fig. 15B, Fig. 16A, Fig. 16B, Fig. 17A, Fig. 17B, Fig. 18A, Fig. 18B, Fig. 19A, Fig. 19B, Fig. 20A, Fig. 20B, Fig. 21A, Fig. 21B, Fig. 22A and Fig. Figure 22B shows views of the intermediate stages in the fabrication of nano-FETs according to some embodiments. Fig. 23A and Fig. 23B are views of nano-FETs according to some other embodiments. DETAILED DESCRIPTION

[0008] The following disclosure provides many different embodiments or examples of the implementation of various features of the invention. Specific examples of the components and arrangements are described below to simplify the present disclosure. For example, the formation of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are in direct contact, and may also include embodiments in which additional elements are formed between the first and second elements, so that the first and second elements may not be in direct contact. Furthermore, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves the purpose of simplification and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0009] Furthermore, spatially relative terms such as "below," "under," "lower," "above," "upper," and the like may be used herein to simplify the description and to describe the relationship of one element or feature to one or more other elements or features, as illustrated in the figures. It is intended that the spatially relative terms include different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may also be oriented differently (rotated by 90 degrees or other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0010] According to various embodiments, gate electrodes are formed with multiple work function tuning layers. A barrier layer is formed on a lower work function tuning layer, and an upper work function tuning layer is deposited on top of the barrier layer. The barrier layer can be so thin that it does not significantly modify the work function of the gate electrodes and prevents (e.g., substantially prevents or at least reduces) modification of the lower work function tuning layer during the deposition of the upper work function tuning layer. The threshold voltages of the resulting devices can therefore be tuned more precisely.

[0011] The embodiments are described in a specific context, a die containing nano-FETs. However, instead of or in combination with the nano-FETs, various embodiments can be applied to the die, including other types of transistors (e.g., fin field-effect transistors (FinFETs), planar transistors, or the like).

[0012] Fig. Figure 1 illustrates an example of nano-FETs (e.g., nanowire FETs, nanosheet FETs, or the like) according to some embodiments. Fig. Figure 1 is a three-dimensional view in which some features of the nano-FETs have been omitted for clarity. The nano-FETs can be nanosheet field-effect transistors (NSFETs), nanowire field-effect transistors (NWFETs), gate all-around field-effect transistors (GAAFETs), or the like.

[0013] The nanoFETs contain nanostructures 66 (e.g., nanosheets, nanowires, or the like) above fins 62 on a substrate 50 (e.g., a semiconductor substrate), the nanostructures 66 serving as channel regions for the nanoFETs. The nanostructures 66 can be p-type, n-type, or a combination thereof. Insulation regions 70, such as shallow trench insulation regions (STI regions), are arranged between adjacent fins 62, which may project above and from between adjacent insulation regions 70. Although the insulation regions 70 are described / illustrated as separate from the substrate 50, the term "substrate," as used herein, can refer to the semiconductor substrate alone or a combination of the semiconductor substrate and the insulation regions.Furthermore, although a soil section of the fins 62 is illustrated as a single element, continuous materials with the substrate 50, the soil section of the fins 62, and / or the substrate 50 may contain a single material or a variety of materials. In this context, the fins 62 refer to the section that extends across and from between the adjacent isolation areas 70.

[0014] Gate dielectrics 122 are located on the upper surfaces of the fins 62 and along the upper surfaces, side walls, and bottom surfaces of the nanostructures 66. Gate electrodes 124 are located above the gate dielectrics 122. Epitaxial source / drain regions 98 are arranged on the fins 62 on opposite sides of the gate dielectrics 122 and the gate electrodes 124. The epitaxial source / drain regions 98 can be shared by different fins 62. Adjacent epitaxial source / drain regions 98 can be electrically connected, for example, by coalescing the epitaxial source / drain regions 98 through epitaxial growth or by coupling the epitaxial source / drain regions 98 with a common source / drain contact.

[0015] Fig. Figure 1 further illustrates reference cross-sections used in later figures. Cross-section AA' runs along a longitudinal axis of a gate electrode 124 and, for example, in a direction perpendicular to a current flow direction between the epitaxial source / drain regions 98 of a nanoFET. Cross-section BB' runs along a longitudinal axis of a fin 62 and, for example, in a current flow direction between the epitaxial source / drain regions 98 of the nanoFET. Cross-section CC' runs parallel to cross-section AA' and extends through epitaxial source / drain regions 98 of the nanoFETs. For clarity, subsequent figures refer to these reference cross-sections.

[0016] Some of the embodiments discussed herein are explained in the context of nanoFETs fabricated using a gate-last process. In other embodiments, a gate-first process may be used. Some embodiments also consider aspects used in planar devices, such as planar FETs, or in fin field-effect transistors (FinFETs). For example, FinFETs may contain fins on a substrate, with the fins acting as channel regions for the FinFETs. Similarly, planar FETs may contain a substrate, with sections of the substrate acting as channel regions for the planar FETs.

[0017] Fig. Figures 2-22B show views of intermediate stages in the fabrication of nano-FETs according to some embodiments. Fig. 2, Fig. 3, Fig. 4, Fig. 5 and Fig. 6 are three-dimensional views that provide a similar three-dimensional view to Fig. Show 1. Fig. 7A, Fig. 8A, Fig. 9A, Fig. 10A, Fig. 11A, Fig. 12A, Fig. 13A, Fig. 14A, Fig. 14B, Fig. 15A, Fig. 15B, Fig. 16A, Fig. 16B, Fig. 17A, Fig. 17B, Fig. 18A, Fig. 18B, Fig. 19A, Fig. 19B, Fig. 20A, Fig. 21A and Fig. 22A illustrates the in Fig. 1 illustrated reference cross-section A-A'. Fig. 7B, Fig. 8B, Fig. 9B, Fig. 10B, Fig. 11B, Fig. 12B, Fig. 13B, Fig. 20B, Fig. 21B and Fig. 22B illustrate the in Fig. 1 illustrated reference cross-section B-B'. Fig. 9C and Fig. 9D illustrates the in Fig. 1 illustrated reference cross-section C-C'.

[0018] In Fig. 2. A substrate 50 is provided for the fabrication of nanoFETs. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or n-type impurity) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. In general, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide layer (BOX layer), a silicon oxide layer, or the like. The insulating layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multilayer or gradient substrate, may also be used.In some embodiments, the semiconductor material of substrate 50 may contain silicon; germanium; a composite semiconductor containing silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor containing silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium indium arsenide phosphide; combinations thereof; or the like.

[0019] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form n-type devices, such as NMOS transistors, e.g., n-type nanoFETs, and the p-type region 50P can be used to form p-type devices, such as PMOS transistors, e.g., p-type nanoFETs. The n-type region 50N can be physically separated from the p-type region 50P (not shown separately), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be placed between the n-type region 50N and the p-type region 50P. Although only one n-type area 50N and one p-type area 50P are illustrated, any number of n-type areas 50N and p-type areas 50P can be provided.

[0020] Substrate 50 can be lightly doped with a p-type or an n-type impurity. Anti-punch-through (APT) implantation can be performed on an upper portion of substrate 50 to form an APT region. During APT implantation, impurities can be implanted into substrate 50. The impurities can have a conductivity type opposite to that of the source / drain regions subsequently formed in the n-type region 50N and the p-type region 50P, respectively. The APT region can extend below the source / drain regions in the nanoFETs. The APT region can be used to reduce the leakage current from the source / drain regions to substrate 50. In some embodiments, the dopant concentration in the APT region can be in the range of approximately 10 18 cm -3 up to about 10 19 cm -3 lay.

[0021] A multilayer stack 52 is formed on top of the substrate 50. The multilayer stack 52 contains alternating first semiconductor layers 54 and second semiconductor layers 56. The first semiconductor layers 54 are formed from a first semiconductor material, and the second semiconductor layers 56 are formed from a second semiconductor material. The semiconductor materials can each be selected from candidate semiconductor materials of the substrate 50. In the illustrated embodiment, the multilayer stack 52 contains three layers each of the first semiconductor layers 54 and the second semiconductor layers 56. It should be noted that the multilayer stack 52 can contain any number of first semiconductor layers 54 and second semiconductor layers 56.

[0022] In the illustrated embodiment, and as described in more detail later, the first semiconductor layers 54 are removed and the second semiconductor layers 56 are patterned to form channel regions for the nanoFETs in both the n-type region 50N and the p-type region 50P. The first semiconductor layers 54 are sacrificial (or dummy) layers that are removed in subsequent processing to expose the top and bottom faces of the second semiconductor layers 56. The first semiconductor material of the first semiconductor layers 54 is a material exhibiting high etch selectivity for the etching of the second semiconductor layers 56, such as silicon-germanium. The second semiconductor material of the second semiconductor layers 56 is a material suitable for both n-type and p-type devices, such as silicon.

[0023] In another embodiment (not shown separately), the first semiconductor layers 54 are structured to form channel regions for nano-FETs in one region (e.g., the p-type region 50P), and the second semiconductor layers 56 are structured to form channel regions for nano-FETs in another region (e.g., the n-type region 50N). The first semiconductor material of the first semiconductor layers 54 can be a material suitable for p-type devices, such as silicon-germanium (e.g., Si3). x Ge 1-x, where x can be in the range 0 to 1), pure germanium, a III-V composite semiconductor, a II-VI composite semiconductor, or the like. The second semiconductor material of the second semiconductor layers 56 can be a material suitable for n-type devices, such as silicon, silicon carbide, a III-V composite semiconductor, a II-VI composite semiconductor, or the like. The first semiconductor material and the second semiconductor material can exhibit high etch selectivity with respect to each other, such that the first semiconductor layers 54 can be removed without removing the second semiconductor layers 56 in the n-type region 50N, and the second semiconductor layers 56 can be removed without removing the first semiconductor layers 54 in the p-type region 50P.

[0024] Each of the layers of the multilayer stack 52 can be grown by a process such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), and deposited by a process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), or the like. Each of the layers can have a small thickness, such as a thickness in the range of about 5 nm to about 30 nm. In some embodiments, some layers (e.g., the second semiconductor layers 56) are formed thinner than other layers (e.g., the first semiconductor layers 54). In embodiments in which the first semiconductor layers 54 are sacrificial layers (orSince the first semiconductor layers 54 are dummy layers and the second semiconductor layers 56 are structured to form channel regions for the nanoFETs in both the n-type region 50N and the p-type region 50P, the first semiconductor layers 54 can, for example, have a first thickness and the second semiconductor layers 56 can have a second thickness, the second thickness being about 30% to about 60% smaller than the first thickness. Forming the second semiconductor layers 56 to a smaller thickness allows the channel regions to be formed with a higher density.

[0025] In Fig. In 3, trenches are structured in the substrate 50 and the multilayer stack 52 to form fins 62, first nanostructures 64, and second nanostructures 66. The fins 62 are semiconductor strips structured into the substrate 50. The first nanostructures 64 and the second nanostructures 66 contain the remaining portions of the first semiconductor layers 54 and the second semiconductor layers 56, respectively. The trenches can be structured by an acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or a combination thereof. The etching can be anisotropic.

[0026] The fins 62 and the nanostructures 64, 66 can be structured by any suitable method. For example, the fins 62 and the nanostructures 64, 66 can be structured using one or more photolithographic processes, including dual- or multiple-structuring processes. In general, dual- or multiple-structuring processes combine photolithography and self-aligning processes, which makes it possible to create structures with, for example, smaller pitches than can otherwise be achieved using a single, direct photolithography process. In one embodiment, for example, a sacrificial layer is formed and structured over a substrate using a photolithography process. Spacers are formed along the structured sacrificial layer using a self-aligning process.The sacrificial layer is then removed, and the remaining spacers can then be used as masks for structuring the fins 62 and the nanostructures 64, 66. In some embodiments, the mask (or other layer) can remain on the nanostructures 64, 66.

[0027] The fins 62 and the nanostructures 64, 66 can each have widths in a range of approximately 8 nm to approximately 40 nm. In the illustrated embodiment, the fins 62 and the nanostructures 64, 66 have essentially the same widths in the n-type region 50N and the p-type region 50P. In another embodiment, the fins 62 and the nanostructures 64, 66 are wider or narrower in one region (e.g., the n-type region 50N) than the fins 62 and the nanostructures 64, 66 in another region (e.g., the p-type region 50P).

[0028] In Fig. 4. STI regions 70 are formed above the substrate 50 and between adjacent fins 62. The STI regions 70 are arranged around at least one section of the fins 62 such that at least one section of the nanostructures 64, 66 protrudes between adjacent STI regions 70. In the illustrated embodiment, the upper surfaces of the STI regions 70 are coplanar (within process variations) with the upper surfaces of the fins 62. In some embodiments, the upper surfaces of the STI regions 70 lie above or below the upper surfaces of the fins 62. The STI regions 70 separate the features of adjacent devices.

[0029] The STI regions 70 can be formed by any suitable method. For example, an insulating material can be formed over the substrate 50 and the nanostructures 64, 66, and between adjacent fins 62. The insulating material can be an oxide, such as silicon oxide, a nitride, such as silicon nitride, the like, or a combination thereof, formed by a chemical vapor deposition (CVD) process, such as high-density plasma (HDP) CVD, flowable CVD (FCVD), the like, or a combination thereof. Other insulating materials formed by an acceptable process can also be used. In some embodiments, the insulating material is silicon oxide formed by FCVD. After the insulating material has been formed, an annealing process can be carried out.In one embodiment, the insulating material is formed such that excess insulating material covers the nanostructures 64, 66. Although the STI regions 70 are each illustrated as a single layer, some embodiments can utilize multiple layers. In some embodiments, for example, a lining (not shown separately) can first be formed along surfaces of the substrate 50, the fins 62, and the nanostructures 64, 66. Subsequently, a filler material, such as those described above, can be formed over the lining.

[0030] A removal process is then applied to the insulation material to remove excess insulation material over the nanostructures 64, 66. In some embodiments, a planarization process, such as chemical-mechanical polishing (CMP), a back-etching process, combinations thereof, or the like, may be used. In embodiments where a mask remains on the nanostructures 64, 66, the planarization process may expose or remove the mask. After the planarization process, the top surfaces of the insulation material and the mask (if present) or the nanostructures 64, 66 are coplanar (within process variations). Accordingly, the top surfaces of the mask (if present) or the nanostructures 64, 66 are exposed by the insulation material. In the illustrated embodiment, no mask remains on the nanostructures 64, 66.The insulating material is then recessed to form the STI regions 70. The insulating material is recessed such that at least one section of the nanostructures 64, 66 protrudes between adjacent sections of the insulating material. Furthermore, the upper surfaces of the STI regions 70 can have a flat surface, as illustrated, a convex surface, a concave surface (such as curved), or a combination thereof. The upper surfaces of the STI regions 70 can be formed flat, convex, and / or concave by suitable etching. The insulating material can be recessed using any acceptable etching process, such as one that is selective with respect to the insulating material (e.g., that etches the insulating material of the STI regions 70 faster than the materials of the fins 62 and the nanostructures 64, 66). For example, oxide removal can be performed using dilute hydrofluoric acid (dHF).

[0031] The process described above is merely one example of how the fins 62 and the nanostructures 64, 66 can be formed. In some embodiments, the fins 62 and / or the nanostructures 64, 66 can be formed using a mask and an epitaxial growth process. For example, a dielectric layer can be formed over a top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Epitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the epitaxial structures protrude from the dielectric layer to form the fins 62 and / or the nanostructures 64, 66. The epitaxial structures can contain the previously described alternating semiconductor materials, such as the first semiconductor material and the second semiconductor material.In some embodiments where epitaxial structures are grown epitaxially, the epitaxially grown materials can be doped in situ during growth, which can preempt previous and / or subsequent implantations, although in situ and implantation doping can also be used together.

[0032] Furthermore, corresponding wells (not shown separately) can also be formed in the substrate 50, the fins 62, and / or the nanostructures 64, 66. The wells can have a conductivity type that is opposite to the conductivity type of the source / drain regions subsequently formed in the n-type region 50N and the p-type region 50P. In some embodiments, a p-type well is formed in the n-type region 50N and an n-type well is formed in the p-type region 50P. In some embodiments, a p-type well or an n-type well is formed in both, the n-type region 50N and the p-type region 50P.

[0033] In embodiments with different well types, the different implantation steps for the n-type region 50N and the p-type region 50P can be achieved using a mask (not shown separately), such as a photoresist. For example, a photoresist can be formed over the fins 66, the nanostructures 64 and 66, and the STI regions 70 in the n-type region 50N. The photoresist is structured to expose the p-type region 50P. The photoresist can be formed using a spin-on technique and can be structured using acceptable photolithography techniques. After the photoresist has been structured, n-type impurity implantation is performed in the p-type region 50P, and the photoresist can act as a mask to essentially prevent n-type impurities from being implanted into the n-type region 50N.The n-type impurities can be phosphorus, arsenic, antimony, or the like, occurring in concentrations up to approximately 10. 13 cm -3 up to about 10 14 cm -3 It can be implanted. After implantation, the photoresist can be removed, for example by any acceptable ashing process.

[0034] Before or after the implantation of the p-type region 50P, a mask (not shown separately), such as a photoresist, is formed over the fins 62, the nanostructures 64 and 66, and the STI regions 70 within the p-type region 50P. The photoresist is then patterned to expose the n-type region 50N. The photoresist can be formed using a spin-on technique and can be patterned using acceptable photolithography techniques. After the photoresist has been patterned, p-type impurity implantation is performed within the n-type region 50N, and the photoresist can act as a mask to essentially prevent p-type impurities from being implanted into the p-type region 50P. The p-type impurities can be boron, boron fluoride, indium, or the like, which are introduced into the region up to a concentration in the range of approximately 10 13 cm -3 up to about 10 14 cm -3It can be implanted. After implantation, the photoresist can be removed, for example by any acceptable ashing process.

[0035] Following the implantation of the n-type region 50N and the p-type region 50P, a tempering process is performed to repair implantation damage and to activate the implanted p-type and / or n-type impurities. In some embodiments where epitaxial structures for the fins 62 and / or the nanostructures 64, 66 are epitaxially grown, the grown materials can be doped in situ during growth, which may eliminate the need for implantation, although in situ and implantation doping can also be used together.

[0036] In Fig. A dielectric dummy layer 72 is formed on the fins 62 and the nanostructures 64, 66. The dielectric dummy layer 72 can be formed from a dielectric material such as silicon oxide, silicon nitride, a combination thereof, or the like, which can be deposited or thermally grown using acceptable techniques. A dummy gate layer 74 is formed over the dielectric dummy layer 72, and a mask layer 76 is formed over the dummy gate layer 74. The dummy gate layer 74 can be deposited over the dielectric dummy layer 72 and then planarized, for example, by a CMP process. The mask layer 76 can be deposited over the dummy gate layer 74.The dummy gate layer 74 can be formed from a conductive or non-conductive material, such as amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon-germanium (poly-SiGe), a metal, a metal nitride, a metal silicide, a metal oxide, or the like, which can be deposited by physical vapor deposition (PVD), CVD, or the like. The dummy gate layer 74 can be formed from one or more materials that exhibit high etch selectivity with respect to insulating materials, e.g., the STI regions 70 and / or the dielectric dummy layer 72. The mask layer 76 can be formed from a dielectric material, such as silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 74 and a single mask layer 76 are formed over the n-type region 50N and the p-type region 50P.In the illustrated embodiment, the dielectric dummy layer 72 covers the fins 62, the nanostructures 64, 66, and the STI regions 70 such that the dielectric dummy layer 72 extends over the STI regions 70 and between the dummy gate layer 74 and the STI regions 70. In another embodiment, the dielectric dummy layer 72 covers only the fins 62 and the nanostructures 64, 66.

[0037] In Fig. The mask layer 76 is structured using acceptable photolithography and etching techniques to form masks 86. The structure of the masks 86 is then transferred to the dummy gate layer 74 using any acceptable etching technique to form dummy gates 84. The structure of the masks 86 can optionally be further transferred to the dielectric dummy layer 72 using any acceptable etching technique to form dummy dielectrics 82. The dummy gates 84 cover portions of the nanostructures 64, 66 that are exposed during subsequent processing to form channel regions. In particular, the dummy gates 84 extend along the portions of the nanostructures 66 that are structured to form channel regions 68. The structure of the masks 86 can be used to physically separate adjacent dummy gates 84.The dummy gates 84 can also have longitudinal directions essentially perpendicular (within process variations) to the longitudinal directions of the fins 62. The masks 86 can optionally be removed after structuring, for example by any acceptable etching technique.

[0038] Fig. Figure 7A-22B illustrates various additional steps in the manufacturing of embodiment devices. Fig. Figures 7A–13B and 20A–22B illustrate features in either the n-type region 50N or the p-type region 50P. The illustrated structures can, for example, be applied to both the n-type region 50N and the p-type region 50P. Differences (where any) between the structures of the n-type region 50N and the p-type region 50P are described in the text accompanying each figure. Fig. 14A, Fig. 15A, Fig. 16A, Fig. 17A, Fig. 18A and Fig. 19A illustrates features in the p-type range 50P. Fig. 14B, Fig. 15B, Fig. 16B, Fig. 17B and Fig. 19B illustrate features in the n-type range 50N.

[0039] In Fig. 7A and Fig. 7B are formed over the nanostructures 64, 66, on exposed sidewalls of the masks 86 (if present), the dummy gates 84, and the dummy dielectrics 82. Gate spacers 90 can be formed by conformal deposition of one or more dielectric material(s) and subsequent etching of the dielectric material(s). Acceptable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, or the like, which can be formed by a conformal deposition process such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), or the like. Other insulating materials formed by an acceptable process may also be used.In the illustrated embodiment, the gate spacers 90 each contain several layers, e.g., a first spacer layer 90A and a second spacer layer 90B. In some embodiments, the first spacer layers 90A and the second spacer layers 90B are made of silicon oxycarbonitride (e.g., SiO₂). x N y C 1-x-y, where x and y lie in the range 0 to 1) are formed, wherein the first spacer layers 90A are formed from a silicon oxycarbonitride composition similar to or different from that of the second spacer layers 90B. An acceptable etching process, such as dry etching, wet etching, the like, or a combination thereof, can be used to structure the dielectric material(s). The etching can be anisotropic. When etched, the dielectric material(s) exhibit sections on the left side of the dummy gates 84 (thus forming the gate spacers 90). As described in more detail later, when etched, the dielectric material(s) can also exhibit sections on the left side of the fins 62 and / or the nanostructures 64, 66 (thus forming fin spacers 92, see Figure 1). Fig. 9C and Fig. 9D). After etching, the fin spacers 92 and / or the gate spacers 90 may have straight sidewalls (as illustrated) or they may have curved sidewalls (not illustrated separately).

[0040] Furthermore, implantations can be performed to form lightly doped source / drain regions (LDD regions) (not illustrated separately). In embodiments with different device types, similar to the previously described implantations for the basins, a mask (not illustrated separately), such as a photoresist, can be formed over the n-type region 50N while the p-type region 50P is exposed, and corresponding type impurities (e.g., p-type) can be implanted into the fins 62 and / or the nanostructures 64, 66 exposed in the p-type region 50P. The mask can then be removed. Subsequently, a mask (not illustrated separately), such as a photoresist, can be formed over the p-type region 50P while the n-type region 50N is exposed, and corresponding type impurities (e.g.,n-type impurities can be implanted into the fins 62 and / or the nanostructures 66 exposed in the n-type region 50N. The mask can then be removed. The n-type impurities can be any of the n-type impurities described above, and the p-type impurities can be any of the p-type impurities described above. During implantation, the channel regions 68 remain covered by the dummy gates 84, so that the channel regions 68 remain essentially free of the impurity implanted to form the LDD regions. The LDD regions can have an impurity concentration in the range of approximately 10. 15 cm -3 up to about 10 19 cm -3 exhibiting [unclear]. A tempering process can be used to repair implant damage and to activate the implanted impurities.

[0041] It should be noted that the preceding disclosure generally describes a process for forming spacers and LDD regions. Other processes and sequences can also be used. For example, fewer or additional spacers can be used, a different step sequence can be used, additional spacers can be formed and removed, and / or the like. Furthermore, the n-type and p-type devices can be formed using other structures and steps.

[0042] In Fig. 8A and Fig. Source / drain recesses 94 are formed in the nanostructures 64, 66. In the illustrated embodiment, the source / drain recesses 94 extend through the nanostructures 64, 66 and into the fins 62. The source / drain recesses 94 can also extend into the substrate 50. In various embodiments, the source / drain recesses 94 can extend to an upper surface of the substrate 50 without etching the substrate 50; the fins 62 can be etched such that bottom surfaces of the source / drain recesses 94 are located below the upper surfaces of the STI regions 70; or the like. The source / drain recesses 94 can be formed by etching the nanostructures 64, 66 using anisotropic etching processes such as RIE, NBE, or the like.The gate spacers 90 and the dummy gates 84 together mask sections of the fins 62 and / or the nanostructures 64, 66 during the etching processes used to form the source / drain recesses 94. A single etching process can be used to etch each of the nanostructures 64, 66, or multiple etching processes can be used to etch all of them. Timed etching processes can be used to stop the etching of the source / drain recesses 94 once they have reached a desired depth.

[0043] Optionally, internal spacers 96 are formed on the sidewalls of the remaining sections of the first nanostructures 64, e.g., those sidewalls exposed by the source / drain recesses 94. As described in more detail later, source / drain regions are subsequently formed in the source / drain recesses 94, and the first nanostructures 64 are then replaced by corresponding gate structures. The internal spacers 96 serve as insulating features between the subsequently formed source / drain regions and the subsequently formed gate structures. Furthermore, the internal spacers 96 can be used to essentially prevent damage to the subsequently formed source / drain regions by subsequent etching processes, such as those used to later remove the first nanostructures 64.

[0044] To form the inner spacers 96, the source / drain recesses 94 can, for example, be laterally extended. In particular, sections of the sidewalls of the first nanostructures 64, exposed by the source / drain recesses 94, can be recessed. Although the sidewalls of the first nanostructures 64 are illustrated as straight, they can also be concave or convex. The sidewalls can be recessed by any acceptable etching process, such as one that is selective with respect to the material of the first nanostructures 64 (e.g., selectively etching the material of the first nanostructures 64 faster than the material of the second nanostructures 66). The etching can be isotropic.For example, if the second nanostructures 66 are formed from silicon and the first nanostructures 64 are formed from silicon-germanium, the etching process can be a wet etching using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like. In another embodiment, the etching process can be a dry etching using a fluorine-based gas, such as hydrogen fluoride (HF) gas. In some embodiments, the same etching process can be performed continuously to form both the source / drain recesses 94 and the sidewalls of the first nanostructures 64. The internal spacers 96 can then be formed by conformal forming of an insulating material and subsequent etching of the insulating material.The insulating material can be silicon nitride or silicon oxynitride, although any suitable material can be used, such as materials with a low dielectric constant (low k-value) with a k-value less than approximately 3.5. The insulating material can be deposited by a conformal deposition process, such as ALD, CVD, or the like. The etching of the insulating material can be anisotropic. The etching process can be, for example, a dry etch, such as RIE, NBE, or the like. Although the outer sidewalls of the inner spacers 96 are illustrated as being flush with the sidewalls of the gate spacers 90, the outer sidewalls of the inner spacers 96 can extend over the sidewalls of the gate spacers 90 or be recessed from them. In other words, the inner spacers 96 can partially fill, completely fill, or overfill the sidewall recesses.Furthermore, although the side walls of the inner spacers 96 are illustrated as straight, they can also be concave or convex.

[0045] In Fig. 9A and Fig. 9B, epitaxial source / drain regions 98 are formed in the source / drain recesses 94. The epitaxial source / drain regions 98 are formed in the source / drain recesses 94 such that each dummy gate 84 (and corresponding channel regions 68) is arranged between adjacent pairs of epitaxial source / drain regions 98. In some embodiments, the gate spacers 90 and the inner spacers 96 are used to separate the epitaxial source / drain regions 98 from the dummy gates 84 and the first nanostructures 64 by a corresponding lateral distance, so that the epitaxial source / drain regions 98 do not short-circuit with subsequently formed gates of the resulting nanoFETs. A material of the epitaxial source / drain regions 98 can be selected to exert stress in the respective channel regions 68, thereby improving performance.

[0046] The epitaxial source / drain regions 98 in the n-type region 50N can be formed by masking the p-type region 50P. The epitaxial source / drain regions 98 in the n-type region 50N are then formed epitaxially in the source / drain recesses 94 in the n-type region 50N. The epitaxial source / drain regions 98 can comprise any acceptable material suitable for n-type devices. For example, the epitaxial source / drain regions 98 in the n-type region 50N can contain materials that exert a tensile load on the channel regions 68, such as silicon, silicon carbide, phosphor-doped silicon carbide, silicon phosphide, or the like. The epitaxial source / drain regions 98 in the n-type region 50N can be referred to as “n-type source / drain regions”.The epitaxial source / drain regions 98 in the n-type region 50N can have surfaces that are raised from the respective surfaces of the fins 62 and the nanostructures 64, 66 and they can have facets.

[0047] The epitaxial source / drain regions 98 in the p-type region 50P can be formed by masking the n-type region 50N. The epitaxial source / drain regions 98 in the p-type region 50P are then epitaxially grown in the source / drain recesses 94 in the p-type region 50P. The epitaxial source / drain regions 98 can contain any acceptable material suitable for p-type devices. For example, the epitaxial source / drain regions 98 in the p-type region 50P can contain materials that exert a pressure load on the channel regions 68, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, or the like. The epitaxial source / drain regions 98 in the p-type region 50P can be referred to as "source / drain regions of p-type".The epitaxial source / drain regions 98 in the p-type region 50P may have surfaces that are raised from the respective surfaces of the fins 62 and the nanostructures 64, 66 and they may have facets.

[0048] The epitaxial source / drain regions 98, the nanostructures 64, 66, and / or the fins 62 can be doped with impurities to form source / drain regions, similar to the previously described process for forming LDD regions followed by annealing. The source / drain regions can have an impurity concentration in the range of approximately 10 19 cm -3 up to about 10 21 cm -3 exhibiting the following impurities: The n-type and / or p-type impurities for source / drain regions can be any of the impurities described above. In some embodiments, the epitaxial source / drain regions 98 can be doped in situ during growth.

[0049] As a result of the epitaxial processes used to form the epitaxial source / drain regions 98, the upper surfaces of the epitaxial source / drain regions exhibit facets that extend laterally outward beyond the sidewalls of the fins 62 and the nanostructures 64, 66. In some embodiments, these facets cause adjacent epitaxial source / drain regions 98 to merge, as shown in Fig. Figure 9C illustrates this. In some embodiments, adjacent epitaxial source / drain regions 98 remain separated after the epitaxial process is complete, as shown in Fig. Figure 9D illustrates this. In the illustrated embodiments, the spacer etching used to form the gate spacers 90 is discontinued to also form fin spacers 92 on the sidewalls of the fins 62 and / or the nanostructures 64, 66. The fin spacers 92 are formed to cover a portion of the sidewalls of the fins 62 and / or the nanostructures 64, 66 that extend over the STI region 70, thereby blocking epitaxial growth. In another embodiment, the spacer etching used to form the gate spacers 90 is discontinued to not form fin spacers, thus allowing the epitaxial source / drain regions 98 to extend to the surface of the STI region 70.

[0050] The epitaxial source / drain regions 98 can contain one or more semiconductor material layers. For example, each epitaxial source / drain region 98 can contain a liner layer 98A, a main layer 98B, and an end layer 98C (or, more generally, a first semiconductor material layer, a second semiconductor material layer, and a third semiconductor material layer). Any number of semiconductor material layers can be used for the epitaxial source / drain regions 98. Each of the liner layer 98A, the main layer 98B, and the end layer 98C can be formed from different semiconductor materials and can be doped with different impurity concentrations.In some embodiments, the lining layer 98A can have a lower impurity concentration than the main layer 98B, and the end layer 98C can have a higher impurity concentration than the lining layer 98A and a lower impurity concentration than the main layer 98B. In embodiments where the epitaxial source / drain regions 98 contain three semiconductor material layers, the lining layers 98A can be grown in the source / drain recesses 94, the main layers 98B can be grown on the lining layers 98A, and the end layers 98C can be grown on the main layers 98B.

[0051] In Fig. 10A and Fig. 10B A first dielectric intermediate layer (ILD layer) 104 is deposited over the epitaxial source / drain regions 98, the gate spacers 90, the masks 86 (if present), or the dummy gates 84. The first ILD 104 can be formed from a dielectric material that can be deposited by any suitable process, such as CVD, plasma-enhanced CVD (PECVD), FCVD, or the like. Acceptable dielectric materials may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials formed by an acceptable process may also be used.

[0052] In some embodiments, a contact etch stop layer (CESL) 102 is formed between the first ILD 104 and the epitaxial source / drain regions 98, the gate spacers 90, and the masks 86 (if present) or the dummy gates 84. The CESL 102 can be formed from a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, with high etch selectivity with respect to the etching of the first ILD 104. The CESL 102 can be formed by any suitable method, such as CVD, ALD, or the like.

[0053] In Fig. 11A and Fig. In 11B, a removal process is performed to level the upper surfaces of the first ILD 104 with the upper surfaces of the masks 86 (if present) or the dummy gates 84. In some embodiments, a planarization process, such as chemical-mechanical polishing (CMP), a back-etching process, combinations thereof, or the like, may be used. The planarization process may also remove the masks 86 on the dummy gates 84 and sections of the gate spacers 90 along the side walls of the masks 86. After the planarization process, the upper surfaces of the gate spacers 90, the first ILD 104, the CESL 102, and the masks 86 (if present) or the dummy gates 84 are coplanar (within process variations). Accordingly, the upper surfaces of the masks 86 (if present) or the dummy gates 84 are exposed by the first ILD 104.In the illustrated embodiment, the masks 86 remain and the planarization process levels the upper surfaces of the first ILD 104 with the upper surfaces of the masks 86.

[0054] In Fig. 12A and Fig. In 12B, the masks 86 (if present) and the dummy gates 84 are removed in an etching process, forming recesses 106. Sections of the dummy dielectrics 82 in the recesses 106 are also removed. In some embodiments, the dummy gates 84 are removed by an anisotropic dry etching process. The etching process may, for example, include a dry etching process using one or more reactive gases that selectively etches the dummy gates 84 faster than the first ILD 104 or the gate spacers 90. During removal, the dummy dielectrics 82 can be used as etch stop layers when the dummy gates 84 are etched. Then, the dummy dielectrics 82 are removed. Each recess 106 exposes and / or overlays sections of the channel regions 68.Sections of the second nanostructures 66, which serve as the channel regions 68, are arranged between adjacent pairs of the epitaxial source / drain regions 98.

[0055] The remaining portions of the first nanostructures 64 are then removed to enlarge the recesses 106 such that openings 108 are formed in regions 501 between the second nanostructures 66. The remaining portions of the first nanostructures 64 can be removed by any acceptable etching process that selectively etches the material of the first nanostructures 64 faster than the material of the second nanostructures 66. The etching can be isotropic. For example, if the first nanostructures 64 are formed from silicon germanium and the second nanostructures 66 are formed from silicon, the etching process can be a wet etching using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like. In some embodiments, a trimming process (not shown separately) is performed to reduce the thicknesses of the exposed portions of the second nanostructures 66. As in Fig. As illustrated more clearly in Figures 14A - 19B (and described in more detail below), the remaining sections of the second nanostructures can have 66 rounded corners.

[0056] In Fig. 13A and Fig. In the recesses 106 of 13B, a dielectric gate layer 112 is formed. A gate electrode layer 114 is formed on the dielectric gate layer 112. The dielectric gate layer 112 and the gate electrode layer 114 are layers for replacement gates, and each of them encloses all (e.g., four) sides of the second nanostructures 66.

[0057] The dielectric gate layer 112 is arranged on the side walls and / or the upper surfaces of the fins 62; on the upper surfaces, side walls, and bottom surfaces of the second nanostructures 66; and on the side walls of the gate spacers 90. The dielectric gate layer 112 can also be formed on the upper surfaces of the first ILD 104 and the gate spacers 90. The dielectric gate layer 112 can contain an oxide, such as silicon oxide or a metal oxide, a silicate, such as a metal silicate, combinations thereof, multiple layers thereof, or the like. The dielectric gate layer 112 can contain a dielectric material with a k-value greater than about 7.0, such as a metal oxide or a silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. Although in Fig. 13A and Fig. Figure 13B illustrates a single-layer dielectric gate layer 112. As will be described in more detail later, the dielectric gate layer 112 can contain an interface layer and a main layer.

[0058] The gate electrode layer 114 can contain a metal-containing material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof or multiple layers thereof, or the like. Although in Fig. 13A and Fig. Figure 13B illustrates a single-layer gate electrode layer 114. As will be described in more detail later, the gate electrode layer 114 can contain any number of work function tuning layers, any number of barrier layers, any number of adhesive layers, and a filler material.

[0059] The formation of the dielectric gate layers 112 in the n-type region 50N and the p-type region 50P can occur simultaneously, so that the dielectric gate layers 112 in each region are formed from the same materials, and the formation of the gate electrode layers 114 can also occur simultaneously, so that the gate electrode layers 114 in each region are formed from the same materials. In some embodiments, the dielectric gate layers 112 in each region can be formed by different processes, so that the dielectric gate layers 112 consist of different materials and / or have a different number of layers, and / or the gate electrode layers 114 in each region can be formed by different processes, so that the gate electrode layers 114 consist of different materials and / or have a different number of layers.Different masking steps can be used to mask and expose suitable areas when employing different processes. In the following description, at least sections of the gate electrode layers 114 in the n-type region 50N and the gate electrode layers 114 in the p-type region 50P are formed separately.

[0060] Fig. Figures 14A–19B illustrate a process in which dielectric gate layers 112 and gate electrode layers 114 are formed for replacement gates in the recesses 106. Features are illustrated in areas corresponding to a 50R region in Fig. 13A are similar. When forming the replacement gate layers, a first exit work adjustment layer 114A (see Fig. 17A) and a barrier layer 114B (see Fig. 17A) in a first area (e.g., the p-type area 50P). Then a second output work adjustment layer 114C (see Fig. 18A and Fig. 18B) is formed in both the first region (e.g., the p-type region 50P) and a second region (e.g., the n-type region 50N). Because the first region (e.g., the p-type region 50P) and the second region (e.g., the n-type region 50N) contain different quantities and types of output function tuning layers, the devices formed in the regions exhibit different threshold stresses. Furthermore, the barrier layer 114B is arranged between the first output function tuning layer 114A and the second output function tuning layer 114C in the first region (e.g., the p-type region 50P). During the deposition of the second work function tuning layer 114c, the barrier layer 114B protects the underlying first work function tuning layer 114A, so that its work function is not modified by diffusion of the metal into the first work function tuning layer 114A.The threshold voltages of the resulting devices can therefore be adjusted more precisely.

[0061] In Fig. 14A and Fig. In 14B, the dielectric gate layer 112 is deposited in the recesses 106 in both the first region (e.g., the p-type region 50P) and the second region (e.g., the n-type region 50N). The dielectric gate layer 112 can also be deposited on the upper surfaces of the first ILD 104 and the gate spacers 90 (see Fig. 13B). The formation methods of the dielectric gate layer 112 can include molecular beam deposition (MBD), ALD, PECVD, and the like. The dielectric gate layer 112 envelops all (e.g., four) sides of the second nanostructures 66. In the illustrated embodiment, the dielectric gate layer 112 is multilayered and comprises an interface layer 112A (or more generally: a first dielectric gate layer) and an overlying high-k dielectric layer 112B (or more generally: a second dielectric gate layer). The interface layer 112A can be formed from silicon oxide, and the high-k dielectric layer 112B can be formed from hafnium oxide.

[0062] In Fig. 15A and Fig. In step 15B, a first output function tuning layer 114A is deposited on the dielectric gate layer 112 in both the first region (e.g., the p-type region 50P) and the second region (e.g., the n-type region 50N). As will be described in detail later, the first output function tuning layer 114A is structured to remove sections of the first output function tuning layer 114A in the second region (e.g., the n-type region 50N), while leaving sections of the first output function tuning layer 114A in the first region (e.g., the p-type region 50P). The first exit work adjustment layer 114A can be described as a "p-type exit work adjustment layer" if it has been removed from the second area (e.g., the n-type area 50N) and remains in the first area (e.g., the p-type area 50P).The first work function tuning layer 114A contains any acceptable material for tuning the work function of a device to a desired value according to the application of the device to be formed and can be deposited using any acceptable deposition process. For example, if the first work function tuning layer 114A is a p-type work function tuning layer, it can be formed from a p-type work function metal (PWFM), such as titanium nitride (TiN), tantalum nitride (TaN), combinations thereof, or the like, which can be deposited by ALD, CVD, PVD, or the like. Although the first work function tuning layer 114A is shown as a single layer, it can be multilayered. The first exit work tuning layer 114A can, for example, contain a layer of titanium nitride (TiN) and a layer of tantalum nitride (TaN).

[0063] The first output work tuning layer 114A fills the remaining sections of the areas 50I between the second nanostructures 66 (e.g. filling the openings 108, see Fig. 14A and Fig. 14B) of both the first region (e.g., the p-type region 50P) and the second region (e.g., the n-type region 50N). The first output work tuning layer 114A is deposited, in particular, on the dielectric gate layer 112 until it is thick enough to fuse and weld. In some embodiments, interfaces 116 are formed by contacting adjacent sections of the first output work tuning layer 114A (e.g., those sections around the second nanostructures 66). As a result, the openings 108 are completely filled by the dielectric material(s) of the dielectric gate layer 112 and the output work metal of the first output work tuning layer 114A, so that no barrier layers (described in more detail below) can form in the openings 108.By eliminating the need to deposit barrier layers in the openings 108, the simplicity of fabrication can be improved, particularly for advanced semiconductor nodes with small feature sizes, since barrier layer materials are difficult to deposit in small spaces. Respective sections of the dielectric gate layer 112 envelop each of the second nanostructures 66, and respective sections of the first work function tuning layer 114A fill regions between the respective sections of the dielectric gate layer 112 in both the first region (e.g., the p-type region 50P) and the second region (e.g., the n-type region 50N). In some embodiments, the first work function tuning layer 114A is formed to a thickness in the range of about 0.5 nm (5 Å) to about 6 nm (60 Å).Forming the first output work tuning layer 114A to a thickness of less than approximately 0.5 nm (5 Å) may not result in fusion of sections of the first output work tuning layer 114A. Forming the first output work tuning layer 114A to a thickness greater than approximately 6 nm (60 Å) may adversely affect the threshold stresses of the resulting devices.

[0064] In Fig. 16A and Fig. In embodiment 16B, a barrier layer 114B is deposited on the first output work tuning layer 114A. As described in more detail later, a second output work tuning layer is formed above the barrier layer 114B, and the second output work tuning layer can be formed from a metal that diffuses readily. The barrier layer 114B is formed from a barrier material that is resistant to the diffusion of metal, thereby preventing (e.g., substantially preventing or at least reducing) modification of the output work of the first output work tuning layer 114A. In some embodiments, forming the second output work tuning layer involves depositing aluminum, and the barrier layer 114B is formed from a barrier material that is resistant to the diffusion of aluminum, thereby preventing the diffusion of aluminum into the first output work tuning layer 114A.As described in more detail below, a suitable barrier material includes amorphous silicon, which can be deposited by CVD, ALD or the like.

[0065] The barrier layer 114B is deposited to a thickness sufficient to prevent modification of the work function of the first work function tuning layer 114A during subsequent processing. In some embodiments, the barrier layer 114B is formed to a thickness in the range of about 0.7 nm (7 Å) to about 4 nm (40 Å). Forming the barrier layer 114B to a thickness of less than about 0.7 nm (7 Å) may not be sufficient to protect the first work function tuning layer 114A. Forming the barrier layer 114B to a thickness greater than about 4 nm (40 Å) may adversely affect the threshold stresses of the resulting devices. The barrier layer 114B may be thinner than the first work function tuning layer 114A.

[0066] In some embodiments, the barrier layer 114B is formed from amorphous silicon deposited by a CVD process. In particular, the barrier layer 114B can be formed by placing the substrate 50 in a deposition chamber and dispensing a silicon source precursor into the deposition chamber. Acceptable silicon source precursors include, among others, binary silicon-hydrogen composite silanes, such as silane (SiH4), disilane (Si2H6), and the like. The CVD process can be carried out at a temperature in the range of about 275 °C to about 500 °C and at a pressure in the range of about 400 Pa (3 Torr) to about 6 kPa (45 Torr), for example, by maintaining the deposition chamber at such a temperature and pressure. The CVD process can be carried out for a duration ranging from approximately 0.2 seconds to approximately 990 seconds, for example by holding the silicon source precursor in the deposition chamber for such a duration.Performing the CVD process with parameters within these ranges enables the formation of barrier layer 114B to the desired thickness (described above) and quality. Performing the CVD process with parameters outside these ranges may not enable the formation of barrier layer 114B to the desired thickness or quality.

[0067] In some non-inventional examples, the barrier layer 114B is formed from fluorine-free tungsten deposited by an ALD process. In particular, the barrier layer 114B can be formed by placing the substrate 50 in a deposition chamber and cyclically dispensing several source precursors into the deposition chamber. Fluorine-free tungsten is tungsten that is free of fluorine, and it is deposited with a fluorine-free tungsten source precursor, for example, a tungsten source precursor that is free of fluorine. Deposition of tungsten with a fluorine-free tungsten source precursor avoids the undesired production of corrosive fluoride byproducts during deposition. A first pulse of an ALD cycle is carried out by dispensing a fluorine-free tungsten source precursor into the deposition chamber. Acceptable fluorine-free tungsten source precursors include, among others, tungsten chlorides, such as tungsten(V) chloride (WCl5) and the like.The first pulse can be performed at a temperature in the range of approximately 250 °C to approximately 550 °C and at a pressure in the range of approximately 13 Pa (0.1 Torr) to approximately 8 kPa (60 Torr), for example, by maintaining the deposition chamber at such a temperature and pressure. The first pulse can be performed for a duration in the range of approximately 0.1 seconds to approximately 300 seconds, for example, by holding the fluorine-free tungsten source precursor in the deposition chamber for such a duration. The fluorine-free tungsten source precursor is then purged from the deposition chamber, for example, by an acceptable vacuum process and / or by introducing an inert gas into the deposition chamber. A second pulse of the ALD cycle is performed by dispensing a hydrogen source precursor into the deposition chamber. Acceptable hydrogen source precursors include, among others, hydrogen gas (H₂) and the like.The second pulse can be performed at a temperature in the range of approximately 250 °C to approximately 550 °C and at a pressure in the range of approximately 13 Pa (0.1 Torr) to approximately 8 kPa (60 Torr), for example, by maintaining the deposition chamber at such a temperature and pressure. The second pulse can be performed for a duration in the range of approximately 0.1 seconds to approximately 300 seconds, for example, by holding the hydrogen source precursor in the deposition chamber for such a duration. The hydrogen source precursor is then purged from the deposition chamber, for example, by an acceptable vacuum process and / or by introducing an inert gas into the deposition chamber. Each ALD cycle results in the deposition of an atomic layer (sometimes referred to as a monolayer) of fluorine-free tungsten. The ALD cycles are repeated until the barrier layer 114B has a desired thickness (as previously described).The ALD cycles can be repeated from approximately 1 to approximately 500 times. Performing the ALD process with parameters within this range allows the formation of the 114B barrier layer to a desired thickness (described above) and quality. Performing the ALD process with parameters outside this range may not allow the formation of the 114B barrier layer to the desired thickness or quality.

[0068] In the illustrated embodiment, the barrier layer 114B is a multilayered layer of barrier material(s), including a first barrier sublayer 114B1 and a second barrier sublayer 114B2. Such a barrier layer 114B is formed by depositing the first barrier sublayer 114B1 and then depositing the second barrier sublayer 114B2 over the first barrier sublayer 114B1. In some embodiments, an upper portion of the first barrier sublayer 114B1 is oxidized after the deposition of the first barrier sublayer 114B1 and before the deposition of the second barrier sublayer 114B2, thereby forming a third barrier sublayer 114B3 between the first barrier sublayer 114B1 and the second barrier sublayer 114B2. The upper section of the first barrier sublayer 114B1 can be oxidized by exposing the first barrier sublayer 114B1 to an oxygen-containing environment.The oxygen-containing environment can be the same process chamber in which the first barrier sublayer 114B1 is deposited, or it can be a different process chamber. Accordingly, the material of the third barrier sublayer 114B3 is an oxide of the barrier material of the first barrier sublayer 114B1. For example, if the first barrier sublayer 114B1 is formed from amorphous silicon, the third barrier sublayer 114B3 is formed from silicon oxide. The first barrier sublayer 114B1 and the second barrier sublayer 114B2 can be formed from the same barrier material, or they can contain different barrier materials. Continuing the above example, if the first barrier sublayer 114B1 is formed from amorphous silicon, the second barrier sublayer 114B2 can also be formed from amorphous silicon, or the second barrier sublayer 114B2 can be formed from a different barrier material, such as fluorine-free tungsten.If the first barrier sublayer 114B1 and the second barrier sublayer 114B2 are formed from the same barrier material, the deposition of the second barrier sublayer 114B2 may involve the deposition of more of the barrier material from the first barrier sublayer 114B1. The third barrier sublayer 114B3 may be thin, for example, thinner than the first barrier sublayer 114B1 and the second barrier sublayer 114B2. The third barrier sublayer 114B3 may, for example, constitute from about 20% to about 75% of the total thickness of the barrier layer 114B. If the third barrier sublayer 114B3 is formed from an oxide and is thin, it may be referred to as a "thin oxide". As described in more detail below, the inclusion of the third barrier sublayer 114B3 (e.g., a thin oxide) in the barrier layer 114B can contribute to making the barrier layer 114B more resistant to metal diffusion. In another embodiment (hereinafter referred to as . Fig. 23A and Fig. (as described in 23B) barrier layer 114B is a single continuous layer of barrier material that does not contain an intermediate thin oxide sublayer.

[0069] In Fig. 17A and Fig. Sections of the barrier layer 114B and the first output function tuning layer 114A from the second region (e.g., the n-type region 50N) are removed. Removing these sections of barrier layer 114B and the first output function tuning layer 114A from the second region (e.g., the n-type region 50N) enlarges the recesses 106 in the second region (e.g., the n-type region 50N) to re-expose the dielectric gate layer 112 and re-form the openings 108 in the second region (e.g., the n-type region 50N). The removal can be accomplished by acceptable photolithography and etching techniques. The etching can involve an acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or the like, or a combination thereof. The etching can be anisotropic.

[0070] In some embodiments, a first etching is performed to remove the portions of the barrier layer 114B, and a second etching is performed to remove the portions of the first output work tuning layer 114A. The first etching can be selective with respect to the barrier layer 114B (e.g., selective etching of the barrier layer 114B material at a faster rate than that of the first output work tuning layer 114A material). For example, if the barrier layer 114B is formed from amorphous silicon, it can be removed by wet etching using dilute hydrofluoric acid (dHF). The second etching can be selective with respect to the first output work tuning layer 114A (e.g., selective etching of the first output work tuning layer 114A material at a faster rate than that of the dielectric gate layer 112 material).If the first exit work tuning layer 114A is formed, for example, from titanium nitride, it can be removed by wet etching using ammonium hydroxide (NH4OH) and hydrogen peroxide (H2O2). In other embodiments, a single etching process is carried out to remove sections of both the barrier layer 114B and the first exit work tuning layer 114A.

[0071] In Fig. 18A and Fig. In 18B, a second output function tuning layer 114C is deposited on the junction layer 114B in the first region (e.g., the p-type region 50P) and on the dielectric gate layer 112 in the second region (e.g., the n-type region 50N). As described in more detail below, n-type devices are formed with the second output function tuning layer 114C in the second region (e.g., the n-type region 50N), and p-type devices are formed with the first output function tuning layer 114A and the second output function tuning layer 114C in the first region (e.g., the p-type region 50P). The second exit work adjustment layer 114C can be referred to as an "n-type exit work adjustment layer" if it is the only exit work adjustment layer in the second area (e.g., the n-type area 50N).The second work function tuning layer 114C contains any acceptable material for tuning the work function of a device to a desired value according to the application of the device to be formed and can be deposited using any acceptable deposition process. For example, if the second work function tuning layer 114C is an n-type work function tuning layer, it can be formed from an n-type work function metal (NWFM), such as titanium-aluminum (TiAl), titanium-aluminum carbide (TiAlC), titanium-aluminum nitride (TiAlN), combinations thereof, or the like, which can be deposited by ALD, CVD, PVD, or the like. Although the second work function tuning layer 114C is shown as a single layer, it can also be multilayered.The second exit work tuning layer 114C can, for example, contain a layer of titanium aluminum nitride (TiAlN) and a layer of titanium nitride (TiN).

[0072] In embodiments where the second output function tuning layer 114C is an n-type output function tuning layer, it may contain a metallic element suitable for tuning the threshold voltages of n-type devices, such as aluminum, which can also diffuse readily. For example, if the second output function tuning layer 114C contains aluminum, it may be deposited by ALD or CVD using an aluminum-containing precursor, such as triethylaluminum (TEA) (Al₂(C₂H₅)₆), trimethylaluminum (TMA) (Al₂(CH₃)₆), or the like. During deposition, aluminum dissociates from the aluminum-containing precursor to form the material of the second output function tuning layer 114C; however, aluminum may also dissociate from the aluminum-containing precursor and diffuse into the barrier layer 114B.Similarly, the second output work tuning layer 114C can also be deposited by PVD, whereby in this case sputtered aluminum ions can diffuse into the barrier layer 114B. The barrier layer 114B is formed from a barrier material that is resistant to metal diffusion, thus preventing the diffusion of the metal element (e.g., aluminum) into the underlying first output work tuning layer 114A. Deposition of the second output work tuning layer 114C can therefore form a residue 120 of the metal element (e.g., aluminum) in the barrier layer 114B, with the concentration of the residue 120 being higher in the upper part of the barrier layer 114B than in the lower part of the barrier layer 114B.The upper section of the barrier layer 114B is the section distal to the dielectric gate layer 112 and the first output function tuning layer 114A and proximal to the second output function tuning layer 114C. The lower section of the barrier layer 114B is the section proximal to the dielectric gate layer 112 and the first output function tuning layer 114A and distal to the second output function tuning layer 114C. The concentration of the residue 120 can decrease through the barrier layer 114B in a direction extending from the upper section of the barrier layer 114B to the lower section of the barrier layer 114B. In some embodiments, the lower section of the barrier layer 114B is free of residue 120. Oxides can be particularly resistant to diffusion of some metals (e.g., aluminum) that readily bind with oxygen, and therefore this can occur when the third barrier sublayer 114B3 (e.g.,The presence of a thin oxide in barrier layer 114B can be particularly effective in preventing the metal from diffusing into the underlying first exit-work tuning layer 114A. For example, if barrier layer 114B is a multiple layer of barrier material(s), the second barrier sublayer 114B2 can contain residue 120, while the first barrier sublayer 114B1 is free of residue 120.

[0073] The second output work tuning layer 114C fills the remaining sections of the areas 50I between the second nanostructures 66 (e.g. filling the openings 108, see Fig. 17B) in the second region (e.g., the n-type region 50N). The second output function tuning layer 114C is deposited, in particular, on the dielectric gate layer 112 until it is thick enough to fuse and weld. In some embodiments, interfaces 118 are formed by contacting adjacent sections of the second output function tuning layer 114C (e.g., those sections around the second nanostructures 66). As a result, the openings 108 in the second region (e.g., the n-type region 50N) are completely filled by the dielectric material(s) of the dielectric gate layer 112 and the output function metal of the second output function tuning layer 114C, so that no adhesive layers (described in more detail below) can form in the openings 108.By eliminating the need to deposit adhesive layers in the openings 108, the simplicity of fabrication can be improved, particularly for advanced semiconductor nodes with small feature sizes, since adhesive layer materials are difficult to deposit in small spaces. Respective sections of the dielectric gate layer 112 envelop each of the second nanostructures 66, and respective sections of the second work function tuning layer 114C fill regions between the respective sections of the dielectric gate layer 112 in the second region (e.g., the n-type region 50N). In some embodiments, the second work function tuning layer 114C is formed to a thickness in the range of about 0.5 nm (5 Å) to about 6 nm (60 Å).Forming the second output work tuning layer 114C to a thickness of less than approximately 0.5 nm (5 Å) may not result in fusion of sections of the second output work tuning layer 114C. Forming the second output work tuning layer 114C to a thickness greater than approximately 6 nm (60 Å) may adversely affect the threshold stresses of the resulting devices. The barrier layer 114B may have a smaller thickness than the second output work tuning layer 114C.

[0074] The material of the first output working adjustment layer 114A differs from the material of the second output working adjustment layer 114C. As mentioned above, the first output working adjustment layer 114A can be formed from a p-type output working metal (PWFM), and the second output working adjustment layer 114C can be formed from an n-type output working metal (NWFM). The PWFM differs from the NWFM. Furthermore, the material(s) of the barrier layer 114B differs from the material of the first output working adjustment layer 114A and the material of the second output working adjustment layer 114C.

[0075] In Fig. 19A and Fig. In step 19B, a filler layer 114E is deposited on the second output function tuning layer 114C. Optionally, an adhesive layer 114D is formed between the filler layer 114E and the second output function tuning layer 114C. After completion of the formation, the gate electrode layer 114 contains the first output function tuning layer 114A, the barrier layer 114B, the second output function tuning layer 114C, the adhesive layer 114D, and the filler layer 114E.

[0076] The adhesive layer 114D contains any acceptable material to promote adhesion and prevent diffusion. For example, the adhesive layer 114D can be formed from a metal or metal nitride, such as titanium nitride, titanium aluminide, titanium aluminum nitride, silicon-doped titanium nitride, tantalum nitride, or the like, which can be deposited by ALD, CVD, PVD, or the like.

[0077] The filler layer 114E contains any acceptable material with low resistance. The filler layer 114E can, for example, be formed from a metal such as tungsten, aluminum, cobalt, ruthenium, combinations thereof, or the like, which can be deposited by ALD, CVD, PVD, or the like. The filler layer 114E fills the remaining portions of the recesses 106.

[0078] Although the barrier layer 114B is used to protect the first work function tuning layer 114A during processing, it need not significantly affect the electrical properties of the resulting devices and can be left in the sections of the gate electrode layer 114 in the first region (e.g., the p-type region 50P). The barrier layer 114B can, for example, be thin enough not to significantly modify the work function of the gate electrode layers 114. The barrier layer 114B is located between the sections of the first work function tuning layer 114A and the second work function tuning layer 114C in the first region (e.g., the p-type region 50P) and physically separates them. In contrast, the second region (e.g.,The n-type region 50N) is free from the first output function tuning layer 114A and the barrier layer 114B, so that the second output function tuning layer 114C and the dielectric gate layer 112 in the second region (e.g., the n-type region 50N) are not separated by a barrier layer and can be in physical contact. Thus, the material of the second output function tuning layer 114C can extend continuously between the dielectric gate layer 112 and the adhesive layer 114D in the second region (e.g., the n-type region 50N).

[0079] In Fig. 20A and Fig. 20B, a removal process is performed to remove the excess sections of material from the dielectric gate layer 112 and the gate electrode layer 114, wherein the excess sections lie above the upper surfaces of the first ILD 104 and the gate spacers 90, thereby forming gate dielectrics 122 and gate electrodes 124. In some embodiments, a planarization process, such as chemical-mechanical polishing (CMP), a back-etching process, combinations thereof, or the like, may be used. When planarized, the dielectric gate layer 112 has sections to the left in the recesses 106 (forming the gate dielectrics 122). When planarized, the gate electrode layer 144 has sections to the left in the recesses 106 (forming the gate electrodes 124). The upper surfaces of the gate spacers 90; the CESL 102; the first ILD 104; the gate dielectrics 122 (e.g.the interface layers 112A and the dielectric layers with high k-value 112B, see . Fig. 19A and Fig. 19B); and the gate electrodes 124 (e.g. the first output function tuning layer 114A, the barrier layer 114B, the second output function tuning layer 114C, the adhesive layer 114D and the filler layer 114E, see Fig. 19A and Fig. 19B) are coplanar (within process variations). The gate dielectrics 122 and the gate electrodes 124 form substitute gates of the resulting nanoFETs. Each pair of a gate dielectric 122 and a gate electrode can be collectively referred to as a “gate structure”. The gate structures extend along the top surfaces, side walls, and bottom surfaces of a channel region 68 of the second nanostructures 66.

[0080] In Fig. 21A and Fig. In embodiment 21B, a second ILD 134 is deposited over the gate spacers 90, the CESL 102, the first ILD 104, the gate dielectrics 122, and the gate electrodes 124. In some embodiments, the second ILD 134 is a flowable film formed by a flowable CVD process. In other embodiments, the second ILD 134 is formed from a dielectric material such as PSG, BSG, BPSG, USG, or the like, which can be deposited by any suitable process, such as CVD, PECVD, or the like.

[0081] In some embodiments, an etch stop layer (ESL) 132 is formed between the second ILD 134 and the gate spacers 90, the CESL 102, the first ILD 104, the gate dielectrics 122, and the gate electrodes 124. The ESL 132 contains a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, with high etch selectivity for the etching of the second ILD 134.

[0082] In Fig. 22A and Fig. Gate contacts 142 and source / drain contacts 144 are formed at 22B to contact the gate electrodes 124 and the epitaxial source / drain regions 98, respectively. The gate contacts 142 are physically and electrically coupled to the gate electrodes 124. The source / drain contacts 144 are physically and electrically coupled to the epitaxial source / drain regions 98.

[0083] To form the gate contacts 142 and the source / drain contacts 144, openings for the gate contacts 142 are formed, for example, by the second ILD 134 and the ESL 132, and openings for the source / drain contacts 144 are formed by the second ILD 134, the ESL 132, the first ILD 104, and the CESL 102. The openings can be formed using acceptable photolithography and etching techniques. A lining (not shown separately), such as a diffusion barrier, an adhesive layer, or the like, and a conductive material are formed in the openings. The lining can contain titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material can be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as a CMP, can be carried out to remove excess material from a surface of the second ILD 134.The remaining lining and conductive material form the gate contacts 142 and the source / drain contacts 144 in the openings. The gate contacts 142 and the source / drain contacts 144 can be formed in different processes or they can be formed in the same process. Although shown as formed in the same cross-sections, it should be noted that each of the gate contacts 142 and the source / drain contacts 144 can be formed in different cross-sections, which can prevent short-circuiting of the contacts.

[0084] Optionally, metal-semiconductor alloy regions 146 are formed at the interfaces between the epitaxial source / drain regions 98 and the source / drain contacts 144. These metal-semiconductor alloy regions 146 can be silicide regions formed from a metal silicide (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), germanide regions formed from a metal germanide (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.), silicon-germanide regions formed from both a metal silicide and a metal germanide, or the like. The metal-semiconductor alloy regions 146 can be formed upstream of the source / drain contact material(s) 144 by depositing a metal in the openings for the source / drain contacts 144 and then performing a thermal tempering process. The metal can be any metal capable of reacting with semiconductor materials (e.g. silicon, silicon germanium, germanium, etc.).The epitaxial source / drain regions 98 are to react with a low-resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other high-melting-point metals, rare earth metals, or their alloys. The metal can be deposited by a deposition process such as ALD, CVD, PVD, or the like. After the thermal annealing process, a cleaning process, such as wet cleaning, can be performed to remove any residual metal from the source / drain contact openings 144, such as from surfaces of the metal-semiconductor alloy regions 146. The source / drain contact material(s) 144 can then be formed on the metal-semiconductor alloy regions 146.

[0085] Fig. 23A and Fig. Figure 23B shows views of nano-FETs according to some other embodiments. This embodiment is the embodiment of Fig. 19A and Fig. 19B is similar, except that the barrier layer 114B is a single continuous layer of a barrier material. The barrier layer 114B can, for example, be a single continuous layer of amorphous silicon. The change in the concentration of the residue 120 by the barrier layer 114B can be carried out in stages in this embodiment. In the embodiment of Fig. 19A and Fig. In 19B, the concentration of residue 120 can, for example, drop abruptly at the third barrier sublayer 114B3. In the embodiment of Fig. 23A and Fig. 23B can, however, continuously decrease the concentration of residue 120 through barrier layer 114B.

[0086] Embodiments can offer advantages. Including the second output work tuning layer 114C in both the first region (e.g., the p-type region 50P) and the second region (e.g., the n-type region 50N) allows the output works of the gate electrodes 124 to be tuned in both regions. Forming the barrier layer 114B between the first output work tuning layer 114A and the second output work tuning layer 114C protects the first output work tuning layer 114A from metal diffusion during the deposition of the second output work tuning layer 114C, particularly if the second output work tuning layer 114C is formed from a metal that diffuses readily, such as aluminum. The barrier layer 114B thus helps to prevent modification of the output work of the first output work tuning layer 114A during deposition of the second output work tuning layer 114C.The threshold voltages of the resulting devices in both the n-type range 50N and the p-type range 50P can thus be more precisely adjusted.

Claims

[1] Device comprising: a canal area (68); a dielectric gate layer (112) on the channel area (68); a first work function tuning layer (114A) on the dielectric gate layer (112), wherein the first work function tuning layer (114A) has a p-type work function metal; a barrier layer (114B) on the first output work tuning layer (114A), wherein the barrier layer (114B) comprises amorphous silicon; a second output work tuning layer (114C) on the barrier layer (114B), wherein the second output work tuning layer (114C) comprises an n-type output work metal, the n-type output work metal being different from the p-type output work metal; and a filler layer on the second outlet work adjustment layer (114C). [2] Device according to claim 1, wherein the n-type exit work metal comprises a metal element and the barrier layer (114B) is a single continuous layer of a barrier material, wherein the barrier layer (114B) has a lower section near the first exit work tuning layer (114A) and an upper section near the second exit work tuning layer (114C), the upper section of the barrier layer (114B) having a residue of the metal element at a higher concentration than the lower section of the barrier layer (114B). [3] Device according to claim 1, wherein the exit working metal of n-type comprises a metal element and the barrier layer (114B): a first layer; a second layer on top of the first layer, wherein the second layer contains a residue of the metal element at a higher concentration than the first layer; and an oxide layer between the first layer and the second layer, wherein the oxide layer is thinner than the first layer and the second layer. [4] Device according to claim 3, wherein the first layer comprises a first barrier material, the oxide layer comprises an oxide of the first barrier material and the second layer comprises a second barrier material, wherein the second barrier material differs from the first barrier material. [5] Device according to claim 3, wherein the first layer comprises a barrier material, the oxide layer comprises an oxide of the barrier material and the second layer comprises the barrier material. [6] Device according to any one of claims 3 to 5, wherein the second layer comprises fluorine-free tungsten. [7] Device according to one of the preceding claims, wherein the barrier layer (114B) has a thickness in the range of 0.7 nm to 4 nm. [8] Device comprising: a first transistor (50P), comprising: a first canal area; a first dielectric gate layer (112) on the first channel region; a p-type output function tuning layer on the first dielectric gate layer (112); a barrier layer (114B) on the p-type exit work adjustment layer; a first n-type output work tuning layer (114A) on the barrier layer (114B), wherein the first n-type output work tuning layer (114A) comprises a metal, an upper section of the barrier layer (114B) has a residue of the metal in a higher concentration than a lower section of the barrier layer (114B), wherein the upper section of the barrier layer (114B) is located near the first n-type output work tuning layer (114A), and the lower section of the barrier layer (114B) is located near the p-type output work tuning layer; and a first fill layer on the first outlet work tuning layer (114A) of n-type; and a second transistor (50N), comprising: a second canal area; a second dielectric gate layer (112) on the second channel area; a second n-type output function tuning layer (114C) on the second dielectric gate layer (112), wherein the second n-type output function tuning layer (114C) comprises the metal; and a second filler layer on the second n-type output work tuning layer (114C); wherein the barrier layer (114B) comprises amorphous silicon as the barrier material. [9] Device according to claim 8, wherein the barrier layer (114B) comprises a single continuous layer of barrier material between the p-type output work tuning layer and the first n-type output work tuning layer (114A). [10] Device according to claim 8, wherein the barrier layer (114B) comprises a multiple layer of barrier materials between the p-type output work tuning layer and the first n-type output work tuning layer (114A). [11] Device according to any one of claims 8 to 10, wherein the metal is aluminium. [12] Procedures, including: Deposition of a dielectric gate layer (112) comprising a first section and a second section, wherein the first section is deposited on a first channel region and the second section is deposited on a second channel region; Forming a first output work tuning layer (114A) on the first section of the dielectric gate layer (112); Forming a barrier layer (114B) on the first exit work coordination layer (114A); and Depositing a second work function tuning layer (114C) on the junction (114B) and the second section of the dielectric gate layer (112), wherein the junction (114B) prevents a modification of a first work function of the first work function tuning layer (114A) during the deposition of the second work function tuning layer (114C); wherein the deposition of the barrier layer (114B) involves the deposition of amorphous silicon by a CVD process. [13] Method according to claim 12, wherein the CVD process is carried out with silane, the CVD process is carried out at a temperature in a range of 275 °C to 500 °C, the CVD process is carried out at a pressure in a range of 400 Pa to 6 kPa, and the barrier layer (114B) is deposited to a thickness in a range of 0.7 nm to 4 nm. [14] Method according to claim 12 or 13, wherein the deposition of the second output work tuning layer (114C) comprises the deposition of a metal, wherein the barrier layer (114B) prevents diffusion of the metal into the first output work tuning layer (114A) during the deposition of the second output work tuning layer (114C). [15] Method according to any one of claims 12 to 14, wherein forming the first output function tuning layer (114A) comprises depositing the first output function tuning layer (114A) on the first section and the second section of the dielectric gate layer (112), and wherein forming the barrier layer (114B) comprises: Separation of the blocking layer (114B) on the first exit work coordination layer (114A); and Removing sections of the junction layer (114B) and the first output work tuning layer (114A) to expose the second section of the dielectric gate layer (112). [16] Method according to any one of claims 12 to 15, wherein the deposition of the barrier layer (114B) comprises the deposition of a single continuous layer of a barrier material. [17] Method according to any one of claims 12 to 15, comprising the deposition of the barrier layer (114B): Deposition of an initial barrier material; Oxidation of an upper section of the first barrier material; and After oxidizing the upper section of the first barrier material, a second barrier material is deposited on top of the first barrier material. [18] Method according to claim 17, wherein the second barrier material comprises fluorine-free tungsten. [19] Method according to any one of claims 12 to 15, comprising the deposition of the barrier layer (114B): Separation of a barrier material; Oxidation of an upper section of the barrier material; and After the upper section of the barrier material has oxidized, more of the barrier material is deposited.

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