Self-aligning metal gate for a multi-gate device and method for manufacturing the same

Abstract

Device comprising: a substrate (202); a first gate structure (2002A) which encloses a channel layer (208) arranged above the substrate (202); a second gate structure (2002B) which encloses a further channel layer (208) arranged above the substrate (202); a dielectric fin structure formed over a flat trench insulation element (STI element), wherein the dielectric fin structure is arranged between the first gate structure (2002A) and the second gate structure (2002B); at least one metallization layer (2602, 2604) on the first gate structure (2002A), the dielectric fin structure and the second gate structure (2002B), which extends continuously from the first gate structure (2002A) to the second gate structure (2002B).

Description

BACKGROUND

[0001] The electronics industry has recently experienced a steadily increasing demand for smaller and faster electronic components capable of supporting a greater number of increasingly complex and demanding functions. To meet this demand, the integrated circuit (IC) industry has a continuing trend toward manufacturing cost-effective, high-performance, and energy-efficient ICs. So far, these goals have largely been achieved by reducing the dimensions of ICs (for example, the minimum IC feature size), thereby improving production efficiency and reducing associated costs. However, this miniaturization has also led to increased complexity in the IC manufacturing process.Therefore, implementing ongoing advances in IC devices and their performance requires similar advances in IC manufacturing processes and related technology.

[0002] Recently, multi-gate devices have been introduced to improve gate control. It has been recognized that multi-gate devices increase gate-channel coupling, reduce turn-off current, and / or mitigate short-channel effects (SCEs). One such multi-gate device is the wraparound gate device (GAA device), which features a gate structure that can partially or completely surround a channel area to provide access to the channel area from at least two sides. GAA devices enable significant miniaturization of IC technologies while maintaining gate control and reducing SCEs, and can be seamlessly integrated into conventional IC manufacturing processes.However, with the progressive miniaturization of GAA devices, non-self-aligning gate-cutting techniques, typically used to isolate gates of different GAA devices from each other—for example, the first gate of a first GAA transistor from the second gate of a second GAA transistor—hinder the dense packing of IC structural elements necessary for advanced IC technology nodes. While existing GAA devices and fabrication methods have generally been adequate for their intended purposes, they have by no means been entirely satisfactory in all respects.

[0003] US 2016 / 0027703A1 discloses a method for fabricating a semiconductor device with a field-effect transistor. The method comprises forming a first gate electrode and a second gate electrode, which are substantially parallel to each other and each intersect a PMOSFET region and an NMOSFET region on a substrate; forming an insulating interlayer covering the first and second gate electrodes; structuring the insulating interlayer to form a first undercontact hole on the first gate electrode, wherein the first undercontact hole is located, in plan view, between the PMOSFET region and the NMOSFET region; and structuring the insulating interlayer to form a first gate contact hole and to expose a surface of the second gate electrode, wherein the first undercontact hole and the first gate contact hole form a single interconnect hole.Further state of the art is known from US 2020 / 0 1058 89 A1, US 2020 / 0 006 155 A1 and US 2020 / 0 098 878 A1. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The present disclosure is best understood with reference to the following detailed description in conjunction with the accompanying figures. It should be noted that, in accordance with industry practice, various elements are not shown to scale and are for illustrative purposes only. In fact, the dimensions of the various elements may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 is a flowchart of a process for manufacturing a multi-gate device in accordance with various aspects of the present disclosure. The Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19, Fig. 20A, Fig. 21A, Fig. 22A, Fig. 23A, Fig. 24A, Fig. 25A, Fig. 26A, Fig. 27A and Fig. Figures 28A are perspective partial views of sections of, or a complete, multi-gate device at various stages of manufacturing (such as those relating to the process in Fig. 1) in accordance with various aspects of the present revelation. The Fig. 20B, Fig. 21B, Fig. 22B, Fig. 23B, Fig. 24B, Fig. 25B, Fig. 26B, Fig. 27B and Fig. Figure 28B shows partial cross-sectional views of sections of, or a complete, multi-gate device at various stages of manufacturing (such as those relating to the process in Fig. 1) in accordance with various aspects of the present revelation. The Fig. 29A and Fig. Figure 29B is a perspective partial view and a cross-sectional view of sections of, or of, a complete second multi-gate device, which can be manufactured in accordance with various aspects of the present disclosure. The Fig. 30A and Fig. Figure 30B is a perspective partial view and a cross-sectional view of sections of, or a complete further embodiment of, a third multi-gate device which can be manufactured in accordance with various aspects of the present disclosure. The Fig. 31A and Fig. Figure 32B is a perspective partial view and a cross-sectional view of sections of, or a complete further embodiment of, a fourth multi-gate device which can be manufactured in accordance with various aspects of the present disclosure. Fig. Figure 32 is a partial cross-sectional view of a detailed view of a metallization of a multi-gate device in accordance with one or more aspects of the present disclosure. DETAILED DESCRIPTION

[0005] The present disclosure relates generally to integrated circuit components, and in particular to a metal gate cutting technique for multi-gate devices.

[0006] The following disclosure provides numerous different embodiments, or examples, for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, the formation of a first element above or on top of a second element in the following description may include embodiments in which the first and second elements are formed in direct contact with each other, but may also include embodiments in which additional elements may be formed between the first and second elements such that the first and second elements need not be in direct contact with each other. Furthermore, terms of spatial relationships, for example, "lower," "upper," "horizontal," "vertical," "above," "over," "below," "underneath," "upward," "downward," "above," "below," etc., are used., as well as their derivatives (for example, adverbial forms thereof, etc.), are used to simplify the present disclosure of the relationship of one feature to another feature. The terms spatial relationships are intended to cover different orientations of the device which has the features. Furthermore, when a numerical value or a range of numerical values ​​is described by "about," "approximately," and the like, the expression is intended to include numerical values ​​which are within a reasonable range by taking into account variations which, in accordance with the understanding of reasonably trained experts in the field, naturally occur during manufacturing.For example, the numerical value or range of numerical values ​​based on known manufacturing tolerances associated with the manufacture of a feature that has a property related to the numerical value includes a reasonable range around the described value, such as + / -10% of the described value. For example, a material layer having a thickness of "approximately 5 nm" may include a dimensional range of 4.5 nm to 5.5 nm if it is known to reasonably trained persons skilled in the art that manufacturing tolerances associated with the application of the material layer are + / -10%. Furthermore, the present disclosure may repeat reference numerals and / or symbols in the various examples. This repetition is for the purpose of simplification and clarity and does not in itself prescribe a relationship between the various embodiments and / or configurations discussed.

[0007] When constructing an integrated circuit, designs may include isolating certain gate structures from one another. To provide this isolation, processes sometimes referred to as gate-cutting techniques are used to separate and isolate a first gate structure over a first channel region from a second gate structure over a second channel region.A gate isolation feature or gate separator, which may be made of insulating layers, for example, can be formed to provide electrical isolation between the first gate, which may be located above a first channel layer of a first GAA device (i.e., a first active device area), and the second gate, which may be located above a second channel layer of a second GAA device (i.e., a second active device area), and the respective electrical contacts to these gates. In other sections of the device, the processes involve providing a third gate structure, which is electrically connected to another gate structure, such as the first gate structure.

[0008] In this context, it is important to recognize the crucial importance of providing processes, such as etching, that can form the separation structure between adjacent gates without affecting or damaging the gate itself. Unintended etching or gate loss during separation structure formation can lead to an unintended reduction in gate height, potentially impacting the expected reliability and / or performance of the device. The methods and devices discussed herein provide the ability to form a separation between gate structures while connecting other gate structures, thereby preventing material loss from the gate structure in some implementations. Avoiding material loss from the gate structure allows for a lower gate height in the device design, which in turn can provide improved AC performance.

[0009] Furthermore, it has also been recognized that the present disclosure, in some implementations, provides devices and methods that enable the cutting of gates, as well as certain gate connections, through self-aligning processes. The present disclosure thus provides techniques for multi-gate devices that allow for smaller distances between active device areas compared to the distances required between active device areas in non-self-aligning gate cutting techniques, where additional distances are necessary to compensate for misalignment in certain processes. Therefore, in some implementations, the proposed self-aligning gate cutting technique enables a reduction in dimensions, such as the metal gate dimensions, thereby increasing the structural density.Details of specific embodiments of the proposed self-aligning gate separation (or cutting) technique for multi-gate devices are described herein on the following pages. Likewise, details of specific embodiments of the proposed technique for forming a self-aligning electrical gate connection between gate structures for multi-gate devices, as well as the resulting multi-gate devices, are described herein on the following pages.

[0010] Now referring to Fig. Figure 1 shows a method 100 for manufacturing a semiconductor device 200, wherein a partial cross-sectional view of the same is shown in the Fig. 2 - 19, 20A, 21A, 22A, 23A, 24A, 25A, 26A, 27A and 28A are shown, and partial cross-sectional views of the same in the Fig. 20B, Fig. 21B, Fig. 22B, Fig. 23B, Fig. 24B, Fig. 25B, Fig. 26B, Fig. 27B, Fig. 28B and Fig. 32 are shown. Devices 200', 200'' and 200''' are shown in aspects of the figures mentioned above, as well as in the Fig. 29A / B, 30A / B and 31A / B, which are also exemplary devices that can be formed by aspects of method 100. It should be noted that the present examples of device 200 feature GAA devices, although aspects of the present disclosure can also be applied to other types of devices, such as fin-type field-effect transistors (FinFETs).

[0011] Method 100 serves only as an example and is in no way intended to limit the present disclosure to what is explicitly shown therein. Additional steps may be provided before, during, and after Method 100, and some of the described steps may be substituted, omitted, or postponed for additional embodiments of the method. For the sake of simplicity, not all steps are described in detail herein. Apart from what is explicitly shown in the figures of this disclosure, the semiconductor device 200 may include additional transistors, bipolar transistors, resistors, capacitors, diodes, fuses, etc. Unless otherwise stated or described, similar reference numerals throughout this disclosure denote similar features.Apart from the specifically stated differences of the exemplary devices 200, 200', 200'' and 200''', a description of one of these devices also applies to the other exemplary devices.

[0012] Method 100 begins at block 102, in which a substrate is taken up that has a plurality of fin structures formed on it. Referring to the example of Fig. 2. A substrate 202 is provided. In one embodiment, the substrate 202 can be a silicon substrate (Si substrate). In some other embodiments, the substrate 202 can contain other semiconductors, such as germanium (Ge), silicon germanium (SiGe), or a semiconductor material from Group III-V. Examples of Group III-V semiconductor materials include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium phosphide (GaInP), and indium gallium arsenide (InGaAs). The substrate 202 can also have an insulating layer, such as a silicon oxide layer, to exhibit a silicon-on-insulator (SOI) structure or a germanium-on-insulator (GeOI) structure.In some embodiments, the substrate 202 can have one or more well regions, such as n-well regions doped with an n-doper (i.e., phosphorus (P) or arsenic (As)) or p-well regions doped with a p-doper (i.e., boron (B)), to form different device types. An ion implantation process, a diffusion process, and / or another suitable doping process can be carried out to form the different doped regions.

[0013] Further referring to Fig. 2. A stack 204 of epitaxial layers can be arranged on the substrate 202. The stack 204 can have a plurality of channel layers 208, which are interspersed with a plurality of sacrificial layers 206. The channel layers 208 and the sacrificial layers 206 can have different semiconductor compositions. The sacrificial layers 206 and the channel layers 208 are deposited alternately, one after the other, to form the stack 204. In some reactions, the channel layers 208 are formed from silicon (Si), and the sacrificial layers 206 are formed from silicon germanium (SiGe). In some reactions, the additional germanium content in the sacrificial layers 206 allows the selective removal or deepening of the sacrificial layers 206 without causing significant damage to the channel layers 208, as discussed below.In some embodiments, the stack 204, comprising the sacrificial layers 206 and the channel layers 208, can be formed using an epitaxial process to deposit the materials. Example techniques include, but are not limited to, CVD deposition techniques (for example, vapor phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV CVD)), molecular beam epitaxy, and / or other suitable processes. It should be noted that three (3) layers of the sacrificial layers 206 and three (3) layers of the channel layers 208 are arranged alternately and vertically, as shown in [Figure]. Fig. Figure 2 is shown. However, this serves only for illustrative purposes and should in no way be considered a limitation of what is specifically set forth in the claims. The number of layers depends on the desired number of channel elements for the semiconductor device 200. In some embodiments, the number of channel layers 208 is between 2 and 10. For the purpose of structuring, a hard mask layer 210 can be arranged over the stack 204. The hard mask layer 210 can be a single layer or a multiple layer. In one embodiment, the hard mask layer 210 comprises a silicon oxide layer 210A and a silicon nitride layer 210B.

[0014] Block 102 of process 100 can include the formation of a plurality of fin structures extending across the substrate. Each fin structure defines an active region on the substrate. Referring to the example of Fig. 2. Fin structures 212 are formed from the epitaxial stack 204. Although two (2) or four (4) fin structures are shown in the exemplary figures, this is for illustrative purposes only and is not to be construed as limiting what is specifically set forth in the claims. The fin structures 212 can be produced using suitable processes, such as photolithography and etching processes. The photolithography process can include forming a photoresist layer arranged over the substrate 202, exposing the photoresist layer with a structure, performing post-exposure baking processes, and developing the photoresist layer to form a masking element comprising the photoresist layer. In some embodiments, the masking element further comprises the hard mask layer 210 discussed above.In some embodiments, the structuring of the photoresist layer to form the masking element can be performed using an electron beam lithography process. The fin structures 212 can be structured using suitable processes, such as dual or multiple structuring processes. Typically, dual or multiple structuring processes combine photolithography and self-aligning processes, thereby enabling the creation of structures with, for example, smaller spacing dimensions than those that could otherwise be achieved using a single, direct photolithography process. For example, in one embodiment, a material layer is formed over a substrate and structured using a photolithography process.Spacers are formed along the structured material layer using a self-aligning process. The material layer is then removed, and the remaining spacers, or mandrels, can then be used to structure the fins.Thus, example processes include a structuring lithography process (DPL process) (for example, a lithography-etch-lithography-etch process (LELE process), a self-aligning double structuring process (SADP process), a spacer-is-dielectric SADP process (SID SADP process), other double structuring processes or combinations thereof), a triple structuring process (for example, a lithography-etch-lithography-etch-lithography-etch process (LELELE process), a self-aligning triple structuring process (SATP process), other triple structuring processes or combinations thereof), other multiple structuring processes (for example, a self-aligning quadruple structuring process (SAQP process)) or combinations thereof.

[0015] The masking element(s) described above can then be used to protect areas of the stack 204 and / or the substrate 202 while the fin structures 212 are etched. Trenches 214 can be etched using dry etching (for example, chemical oxide removal), wet etching, reactive ion etching (RIE), and / or other suitable processes. Numerous other embodiments of methods for forming the fin structures 212 on the substrate 202 can also be used. The fin structures 212 extend vertically (Z-direction) above the substrate 202 and longitudinally along the Y-direction away from the substrate 202, and are spaced apart in the X-direction from neighboring fin structures 212. Each of the fin structures 212 has a base section formed from the substrate section 202' and an overlying section formed from materials of the stack 204.

[0016] In some embodiments, block 102 of method 100 comprises forming one or more layers on the etched fin structures. In some embodiments, an oxide lining layer (for example, silicon oxide) is formed over the substrate and the fin structures. In some embodiments, a silicon lining layer is formed over the substrate and the fin structures. Referring to Fig. 3. An oxide lining layer 216 and a silicon lining layer 218 are formed over the fin structures 212. In some embodiments, the oxide lining layer 216 and / or the silicon lining layer 218 are conformal layers having a substantially uniform thickness. In some embodiments, the silicon lining layer 218 and / or the oxide lining layer 216 are formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), high-density plasma evaporation (HDPCVD), metal-organic CVD (MOCVD), remote plasma evaporation (RPCVD), plasma-enhanced CVD (PECVD), low-pressure CVD (LPCVD), atomic layer CVD (ALCVD), atmospheric pressure CVD (APCVD), subatmospheric evaporation (SAVCD), other suitable methods, or combinations thereof. In some embodiments, the silicon lining layer contains 218 n-dopers and / or p-dopers.

[0017] Procedure 100 then continues at Block 104, in which isolation elements are formed between the majority of fin structures. These isolation elements can also be referred to as shallow trench isolation elements (STI elements). Referring to the example of Fig. 4. An insulating layer 402 is formed between the fin structures 212 and within the grooves 214. In one embodiment, the insulating material is a multilayer, comprising, for example, a lining layer and an overlying layer, such as an oxide material. In some embodiments, the oxide material is applied by a flowable CVD process (FCVD process), which includes, for example, applying a flowable oxide material (e.g., in a liquid state) over the multi-gate device 200 and converting the flowable oxide material into a solid oxide material by an annealing process. The flowable oxide material can flow into grooves 214 and conform to exposed surfaces of the multi-gate device 200, thereby enabling void-free filling of the grooves 214 in some implementations.

[0018] In some embodiments, the insulating material forming the insulating layer 402 can comprise SiO2, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a dielectric with a low k-value, combinations thereof, and / or other suitable materials known in the field. In various examples, the dielectric material can be applied by a CVD process, a subatmospheric CVD process (SACVC process), a flowable CVD process, an ALD process, a PVD process, or another suitable process.

[0019] The deposition process can overfill the trenches 214 (not shown) such that the thickness of the material for the insulation feature 402 is greater than the height of the fins 212. After the deposition process, a planarization process, such as a chemical-mechanical polishing (CMP) process, is performed on the materials, thereby reducing the thickness. In some embodiments, the silicon lining layer 218 serves as an etch stop layer, and the planarization prevents the exposure of the silicon lining layer 218 above the fin structures 212. This planarization forms a surface, such as the one shown in Fig. 4 shown.

[0020] Now referring to Fig. 5. The insulating material(s) can then be recessed such that fin structures 212 extend (protrude) between the insulating elements formed by the insulating layer 402. The etching process for recessing the insulating material is designed to selectively remove material (for example, oxide) with respect to the silicon lining layer 218. For the etching process, for example, an etchant is selected which etches silicon oxide (i.e., that of the insulating feature 402) at a higher rate than silicon (i.e., that of the silicon lining layer 218). Thus, the insulating elements 402 fill sections of the trenches 214 between the fin structures 212. In some embodiments, a field oxide, a LOCOS feature, and / or other suitable insulating elements can additionally or alternatively be implemented on and / or within the substrate.

[0021] Process 100 then continues at block 106, where a mantle layer is formed over the fin structure. The mantle layer can be a sacrificial layer. The mantle layer can be formed over any of the fin structures. Referring to the example of Fig. 6 A shell layer 602 is formed on each of the fin elements 212. In some embodiments, the shell layer 602 can have a composition similar to that of the sacrificial layers 206. In one embodiment, the shell layer 602 is formed of silicon germanium (SiGe). In some implementations, the shell layer 602 and the sacrificial layers 206 contain a composition that allows selective removal of the sacrificial layers 206 and the shell layer 602 during the release of the channel layers 208 in a subsequent process by a single etching agent, as discussed below.In one embodiment, the cladding layer 602 can be epitaxially grown using vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or can be formed by a deposition process such as a CVD process, a subatmospheric CVD process (SACVD process), a flowable CVD process, an ALD process, a PVD process, or another suitable process. Following deposition, the operations at block 106 in some embodiments may include etch-back processes to remove material from the cladding layer 602, which, for example, was conformally deposited, from the insulating feature 402. In some implementations, block 106 may be omitted.

[0022] Method 100 then continues at block 108, in which separation structures, also known as dielectric fins, are formed between the upper sections of the fin structures, thereby separating the adjacent active areas from one another. The separation structures can have a multilayered structure that fills the gap between fin structures and is arranged above the STI elements of block 104. Fig. Figures 7-10 represent an embodiment for forming a multilayer separation structure or dielectric fins between active areas. Referring first to the example of Fig. 7 A first dielectric layer 702 is applied over the device 200. In one embodiment, the first dielectric layer is a dielectric with a high k-value. In another embodiment, the first dielectric layer 702 can be silicon nitride, silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), or combinations thereof. In some embodiments, the dielectric layer 702 contains HfO₂, HfSiO₂, HfSiO₄, HfSiON₄, HfLaO₂, HfTaO₂, HfTiO₂, HfZrO₂, or HfAlO₂. x ZrO, ZrO2, ZrSiO2, AlO, AlSiO, Al2O3, TiO, TiO2, LaO, LaSiO, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3, (Ba,Sr)TiO3, HfO2-Al2O3, another suitable dielectric material with a high k-value, or combinations thereof. After the first layer, referring to the example of Fig. 8. An oxide layer 802 is formed over the first dielectric layer 702. In some embodiments, the oxide layer 802 can be applied by a flowable CVD process, HARP, and / or another process that provides suitable gap-filling properties. In some implementations, the trenches 214 can be overfilled with the oxide layer, and after deposition of the oxide layer 802, a CMP process can be carried out, which provides a substantially planar top surface, as shown in Fig. Figure 8 shows that in one embodiment, the cladding layer 602 provides an etching stop for this planarization process.

[0023] Referring to Fig. 9. Layers 702 and / or 802 are back-etched to form an opening 902. In one embodiment, the oxide layer 802 is removed to form the opening 902, which has side walls defined by the first dielectric layer 702 and bounded by the grooves 214. The etching process for forming the opening 902 can be a dry etching process, a wet etching process, or a combination thereof.

[0024] As in Fig. As shown in Figure 10, a dielectric material 1002 is formed within the opening 902. The dielectric material 1002 can be applied such that the opening 902 overflows, and subsequently, excess material can be removed by a planarization process. In one embodiment, the dielectric material 1002 is a dielectric with a high k-value. In some embodiments, the dielectric material 1002 has essentially the same composition as the first dielectric layer 702. In one embodiment, the dielectric material 1002 can be silicon nitride, silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), or combinations thereof. In some embodiments, the dielectric layer 702 contains HfO₂, HfSiO₂, HfSiO₄, HfSiON, HfLaO, HfTaO, HfTiO₂, HfZrO₂, or HfAlO₂. xZrO, ZrO2, ZrSiO2, AlO, AlSiO, Al2O3, TiO, TiO2, LaO, LaSiO, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3, (Ba,Sr)TiO3, HfO2-Al2O3, another suitable dielectric material with a high k-value, or combinations thereof. The dielectric material 1002 can be deposited by a suitable process, such as a subatmospheric CVD process (SACVC process), a flowable CVD process, another CVD process, an ALD process, a PVD process, or another suitable process. In some reactions, a planarization process is carried out after deposition, in which the deposited dielectric material 1002 is diluted to provide a planar top surface. In some implementations, the planarization process may end at hard mask 210.

[0025] The dielectric layers 702, 802, and 1002 discussed above together form the separation structure, which is referred to as the dielectric fin 1004. The dielectric fin 1004 extends between adjacent active regions, the fin structures 212, and between sections of the cladding layer 602. Like the fin structures 212, the dielectric fin 1004 extends vertically (Z-direction) over the substrate 202 (in particular over the insulating structure 402) and longitudinally along the Y-direction from the substrate 202, and is spaced apart in the X-direction from the adjacent dielectric fin 1004.

[0026] In some embodiments, after forming the separation structure or dielectric fin 1004 and before forming the dummy gate, the hard mask and adjacent cladding layers are etched to form an opening 1102, as shown in Fig. Figure 11 shows that in some embodiments the etching exposes an upper surface of a channel area on which the gate structure can be formed, as discussed below.

[0027] Procedure 100 then continues at block 110, in which a dummy gate is formed over the fin structures. Referring to Fig. The dummy gate structures 1202 are formed over sections of the fins 212 and the dielectric fins 1004. The dummy gate structures 1202 fill sections of the openings 1102 and can extend over the dielectric fins 1004. The dummy gate structures 1202 extend longitudinally in a direction that differs from the longitudinal direction of the fin structures 212 (for example, perpendicular to them). For example, the dummy gate structures 1202 extend substantially parallel to each other along the X-direction and have a length defined in the X-direction, a width defined in the Y-direction, and a height defined in the Z-direction. The dummy gate structures 1202 are arranged above channel areas of the multi-gate device 200 and between source / drain areas (S / D areas) of the multi-gate device 200, which have been exposed by a remainder of the openings 1102.Each of the dummy gate structures 1202 comprises a dummy gate dielectric 1204, a dummy gate electrode 1206, and a hard mask 1208 (which, for example, has a first mask layer 1208A and a second mask layer 1208B, and in some embodiments, a pad oxide 1208A and a pad nitride 1208B). The dummy gate dielectric 1204 contains a dielectric material, such as silicon oxide, a high k-value dielectric material, another suitable dielectric material, or combinations thereof. In some embodiments, the dummy gate dielectric 1204 has an interface layer (which, for example, contains silicon oxide) and a high k-value dielectric layer arranged above the interface layer. The dummy gate electrode 1206 contains a suitable dummy gate material, such as polysilicon.In some embodiments, the dummy gate structures 1202 have numerous additional layers, such as cladding layers, interface layers, diffusion layers, barrier layers, or combinations thereof. The dummy gate structures 1202 are formed by deposition processes, lithography processes, etching processes, other suitable processes, or combinations thereof. For example, a first deposition process is carried out to form a dielectric dummy gate layer over the multi-gate device 200, a second deposition process is carried out to form a dummy gate electrode layer over the dielectric dummy gate layer, and a third deposition process is carried out to form a hard mask layer over the dummy gate electrode layer. In one embodiment, the hard mask layer 1208 comprises a silicon oxide layer 1208A and a silicon nitride layer 1208B.The deposition processes include CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, plating, other suitable processes, or combinations thereof. A lithography structuring and etching process is then performed to structure the hard mask layer, the dummy gate electrode layer, and the dielectric dummy gate layer to form the dummy gate structures 1202, which comprise the dummy gate dielectric 1204, the dummy gate electrode 1206, and the hard mask 1208, as shown in [reference missing]. Fig. Figure 12 illustrates the lithographic texturing processes. These include photoresist coating (e.g., spin coating), soft firing, mask alignment, exposure, post-exposure firing, photoresist development, rinsing, drying (e.g., hard firing), other suitable lithographic processes, or combinations thereof. Etching processes include dry etching, wet etching, other etching methods, or combinations thereof.

[0028] Now referring to Fig. 13. The dummy gate structures 1202 can further comprise gate spacers 1302 formed along side walls of the dummy gate stacks 1202. The gate spacers 1302 can be formed from a suitable dielectric material. The dielectric material can contain silicon, oxygen, carbon, nitrogen, another suitable material, or combinations thereof (for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbon nitride, silicon oxycarbide, and / or silicon oxycarbon nitride). In some embodiments, the gate spacers 1302 have a multilayer structure, such as a first dielectric layer containing silicon nitride and a second dielectric layer containing silicon oxide.In some embodiments, more than one set of spacer elements, such as sealing spacer elements, compensating spacer elements, sacrificial spacer elements, dummy spacer elements and / or principal spacer elements, is formed adjacent to the dummy gate structures 1202.

[0029] Procedure 100 then continues at block 112, in which the source / drain areas of the fin structures adjacent to the dummy gate structures are deepened. Fig. 13. Sections of the fin structures 212 in the source / drain regions of the multi-gate device 200 (that is, source / drain regions of the fin structures 212 that are not covered by the gate structures 1202) are also at least partially removed to form source / drain depressions or grooves 1304. In the illustrated embodiment, an etching process completely removes the semiconductor layer stack 204 in the source / drain regions of the multi-gate device 200, thereby exposing fin sections 202' in the source / drain regions. In some embodiments, the etching process also completely removes sections of the cladding layer 602 in the source / drain regions. Thus, in the illustrated embodiment, each of the source / drain recesses 1304 has a side wall defined by a respective dielectric fin 1004 and a bottom defined by a respective fin section 202' and a respective insulation feature 402.The etching process may include a dry etching process, a wet etching process, another suitable etching process, or combinations thereof. In some embodiments, the etching process is a multi-stage etching process.

[0030] Referring to the Fig. 14 and Fig. In some embodiments, section 15 further comprises the slight (lateral) etching of the sacrificial layers 206 to form an opening 1402 (for example, beneath the gate structure 1202, which includes the gate spacer elements 1302). The openings 1402 are formed between freely arranged end regions of the channel layers 208. Internal spacer elements 1502 may be formed within the opening 1402. In some embodiments, the internal spacer element contains a dielectric material comprising silicon, oxygen, carbon, nitrogen, another suitable material, or combinations thereof (for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, and / or silicon oxycarbonitride). In some embodiments, the internal spacer elements 1502 contain a dielectric material with a low k-value, such as those described herein.

[0031] Procedure 100 then continues at block 114, in which the source / drain elements are grown in the source / drain regions of the fin structures. Referring to Fig. 16. Epitaxial source / drain elements 1602, designated 1602A and 1602B respectively, are formed in the source / drain depressions 1304. In some reactions, a semiconductor material is epitaxially grown from a seeding area, which has the exposed area of ​​the fin sections 202' of the substrate 202, whereby epitaxial source / drain elements 1602A, which correspond to a first type of transistor, such as an n-transistor, are formed in the source / drain depressions 1304, and epitaxial source / drain elements 1602B, which correspond to a second type of transistor, such as a p-transistor, are formed in the source / drain depressions 1304. In some implementations, the epitaxy process for forming the source / drain elements can use CVD deposition techniques (for example, LPCVD, VPE and / or UHV-CVD), molecular beam epitaxy, other suitable epitaxial growth processes, or combinations thereof.The epitaxial process can utilize gaseous and / or liquid precursors that interact with the composition of the seeding region(s). The epitaxial source / drain elements 1602 are doped with n-type and / or p-type dopants. In some embodiments for the n-transistors, the epitaxial source / drain elements 1602A contain silicon doped with carbon, phosphorus, arsenic, other n-type dopants, or combinations thereof (for example, to form epitaxial Si:C source / drain elements, epitaxial Si:P source / drain elements, or epitaxial Si:C:P source / drain elements). In some embodiments for p-transistors, the epitaxial source / drain elements contain 1602B silicon germanium or germanium doped with boron, another p-dopant, or combinations thereof (for example, to form epitaxial Si:Ge:B source / drain features).In some embodiments, the epitaxial source / drain features 1602 have more than one epitaxial semiconductor layer, wherein the epitaxial semiconductor layers may have the same or different materials and / or dopant concentrations. In some embodiments, the epitaxial source / drain elements 1602 are doped during deposition by adding impurities to a starting material of the epitaxial process (i.e., in situ). In some embodiments, the epitaxial source / drain elements 1602 are doped by an ion implantation process following a growth process. When epitaxial source / drain elements of different device types are formed, in some embodiments the epitaxial source / drain elements 1602A are formed in processing sequences that are independent of those for the epitaxial source / drain elements 1602B.

[0032] The process 100 then continues at block 116, in which insulating materials are formed on the substrate, including over the source / drain elements. These insulating materials can subsequently form a contact element with the source / drain elements. The insulating materials provide insulation between the source / drain contact and, for example, the adjacent gate structure. The insulating materials can be described as a contact etch stop layer (CESL) and a dielectric intermediate layer (ILD). The CESL can be used as an etch stop during the formation of contact elements with the source / drain elements (not shown). Referring to the example of Fig. 17. One or more deposition processes (such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, FCVD, HARP, HDP, other suitable processes, or combinations thereof) are carried out to form dielectric layers 1702 and 1704 on the device 200. In one embodiment, the dielectric layer 1704 is an intermediate dielectric layer (ILD layer), and the dielectric layer 1702 is a bottom contact etch stop layer (B-CESL).The dielectric layer 1704 can comprise a dielectric material, which may include, for example, silicon dioxide, carbon-doped silicon dioxide, silicon nitride, silicon oxynitride, TEOS-formed oxide, PSG, BSG, BPSG, FSG, Black Diamond® (Applied Materials in Santa Clara, California), xerogel, aerogel, amorphous fluorinated carbon, parylene, BCB-based dielectric material, SiLK (Dow Chemical, Midland, Michigan), polyimide, another suitable dielectric material, or combinations thereof. In some embodiments, the dielectric layer 1704 may comprise a dielectric material with a dielectric constant that is less than that of silicon dioxide (for example, k < 3.9).In some embodiments, the dielectric layer 1704 contains a dielectric material having a dielectric constant of less than approximately 2.5 (that is, an extremely low k-value dielectric material (ELK dielectric material)), such as silicon dioxide (SiO2) (for example, porous silicon dioxide), silicon carbide (SiC), and / or carbon-doped oxide (for example, a SiCOH-based material (which, for example, has Si-CH3 bonds)), each of which is designed to have a dielectric constant of less than approximately 2.5. The dielectric layer 1702 contains a material that differs from that of the dielectric layer 1704. Exemplary compositions of the dielectric layer 1702 include, but are not limited to, silicon nitride or silicon oxynitride.

[0033] In some implementations, a CMP process and / or another planarization process is performed after deposition until upper sections of the dummy gate structures 1202 have been exposed. In some embodiments, the planarization process removes the hard mask layers 1208 of the dummy gate structures 1202 to expose the underlying dummy gate electrodes 1206 (for example, polysilicon).

[0034] Then, the process 100 continues with block 118, in which openings for a metal gate structure are formed, the dummy gate structure is removed, and the channel layers within the channel area of ​​the fin structure are released. In one embodiment of block 118, the dummy gate structure of block 110 is removed. Referring to the example of Fig. In step 18, the dummy gate structure 1202 is removed to form the opening 1802, as shown in Fig. 18 shown. It should be noted that Fig. 18, as well as the following figures, a perspective view with a section through the channel area offset from the source / drain elements 1602, to the in Fig. 17, which is why these are not visible. In some embodiments, for example, the etching process, as shown, does not remove the dummy gate dielectric 1204 when the gate electrode 1206 is removed. In some embodiments, the etching process or a subsequent etching process partially or completely removes the dummy gate dielectric 1204. The etching process(es) can be a dry etching process, a wet etching process, or a combination thereof.

[0035] Referring to the example of Fig. 19. A channel release process can involve the removal of the sacrificial layers 206 in the channel region, thereby forming freely arranged semiconductor layers 208 in the channel region, which are spaced apart from each other and / or from the fin sections 202' by gaps. The etching process that releases the channel layers 208 is a dry etching process, a wet etching process, or a combination thereof. The channel release process can further include the removal of the cladding layer 602 in the channel region. The channel release process can be an etching process selective for a composition (for example, silicon-germanium) of the cladding layer 602 and / or the sacrificial layers 206, while no or only minimal etching of the channel layers 208 takes place. The release of the channel layers, the removal of the dummy gate structure, and the removal of the cladding layer 602 create respective openings 1902 in the channel region of the device 200, as shown in Fig. 19 shown.

[0036] In some implementations, the dielectric fin 1004 is not removed between adjacent channel regions of a different device type (for example, type n or type p) and thus continues to provide insulation between adjacent devices of different types. In some embodiments, the dielectric fin 1004 is also not removed between adjacent channel regions of the same device type (for example, type n or type p), and any intermediate connection of the gate structure for those devices can be provided not by the gate electrode structure itself, but by a metallization formed over the dielectric fin 1004 as discussed below.

[0037] The process 200 then continues at block 120, in which a metal gate structure is formed in the openings created at block 118. The metal gate structure can be the functional gate(s) of the completed device 200. Referring to the example of Fig. 20A and Fig. Figure 20B shows metal gate structures 2002 formed in the openings 1902 created at Block 118. The metal gate structures 2002 are designed to achieve the desired functionality in accordance with the design requirements of the multi-gate device 200. Each metal gate structure 2002 comprises a gate dielectric 2004 (for example, high k-value dielectric gate layers or interface layers such as silicon oxide or silicon oxynitride) and a gate electrode 2006 (for example, an exit working layer and a bulk conductive layer). The metal gate structures 2002 can include numerous other layers, such as cladding layers, interface layers, diffusion layers, barrier layers, hard mask layers, or combinations thereof.In some embodiments, the formation of the metal gate structures 2002 comprises the application of a dielectric gate layer 2004 over the channel regions, wherein the dielectric gate layer partially fills gaps between the channel layers 208, and the application of a gate electrode layer 2006 over the dielectric gate layer 2004, wherein the gate electrode layer fills a remainder of the gaps between the channel layers 208.

[0038] The gate dielectric 2004 features a high-k dielectric layer containing a high-k dielectric material. For the purposes of the metal-gate structure 2002, this dielectric material should have a dielectric constant greater than that of silicon dioxide (k ≈ 3.9). For example, the high-k dielectric gate layer contains HfO₂, HfSiO₂, HfSiO₄, HfSiON₄, HfLaO₂, HfTaO₂, HfTiO₂, HfZrO₂, and HfAlO₂. xZrO, ZrO2, ZrSiO2, AlO, AlSiO, Al2O3, TiO, TiO2, LaO, LaSiO, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3 (BTO), (Ba,Sr)TiO3 (BST), Si3N4, hafnium dioxide-aluminum oxide alloy (HfO2-Al2O3), another suitable high k-value dielectric material for metal gate stacks, or combinations thereof. The high k-value dielectric layer is formed by any of the processes described herein, such as ALD, CVD, PVD, an oxidation-based deposition process, another suitable process, or combinations thereof. For example, an ALD process deposits the high k-value dielectric layer. In some embodiments, the ALD process is a conformal deposition process such that the thickness of the high k-value dielectric layer is essentially uniform (conformal) over the various surfaces of the multi-gate device 200.In some embodiments, the gate dielectric 2004 has an interface layer located between the high k-value dielectric layer and the channel layers 208. The interface layer contains a dielectric material, such as SiO2, HfSiO, SiON, another silicon-containing dielectric material, another suitable dielectric material, or combinations thereof. The interface layer is formed by any of the processes described herein, such as thermal oxidation, chemical oxidation, ALD, CVD, another suitable process, or combinations thereof. For example, the interface layer is formed by a chemical oxidation process that exposes exposed surfaces of the channel layers 208 to hydrofluoric acid.In some embodiments, the interface layer is formed by a thermal oxidation process that exposes the exposed surfaces of the channel layers 208 to an oxygen and / or air environment. In some embodiments, the interface layer is formed after the formation of the high k-value dielectric layer. For example, in some embodiments, the multi-gate device 200 can be annealed in an oxygen and / or nitrogen environment (for example, nitrogen oxide) after the formation of the high k-value dielectric layer.

[0039] The gate electrode 2006 is formed above the gate dielectric 2004, fills a remainder of the gate openings 1902, and surrounds the channel layers 208 such that the gate electrode 2006 fills a remainder of the gaps between the channel layers. The gate electrode 2006 contains a conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, other conductive materials, or combinations thereof. In some embodiments, the gate electrode 2006 has an exit working layer and a conductive bulk layer. The work function layer is a conductive layer designed to exhibit a desired work function (for example, an n-work function or a p-work function), and the conductive volume layer is a conductive layer formed above the work function layer.In some embodiments, the exit layer contains n-exit work materials, such as Ti, silver, manganese, zirconium, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, other suitable n-exit work materials, or combinations thereof. In some embodiments, the exit layer contains a p-exit work material, such as ruthenium, Mo, Al, TiN, TaN, WN, ZrSi2, MoSi2, TaSi2, NiSi2, other suitable p-exit work materials, or combinations thereof. The conductive bulk layer (or filler layer) contains a suitable conductive material, such as Al, W, Ti, Ta, polysilicon, Cu, metal alloys, other suitable materials, or combinations thereof. The gate electrode 2006 is formed by any of the processes described herein, such as ALD, CVD, PVD, plating, another suitable process, or combinations thereof.In one implementation, a planarization process is performed to remove some excess gate material from the multi-gate device 200. For example, a CMP process is performed such that, after the CMP process, a top surface of the gate structures 2002 is essentially planar with a top surface of the ILD layer 1704.

[0040] Referring to the example of the Fig. 21A and Fig. In step 21B, the gate structure 2006 is back-etched such that an upper surface of the metal gate structure 2002 is substantially coplanar with an upper surface of the dielectric fin 1004. This leaves an opening 2102 positioned above the metal gate structure 2600. The dielectric fins 1004 extend between the metal gate structures 2002 in various channel regions. For example, a back-etching process is performed to deepen the gate electrodes 2006 until the upper surfaces of the dielectric fins 1004 are free of the gate electrode material 2006.

[0041] In some embodiments, the gate structure 2006 is further recessed by an upper surface of the dielectric fins 1004, and one or more additional layers are formed on the recessed gate structure 2006. In one embodiment, an inoculation layer is arranged over the metal gate structure and adjacent to the dielectric fin. The inoculation layer can be Ti, TiN, TaN, W, Ru, and / or combinations thereof. Exemplary thicknesses of the inoculation layer are in the range of approximately 1 nm to 2 nm. In some embodiments, the thickness is chosen such that sufficient thickness is provided for adhesion to an overlying layer and for the desired resistivity of the overlying metallization discussed below.The deposition processes of the vaccine layer can include CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, PEALD, electroplating, electroless plating, other suitable deposition methods, or combinations thereof. Fig. 30A and Fig. Figure 30B represents an inoculation layer 2602 formed over the gate electrode 2006 and having side walls that abut the dielectric fins 1004, thus representing the recessed gate structure 2006 on which the inoculation layer 2602 is arranged. Although in some implementations the inoculation layer 2602 of the Fig. 30A and Fig. 30B is formed before the application of the dummy layer 2202 discussed herein, the inoculation layer 2602 is formed as described in the Fig. 30A and Fig. 30B shown in other embodiments formed after the gate separating element.

[0042] In some implementations, the gate structure is further recessed from an upper surface of the dielectric fins 1004, and an etch stop layer is placed over the metal gate structure and adjacent to the dielectric fin. The etch stop layer may comprise a metal nitride and / or other suitable compositions. The etch stop layer is conductive to allow for an intermediate connection of the gate structure. The deposition processes for the etch stop layer may include CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, PEALD, electroplating, electroless plating, other suitable deposition methods, or combinations thereof. Fig. 31A and Fig. Reference 32A provides an example of an etch stop layer 3102 over the gate structure 2002 adjacent to the dielectric fins 1004. The etch stop layer 3102 can provide additional protection for the gate structure 2002 when the trenches 2302 are etched, as discussed below. Thus, the etch stop layer 3102 can have a composition chosen to provide etch selectivity with respect to the dummy layer 2202.

[0043] After the etching process(s) and / or planarization, adjacent gate electrodes 2006 cannot extend between a first channel region (fin 212) and a second channel region (adjacent fin 212). In other words, the conductivity of the gate structures 2002 between adjacent channel regions is interrupted (for example, by the dielectric fins 1004). Thus, at this stage of the process 100, the gate electrodes 2006 are electrically isolated from each other in some embodiments. The metal-gate cutting or separation process can be described as "self-aligning" because gate isolation structures (in this case, the dielectric fins 1004) align between adjacent metal-gate structures 2002 without the need for a lithography process after the metal-gate structures 2002 have been formed.The self-aligning placement of the dielectric fins 1004 provides electrical insulation between components in adjacent active areas.

[0044] Method 100 then continues at block 122, in which a dummy material layer is formed over the gate structure. In one embodiment, the dummy material layer is silicon. In other embodiments, the dummy material comprises SiO₂, SiN, SiC, SiCN, SiON, SiCN, SiOCN, AlO, AlN, AION, ZrO₂, ZrN, ZrAlO₂, HfO₂, and / or other suitable materials. The dummy material can be a sacrificial material and can be selected such that it exhibits suitable etch selectivity, for example, when forming the trenches discussed in block 124. In one embodiment, the dummy layer exhibits high etch selectivity with respect to the material of the metal gate structure 2002 and, in particular, the gate electrode 2006. The dielectric material layer can be applied using rotational coating, CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, PEALD, other suitable deposition methods or combinations thereof.Referring to the example of the . Fig. 22A and Fig. 22B forms a dummy layer 2202. In some implementations, a planarization process, such as CMP, is performed after deposition to remove excess dummy material and provide a planar top surface, as in the Fig. 22A and Fig. 22B shown.

[0045] Method 100 then continues at block 124, in which a plurality of trenches defining gate separation regions are formed in the dummy layer. The gate separation regions are those areas designated as sections of the device in which adjacent gate structures (for example, of neighboring GAA devices) are to be isolated from one another. In some embodiments, the gate separation regions are arranged between a device of a first type (for example, n-FET) and a device of a second type (for example, p-FET). The plurality of trenches defining the gate separation regions can be formed by creating a structure of features above the dummy layer. In some embodiments, masking elements are provided to define openings above the dummy layer into which a plurality of trenches are to be etched.In some embodiments, the photolithography processes may include forming a photoresist layer arranged over the device 200 and the dummy layer 2202, exposing the photoresist layer with a structure, performing post-exposure baking processes, and developing the photoresist layer to form a masking element which includes the photoresist layer.

[0046] According to the structure provided by the photoresist layer, trenches are etched into the dummy layer. Referring to the example of the Fig. 23A and Fig. In 23B, trenches 2302 are formed in the dummy layer 2202, extending to the dielectric layer 1002 and / or the top surface of the dielectric fin 1004. Due to the composition of the dummy layer 2202 and the gate structure 2002, in particular the gate electrode 2006, and the etch selectivity existing between them, it is possible in some embodiments to form trenches 2302 such that substantially no material of the metal gate structure 2002 is etched. In some embodiments, due to the composition of the dummy layer 2202 and the dielectric layer 1002, and the etch selectivity existing between them, it is possible in some embodiments to form the trenches 2302 such that the dielectric layer 1002 remains substantially unetched. The etching process may include a dry etching process.

[0047] Procedure 100 then continues at Block 126, where the trenches are filled with one or more dielectric materials to form a gate separator. Examples of dielectric materials for filling the trenches include SiO₂, SiN, SiC, SiCN, SiON₂, SiCN, SiOCN, AlO₂, AlN, AlON₂, ZrO₂, ZrN, ZrAlO₂, HfO₂, and / or combinations thereof. Examples of deposition techniques include CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, PEALD, or other suitable deposition methods. After deposition, planarization or another etching process can remove excess material to form the gate separator.

[0048] Referring to the example of the Fig. 24A and Fig. In 24B, dielectric material is formed in the grooves 2302 to create the gate separators 2402. In some implementations, the gate separators 2402 are a multilayer component. The dielectric material can be deposited by various deposition methods and subsequently planarized, for example by CMP, to provide a planar top surface with the dummy layer 2202, as in the Fig. 24A and Fig. 24B shown.

[0049] After applying material to the trenches, the remaining dummy layer is removed. The dummy layer can be removed by a suitable selective etching process, such as dry etching, wet etching, or peeling. As in the example of the Fig. 25A and Fig. In 25B, the dummy layer 2202 is then removed. In some implementations, the dummy layer 2202 is removed without affecting the gate (for example, by etching).

[0050] Method 100 then continues at block 128, in which at least one metallization layer is formed over the gate structures. In some implementations, at least one metallization layer is formed over adjacent gate structures and extends between them. In other words, the metallization layer(s) can be arranged over and in contact with a first gate structure of a first device and extend such that they are arranged over and in contact with a second, adjacent gate structure of a second device, thereby electrically connecting the two gate structures. Between the two connected gate structures, the metallization layer(s) extends over the dielectric fin between the active regions of the adjacent devices.Due to the gate isolators discussed above in Block 126, other adjacent gate structures (for example, a third gate structure on one side opposite the first gate structure) can be isolated from each other by the interposed gate isolator. In other words, the metallization layer(s) do not extend between certain gates of devices that have the interposed gate isolator, thus preventing any electrical connection between said gates. The structuring of the gate structures to be connected or isolated is determined by the device design and is defined by the structure that forms the trenches in Block 124, thereby creating the gate isolators.

[0051] Referring to the example of the Fig. 26A and Fig. In one embodiment, a first conductive layer, which is referred to as the inoculation layer 2602, and a metallization layer 2604 are formed on the device 200. As in Fig. As shown in Figure 26A, the inoculation layer 2602 and the metallization layer 2604 can extend between certain gate structures 2002, such as from a first gate structure designated 2002A to a second gate structure designated 2002B, and between a third gate structure 2002C and a fourth gate structure 2002D. The gate separator 2402 is positioned between the second gate structure 2002B and the third gate structure 2002C such that the metallization of layers 2602 and 2604 does not extend between gate structures 2002B and 2002C. Thus, the metallization layers 2602 and 2604 each have a termination end that rests against the gate separator 2402. Here too, each of the gate structures 2002A, 2002B, 2002C, 2002D provides a gate structure for a GAA component of the device 200.

[0052] The inoculation layer 2602 can contain Ti, TiN, TaN, W, Ru, and / or combinations thereof. Exemplary thicknesses range from approximately 1 nm to 2 nm. In some implementations, the thickness is chosen to provide sufficient adhesion to an overlying layer and the desired resistivity of the metallization stack. The metal layer 2604 can contain W, Ru, Co, and / or combinations thereof. Exemplary thicknesses range from approximately 2 nm to 5 nm. In some implementations, the thickness is chosen to provide sufficient conductivity to an adjacent gate stack. The deposition processes of the inoculation layer 2602 and / or the metallization layer 2604 may include CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, PEALD, electroplating, electroless plating, other suitable deposition methods or combinations thereof.In some implementations, the material for the inoculation layer 2602 is applied and then etched back to ensure it is positioned within the relevant openings.

[0053] In one embodiment, the inoculation layer 2602 is omitted, while the metal layer 2604 provides the at least one metallization layer which connects a subset of the gates. This is demonstrated, for example, by the embodiment of the device 200' in the Fig. 23A and Fig. 23B shown. The metallization layer 2604 of the device 200' in the Fig. 23A and Fig. 23B may be essentially the same as discussed above with regard to device 200.

[0054] Process 100 then continues with block 130, in which an insulating layer is formed over the metallization layer(s) of block 128. Examples of insulating layer materials include SiO₂, SiN, SiC, SiCN, SiON₂, SiCN, SiOCN, AlO₂, AlN, AION, ZrO₂, ZrN, ZrAlO₂, HfO₂, and / or combinations thereof. The insulating material can be applied by spin coating, HARP, CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, PEALD, and / or other suitable methods. In some implementations, the insulating material is back-etched after deposition, for example, by a planarization process (e.g., CMP), to provide a top surface that is substantially coplanar with the gate separator. Referring to the example of the Fig. 27A and Fig. In 27B, the insulating layer 2702 is formed over the seeding / metallization layers 2602 and 2604 and adjacent to the gate separator 2402. In some embodiments, the insulating layer 2702 has the same composition as the gate separator 2402. In other embodiments, the insulating layer 2702 differs from the gate separator 2402 in its composition.

[0055] In one embodiment, the insulating layer 2702 can be in contact with the gate spacer elements, which in turn are in contact with the B-CESL 1702, which is adjacent to the ILD 1704.

[0056] The process 100 then continues with block 132, in which a contact element is formed with respect to the metallization layer(s) of block 128. Referring to the example of the Fig. 28A and Fig. 28B forms a contact element 2802 for connection to the metallization layer 2604. The contact element 2802 can provide a path for an electrical connection from a multilayer interconnect (MLI) formed above the device 200 to the gate structures 2002.

[0057] An MLI electrically couples various devices (for example, p-transistors and / or n-transistors of the Multi-Gate Device 200, resistors, capacitors, and / or inductors) and / or components (for example, gate electrodes and / or epitaxial source / drain elements of p-transistors and / or n-transistors) to each other in such a way that the various devices and / or components can operate according to the specifications defined by the design requirements of the Multi-Gate Device 200. An MLI element typically has a combination of dielectric layers and electrically conductive layers (for example, metal layers) configured to form various interconnect structures. The conductive layers are configured to form vertical interconnect elements, such as contacts and / or vias at the device level, and / or horizontal interconnect elements, such as conductor tracks.Vertical interconnect elements typically connect horizontal interconnect elements in different layers (or different levels) of the MLI. During operation, the interconnect elements are configured to relay signals between the components of the Multi-Gate Device 200, and / or to distribute signals (for example, clock signals, voltage signals, and / or ground signals) to the components of the Multi-Gate Device 200.

[0058] In some embodiments, the contact is formed by first etching a via into the insulating layer, extending to the metallization layer(s) above the gate structure. In some embodiments, the via is defined by a photolithography process. The lithography processes may include forming a photoresist layer over the insulating layer 2702, exposing the photoresist layer with structured radiation, and developing the exposed photoresist layer, thereby forming a structured photoresist layer that can be used as a masking element for etching one or more contact openings extending through the insulating layer 2702 to expose the metallization layer(s) for the device 200, in particular at least to the metal layer 2604. The etching processes include dry etching processes, wet etching processes, other etching processes, or combinations thereof.The contact opening(s) are then filled with one or more electrically conductive materials, such as tungsten, ruthenium, cobalt, copper, aluminum, iridium, palladium, platinum, nickel, another metallic component with low resistivity, alloys thereof, or combinations thereof. The conductive material(s) can be applied by PVD, CVD, ALD, electroplating, electroless plating, another suitable deposition process, or combinations thereof. In some embodiments, contact elements 2802 have a ground layer (which is also referred to as a conductive connector). In some embodiments, the contact elements 2802 have a barrier layer, an adhesive layer, and / or another suitable layer arranged between the ground layer and the insulating layer 2702.In some embodiments, the barrier layer, the adhesive layer, and / or another suitable layer contain titanium, a titanium alloy (for example, TiN), tantalum, a tantalum alloy (for example, TaN), another suitable component, or combinations thereof. Additional features of the MLI may border an upper surface of the contact element 2802, for example, a metal conductor or a conductive via.

[0059] The process 100 then continues with block 134, in which additional manufacturing steps are carried out. The additional manufacturing steps may include the formation of other elements of the MLI discussed above, including contacts to the source / drain elements, such as the source / drain elements 1602. Like the contact element 2802, the contacts to the source / drain elements may involve performing lithographic processes, which include forming a photoresist layer over a respective ILD layer 1704 and CESL 1702, exposing the photoresist layer with structured radiation, and developing the exposed photoresist layer, thereby forming a structured photoresist layer that can be used as a masking element for etching one or more source / drain contact openings extending through the ILD layer 1704 and the CESL 1702 to expose epitaxial source / drain elements 1602.The etching processes include dry etching, wet etching, other etching processes, or combinations thereof. Subsequently, the source / drain contact opening(s) are filled with one or more electrically conductive materials, such as tungsten, ruthenium, cobalt, copper, aluminum, iridium, palladium, platinum, nickel, another metal component with low resistivity, alloys thereof, or combinations thereof. The conductive material(s) may be applied by PVD, CVD, ALD, electroplating, electroless plating, another suitable deposition process, or combinations thereof. In some embodiments, the source / drain contacts have a ground plane (also referred to as a conductive connector) and further have a barrier layer, an adhesive layer, and / or another suitable layer arranged between the ground plane and the ILD layer 1704 and / or the CESL 1702.In some embodiments, the barrier layer, the adhesive layer and / or another suitable layer contains titanium, titanium alloy (for example, TiN), tantalum, tantalum alloy (for example, TaN), another suitable component or combinations thereof.

[0060] Consequently, the multi-gate device 200 features a plurality of gate structures 2002. In some implementations, gate structures 2002A and 2002B serve a first device type (for example, NFET). In some implementations, gate structures 2002C and 2002D serve a second device type (for example, PFET).

[0061] Referring again to the Fig. 29A and Fig. Figure 29B shows the device 200', which is essentially the same as the device 200, but has a metallization layer 2604 and omits an inoculation layer 2602. Referring again to the Fig. 30A and Fig. Figure 30B shows the device 200'', which is essentially the same as the device 200, but has a metallization layer 2604 and an inoculation layer 2602, which is arranged above the gate structure 2002 and does not extend between the gate structures. Referring again to the Fig. 31A and Fig. Figure 31B shows the device 200''', which is essentially the same as the device 200, but has a metallization layer 2604, an inoculation layer 2602 and an etch stop layer 3102. The etch stop layer 3102 is discussed in detail below.

[0062] Now referring to Fig. Figure 32 shows a detailed view of the interface between the inoculation layer 2602, the metallization 2604, the gate structure 2002, the gate separator element 2402, and the insulating layer 2702. As shown by Fig. As shown in Figure 32, a terminal end of at least one of the metallization layers, represented here by metallization layer 2604, is rounded such that it has a curved end face. In particular, the end of metallization layer 2604 that abuts the gate separating element 2402 is rounded / curved. In some embodiments, this curved end is formed by the metallization layer 2604 within the opening (see the Fig. 25A, Fig. 25B) created adjacent to the gate separator 2402. Although Fig. 32 The rounding off of the embodiment of the device 200 represents the rounding off, the rounding can also be applied to one or more of the metallization layers of the devices 200', 200'' and / or 200'''.

[0063] It is evident from the foregoing description that the multi-gate devices described herein offer advantages compared to conventional multi-gate devices. It is understood, however, that other embodiments may offer additional advantages, and not all advantages have necessarily been disclosed herein, nor is any particular advantage required for all embodiments. One advantage is that the manufacturing processes described herein reduce the size and / or footprint of metal gates of transistors compared to transistors manufactured using conventional metal-gate cutting techniques, thereby enabling a higher transistor packing density and increasing IC feature density.Furthermore, some embodiments provide a way to prevent damage to the gate structure, such as the exit working material of the gate electrode, while creating separation between adjacent gate structures. By providing the separation, the "cut," before applying the metallization layers that connect adjacent gate structures, damage to gates can be avoided compared to methods where the metallization layers over the metal gate structures are not cut, which may result in limited etch selectivity.

[0064] The present disclosure provides many different embodiments. One exemplary device comprises a substrate, a first gate structure enclosing a channel layer arranged over the substrate, a second gate structure enclosing another channel layer arranged over the substrate, and a dielectric fin formed over a flat trench insulation element (STI element). The dielectric fin structure is arranged between the first gate structure and the second gate structure. At least one metallization layer is formed on the first gate structure, the dielectric fin structure, and the second gate structure, and extends continuously from the first gate structure to the second gate structure.

[0065] In another embodiment, the at least one metallization layer comprises an inoculation layer and a first metal layer. The inoculation layer can contain at least one of the materials from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (TaN), and tungsten (W). In some embodiments, a side wall of the inoculation layer abuts the dielectric fin structure. In one embodiment, the at least one metallization layer physically abuts an upper surface of the dielectric fin structure. The upper surface of the dielectric fin structure can be a dielectric material with a high k-value. In one embodiment, a third gate structure is separated from the second gate structure by a second dielectric fin. A gate separator element can be arranged above the second dielectric fin. In some embodiments, the at least one metallization layer abuts a side wall of the gate separator element.In another embodiment, one end of the at least one metallization layer, which abuts the side wall of the gate separating element, has a curved surface.

[0066] In another embodiment disclosed herein, a device is provided which has a first channel layer arranged between first source / drain elements above a substrate. A first metal gate surrounds the first channel layer. A second channel layer is arranged between second source / drain elements above the substrate. A second metal gate surrounds the second channel layer, and a dielectric fin is arranged between the first and second metal gates, separating them. A first section of a conductive layer is formed above the first metal gate, and a second section of the conductive layer is formed above the second metal gate. The device further comprises an insulating layer between the first and second sections of the conductive layer and above the dielectric fin.At least either the first section of the conductive layer or the second section of the conductive layer has a rounded end that rests against the insulating layer.

[0067] In another embodiment, the insulating layer of the device borders an upper surface of the dielectric fin. In one embodiment, an etch stop layer is arranged between the first section of the conductive layer and the first metal gate. In another embodiment, an inoculation layer is arranged between the first section of the conductive layer and the first metal gate. In some implementations, an upper surface of the inoculation layer is arranged below an upper surface of the dielectric fin.

[0068] In further, more general embodiments discussed herein, a method is provided which comprises forming a first gate structure, a first source structure, and a first drain structure of a first wraparound gate device (GAA device) over a substrate. Subsequently, the method comprises forming a second gate structure, a second source structure, and a second drain structure of a second GAA device over the substrate, wherein a dielectric fin is arranged between the first gate structure and the second gate structure. A dummy layer is applied over the first gate structure, the second gate structure, and the dielectric fin. The dummy layer is structured such that a groove is formed within the dummy layer over the dielectric fin. The groove is filled with a dielectric material to form a dielectric feature.The process then removes the structured dummy layer after the trench has been filled. At least one conductive layer is applied, comprising a first section over the first gate structure and a second section over the second gate structure. The dielectric element is positioned between the first and second sections.

[0069] In a further embodiment, the method comprises applying insulating material over the first and second sections of the conductive layer. In another embodiment, the method comprises forming a conductive through-hole to the second section of the conductive layer. In yet another embodiment, the method comprises structuring the dummy layer to form the trench, which includes selectively etching material from the dummy layer while substantially leaving either the first gate structure or the second gate structure unetched. The method may further comprise applying the at least one conductive layer, which includes applying an inoculation layer and an overlying metal layer.In one embodiment, the application of the at least one conductive layer (2604) of the method comprises the application of conductive material having a rounded termination area which rests against the dielectric element.

Claims

[1] Device comprising: a substrate (202); a first gate structure (2002A) which encloses a channel layer (208) arranged above the substrate (202); a second gate structure (2002B) which encloses a further channel layer (208) arranged above the substrate (202); a dielectric fin structure formed over a flat trench insulation element (STI element), wherein the dielectric fin structure is arranged between the first gate structure (2002A) and the second gate structure (2002B); at least one metallization layer (2602, 2604) on the first gate structure (2002A), the dielectric fin structure and the second gate structure (2002B), which extends continuously from the first gate structure (2002A) to the second gate structure (2002B). [2] Device according to claim 1, wherein the at least one metallization layer (2602, 2604) comprises an inoculation layer (2602) and a first metal layer. [3] Device according to claim 2, wherein the inoculation layer (2602) contains at least one of the materials from the group comprising titanium (Ti), titanium nitride (TiN), tantalum (TaN) and tungsten (W). [4] Device according to claim 2 or 3, wherein a side wall of the inoculation layer (2602) borders the dielectric fin structure. [5] Device according to one of the preceding claims, wherein the at least one metallization layer (2602, 2604) physically borders an upper surface of the dielectric fin structure. [6] Device according to claim 5, wherein the upper surface of the dielectric fin structure is a dielectric material (1002) with a high k-value. [7] Device according to one of the preceding claims, further comprising: a third gate structure (2002C) which is separated from the second gate structure (2002B) by a second dielectric fin (1004), wherein a gate separating element (2402) is arranged over the second dielectric fin (1004). [8] Device according to claim 7, wherein the at least one metallization layer (2602, 2604) is located on a side wall of the gate separating element (2402). [9] Device according to claim 8, wherein one end of the at least one metallization layer (2602, 2604) which abuts the side wall of the gate separating element (2402) has a curved surface. [10] Device comprising: a first channel layer arranged between first source / drain elements over a substrate (202); a first metal gate (2002A) that surrounds the first channel layer; a second channel layer arranged between second source / drain elements above the substrate (202); a second metal gate (2002B) that surrounds the second channel layer; a dielectric fin (1004) arranged between the first metal gate (2002A) and the second metal gate (2002B) and separating them from each other; a first section of a conductive layer (2604) over the first metal gate (2002A); a second section of the conductive layer (2604) above the second metal gate (2002B); and an insulating layer (402) between the first section and the second section of the conductive layer (2604) and over the dielectric fin (1004), wherein at least either the first section of the conductive layer (2604) or the second section of the conductive layer (2604) has a rounded termination end which rests against the insulating layer (402). [11] Device according to claim 10, wherein the insulating layer (402) borders an upper surface of the dielectric fin (1004). [12] Device according to claim 10 or 11, further comprising: an etch stop layer (3102) between the first section of the conductive layer (2604) and the first metal gate (2002A). [13] Device according to one of claims 10 to 12, wherein an inoculation layer (2602) is arranged between the first section of the conductive layer (2604) and the first metal gate (2002A). [14] Device according to claim 13, wherein an upper surface of the inoculation layer (2602) is arranged below an upper surface of the dielectric fin (1004). [15] Procedures, including: Forming a first gate structure (2002A), a first source structure and a first drain structure of a first all-around gate device (GAA device) over a substrate (202); Forming a second gate structure (2002B), a second source structure and a second drain structure of a second GAA device over the substrate (202), wherein a dielectric fin (1004) is arranged between the first gate structure (2002A) and the second gate structure (2002B); Applying a dummy layer (2202) over the first gate structure (2002A), the second gate structure (2002B) and the dielectric fin (1004); Structuring the dummy layer (2202) such that a trench (214, 1304, 2302) is formed within the dummy layer (2202) above the dielectric fin (1004); Filling the trench (214, 1304, 2302) with a dielectric material (1002) to form a dielectric element; Removing the structured dummy layer after filling the trench (214, 1304, 2302); and Applying at least one conductive layer (2604) comprising a first section over the first gate structure (2002A) and a second section over the second gate structure (2002B), wherein the dielectric element is arranged between the first and the second section. [16] The method of claim 15, further comprising: Application of insulating material over the first and second sections of the conductive layer (2604). [17] Method according to claim 15 or 16, further comprising: Forming a conductive via to the second section of the conductive layer (2604). [18] Method according to any one of claims 15 to 17, wherein structuring the dummy layer (2202) to form the trench (214, 1304, 2302) comprises selectively etching material of the dummy layer (2202) while the first gate structure (2002A) or the second gate structure (2002B) is not etched. [19] Method according to any one of claims 15 to 18, wherein the application of the at least one conductive layer (2604) comprises the application of an inoculation layer (2602) and a metal layer above it. [20] Method according to any one of claims 15 to 19, wherein the application of the at least one conductive layer (2604) comprises the application of conductive material to the at least one conductive layer (2604) having a rounded termination area which rests against the dielectric element.

Images